MICROELECTRONIC DEVICE OBTAINED BY 3D INTEGRATION AND CORRESPONDING PRODUCTION METHOD

Abstract

A 3D microstructure is formed by bonding an upper wafer (1) to a lower wafer (2), by hybrid bonding with metallic bonding pads (17b, 17c; 27b, 27c) at the interface between the upper metallization level (HBM) of the respective interconnection structure of each of the wafers. These interconnection structures further comprise a horizontal interconnection level (MX) which is directly below the upper interconnection level (HBM). These pads are distributed horizontally in a substantially homogeneous manner and with a fine bonding pitch. Among these pads, bonding pads (17b; 27b) only are electrically isolated from any horizontal metallization element (15; 25) of the horizontal interconnection level (MX).Conversely, bonding and electrical connection pads (17c; 27c) are electrically coupled, without vias, to an underlying horizontal metallization element (15; 25) formed in the horizontal interconnection level (MX). Figure 2.

Description

Title of the invention: MICROELECTRONIC DEVICE OBTAINED BY 3D INTEGRATION AND REACTION METHOD CORRESPONDING READING Technical field

[0001] The invention relates generally to the field of the microelectronics industry or semiconductor industry. It relates more particularly to three-dimensional (3D) integration, by the vertical assembly of two two-dimensional (2D) microelectronic devices each formed on a plate ("Wafer" in English) or a chip ("Die" in English) based on a respective semiconductor material, called W2W (from the English "Wafer-to-Wafer") or D2W (from the English "Die-to-Wafer") or D2D (from the English "Die-to-Die") bonding, for the production of a 3D microelectronic device.

[0002] More specifically, the invention relates to a 3D microelectronic structure (or 3D micro structure) obtained by bonding a first upper wafer to a lower wafer with a high interconnection density between said wafers, as well as a method for producing such a 3D microelectronic structure for the manufacture of an integrated semiconductor product.

[0003] It finds applications, in particular, in the manufacture of microsystems and components with high integration density, such as microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS), actuators, radiofrequency (RF) components, power devices, or microelectronic devices such as advanced microprocessors, graphics chips, optoelectronic circuits such as, for example, image sensors (or imagers) in CMOS (Complementary Metal-Oxide-Semiconductor) technology, or other. STATE OF THE PRIOR ART

[0004] The microelectronic devices used in the composition of semiconductor products integrated in a package (or integrated circuits) are produced by essentially planar technological steps. These steps are carried out on wafers or wafers based on semiconductor material, such as doped silicon. More particularly, a succession of technological steps are implemented, starting from a flat substrate forming the support of the device, with each time access to the microstructure being produced via the upper face of the wafer, also called the "front face". The size of a wafer is generally around 200 mm in diameter in technology 6" (ie, 6 inches, or "inch" in English) or approximately 300 mm in diameter in 8" technology.

[0005] A wafer on which a microelectronic device is produced in fact comprises a substantially planar substrate, with an active area in the upper part of said substrate in which the active components of the device are produced, as well as a multilayer interconnection structure formed above said active area of ​​the substrate to connect the previously formed active components, to each other and to the pins of the integrated circuit. Where appropriate, the interconnection structure can also integrate passive components (inductors, capacitors, resistors, etc.) produced in the form of metallic elements in the stacked interconnection layers.

[0006] The production of the active components of the device in the active zone of the substrate corresponds to the FEOL (Front-End-of-Line) phase of the device manufacturing. The production of the interconnection structure takes place during the BEOL (Back-End-of-Line) phase of the manufacturing. The FEOL phase will not be specifically addressed here, the invention being implemented during the BEOL phase.

[0007] The interconnection structure comprises a stack of interconnection layers, produced in sequence with alternating horizontal interconnection layers and vertical interconnection layers. The former comprise horizontal metallizations, i.e. metal tracks which extend parallel to the plane of the wafer to electrically connect respective elements of the active components produced in the active zone of the substrate, and / or where appropriate metal elements forming the aforementioned passive components. The latter comprise vias which extend perpendicular to the plane of the wafer in order to electrically connect together metal tracks and / or passive components belonging to respective horizontal interconnection layers.

[0008] The formation of such an interconnection structure by the process known as Damascene comprises successively, for each level of interconnection to be produced in stacking: • the deposition of a layer of dielectric material on the upper face of the substrate of the microelectronic device, for the first interconnection layer, or on the upper face of an interconnection layer already produced, for any interconnection layer following said first interconnection layer; • etching, in this dielectric layer, of trenches (for horizontal interconnection layers) or via holes (for vertical interconnection layers); • the deposition of copper (Cu) on the dielectric layer thus etched, in order to fill the trenches and / or the via holes, to obtain the desired metallic interconnection elements; and, • chemical-mechanical polishing of the excess copper in order to flatten the upper surface of the interconnection layer thus produced, with a view to forming another level of interconnection above the one which has just been produced.

[0009] Wafer bonding refers to a technology for vertically assembling a first wafer, called the upper wafer (or "top wafer" in English), onto another wafer or lower wafer (or "bottom wafer" in English) also called a "handle" wafer in reference to its function of supporting the microstructure thus obtained. For this purpose, the first wafer is turned vertically, then is aligned and deposited by its front face on the front face of the handle wafer. If a condition of extreme flatness of the upper surfaces of the respective wafers which are thus brought into contact is respected, the Van der Waals forces, namely attraction interactions at the microscopic scale which exist for all materials, ensure adhesion between the lower and upper wafers. In the technical field in question, we speak of "bonding" to designate an assembly based on the use of these adhesion forces.The adhesion is all the stronger as the contact surface between the two plates at the microscopic scale is large, hence the importance of smoothing out all surface roughness at this scale. The upper surfaces of the two plates corresponding to their respective front faces are therefore ultra-polished, prior to their mutual assembly, in order to be extremely smooth to avoid any bonding defects.

[0010] The bonding of two or more wafers, stacked vertically, with or without an intermediate layer, allows the production of a 3D microstructure, even though only 2D production technologies are separately implemented in the FEOL (Front-End-of-Line) phase of manufacturing, to produce the microelectronic devices in each of the two wafers, respectively. Different technological protocols (process flow) exist to produce such a 3D assembly. These various technological protocols can be differently adapted to the specific requirements of the intended applications, which are multiple and varied. Here, we will limit ourselves to hybrid bonding solutions for W2W type semiconductor material wafers, compatible with a bond between assembled wafers that is at the wafer scale (so-called wafer-level bonding).

[0011] The connection between the stacked plates can be ensured by means, in particular, of bonding pads provided for this purpose. These pads are implanted in respective mutual positions on the upper surface of each of the two boards to be assembled. In practice, the bonding pads are metal elements, which are made in the dielectric material of an interconnection layer, by implementing a final step of the Damascene process. Such metal bonding pads are therefore harder than the dielectric material of the layer of insulating material in which they are made.

[0012] The bonding pads are more particularly made in the last metallization level of each of the wafers, i.e., the highest metallization level of the interconnection structure of said wafer, i.e. also the furthest from the substrate. In the following, it will be called the HBM level (from the English "Hybrid Bonding Metal"). The upper face of the bonding pads is therefore exposed on the surface of the interconnection structure of each respective wafer, which is also the surface of the wafer, at the end of the BEOL phase of manufacturing.

[0013] This embodiment of the connecting pads, made of metal, is advantageous for various reasons which are linked, in particular, to the hardness of the metal and to the technological steps of the manufacture of such metal pads. These reasons include, in particular: • the rigidity of the upper face of the plate thus obtained (subject to a sufficient density of metal studs); • the precision of the patterns used to make the plots (using the Damascene process, which is an effective and mature technique); • the quality of the polishing that can be obtained by conventional mechanical-chemical means (due in particular to the relative hardness of the metal); and, • the accuracy of alignment between the pads which can be obtained by using the metal studs for the alignment in relative positions of the two pads, etc.

[0014] The bonding pads being made of metal, and more particularly of copper within a layer of dielectric material by implementing the Damascene process, they are therefore by nature conductive elements of the electric current. The bonding of the plates is called "hybrid" because the bonding interface between the plates is heterogeneous: it comprises portions of metal corresponding to the bonding pads, on the one hand, and portions of dielectric material corresponding to the areas between said pads, on the other hand.

[0015] Another advantage of producing metal bonding pads is the possibility of having the bonding pads participate in the routing map of the electrical operating signals of the 3D microstructure finally obtained. This routing can in fact be carried out by using at least some of the bonding pads to pass current between the lower plate and the upper plate, and vice versa, of the 3D micro structure.

[0016] Among the connecting pads, there are then: • bonding pads of a first type, which are exclusively dedicated to bonding between the wafers, and which are formed by fictitious metallization elements (known by the person skilled in the art by the English term “dummies”). These pads are not connected to elements of the microelectronic device produced in the active zone of the wafer, nor even to other passive elements or to vias which would be produced in the horizontal or vertical interconnection layers, respectively, corresponding to lower metallization levels of the interconnection structure. In other words, they are perfectly electrically isolated from other conductive elements belonging to active or passive devices of the wafer, by the dielectric material which surrounds them. They therefore do not perform any function in the operation of the final microelectronic device, beyond their basic role of bonding support.We will therefore say that they are non-functional bonding pads; as well as, . • bonding pads of a second type which, at the same time, serve as a bonding support just like the pads of the first type above, but also have the role of ensuring an electrical connection between the two wafers assembled vertically by this bonding. They therefore participate in the operation of the final microelectronic device. To make these bonding pads thus functional, vias are created, during the BEOL phase of the production of the individual wafers (i.e. before their bonding), in at least the directly lower vertical interconnection layer.These vias provide the electrical connection between, on the one hand, the functional pads in question and, on the other hand, elements located below, for example active devices (such as transistors or photodiodes, for example) made during the FEOL phase in the active area of ​​the corresponding wafer, and / or passive devices (such as conductive tracks, capacitors, inductors, etc.) made during the BEOL phase, in the underlying horizontal interconnection layer of the interconnection structure of the corresponding wafer. The vias connecting the bonding pads of the second type are therefore made in a dedicated metallization level, which will be called the HBV level (from the English "Hybrid Bonding Vias").

[0017] In summary, the bonding pads of the first type (non-functional pads, or "dummies") of each of the two wafers are made in the last metallization layer of the interconnection structure (i.e., the nth layer for a structure n-layer interconnection) corresponding to the HBM metallization level, being isolated from any underlying element of said wafer by the dielectric material of the penultimate metallization layer, which is a vertical interconnection layer corresponding to the HBV metallization level; whereas the bonding pads of the second type (functional pads) are also made in the last metallization layer of the interconnection structure but are coupled to active elements of the active zone of the substrate or to passive elements of the antepenultimate layer of the interconnection structure (which is a horizontal interconnection layer) by vias made in the penultimate layer of said structure (which is a vertical interconnection layer corresponding to the HBV metallization level).

[0018] Furthermore, the number of bonding pads per unit area (including non-functional bonding pads, on the one hand, and functional bonding and connection pads, on the other hand), as well as their respective positions on the upper surface of the plates, are dictated by manufacturing and reliability constraints of the microelectronic devices. These constraints are defined in a design rules manual, or DRM (from the English "Design Rules Manual"). Compliance with such design constraints allows the development of manufacturable, functional and reliable integrated circuits, with the lowest possible energy budget and the best possible economic competitiveness.

[0019] According to these design rules, a minimum density of bonding pads and a roughly homogeneous distribution of said bonding pads on the upper face of the wafers to be bonded are required. This makes it possible to obtain, by chemical mechanical polishing or CMP (from the English "Chemical Mechanical Polishing"), an upper surface of the wafers to be assembled vertically which is sufficiently flat to produce a 3D microstructure without bonding defects. If these design rules are not respected, it is difficult to obtain wafers with a very flat upper surface. Indeed, polishing by CMP generates differences in topography between the more or less dense zones of metal depending on the CMP brine ("CMP slurry" in English) which is used (erosion phenomenon). These eroded zones then appear as hollows on the surface and are therefore not bonded during bonding. These surface defects therefore materialize by unbonded zones, i.e., interface bubbles called "voids". These voids weaken the 3D microstructure and render chips affected by such bonding defects non-functional (because electrical contact is no longer ensured).

[0020] The bonding pitch defines the upper limit of the spacing of the bonding pads in the horizontal XY plane of the wafer, i.e. the maximum center-to-center distance between the closest adjacent bonding pads in said horizontal XY plane. This is one of the parameters of the DRM to to be respected when designing the integrated circuit. The finer the bonding pitch, the higher the interconnection density, and vice versa. The invention applies in particular to embodiments with hybrid bonding of wafers with a high interconnection density, i.e., with a fine bonding pitch, i.e. one that is less than 10 micrometers (pm), for example of the order of 5 pm.

[0021] In the existing art set out above, the differentiation between functional bonding pads and non-functional bonding pads results from the selective formation, before hybrid bonding, of vias in the vertical interconnection layer corresponding to the so-called "HBV" metallization level, directly below the last layer of the interconnection structure corresponding to the so-called "HBM" metallization level and in which said bonding pads are produced in compliance with the DRM requirements relating to high interconnection density. This penultimate HBV layer is a vertical metallization layer which is produced for this sole purpose in the interconnection structure of each of the wafers to be assembled vertically.

[0022] The scientific article Kim et al., “Multi-Stack Wafer Bonding Demonstration Utilizing Cu to Cu Hybrid Bonding and TSV Enabling Diverse 3D Integration,” IEEE 71 st Electronic Components and Technology Conference (ECTC) - 2021, discloses a vertically stacked integration of three wafers with, in this order: a bottom wafer, an intermediate wafer, and a top wafer. Unlike what is described for the bonding between the intermediate wafer and the bottom wafer, the bonding between the top wafer and the intermediate wafer is achieved without a via, in the usual sense of this term.In other words, neither in the interconnection structure of the upper wafer nor in that of the intermediate wafer intended to be interconnected with said upper wafer, there is a via between metallic bonding pads made in these interconnection structures on one side, and elements (active or passive) made in lower metallization levels of the wafer concerned, on the other side. The bonding pads of the intermediate wafer and of the upper wafer which are disclosed in this document are all electrical connection pads between said intermediate wafer and said upper wafer, i.e., functional bonding pads, and which are used, in addition, as bonding pads.In fact, everything happens as if the connection pads all had the function of electrical connection pads (that is to say the basic function of a via, in reality, but at the interface between the two stacked plates), being put into electrical contact two-by-two by the effect of the vertical bonding between the two plates.

[0023] However, this integration is not compatible with drawing rules such as those imposed by the CMP for hybrid bonding applications, and which were presented above. In particular, the Kim et al. 2021 document does not address the problematic of the size of the bonding step in the integration considered. For example, it does not disclose that bonding pads should be in minimum number per unit area and / or should respect a certain implantation topology (i.e., a spatial distribution) particular to the upper surface of the semiconductor devices corresponding to the upper plate and the intermediate plate. Thus, the bonding support function provided by the vias as disclosed in this document does not seem to be linked to particular morphological considerations relating to constraints of implantation of bonding pads. On the contrary, the document Kim et al. 2021 simply teaches to use the vias which are intended in the first intention for the electrical connection between the wafers, as a hybrid bonding support which makes them functional bonding pads.But nothing is indicated in the document that would suggest the existence of non-functional bonding pads. However, it appears that the type of integration described is not viable for fine bonding pitches (i.e., of the order of 5 pm) or even standard (i.e., up to 10 pm) bonding pitches. Indeed, for microstructures with high interconnection density, the bonding pads cannot in practice be limited to functional bonding pads whose number, location and distribution are dictated only by the routing plan, without addressing the DRM requirements relating to the interconnection density between the wafers.

[0024] Also, this type of integration without a layer of the interconnection structure dedicated to the formation of bonding vias which are not also electrical connection pads (i.e. vertical integration without "dummies" pads), is only conceivable if it is possible to use for hybrid bonding only pads already provided to ensure an electrical connection function in the 3D microstructure considered. In practice, this solution may possibly find applications in simple test structures (or "daisy chains" in English) only, for laboratory applications in which the risk of bonding defects is acceptable. But it cannot be used in the case of the integration of a 3D microstructure, for the manufacture of integrated circuits on an industrial scale intended for commercial applications.In this case, the drawing rules manual (DRM) imposes a minimum density and a substantially homogeneous distribution of bonding pads, which aim to ensure a sufficient interconnection density to avoid bonding defects. Such a density and such a distribution are not generally encountered when the bonding pads are formed exclusively of functional bonding pads provided for other reasons, namely reasons related to the routing plan of the 3D microelectronic device. Statement of the invention

[0025] The invention aims to propose an alternative to the existing art disclosed in this above, making it possible to do without the HBV layer while respecting the DRM requirements relating to the density and homogeneity of the distribution of bonding pads.

[0026] For this, the invention has as its first object a three-dimensional, 3D, microelectronic structure for an integrated semiconductor product, said 3D microelectronic structure comprising a first microelectronic device produced on an upper wafer, as well as a second microelectronic device produced on a lower wafer on which the upper wafer is bonded by hybrid bonding after vertical turning, in which the lower wafer and the upper wafer each comprise a substantially planar substrate as well as an interconnection structure formed above said substrate, in which: • the respective interconnection structure of each of the upper and lower plates is a vertical stack of at least two interconnection levels directly superimposed and each comprising a hybrid layer essentially composed of a dielectric material, namely, respectively: • a higher interconnection level (HBM), with metal bonding pads formed in the dielectric material and adapted to cooperate with corresponding metal bonding pads of the other wafer for hybrid bonding of the upper wafer to the lower wafer; and, • a horizontal interconnection level (MX) which is directly below the upper interconnection level, with horizontal metallization elements, • the respective metal bonding pads of each of the upper and lower wafers are distributed in a substantially homogeneous manner on the upper surface of the upper interconnection level of the interconnection structure of said wafer, with a bonding pitch, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, which is less than a determined associated threshold; • the respective metal bonding pads of each of the upper and lower wafers comprise bonding pads of a first type, which are electrically isolated from any horizontal metallization element of the horizontal interconnection level of the interconnection structure of said wafer; and, • the respective metal bonding pads of each of the upper and lower plates further comprise bonding pads of a second type, which are each electrically coupled to at least one underlying horizontal metallization element formed in the horizontal interconnect level of the interconnect structure of said wafer.

[0027] As the person skilled in the art will have understood, the first microelectronic device formed on the upper wafer and the second microelectronic device formed on the lower wafer are assembled vertically one above the other by full-wafer hybrid bonding, via a hybrid bond at the interface between the upper layer of the respective interconnection structure of each of said upper and lower wafers.

[0028] Some preferred but non-limiting aspects of the method are as follows.

[0029] The horizontal interconnection level of the interconnection structure of each of the lower and upper plates may comprise a passivation film of electrically insulating material which covers the layer of dielectric material of said horizontal metallization level, the bonding pads of the first type of each of the upper and lower plates being electrically insulated from any horizontal metallization element of the horizontal interconnection level of the interconnection structure of said plate, at least by the insulating material of the passivation film covering the layer of dielectric material of said horizontal metallization level.

[0030] The layer of dielectric material of the upper interconnection level of the interconnection structure of each of the upper and lower plates may be a hybrid layer of patterned dielectric material, said patterns defining: • solid areas of said dielectric material; • first through-zones vertically filled with metallic material and at the level of which the insulating material of the passivation layer of the horizontal interconnection level is present, said first through-zones forming the connection pads of the first type of the upper interconnection level; and, • second vertically passing through zones, filled with metallic material, and at the level of which the passivation layer of the horizontal interconnection level has an opening, said second passing through zones forming the connection pads of the second type of the upper interconnection level, each in electrical continuity with one of the horizontal metallization elements of the horizontal interconnection level through said opening of the passivation layer.

[0031] In embodiments, the associated threshold of the bonding pitch is less than or equal to 10 pm, preferably of the order of 5 pm.

[0032] The dielectric material of the hybrid interconnection layers of the structure interconnection of each of the upper and lower plates is for example Silicon Dioxide (SiO2).

[0033] The material constituting the metal bonding pads of the upper interconnection level and / or the material constituting the horizontal metallizations of the horizontal interconnection level of the interconnection structure of each of the upper and lower plates, may be a metal selected from the group comprising copper (Cu), gold (Au), titanium (Ti), aluminum (Al), niobium (Nb) and platinum (Pt), or an alloy based on at least one of said metals.

[0034] In embodiments, the electrically insulating material of the passivation film of the horizontal interconnection level of the interconnection structure of each of the upper and lower wafers is a silicon nitride (SiN) or a silicon carbonitride (SiCN).

[0035] The substrate of the upper wafer and / or the substrate of the lower wafer may each comprise an active zone with active elements in the upper part of said substrate, and in which: • the bonding pads of the first type of the interconnection structure of each of the upper and lower plates are electrically isolated from the active elements of the active zone of the substrate of said plate, whereas, • at least some of the bonding pads of the second type of the interconnection structure of the upper wafer and / or the lower wafer are electrically coupled to at least one of the active elements of the active zone of the substrate of said wafer.

[0036] The invention also relates to a method for producing a three-dimensional, 3D, microelectronic structure, according to the first aspect above, comprising the hybrid bonding of an upper wafer onto a lower wafer after vertically turning over said upper wafer, in which the prior production of the interconnection structure of each of the lower and upper wafers comprises the formation of a vertical stack of at least two interconnection levels directly superimposed above the substrate of said wafer, namely, respectively: • a horizontal interconnection level (MX), with horizontal metallization elements formed in the dielectric material of a corresponding hybrid layer; and, directly above said horizontal interconnection level (MX), • a higher interconnection level (HBM) with metal bonding pads formed in the dielectric material of a corresponding hybrid layer, and adapted to cooperate with corresponding metal bonding pads of the other wafer, for hybrid bonding of the wafer on upper (1) on the lower plate, and in which: • the respective metal bonding pads of the upper metallization level of the interconnection structure of each of the upper and lower plates are produced with a substantially homogeneous distribution on the upper surface of said upper metallization level, and with a bonding pitch, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, which is less than a determined associated threshold; • among the respective metal connecting pads of each of the upper and lower plates, connecting pads of a first type are each produced with electrical insulation from any horizontal metallization element of the horizontal interconnection level of the interconnection structure of said plate; • among the respective bonding pads of each of the upper and lower plates, in addition, bonding pads of a second type are each produced in electrical continuity with at least one underlying horizontal metallization element formed in the horizontal interconnection level of the interconnection structure of said plate.

[0037] In embodiments of the method, forming the upper interconnect level of the interconnect structure of each of the upper and lower wafers may comprise: • the deposition of a passivation film made of electrically insulating material which covers a hybrid layer made of dielectric material comprising horizontal metallization elements of the horizontal metallization level of the wafer; • the formation of a layer of dielectric material as well as a first etching by photolithography, to etch said layer of dielectric material with a stop on the passivation film of the horizontal metallization level in order to form patterns in said layer of dielectric material corresponding to the metal bonding pads of the upper metallization level of the wafer; then, • a second etching by photolithography, to etch the passivation film of the horizontal metallization level in order to open said film in only part of the patterns previously formed in the layer of dielectric material which correspond to the metal bonding pads of the second type of the upper metallization level of the wafer; then, • the simultaneous filling with metal of all the pre- previously formed in the layer of dielectric material, namely both the patterns corresponding to the metal bonding pads of the first type and the patterns corresponding to the metal bonding pads of the second type of the upper metallization level of the wafer.

[0038] The patterns in the dielectric material layer corresponding to the metal bonding pads of the upper metallization level of the wafer may, for example, be filled with metal by electrochemical deposition.

[0039] Thus, the bonding pads of the first type of each wafer are formed in the upper layer of the interconnection structure and are electrically isolated from any metallization element formed in any interconnection layer corresponding to a lower metallization level in the stack of layers forming the interconnection structure, as well as from any active element of the active zone of the lower wafer. This isolation is provided by the insulating material of the passivation layer associated with the horizontal interconnection layer of the interconnection structure which is directly below said upper layer. These bonding pads of the first type are therefore non-functional pads, i.e., fictitious metallizations ("dummies"), which are used only for hybrid bonding.

[0040] On the other hand, the bonding pads of the second type are bonding and electrical connection pads formed in the upper layer of the interconnection structure, in electrical continuity with a metallic element of at least one other horizontal interconnection layer of the interconnection structure which is the metallization layer directly below the upper layer. These bonding pads of the second type are therefore functional pads, serving both for the hybrid bonding of the upper wafer turned vertically onto the lower wafer, and for the electrical connection between the two devices thus assembled vertically.

[0041] The production of the semiconductor product in accordance with the first aspect of the invention above, and the implementation of the method in accordance with the second aspect of the invention above, make it unnecessary to produce a vertical interconnection layer with vias directly below the upper layer of each of the two 2D microelectronic devices to be stacked. This production can therefore be dispensed with, by having functional bonding pads as well as non-functional bonding pads which together make it possible to achieve the desired interconnection density. It is thus possible to comply with the design rules (DRM) to obtain good CMP performance and therefore good quality bonding of the two stacked microelectronic devices.

[0042] According to another advantage, the electrical resistance of a functional bonding pad made in accordance with embodiments of the proposed method is significantly lower than that of vertical electrical connections made by vias according to the prior art. The reduction in the interconnection resistance reduces the dis Joule energy sipation in the integrated circuit during operation, and therefore limits the rise in temperature. This reduction also improves the autonomy of small portable devices (such as smartphones) incorporating the integrated circuit, when they operate on battery.

[0043] It is recalled that the electrical resistance of an interconnection is inversely proportional to the contact surface between the two interconnection elements placed in electrical contact with each other, all other things being equal: the larger this surface, the higher the quantity of current that can pass through the interconnection, and therefore the lower the electrical resistance. However, the person skilled in the art will appreciate that: • in the case of conventional 3D integrations in which the interconnections comprise vias of circular section, the current is limited by the small surface area of ​​the vias compared to those of the bonding pads. For microstructures having a bonding pitch of, for example, 5 pm, the diameter of the circular section of a via can be 0.5 pm, so that the cumulative surface area of ​​the four vias produced for a given bonding pad is equal to 4% 3.14 x (0.25)2, or 0.785 pm2; whereas, • in the case of an interconnection obtained by implementing the method according to the invention, it is the total surface area of ​​the pads (considering an optimal alignment between the respective pads of the two 2D microelectronic devices) which provides the electrical connection surface for the passage of electrons. The square section contact surface can then be equal to 2.5 x 2.5 pm, or 6.25 pm2 which represents approximately eight times the cumulative surface area of ​​four vias conforming to a conventional solution, therefore a passing current which can be eight times higher. Even in the event of an alignment defect, for example with a misalignment of 50%, the contact surface gain represents a factor of four, which means that the contact resistance of an electrical connection element is divided by four, at least, compared to the existing art.

[0044] Furthermore, since the bonding pads are directly connected to the metal lines of the horizontal interconnection layer which is directly below the upper layer of the interconnection structure, the formation of titanium nitride (TiN) passivation layers which are conventionally used in embodiments according to the prior art, which have the disadvantage of being more resistive than metal, is avoided. For this other reason also, the interconnection resistance is improved (it is lower), thanks to the implementation of the invention.

[0045] According to yet another advantage, the thickness of each of the plates can be smaller than in the microstructures according to the prior art, given that there is no no need for an HBV-level interconnect layer to create vias for connecting functional bonding pads. Each wafer is therefore less mechanically stressed, which provides better bonding conditions for the two wafers. This also reduces the risk of bonding defects.

[0046] Overall, and as will be explained in the detailed description of methods of implementing the method, the proposed production method allows the saving of nine technological manufacturing steps, compared to the productions in accordance with the existing art. The ecological and economic impact, as well as the time saving compared to the known methods, are therefore considerable. In particular, the cycle time being shorter, there is less water recovery and therefore a reduced risk of degassing during annealing. In addition, there are two fewer anneals, which brings a reduction in the overall thermal budget. Brief description of the drawings

[0047] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof. This description is given by way of non-limiting example. It is made with reference to the appended drawings, in which:

[0048] [Fig.1A] is a view, in vertical section, of an example of a 2D microelectronic device, suitable for the production of a 3D micro structure by hybrid bonding with another similar device, according to the existing art;

[0049] [Fig.lB] is a schematic representation illustrating the principle of hybrid bonding assembly, of the W2W type, of two 2D microelectronic devices like that shown in [Fig.lA], to arrive at a 3D microstructure;

[0050] [Fig.lC] is a view, in vertical section, of the 3D microstructure obtained by the vertical assembly of two 2D microstructures such as that shown in [Fig.lA] by hybrid bonding as illustrated by [Fig.lB], in accordance with the prior art;

[0051] [Fig.lD] is a top view of an example of a 3D microelectronic device according to the prior art, similar to that shown in section in [Fig.lC];

[0052] [Fig.2] is a view, in vertical section, of an example of a microstructure according to the second object of the invention;

[0053] the figures of [Fig.3A] to [Fig.31] are views, in vertical section, of an example of a 2D microelectronic device at various stages of its production according to a method in accordance with implementations of the first aspect of the invention, to allow the production of the 3D microstructure of [Fig.2] by the vertical assembly of two such identical or similar 2D microelectronic devices;

[0054] [Fig.4] is a step diagram illustrating groups of steps of the method according to implementations of the method according to the first aspect of the invention, and steps of a method in accordance with the prior art; and,

[0055] [Fig.5] gives a comparison table, by matching, of the steps of a method according to the prior art and the steps of the method according to implementations of the first aspect of the invention, respectively. DETAILED DESCRIPTION OF EMBODIMENTS

[0056] In the figures and in the remainder of the description, the same numerical references designate identical or similar elements. In addition, the different elements are not shown to scale, so as to favor the clarity of the figures. Furthermore, the different embodiments and variants which are presented are not mutually exclusive and can be combined with each other.

[0057] In the following, the terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the expressions "between A and B", and equivalent expressions mean that the limits A and B are included, unless explicitly stated otherwise.

[0058] By the expression "formed from", used in reference to a material and to an element of interest, it is meant that the material is a compound formed from a plurality of elements including at least said element of interest.

[0059] The expression "material predominantly comprising" an element of interest means a material of which at least 50% by volume is formed by, or comprises said element of interest.

[0060] The term "wafer" is a term coming from the English which designates a very thin plate (also called "wafer" because of its low thickness) of monocrystalline semiconductor material, on which microelectronic devices can be made. Wafers are thus used to manufacture microelectronic devices. Wafers are made with a doped semiconductor material, such as silicon (Si), gallium arsenide (GaAs) or indium phosphide (InP). Wafers generally have dimensions between 25.4 mm (1" technology) and 300 mm (8" technology), for a thickness of the order of 0.7 mm. Wafers are used in the microelectronics industry as a support for manufacturing microstructures. This manufacturing uses design techniques such as, for example and without limitation: doping, etching, deposition of other materials and photolithography.The doped semiconductor material of which the wafer is made therefore serves as a substrate for the creation of micro structures forming the active microelectronic devices which are used in the composition of integrated circuits, transistors, power semiconductor products, MEMS or NENS, etc.

[0061] In the manufacture of an integrated circuit, the FE (“Front End”) phase designates all the technological stages of manufacturing the circuit before its packaging. The FE includes the FEOL phase (from the English “Front End Of the Line”). ") as well as the BEOL phase (from the English "back end of line"). The FEOL designates the first phase, in which all the manufacturing steps of the active components (transistors) are carried out, for example in CMOS technology, in the active area of ​​the wafer up to the first metallization level (but not included) of the interconnection structure coming above. The BEOL designates the second phase of the integrated circuit manufacturing, which starts from the first metallization level of the stack of metallization layers forming the interconnection structure by which the active components of the active area of ​​the wafer are interconnected with each other according to a routing plan ensuring the wiring of the active components on the wafer. In this second phase, in addition, individual microelectronic devices forming the passive components (capacitors, inductors, resistors, etc.) can be realized in the different metallization levels of the interconnect structure. Commonly used metals are copper (Cu) and aluminum (Al). BEOL begins when the first layer of metal is deposited on the wafer. By extension, BEOL is sometimes referred to as the interconnect structure that includes the insulating layers (dielectrics), the metal traces (horizontal electrical connections), the vias (vertical electrical connections between the traces, and the bonding sites for the connections between the chip and the integrated circuit package).

[0062] The expression "chemical-mechanical polishing" or CMP (from the English "Chemical-Mechanical Polishing"), already used in the introduction, denotes a process of smoothing the surface of a wafer using the combined action of mechanical and chemical forces, having as effect the removal of the material(s) on the surface of the wafer and the erasure of any surface topography, with the result of the planarization of the surface of the wafer exposed to this process.

[0063] The "Damascene process" is a technique for forming metallic elements (also called "metallizations") in copper, which consists of etching trenches and via holes in a layer of dielectric material, then filling the trenches and via holes with copper to form conductive tracks and vias, respectively, and finally planarizing the copper using chemical mechanical polishing (CMP).

[0064] "Annealing" a material is an operation corresponding to a heating cycle, consisting of a step of gradual temperature increase to temperatures ranging from 250°C to 450°C, approximately, followed by controlled cooling. Annealing makes it possible to modify the physical characteristics of the material subjected to this heat treatment.

[0065] "Electrolytic or electrochemical deposition", or ECD (from the English "Elec-troChemical Deposition"), is a deposition technique used for the rapid filling of trenches or via holes with a metal such as copper, for example. Its implementation principle is as follows: the wafer is configured as a negative electrode (cathode) and is immersed in an electrolyte, i.e., an electrolytic solution containing metal salts. Copper is deposited from an anode, i.e., a positive counter-electrode, made of copper. To do this, the metal ions of the anode are reduced by applying a potential difference between this anode and the cathode. In order for the reaction to occur homogeneously on all the desired portions of the wafer surface, these must be conductive. In other words, it is therefore necessary that the resistivity of the bonding layer on the targeted portions of the wafer be as low as possible.

[0066] The term "photoresist" designates a material, more particularly a polymer resin, which is sensitive to light and is used to form a pattern on the substrate, using an optical mask formed of opaque areas and transparent areas which define the pattern which is desired to be reproduced on the wafer through which the photoresist is illuminated and has its properties modified at the transparent areas of the optical filter.For example, a "positive" photoresist is a light-sensitive polymer that, when exposed to ultraviolet (UV) light, transforms into a soluble material: the areas exposed to this illumination can then be dissolved using a solvent, leaving behind a patterned, intaglio layer that can be used as a mask for the formation of a structure through the mask thus formed, for example by etching an underlying material that is selective to the mask material, by ion implantation, or by deposition of new material in the areas exposed by the mask.

[0067] Finally, here and for the remainder of the description, a direct three-dimensional orthogonal reference frame (X, Y, Z) is defined, where the X and Y axes form a plane parallel to the main plane of the "handle" plate considered, and where the Z axis is oriented substantially orthogonal to the main plane of said plate, this Z axis being oriented in the direction of gravity. In the remainder of the description, the terms "vertical" and "vertically" are understood as relating to an orientation substantially parallel to the Z axis, and the terms "horizontal" and "horizontally" as relating to an orientation substantially parallel to the (X, Y) plane.Furthermore, the terms "above" and "below" and their derivatives (such as "above" and "below", or "over" and "below"), as well as the terms "lower" and "upper", used to qualify an element of the microstructure considered, are understood as relating to an increasing positioning when moving away from the wafer upwards, i.e., along the vertical direction +Z.

[0068] The term "back" and the term "front", on the other hand, are used in reference to the face of a plate by which the different treatments are, or have been carried out to produce the microstructure considered. These treatments are systematically carried out from above when the plate is placed flat in an enclosure used for perform the processing, the "front" side is generally (and by default) the top side of the wafer. However, when a wafer or die cut from a wafer is flipped vertically, its front side becomes the bottom side and its back side becomes the top side. The term "back" for the semiconductor substrate of an individual wafer or die is also used in reference to this convention, in that it refers to the part of the substrate that is furthest from the side of the wafer or die at which processing has been performed in the substrate, and is always referred to as the back side even if the wafer or die has been flipped vertically so that this side is now on top and facing upwards.

[0069] By "layer" is meant an area of ​​a material whose thickness along the Z axis is less, for example ten times or even twenty times, than its longitudinal dimensions of width and length in the XY plane.

[0070] By "plot" is meant a volume of a crystalline material, for example based on a specific metal such as copper or aluminum, the thickness of which along the Z axis is substantially equal to its longitudinal dimensions of width and length in the XY plane, and the longitudinal dimensions of which are less than or equal to the thickness along the Z axis of a layer in which they are made. The shape of the plot, in a horizontal section plane (parallel to the XY plane) may be polygonal (for example a square or a rectangle), or curved (for example a circle or an ellipse).

[0071] Particular embodiments will be described with reference to the non-limiting example of the application to the production of a 3D microelectronic structure intended for the manufacture of an integrated semiconductor product, for example in CMOS technology. The embodiments of this 3D micro structure and the methods of implementing the method described can be adapted to the particularities specific to each application concerned, without departing from the teachings of the invention.

[0072] We will first describe, with reference to the diagrams in [Fig.lA] to [Fig.lD], the principle of 3D assembly by hybrid bonding according to the prior art.

[0073] Direct bonding can be used in 3D integration. Two dielectric materials are bonded together to assemble two separate wafers. However, only a mechanical bond is achieved and there is no electrical continuity at the bonding interface. Resumption of electrical connections between the upper wafer and the lower wafer can be achieved, after bonding, by forming through-hole vias (TSVs), which are high aspect ratio vias that pass through the SiO2 and / or Si layers, from one side of the bonding interface to the other. This technique offers only a low interconnect density between the wafers. In addition, its implementation is relatively long and complex, because the TSV implementation process includes many etching steps and deposition steps.

[0074] Hybrid bonding constitutes another approach also well known, per se, to the person skilled in the art. According to this approach, two wafers are processed separately, following a conventional integration process until the last of the standard metallization levels of their respective interconnection structure is achieved, namely the n stacked metallization levels also called levels M1, M2, ..., Mn. After this step, a penultimate metallization level called "hybrid bonding via level" (or HBV level, from the English "Hybrid Bonding Vias"), as well as a final (i.e., last) metallization level called "hybrid bonding metallization level" (or HBM level from the English "Hybrid Bonding Metal"), are added vertically to the interconnection structure of each of the wafers, by continuing the Damascene process after the n underlying metallization levels (or levels M1, M2, ..., Mn) have been achieved.The HBM level is the bonding level of the wafer for hybrid bonding with the other wafer, and for this purpose contains bonding pads. The HBV level, which is directly below the HBM level, contains exclusively vertical metallizations for the electrical connection of some of the bonding pads of the HMB level with lower metallization levels Ml, M2, ..., Mn. The difference with the direct bonding mentioned above is the presence of the copper bonding pads in the respective bonding levels of the two wafers, with a high density. The dielectric material in these levels is SiO2 deposited by chemical vapor deposition (PECVD). The very high density of bonding pads present in this SiO2 layer offers many advantages, not only in terms of the electrical connection between the two wafers once assembled by hybrid bonding, but also in terms of the quality of the resulting bond.

[0075] With reference to [Fig.1A], a first microelectronic device 100 according to the prior art, for example a device in CMOS technology, comprises a substrate 101. The substrate 101 is for example a silicon substrate. Above the substrate 101, the device 100 comprises a layer 102 of electrically insulating material (dielectric), such as silicon dioxide (SiO2). The layer 102 is itself covered by a passivation layer 103, for example a layer of silicon nitride (SiN).

[0076] The microelectronic device 100 comprises an active area (not shown) in the top of the substrate 101, directly below the insulating layer 102. This active area may comprise active components, such as transistors, photonic devices such as photodiodes, etc. Such components, where appropriate, are produced using, for example, the technological manufacturing steps which are the conventional steps of microelectronics in CMOS technology, in order to produce an integrated circuit for a given application. This phase of the circuit manufacturing (or FEOL phase) will not be discussed in the present description, because the invention is implemented during the subsequent BEOL phase, namely the phase of realization of the interconnection structure. This interconnection structure will now be described, still with reference to [Fig.lA].

[0077] The microelectronic device 100 in fact comprises an interconnection structure formed by a stack of n layers each corresponding to a respective metallization level, where n is an integer strictly greater than unity. These n interconnection layers are essentially made of an electrically insulating (dielectric) material, such as silicon dioxide (SiO2). They contain metallic elements, namely conductive tracks or vias. These metallic elements (also called "metallizations" for short) are made by depositing metal in trenches or via holes, respectively, previously formed by any ad-hoc process, in the dielectric material of the corresponding interconnection layer. The trenches and via holes are generally formed by photolithographic etching, then filled with metal.The metal in question is usually copper (Cu), but it could possibly be another metal, such as aluminum (Al) for example. The layers of the interconnection structure correspond to respective metallization levels which are commonly designated by the acronyms Ml, M2, ..., Mn in the relevant literature. There is an alternation of horizontal metallization levels comprising conductive tracks made by deposition of metal in trenches formed in the dielectric material of the corresponding layer, and vertical metallization levels comprising vias made by deposition of metal in via holes formed in the dielectric material of the corresponding layer.The vias of a vertical metallization level are arranged to couple conductive traces of a metallization level above (if any) with conductive traces of a metallization level below and / or with active elements of the active area of ​​the substrate 101.

[0078] In the example of [Fig.1A], n is equal to three (n=3): the interconnection structure comprises three layers 104, 107 and 110 stacked vertically, in this order, above the insulating layer 102 with which the substrate 101 is coated. They are formed successively above the substrate 101, one after the other, starting with the lowest layer and ending with the highest layer. In this example, layer 104 is the lower layer of the interconnection structure, or lowest layer, i.e. also the one closest to substrate 101. It corresponds to the first metallization level, denoted MX in the figure and below, which is formed directly above substrate 101. Opposite in the vertical direction Z, layer 110 is the upper layer of the interconnection structure, or highest layer, i.e. also the one furthest from substrate 101.It corresponds to the last level of metallization which, in the context of the present description, is . designated by the acronym HBM (for "Hybrid Bonding Metal"). Finally, layer 107 is the penultimate layer of the interconnection structure, formed directly below the upper layer 110 with which it cooperates directly from a functional point of view, and is designated by the acronym HBV (for "Hybrid Bonding Vias") in the context of the present description. The function of these three interconnection layers, i.e., MX, HBM and HBV metallization levels is detailed in the following.

[0079] In the example shown in [Fig.1A], the first interconnection layer 104 of the interconnection structure, i.e., the one closest to the substrate 101, corresponds to a horizontal metallization level MX. In the example shown, this metallization level MX comprises a conductive track 105 made in a trench, i.e., a through-hole formed in the dielectric material, which here extends in the longitudinal direction X. If necessary, this conductive track 105 can be electrically connected to one or more active components made in the active area of ​​the substrate 101 of the device 100. More generally, the horizontal metallizations formed in the metallization level MX of the first layer 104 have the function of connecting together elements of the active components made in the active area of ​​the substrate 101. For this purpose, they are coupled to them by vias (not shown).These vias pass through the insulating layer 102 which is directly below the layer 104 as well as the passivation layer 103 which separates the two layers of dielectric material 102 and 104.

[0080] The last layer 110 of the interconnection structure shown in [Fig. 1A], which corresponds to the HBM metallization level, comprises metal bonding pads whose function is to ensure the connection by hybrid bonding of the wafer 100 with another wafer 200. More specifically, it comprises bonding pads of a first type 111a, as well as bonding pads of a second type 111b. All these pads are used for the connection of the microelectronic device corresponding to the wafer 100 by hybrid bonding with another microelectronic device corresponding to the wafer 200. Structurally, these two types of pads are identical, and they are made of the same metal, namely copper in the example, and in the same way by implementing the Damascene process. The difference between these two types of pads is only functional.

[0081] Indeed, on the one hand, the bonding pads 11 la of the first type serve only, i.e., exclusively as a bonding support for the hybrid bonding of the wafer 100 on the other wafer 200, as shown in [Fig.lB], in cooperation with corresponding bonding pads 21 la of said other wafer 200. As a result, the bonding pads 11 la of the first type will also be called "bonding pads only" in the following, or even "non-functional pads" because they play no role in the func- operational operation of the integrated circuit.

[0082] On the other hand, the connecting pads 111b of the second type not only serve for bonding the two plates 100 and 200 together, like the bonding pads 111a only, but they also serve for electrical connection between said wafers, in cooperation with corresponding pads 211b of the other wafer 200. In the following, the connecting pads 111b of the second type are called "bonding and electrical connection pads", or "functional pads" because they play a role in the operational functioning of the integrated circuit by ensuring the passage of electrical signals from one wafer to the other.

[0083] Finally, the penultimate layer 107 of the interconnection structure of [Fig.lA], i.e. the interconnection layer directly below the upper interconnection layer 110, which corresponds to the HBV metallization level, comprises vias 108. These vias 108 are vertical metallization elements adapted to provide electrical coupling between a functional bonding pad of the HBM metallization level in the upper interconnection layer 110, on the one hand, and a metallization element of the MX metallization level in the lower interconnection layer 104, on the other hand.

[0084] In the example shown in [Fig. 1C], such vias 108 are made in electrical continuity with the bonding and electrical connection pads 111b of the wafer 100 of the HBM metallization level formed directly above the HBV metallization level, and also in electrical continuity with the conductive track 105 in the MX metallization level below the HBV metallization level. The vias 108 have the function of electrically connecting the metallization elements to which they are respectively coupled, that is to say with which they are in electrical continuity. Where appropriate, such vias 108 can ensure the electrical continuity of connection pads of the second type 111b directly with metallization elements distributed in metallization layers even lower than the layer 104 of [Fig.lA] in the stack of the n interconnection layers, and even directly with active elements made in the active zone of the substrate 101. These vias 108 can pass through one (or more) intermediate layer(s) of dielectric material based on silicon dioxide (SiO2) before reaching a horizontal metallization in an interconnection layer corresponding to a horizontal metallization level located lower in the stack, or an active element of the active zone of the substrate 101.

[0085] The person skilled in the art will indeed appreciate that several horizontal metallization levels such as the MX metallization level can be formed in respective interconnection layers which are produced in a stack before forming the penultimate layer 107 and the last layer 110 of the interconnection structure, which correspond to the HBV and HBM levels, respectively. Where appropriate, the horizontal metallizations formed in these respective interconnection layers may be connected to each other by vertical metallizations, i.e., by vias which are made in dedicated interconnection layers corresponding to respective vertical metallization levels, interposed between the corresponding horizontal interconnection layers.

[0086] [Fig.lB] symbolically illustrates the hybrid bonding of the wafer 100 of [Fig.lA] on the other wafer 200. This may be a hybrid bonding at the plate level, i.e. a W2W type bonding, but it may also be a hybrid bonding of the D2W type or even a hybrid bonding of the D2D type. [Fig.lC] illustrates the 3D microstructure obtained by this vertical assembly. As symbolically represented by an arrow, the upper plate 100 is turned vertically, and is wedged in the horizontal plane XY (that is to say it is aligned both in the longitudinal direction X and in the transverse direction Y) relative to the lower plate 200. This result is obtained by referencing its connecting pads 111a of the first type as well as its connecting pads of the second type 111b, with the corresponding connecting pads of the lower plate 200.This operation is carried out according to methods, and by the implementation of equipment which are known to the person skilled in the art, and the detailed description of which would go beyond the scope of the present description. The bonding of the upper wafer 100 to the lower wafer 200, as shown in [Fig.lB], is obtained by the effect of the Van der Waals forces, the covalent bonds and the hydrogen bonds implemented during contact, due to the particularly smooth and flat surface state of the respective upper faces of the wafers 100 and 200.

[0087] [Fig.lD] is a top view of a 3D microstructure obtained by a vertical integration method according to the existing art which has been presented above. This microstructure may correspond to the microstructure represented in [Fig.lC], or to any structurally comparable microstructure. With reference to [Fig.lD], we can distinguish: • metal lines 205 which are produced in the metallization level MX of the interconnection structure of the lower wafer 200; • a metal line 105, here shown in slight transparency in order to reveal what is below, and which is produced in the MX metallization level of the interconnection structure of the upper plate 100; • the connecting pads 11 la and 111b of the upper plate 100, which comprise bonding pads only or pads of the first type 111a, as well as bonding and electrical connection pads or pads of the second type 111b (which are surrounded by dotted circles in the figure, in order to distinguish them better). These connecting pads 11 la and 111b coincide spa initially, in the horizontal plane XY, with the corresponding connecting pads of the lower plate 200 in the top view of [Fig.lD], assuming a perfect horizontal alignment between the two plates 100 and 200. In other words, the connecting pads 111a and 111b of the upper plate 100 are perfectly aligned in the X direction as in the Y direction with the corresponding connecting pads 211a and 221b (see [Fig.lC]) of the lower plate 200. Consequently, they mask the latter in an observation direction following the vertical direction Z, from above downwards. The connecting pads 211a and 221b (see [Fig.lC]) of the lower plate 200 are therefore not visible in [Fig.lD]; • the vias 108 which are made in the HBV metallization level of the interconnection structure of the upper wafer 100, and which are represented by small squares in the bonding and connection pads 111b. Here too, and still assuming perfect horizontal alignment between the two plates 100 and 200, the vias 108 of the upper plate 100 mask the corresponding vias 208 of the lower plate 200. In the example shown, there are four vias of square section to connect a pair of connection pads 108 and 208, in order to allow the passage of a current four times greater than with a single via of identical section. The number and shape of the section of the vias may vary from one application to another. For example, vias of rectangular, circular or elliptical section may be preferred.A number of vias less than four, for example a single via of relatively larger section, can also be provided instead of the four vias of relatively smaller section which are shown in the example of [Fig.lD].

[0088] In [Fig. 1D], the bonding pitch defined as the spacing, i.e. the center-to-center distance between two adjacent bonding pads (whether of the first type 111a or of the second type 111b), both in the X direction and in the Y direction, is denoted by the letter “P”. As can be seen in the figure which represents an embodiment in accordance with the prior art, but as is also the case for an embodiment implementing the invention, the bonding pads 111a and 111a are present with a relatively high density, which results in a bonding pitch P which is less than a determined threshold. This threshold is equal to or less than 10 micrometers (pm), for example of the order of approximately 5 pm. In addition, their distribution on the surface of the wafer 100 is substantially uniform, for the reasons already mentioned above.These constraints are usually specified in the applicable DRM, to which the designer of the electronic circuit concerned can refer.

[0089] An example of implementation of the method for producing a 3D micro structure by vertical integration of two separate wafers 1 and 2 in accordance with the invention, will now be explained with reference to the step diagram of [Fig.4]. The implementation of the method makes it possible to produce the example of 3D microstructure shown in [Fig.2], comprising the upper wafer 1 turned over and bonded to the lower wafer 2. In this description, reference will also be made to the sectional views of [Fig.3A] to [Fig.31]. These latter figures show one of the wafers being produced, in this case the upper wafer 1, at the end of the implementation of determined steps or groups of steps of the method for said wafer 1 individually, before the hybrid bonding of the two wafers 1 and 2.It will be noted that, in the very simplified example considered here, the production of the lower plate 2 of the 3D microstructure is identical or comparable to that of the upper plate 1, which will therefore be the only one described here so as not to unnecessarily burden the present description. Furthermore, and still for the sake of simplification, the respective metallization structures of the upper plate 1 and the lower plate 2 shown are structurally identical to each other. This is, however, only a non-limiting example.

[0090] [Fig.2] shows the 3D microstructure resulting from the hybrid bonding of the wafer 1 provided with an original interconnection structure obtained by implementing the method according to the second aspect of the invention, on another wafer 2 (or lower wafer) having an interconnection structure obtained in a similar manner.

[0091] The 3D microstructure of [Fig.2] contains a first microelectronic device produced on an upper wafer 1, as well as a second microelectronic device produced on a lower wafer 2 on which the upper wafer 1 is bonded by hybrid bonding after vertical turning. The lower wafer 2 and the upper wafer 1 each comprise a substantially planar substrate, respectively 11 and 21, as well as an interconnection structure formed above said substrate.

[0092] The respective interconnection structure of each of the upper 1 and lower 2 plates is a vertical stack of at least two superimposed interconnection levels and each comprising a hybrid layer essentially composed of a dielectric material, namely, respectively: • a higher interconnection level (HBM), with metal bonding pads 17b and 17c, formed in the dielectric material and adapted to cooperate with corresponding metal bonding pads 27b and 27c, respectively of the other wafer 2 for the hybrid bonding of the upper wafer 1 on the lower wafer 2; and, • a horizontal interconnection level (MX) which is directly below the upper interconnection level HBM, with metal- horizontal alignments 15 and 25.

[0093] By the adverb "essentially" used above in reference to the composition of the hybrid layer of each of the HBM and MX levels, it is to be understood that one and / or the other of these levels may further comprise, and for example, a passivation layer intended to passivate the dielectric material which is part of the composition of said level. Furthermore, by the expression "directly below" used above in relation to the horizontal interconnection level MX, it is to be understood that there is no other interconnection level between the HBM level and said MX level, and therefore no vertical interconnection level. In other words, the person skilled in the art will appreciate that this means that the first metallization level (here, the MX level) which comes below the HBM hybrid bonding level in the stack of interconnection levels, is a horizontal metallization level and not a vertical metallization level.But this does not prevent the horizontal interconnection level MX from comprising, on top of said level and therefore below the metallization level HBM, a passivation layer, for example a layer of Silicon Nitride (SiN) as will be explained later. In other words, this does not imply that all the dielectric portions and / or all the metallic portions of the HBM level are directly in contact with dielectric portions and / or metallic portions of the MX level.

[0094] The metal bonding pads 17b, 17c and 27b, 27c of each of the upper 1 and lower 2 plates, respectively, are distributed in a substantially homogeneous manner on the upper surface of the upper interconnection level HBM of the interconnection structure of said plate. Also, they are produced with a bonding pitch, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, which is less than a determined associated threshold. This threshold may be less than or equal to 10 μm, which provides a high interconnection density between the two plates 1 and 2 via the bonding pads. Preferably, it may be of the order of 5 μm, for example.

[0095] The respective metal bonding pads 17b, 17c and 27b, 27c of each of the upper 1 and lower 2 wafers comprise bonding pads respectively 17b and 27b of a first type, which are electrically isolated from any horizontal metallization element such as the metallizations 15 and 25, respectively, of the horizontal interconnection level MX of the interconnection structure of said wafer. Furthermore, the respective metal bonding pads 17b, 17c and 27b, 27c of each of the upper 1 and lower 2 wafers further comprise bonding pads respectively 17c and 27c of a second type, which are each electrically coupled to at least one underlying horizontal metallization element, formed in the horizontal metallization level MX of the interconnection structure of said wafer.

[0096] In other words, the interconnection structure of each of the upper 1 and lower 2 plates of the microstructure of [Fig. 2] does not include a vertical metallization level directly below the HBM level, unlike the 3D microstructure of [Fig. 1D] according to the prior art which has already been described in the above, and which had such a vertical metallization level, namely the HBV level. Instead, the bonding pads of the second type 17c or 27c, respectively, of the HBM metallization level of the interconnection structure of each of the plates 1 and 2, ensure the electrical connection of said plate with the other plate. This eliminates one metallization level in each of the plates 1 and 2, therefore two metallization levels for the 3D microstructure formed of these two stacked plates. For each of these levels, a layer of insulating material (e.g.in SiO2) and its associated passivation layer (e.g. in SiN). This reduces the stress level of the 3D microstructure, as this depends on the number of layers of the wafer interconnection structures. Of course, this also reduces the costs and thermal, water, etc. budgets for the production of the individual 2D semiconductor devices, which are each produced on one of the wafers 1 and 2.

[0097] In embodiments, the horizontal interconnection level MX of the interconnection structure of each of the lower 1 and upper 2 wafers comprises a passivation film 16 or 26, respectively, made of electrically insulating material, and which covers the layer of dielectric material of said horizontal metallization level MX. The bonding pads of the first type 17b and 27b of each of the upper 1 and lower 2 wafers, respectively, are then electrically insulated from any horizontal metallization element of the horizontal interconnection level MX located below in the interconnection structure of said wafer, at least by the insulating material of this passivation film 16 or 26 covering the layer of dielectric material of said horizontal metallization level MX.

[0098] In embodiments, the layer 17 or 27 of dielectric material of the upper interconnection level HBM of the interconnection structure of each of the wafers 1 and 2, respectively, is a hybrid layer of patterned dielectric material, said patterns defining: • solid areas 17a or 27a of said dielectric material, i.e. areas of layer 17 or 27 which have not been etched; • first vertically extending through holes 17b or 27b, filled with metallic material and at the level of which the insulating material of the passivation layer of the horizontal interconnection level MX is present. These first through holes, once filled with metal, form the bonding pads of the first type (also designated by the references 17b and 27b in the following) of the upper interconnection level HBM of the wafer; and, • second vertically extending through holes 17c or 27c, filled with metallic material, and at which the passivation layer 16 or 26 of the horizontal interconnection level MX has an opening because the Silicon Nitride (SiN) of said passivation layer 16 or 26, respectively, has been removed there by etching. These second through holes, once filled with metal, form the bonding pads of the second type (also designated by the references 17c and 27c in the following) of the upper interconnection level HBM of the wafer. They are each in electrical continuity with one of the horizontal metallization elements 15 or 25 of the horizontal interconnection level MX of the wafer 1 or 2, respectively, through the opening in the passivation layer 16 or 26, respectively, of said horizontal interconnection level MX.

[0099] As the person skilled in the art will have understood, it is therefore the passivation layer 16 of the metallization level MX which, depending on the openings made or not in said layer, and more specifically at the level of the holes 17c and 17b made in the layer 17 corresponding to the upper metallization level HBM to receive the metal of the functional bonding pads 17c or of the non-functional bonding pads 17b, respectively, which makes it possible to differentiate the function of said functional bonding pads 17c from that of the non-functional bonding pads 17b. Indeed, the Silicon Nitride (SiN) of the passivation layer, when it is still present, prevents electrical continuity between the relevant bonding pad of the metallization level HBM and any metallization element in the horizontal metallization level MX directly below said HBM level.

[0100] In embodiments, the dielectric material of the hybrid interconnection layers of the interconnection structure of each of the upper 1 and lower 2 wafers is Silicon Dioxide (SiO2). The material constituting the metallic bonding pads 17b, 17c and 27b, 27c of the upper interconnection level HBM and / or the material constituting the horizontal metallizations 15 and 25 of the horizontal interconnection level MX of the interconnection structure of the wafers 1 and 2, respectively, may be copper (Cu) or a copper-based alloy. Finally, the electrically insulating material of the passivation film 16 or 26 of the horizontal interconnection level (MX) of the interconnection structure of each of the wafers 1 and 2 may be a nitride, such as silicon nitride (SiN) or another dielectric, for example a carbon derivative of a nitride such as silicon carbonitride (SiCN).

[0101] Thus, after the vertical turning and bonding of the wafer 1 on the wafer 2 allowing the formation of the microstructure shown in [Fig.2], the bonding interface 60 is a hybrid interface. Indeed, it comprises: • a SiO2 / SiO2 interface at the level of zones 17a and 27a opposite; and, • a Cu / Cu interface at the level of the non-functional bonding pads 17b and 27b opposite, as well as at the level of the functional bonding pads 17c and 27c opposite.

[0102] The substrate 11 of the upper wafer 1 and / or the substrate 21 of the lower wafer 2 may each comprise an active zone with active elements, in the upper part of said substrate. In this case: • the non-functional bonding pads 17b and 27b of the interconnection structure of each of the plates 1 and 2 are electrically isolated from the active elements of the active zone of the substrate 11 or 21, respectively, of said plate; whereas, • at least some of the functional bonding pads 17c and 27c of the interconnection structure of the upper wafer 1 and / or of the lower wafer 2 are electrically coupled to at least one of the active elements of the active zone of the substrate 11 or 21, respectively, of said wafer.

[0103] Methods of implementing a method for producing the 3D microstructure of [Fig. 2] which has been presented in the above will now be described. This method comprises fifteen essential technological steps, which will be referred to in the following by the numbers 1 to 15. The grouping of some of these steps in some of the blocks of steps of the step diagram of [Fig. 4] is intended solely to simplify the description which follows. In particular, the figures representing the microstructure being produced are limited to the representation of the wafer at the end of each of the groups of steps considered, when a representation separately at the end of each step of the group would not add anything more to the clarity of the description.

[0104] As indicated in the introduction, the method is essentially implemented during the BEOL phase of the manufacture of each wafer individually, which are then assembled vertically to each other by hybrid bonding. More precisely, the method proposes an alternative to the production of the penultimate layer and the last layer of the interconnection structure which correspond to the HBV metallization level (vertical interconnection) and to the HBM metallization level, respectively, of a wafer according to the prior art, and which were presented above with reference to [Fig. 1A]. These two layers are replaced, in accordance with the invention, by a single bonding layer ensuring on its own the respective functions of the respective HBV and HBM metallization levels of two wafers assembled vertically according to the prior art.It is recalled that, in the interconnection structures according to the existing art, the last layer (HBM metallization level) is the one in which the connection pads are made (non-functional pads and pads). functional) for hybrid bonding, while the penultimate layer (vertical metallization level HBV) is the one in which the vias are made which vertically interconnect the functional bonding pads (and only these, i.e., not the non-functional bonding pads) with horizontal metallizations made in one or more metallization levels lower in the interconnection structure, and / or with active elements made in the active area of ​​the underlying substrate.

[0105] At the end of the FEOL phase of the manufacture of the wafer 1, which is followed by the BEOL phase, said wafer is as shown in [Fig.3A]. The wafer 1 comprises a substrate 11 which is coated with a layer of insulating material 12, itself covered with a passivation layer 13.

[0106] The substrate 11 is for example a bulk silicon substrate (“Si bulk”). In its upper part, located under the insulating layer 12, the substrate 11 comprises active components, not shown, such as transistors or photodiodes. These elements were produced, for example in CMOS technology, during the FEOL phase of the manufacture of the wafer 1. The low resistivity of a bulk silicon substrate is advantageous for reasons of locking (“latch-up” in English) of such MOS transistors. In one example, the substrate 11 is a DSP type substrate (from the English “Double Side Polished”), which has the advantage of being directly usable due to the surface state of its upper and lower faces, which are extremely polished.

[0107] The electrically insulating (dielectric) material of the insulating layer 12 may be silicon dioxide (SiO2), for example. Thin layers of silicon dioxide grow spontaneously on the silicon wafers, by thermal oxidation, giving a very thin layer of about 1 nm of native oxide. The layer 12 may therefore be obtained by growing a layer of silicon dioxide from this thin layer of native oxide, for example by heating the wafer to temperatures between 600 and 1200 °C, in the presence of oxygen (dry oxidation) or water (wet oxidation), according to one or other of the following chemical reactions, respectively: • Si + 02 -> SiO2; or, • Si + 2 H2O -> SiO2 + 2 H2, Wet oxidation has a faster growth rate, but the resulting SiO2 layer is less dense than a layer obtained by dry oxidation.

[0108] The passivation layer 13 is for example a layer of silicon nitride (SiN). Its function is to stabilize the state of the insulating layer 102 after the production of said layer, and to prevent contamination of the active zone of the substrate, in particular by diffusion of copper or water. The layer 13 of silicon nitride can be deposited by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), followed by chemical treatment with phosphoric acid (H3PO4). The production of the passivation layer 13 completes the FEOL phase of the manufacturing process. The following manufacturing steps belong to the BEOL phase of the said manufacturing process.

[0109] The BEOL phase of the manufacturing begins with the production of the first metallization level of the interconnection structure which is produced on the front face (upper face) of the wafer 1. With reference to [Fig.3B], in the very simplified example which is represented in this figure, the interconnection structure comprises only a single metallization level MX dedicated to the formation of horizontal metallizations in a layer 14 of dielectric material. The reference 15 designates such a horizontal metallization, which is for example a conductive track extending in the horizontal plane XY, here in the longitudinal direction X, for example to electrically connect together active elements (not shown) produced in the active layer of the underlying substrate 11.

[0110] Of course, the invention is not intended to be limited by the number of metallization levels formed by respective interconnection layers stacked to contain horizontal metallizations such as the metal track 15, nor by the number or configuration of such tracks, nor of course by their function in the electronic circuit concerned. These may in particular be conductive tracks for electrical connection between various active elements but also passive elements such as inductors, capacitors, etc. produced in the form of copper patterns extending in one or more corresponding metallization levels of the interconnection structure. Where appropriate, horizontal metallizations produced in respective horizontal metallization levels may be electrically connected together by vertical metallizations, i.e., vias.These vias are made in vertical metallization levels interspersed between the corresponding horizontal metallization levels.

[0111] The metallizations in the metallization level MX have an average dimension in the horizontal plane XY which is between a few tens of nanometers and a few tens of microns, for example between 20nm and 20pm, preferably between 200nm and 10pm, and more preferably between 800nm ​​and 5pm, for example of the order of 1pm or 2pm.

[0112] The method according to the invention comprises steps for carrying out the connection of the wafer 1, as an upper wafer for example, with another wafer 2 which is then a lower wafer in this example, after vertical turning and hybrid bonding of said upper wafer 1 on said lower wafer 2. By this connection, the upper and lower wafers are mechanically linked by the effect of Van der Waals forces and are at the same time electrically connected to each other, by non-functional bonding pads (bonding pads only) and by functional bonding pads (bonding and electrical connection pads), respectively. According to embodiments of the invention, the bonding structure ensuring this dual function only comprises a single metallization level, denoted HBM (for "Hybrid Bonding Metal" in English), instead of both the horizontal metallization level HBM and the vertical metallization level HBV provided in the embodiments according to the prior art which are illustrated by Figures 1A-1D described above, in which the HBV level comprises the vias which ensure the electrical connection of the functional bonding pads to horizontal metallizations formed in lower horizontal metallization layers.

[0113] In a first step (step 1), illustrated by block 41 of the diagram of [Fig. 4], a passivation layer 16 is formed over the layer 14 corresponding, where appropriate (i.e. when there are several vertically stacked metallization levels) to the highest horizontal metallization level MX, in which horizontal metallizations for interconnecting the active components and / or the passive components of the electronic circuit are produced. The result of step 1 is shown in [Fig. 3C].

[0114] The passivation layer 16 is for example a layer of silicon nitride (SiN) or silicon carbonitride (SiCN). It makes it possible to stabilize the state of the silicon dioxide (SiO2) of the metallization level MX, i.e., to significantly slow down its corrosion rate, i.e. its natural oxidation rate, and to prevent the formation of scratches on the surface of the copper conductive tracks. It also makes it possible to protect the metallizations such as the conductive track 15 against micro-scratches during handling of the wafer from one processing station to another in the clean room. A thin layer of silicon nitride 16 (of the order of 200 nm for example) can be formed by chemical vapor deposition (CVD) involving gas mixtures such as Si / NH4, SiC14 / NH3 or SiH2C12 / NH3, and chemical treatment with phosphoric acid (H3PO4).The CVD deposition may be low-pressure chemical vapor deposition (LPCVD) which operates at relatively high temperature (between 700 and 900°C, for example, of the order of 775°C). Alternatively, the silicon nitride passivation layer 16 may be formed by plasma-enhanced chemical vapor deposition (PECVD), which is operated at relatively moderate temperature (between 200 and 350°C, for example, of the order of 200°C) and in a vacuum. In one example, the silicon nitride layer 16 may have a thickness of approximately 50 nm.

[0115] With reference to [Fig.4], a group 42 of the following steps is then implemented, to arrive at the microstructure illustrated by [Fig.3D]. The steps of this group of steps 42 comprise steps 2, 3 and 4 of the method, which are implemented successively and in this order.

[0116] In step 2 of the process, the conformal deposition of a layer 17 of TEOS (tetraethylorthosilicate, abbreviated) is carried out on the upper face of the microstructure of [Fig.3C]. TEOS, whose real name is "tetraethyl orthosilicate" and whose chemical formula is Si(OCH2CH3)4 or more simply Si(OEt)4, is used as a precursor of silicon dioxide (SiO2).

[0117] In step 3 of the method, annealing is carried out, i.e. the microstructure coated with the conformal layer of TEOS is heated, for example to a temperature of approximately 400°C, to transform the layer 17 of TEOS into a layer of silicon dioxide (SiO2). In one example, the layer 17 of silicon oxide thus formed may have a thickness of approximately 900 nm. This layer 17 acts as an electrical insulator. It can in fact block the electric current from or to the metallizations made in the underlying layer 14 of the interconnection structure.

[0118] Those skilled in the art will appreciate that there are other ways of making the dielectric layer 17, but the layer obtained as proposed in the above (with steps 2 and 3 above) has the advantage of exhibiting high chemical stability.

[0119] In step 4, a photoresist mask 31 is formed in order to obtain a protective coating on the surface of the microstructure, with a view to carrying out a first photolithography operation 5 (denoted "HBM 1" in [Fig. 4] and hereinafter), to be carried out to produce the HBM metallization level with non-functional bonding pads 17b and functional bonding pads 17c for hybrid bonding. This HBM photolithography 1 aims to produce a mask by etching the silicon oxide layer 17 through the photoresist mask 31, which mask can then be used to open the silicon nitride layer 16 in order to expose the portions of the metallizations of the MX layer intended to be electrically connected to the functional bonding pads 17c.

[0120] More particularly, step 4 comprises: • spreading of the photoresist, for example by a spin coating process, the principle of which consists of spreading on the wafer using centrifugal forces a small quantity of resin mixed with a solvent which temporarily gives it a certain fluidity, and placed in the center of the wafer before it is rotated; then the development of the photoresist which includes • exposing said resin to optical radiation, for example radiation in the ultraviolet (UV) range, through an ad-hoc optical mask. Such a mask comprises opaque areas and trans- areas parents, which define the etching patterns, either positive or negative depending on the nature of the photoresist considered. It makes it possible to define the patterns that one wishes to reproduce on wafer 1, in layer 17 of SiO2, by etching through the layer of resin thus developed which forms an etching mask; and, • selective removal, for example by chemical means (“Chemical etching” in English) of the exposed resin portions, or on the contrary of the unexposed resin portions, depending on the nature (positive or negative) of the photoresist. The removal method implemented may be a chemical vapor phase removal, for example under oxygen plasma, which makes it possible to very cleanly clean any trace of organic materials such as photosensitive resins.

[0121] The optical mask used to reveal the photoresist of layer 31 in step 4 has patterns which correspond to the layout diagram of the bonding pads for hybrid bonding, including the non-functional bonding pads 17c as well as the functional pads 17b.In other words, the first HBM 1 lithography makes it possible to form, in the layer 17 of dielectric material, the boxes 17a in which all the metal bonding pads will then be made for the hybrid bonding of the wafer 1 to the other wafer 2, whether they are functional or non-functional, that is to say whether they are used for bonding only, or both for bonding and for the electrical connection, respectively, between the two wafers 1 and 2.

[0122] It does not appear necessary to detail further the above sub-steps of step 4 which make it possible to obtain the HBM 1 photolithography mask (also called HBM 1 mask for short), which are well known in themselves to the person skilled in the art.

[0123] At the end of the group of steps 42 comprising steps 2, 3 and 4 presented above, the photoresist mask 31 is as shown in [Fig.3D] already mentioned. In the configuration of [Fig.3D], the HBM mask 1 exposes the layer 17 only through its open areas 31a (or openings), and it masks the layer 17 outside said areas 31a.

[0124] In step 5, which is part of the group of steps 5 and 6 represented by block 43 of the flowchart of [Fig.4], the layer 17 of dielectric material (SiO2) is etched through the HBM mask 1, stopping on the layer 16 of silicon nitride.

[0125] This may be chemical etching (or wet etching) using a hydrofluoric acid (HF) solution, for example, or physical etching (or dry etching), i.e. plasma etching. The etching may also be reactive ion etching (or RIE), which is a variation of plasma etching combining the selectivity of chemical etchings and the anisotropy of physical etchings. In embodiments, the plasma can then be a fluorocarbon plasma, based on a gas such as carbon tetrafluoride (CF4) for example, or based on sulfur hexafluoride (SF6) or even based on nitrogen trifluoride (NF3), or any combination of these gases. The layer 17 of insulating material, partially protected by the HBM etching mask 1 formed by the layer 31 of partially open silicon dioxide as explained above, is placed in a chamber in which a vacuum is created. This chamber is provided with two horizontal and parallel electrodes, the lower electrode serving as a tray to receive the wafer 1. Once the vacuum in the chamber has been created, the gas is introduced therein. Then a strong radiofrequency (RF) electric field, for example of a hundred volts per meter or more, is applied to the lower electrode.This generates a plasma in the chamber, i.e. a partially ionized gas. In fact, certain electrons from the gas molecules are torn off by the electric field, which ionizes the molecules. The upper surface of the wafer is then bombarded by ions which disintegrates it.

[0126] The advantage of such an etching is that it is highly anisotropic, the ion bombardment being carried out only in the direction between the electrodes, i.e., the direction normal to the plane of the wafer 1. The boundary between the etched areas and the non-etched areas is therefore quite rectilinear and vertical. But this etching is not very selective, i.e. it destroys the material of the HBM mask 1 formed by the layer 31 at the same time as the areas of the underlying protective layer 17 which are exposed by the openings 31a through said mask. The etching is completed when the Silicon Nitride (SiN) of the layer 16 is reached at the openings 31a of the HBM mask 1.

[0127] In step 6, the resin residues from the HBM mask 1 are removed (“stripping” in English). This can be done by chemical etching, for example with a solution based on sulfuric acid (H2SO4) and hydrogen peroxide or oxygenated water (H2O2).

[0128] It will be noted that even if the etching step 5 leaves the surface of the HBM mask 1 relatively damaged, this is not a real disadvantage since, in step 6 which follows the completion of the etching, the residues of the HBM etching mask 1 are removed. To limit the risk of destruction of the mask before the end of the etching, the ion bombardment of step 5 can be temporarily interrupted during etching, to anneal the wafer in order to reharden the HBM mask 1 by reforming the crystal lattice of the layer 31, before resuming the etching by ion bombardment. This process can possibly be repeated several times in a row, until the completion of the etching, i.e., until reaching the Silicon Nitride layer 16.

[0129] At the end of the group of steps 43 comprising steps 5 and 6 presented above, the microstructure is as shown in [Fig.3E].

[0130] In step 7, which constitutes the only step of block 44 of the step diagram of [Fig.4], a new layer of photoresist 32 is spread to form an etching mask, with a view to carrying out a second lithography denoted "HBM 2". With reference to [Fig.3F], the layer of photoresist 32 is deposited in a conformal manner on the front face of the wafer, for example by spin coating (see above, regarding the layer of photoresist 31 to form the etching mask HBM 1). As can be seen in this figure, the layer 32 matches the relief which results from the openings 17a formed in the layer of dielectric material 17 by the first HBM lithography 1. In other words, said layer 17 has a thickness such that the free face of this layer conformably follows the hollows and / or the projections of the microstructure on which it is deposited.

[0131] The photoresist of layer 32 is then developed in step 7a to form a new etching mask, which is then used to perform a second lithography, called "HBM 2". This HBM 2 lithography is then performed in step 8 to etch the layer 15 of Silicon Nitride. In the following and in the figures of the drawings, this mask is called "HBM 2 mask" for short.

[0132] In the step diagram of [Fig.4], steps 7a and 8 are grouped in step block 45, because the overall result obtained after executing these two steps is shown in [Fig.3G].

[0133] As shown in this figure, the optical mask used to reveal the photoresist of the layer 32 in step 7a has patterns that correspond to the layout diagram of the functional bonding pads 17c. In other words, the optical mask used to reveal the photoresist of the layer 32 in step 7a has patterns that correspond to the interconnection patterns defined by the layout diagram of the functional bonding pads 17c which are intended for the electrical connection of the wafer 1 with the other wafer 2, by the hybrid bonding of said wafers 1 and 2. In other words, the second HBM lithography 2 makes it possible to open the bottom of certain wells 17c among the wells 17a having been formed in the layer 17 in dielectric material by the first HBM lithography 1.

[0134] This result is obtained in step 8 by partially etching the Silicon Nitride layer 16 at the bottom of said wells 17c only, through the HBM etching mask 2. By this partial opening of the layer 16 in the etching step 8, the metal of some of the horizontal metallizations of the MX metallization level in the dielectric layer 14 is exposed at the bottom of the wells 17c, such as the conductive track 15 in the example shown in [Fig.3G]. As will be understood, these are the metallizations which, according to the routing plan of the 3D microelectronic device, need to be taken up at the bonding interface between the plates 1 and 2. The functional connection pads 17c can then be formed by filling the boxes 17c with metal, with coupling, that is to say with electrical continuity up to horizontal metallizations of the metallization level MX, in order to ensure the desired electrical connection between the two plates 1 and 2. Of course, in addition to ensuring this electrical connection, the functional pads 17c thus produced can serve as a support for the hybrid bonding of said plates.

[0135] The other wells 17b among the wells 17a formed by the first HBM 1 lithography, i.e., the wells other than the aforementioned wells 17c, are not opened up to the metal of the hybrid layer 14 by the execution of the etching 8 corresponding to the second HBM 2 lithography. The Silicon Nitride layer 16 is left intact there, being protected by the HBM 2 etching mask. These other wells 17b are those in which the non-functional bonding pads will then be produced by metal deposition, without coupling, i.e. without electrical continuity with the metal of the horizontal metallizations of the MX metallization level.The electrical insulation between the non-functional bonding pads 17b and any horizontal metallization of the MX metallization level in the hybrid layer 14 is ensured by the Silicon Nitride layer 16 (insulating material) which remains intact at the bottom of the wells 17b at the end of the etching carried out in step 8 through the HBM etching mask 2.

[0136] The etching of the Silicon Nitride of the layer 16 carried out in step 8 through the HBM etching mask 2 can, like the etching of the first lithography, be a reactive ion etching (RIE), with a fluoro-carbon plasma, for example based on a gas such as carbon tetrafluoride (CF4) and / or sulfur hexafluoride (SF6) and / or nitrogen trifluoride (NF3).

[0137] In step 9, the material from the HBM2 photolithography mask is removed. As with the removal of the resin residues from the HBM 1 etching mask in step 6, this removal can be obtained by chemical etching with a solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). At the end of this removal, which is shown by block 46 in the step diagram of [Fig. 4], the microstructure illustrated by [Fig. 3H] is obtained.

[0138] It is then appropriate to proceed with the conformal deposition of a layer of copper in order to fill the wells 17c to form the functional pads 17c, as well as the wells 17c to form the non-functional pads 17b. Advantageously, a single deposition step ensures the simultaneous formation of all the bonding pads, namely the non-functional bonding pads 17b and the functional bonding pads 17c. This deposition can be obtained, for example, by an electrochemical deposition (ECD) process. This is the subject of steps 10, 11, 12 and 13 which will now be presented. These steps are part of the group of steps represented by block 47 in the step diagram of [Fig.4].

[0139] In this example, the filling with copper of the boxes 17c and 17b to produce the functional bonding pads 17c and the non-functional bonding pads 17b, respectively, is carried out in two stages.This two-step implementation method makes it possible to overcome the problems of uniformity of the copper deposition, which result in particular from the differences in the respective resistivities of the materials present on the surface to be covered: the resistivity of the layer 17 in Silicon Dioxide (SiO2) is generally between 1012 and 1016 ohms centimeter (Q cm) and the resistivity of the layer 16 in Silicon Nitride (SiN) which is exposed in the bottom of the boxes 17b is of the order of 1016 Q cm, while the resistivity of the horizontal metallizations of the MX metallization level which are exposed in the bottom of the boxes 17c is 17x10 7 Q cm, or 1.7 pQ cm. In a first step, a copper film is deposited, namely a thin layer of copper suitable for covering the entire interior of the boxes 17c and 17b. to fill, and to serve as a copper undercoat.This thin layer then acts as a bonding layer, also known as a germination film (called a “seed layer” in English), for the growth of a thicker layer of solid copper, for example by ECD.

[0140] For electrochemical deposition, the wafer is immersed in an electrolytic solution comprising copper precursor ions, the wafer 1 (and therefore in particular the copper bonding layer) being configured as a cathode, i.e., at the negative terminal. Alternatively or additionally, the copper is deposited on the bonding layer from a copper source configured as an anode, i.e., at the positive terminal, when an electric current is circulated between said positive and negative terminals. In all cases, the electrochemical deposition reaction being a reaction driven by an electric current, it is very sensitive to the ohmic drop at the surface to be coated.To avoid any risk of voids forming in the patterns formed by the boxes 17b and 17c during their electrochemical filling, it is therefore ideal to have previously formed a perfectly conformal bonding layer, i.e. of the most constant thickness possible while matching all of the hollows and / or projections that exist on the surface of the microstructure. This promotes the filling of the bottom of the boxes 17b and 17c, and prevents said boxes from closing prematurely by creating a cavity within them. It would be beyond the scope of this description to set out the technological steps for achieving this result. The person skilled in the art, on the basis of his general knowledge, will be able to refer as necessary to the corresponding technical literature, concerning in particular but not only the so-called "super-conformal" deposition techniques ("super-fill" in English), for example.

[0141] In practice and with reference to the step diagram of [Fig.4], in step 10 we first deposits a very thin copper sub-layer on the microstructure by physical vapor deposition (PVD) at low and medium temperatures, or by chemical vapor deposition (CVD) at medium and high temperatures, to form the copper seed layer.

[0142] This chemical deposition is obtained in the presence of a solution containing a precursor ("seed" in English) of the metal to be deposited. The precursor of a metal mainly comprises ions of this metal. Rather than a monolithic coating, it may be advantageous to produce the bonding layer as a film in an alloy combining different materials each providing their respective advantages (adhesion, melting point, density, coefficient of thermal expansion, electrical resistivity, etc.). The behavior of the precursors during deposition (volatility, vapor pressure, stability, etc.) is also a criterion for selecting the precursor ion(s). In summary, the ionic compounds of the group of materials considered to form the seed film are selected by taking into account thermodynamic, mechanical and physical criteria.In the application concerned by the invention, namely the filling with copper of the bonding patterns in the HBM metallization level of the wafers to be assembled by hybrid bonding, a Ti-TiN-Cu system proves to be a good candidate for the deposition of copper in the vapor phase, physical or chemical. The corresponding solution mainly comprises copper ions, as well as titanium ions and titanium nitride ions.

[0143] As a variant of a PVD or CVD process, the bonding layer can be formed by reduction of a solution of ionic precursors of copper and, where appropriate, of other metals selected to compose a copper alloy. In order to promote conformal deposition, it may in fact be chosen to proceed with the formation of an oxide and in particular of a copper oxide only, which is more thermodynamically favorable than the formation of metallic copper, then to reduce this oxide, for example, during annealing in a reducing atmosphere.

[0144] In all embodiments, the thickness of the copper seed layer that is deposited is a few tens of nanometers. As explained above, this bonding layer has the function of initiating the electrolytic growth of the copper during the implementation of an electrolytic deposition (ECD) process of the copper. In exemplary implementations, the thickness of the bonding layer may be approximately 90 nm.

[0145] In step 11, the actual deposition of the solid copper layer is carried out, for example by ECD. This is achieved, for example, by immersing the wafer in the electrolyte and applying a voltage between the wafer configured as a cathode and an anode, for example a copper source configured as an anode. The patterns cor corresponding to boxes 17b and 17c already covered with the germination film are then filled with copper electrochemically.

[0146] To ensure that the patterns are filled properly, several additives can be added to the electrolyte: a suppressor, an accelerator and a leveler. These additives, detailed below, combine their effects to slow down deposition at the top of the trench and accelerate it at the bottom of the trench: • suppressors are macromolecules, such as polyethylene glycol (PEG), which tend to remain on the surface of the microstructure without diffusing into the trenches, which react with chlorides added in solution, to form a film protecting the surface and limiting the reduction of the metal at this location; • Accelerators inhibit the effect of suppressors, while tending to settle in the trenches. They therefore allow the growth of copper in the trenches. Accelerators are often sulfur molecules, of which SPS (HSO3(CH2)3S) is a non-limiting example; and, • levelers, such as the JGB (Janus Green B) molecule, have the same type of action as suppressors, but tend to be placed in areas of high current density (peaks, protuberances, etc.). They therefore limit deposition in the high points of the microstructure.

[0147] To complete the deposition of copper by the ECD process, a high-temperature stabilization annealing can be carried out in step 12 to cause melting at the deposition interface. This results in less abrupt, and therefore less fragile, interfaces. This annealing also stabilizes the Cu layer. For example, annealing at 400°C allows the microstructure to reach thermodynamic equilibrium.

[0148] The person skilled in the art will appreciate that, instead of electroplating (ECD), another metal deposition process, i.e., a different process for the deposition of solid copper, may also be used. As an alternative to the ECD process described above, one may, for example, choose a technique from among autocatalytic transformation, precipitation, crystallization, crosslinking, aggregation, or the like.

[0149] In the foregoing, embodiments have been proposed in which the filling metal of the wells 17b and 17c to simultaneously form the bonding pads 17b and 17c, respectively, is copper. The invention is however not limited to this example. Another metal may be deposited in the wells to form the bonding pads, for example gold (Au), which may also be deposited by electrodeposition (ECD) from a chemical precursor comprising corresponding metal ions, or titanium (Ti), aluminum (Al), niobium (Nb), or platinum (Pt), which may then preferably be deposited by a PVD-type process. This list of examples of metals is not limiting. Where appropriate, a bonding layer (seed film) suitable for the growth of this metal is then formed in step 10.

[0150] In step 13, the excess copper is removed from the upper surface of the HBM metallization level, for example by a chemical mechanical polishing (CMP) process. The CMP process a very fine level of nano-topography (less than 5 nm, for example) and guarantees a very low level of roughness (less than 0.5 nm, for example) for a hybrid bonding without defects. In other words, the implementation of step 13 results in a wafer 1 whose upper surface is ultra-polished. Step 13 completes the group of steps represented by block 47 in the step diagram of [Fig.4]. We then obtain the micro structure 1 shown in [Fig.31].

[0151] In step 14, the hybrid bonding of the upper wafer 1 to the lower wafer 2 is carried out after vertically turning it over. Of course, the lower wafer 2 has undergone the same treatments as the upper wafer 1, in parallel. It therefore has an interconnection structure with the same characteristics as the upper wafer 1. Its upper surface is also ultra-polished. The bonding is direct - without glue - and is carried out at room temperature. This avoids the risk of degradation and unwanted interaction of an adhesive during a subsequent temperature treatment, if necessary.

[0152] In step 15, a bonding annealing of the obtained 3D microstructure can be carried out, in order to reinforce the bonding interface 60 between the wafers 1 and 2, and to ensure the electrical connection between the functional bonding pads 17c and 27c of the wafers 1 and 2, respectively. For example, a bonding annealing can be carried out at 400°C for two hours. To evaluate the quality of the bonding, scanning acoustic microscopy (SAM) can be used to detect voids, if any.

[0153] In a manner known per se, the rear substrate 11 of the upper plate 1 is finally thinned, for example by a process carried out from the front of the 3D microstructure shown in [Fig.2], for example first mechanically and then chemically in order to reduce the risk of damage to the bonding interface 60.

[0154] In the step diagram of [Fig.4], steps 14 and 15 are grouped in block 48. The result obtained at the end of this group of steps 48 is the 3D microstructure of [Fig.2].

[0155] The table in [Fig. 5] lists the steps for producing the 3D microstructure according to implementations of the method according to the invention (right column) for producing the 3D microstructure of [Fig. 2] in which the upper interconnection level HBM of the interconnection structure of the wafer is directly above the horizontal interconnection level MX, comparing them with the steps of a method according to the prior art (left column) for producing the conventional 3D microstructure of [Fig. 1C], i.e. having a vertical interconnection level HBV with vertical metallizations (vias) between the upper HBM interconnect level and the horizontal MX interconnect level.

[0156] As the person skilled in the art can see, nine technological production steps are eliminated, which is a significant gain in terms of energy balance in particular, as well as in terms of processing time in the clean room.

[0157] Furthermore, by removing the HBV metallization level from the prior art 3D microstructures, two layers of dielectric material are removed (one in each of the upper and lower wafers stacked by hybrid bonding), in this case two layers of Silicon Dioxide (SiO2), which is an improvement in terms of mechanical constraints. Two layers of insulator are also removed, namely the Silicon Nitride (SiN) insulator layer covering the dielectric material layer of the HBV metallization level of the upper and lower wafers of the prior art 3D microstructures.

[0158] Particular embodiments have just been described. Different variants and modifications will appear to those skilled in the art. In particular, it goes without saying that the invention is not limited by the number of metallization levels provided in the interconnection structure, which may comprise several levels such as the MX metallization level considered here. Furthermore, the method of producing in accordance with the invention a 3D micro structure by vertical integration of more than two wafers. It is indeed possible to repeat the operations so as to continue the vertical integration with the bonding, each time, of a new wafer over the microstructure obtained in the previous iteration, by implementing the method of the invention.The only constraints in this regard are those which are, classically, related to the capacity to take up the surfaces in order to flatten them to allow a new bonding, and of course to the limit of the mechanical stress on the plates which is generated by the stacking.

Claims

Claims

1. A three-dimensional, 3D, microelectronic structure for an integrated semiconductor product, said 3D microelectronic structure comprising a first microelectronic device produced on an upper wafer (1), as well as a second microelectronic device produced on a lower wafer (2) on which the upper wafer (1) is bonded by hybrid bonding after vertical flipping, in which the lower wafer and the upper wafer each comprise a substantially planar substrate as well as an interconnection structure formed above said substrate, characterized in that: the respective interconnection structure of each of the upper (1) and lower (2) plates is a vertical stack of at least two interconnection levels directly superimposed and each comprising a hybrid layer essentially composed of a dielectric material, namely, respectively: • a higher interconnection level (HBM), with metal bonding pads (17b, 17c) formed in the dielectric material and adapted to cooperate with corresponding metal bonding pads (27b, 27c) of the other wafer for hybrid bonding of the upper wafer (1) on the lower wafer (2); and, • a horizontal interconnection level (MX) which is directly below the upper interconnection level (HBM), with horizontal metallization elements (15; 25), the respective metal bonding pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) wafers are distributed in a substantially homogeneous manner on the upper surface of the upper interconnection level (HBM) of the interconnection structure of said wafer, with a bonding pitch, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, which is less than a determined associated threshold; • the respective metal bonding pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) wafers comprise bonding pads of a first type (17b; 27b), which are electrically isolated from any horizontal metallization element (15; 25) of the horizontal interconnection level (MX) of the interconnection structure of said wafer; and, • the respective metal bonding pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) wafers further comprise bonding pads of a second type (17c; 27c), which are each electrically coupled to at least one underlying horizontal metallization element (15; 25) formed in the horizontal interconnection level (MX) of the interconnection structure of said wafer.

2. 3D microelectronic structure according to claim 1, wherein the horizontal interconnection level (MX) of the interconnection structure of each of the lower (1) and upper (2) wafers comprises a passivation film (16; 26) of electrically insulating material which covers the layer (14; 24) of dielectric material of said horizontal metallization level (MX), and wherein the bonding pads of the first type (17b; 27b) of each of the upper (1) and lower (2) wafers are electrically insulated from any horizontal metallization element of the horizontal interconnection level (MX) of the interconnection structure of said wafer, at least by the insulating material of the passivation film covering the layer (14; 24) of dielectric material of said horizontal metallization level (MX).

3. 3D microelectronic structure according to claim 1 or claim 2, in which the layer (14; 24) of dielectric material of the upper interconnection level (HBM) of the interconnection structure of each of the upper (1) and lower (2) plates is a hybrid layer of patterned dielectric material, said patterns defining: • solid areas of said dielectric material; • first through areas vertically filled with metallic material and at the level of which the insulating material of the passivation layer of the ho- interconnection level horizontal (MX) is present, said first through-zones forming the bonding pads of the first type (17b; 27b) of the upper interconnection level (HBM); and, • second through-zones vertically, filled with metallic material, and at the level of which the passivation layer of the horizontal interconnection level (MX) has an opening, said second through-zones forming the bonding pads of the second type (17c; 27c) of the upper interconnection level (HBM), each in electrical continuity with one of the horizontal metallization elements (15; 25) of the horizontal interconnection level (MX) through said opening of the passivation layer.

4. 3D microelectronic structure according to any one of claims 1 to 3, in which the associated threshold of the bonding pitch is less than or equal to 10 pm, preferably of the order of 5 pm.

5. A 3D microelectronic structure according to any one of claims 1 to 4, wherein the dielectric material of the hybrid interconnection layers of the interconnection structure of each of the upper (1) and lower (2) wafers is Silicon Dioxide (SiO2).

6. 3D microelectronic structure according to any one of claims 1 to 5, in which the material constituting the metallic bonding pads of the upper interconnection level (HBM) and / or the material constituting the horizontal metallizations (15, 25) of the horizontal interconnection level (MX) of the interconnection structure of each of the upper (1) and lower (2) plates, is a metal selected from the group comprising copper (Cu), gold (Au), titanium (Ti), aluminum (Al), niobium (Nb) and platinum (Pt), or an alloy based on at least one of said metals.

7. 3D microelectronic structure according to any one of claims 2 to 6, wherein the electrically insulating material of the passivation film (16,26) of the horizontal interconnection level (MX) of the interconnection structure of each of the upper (1) and lower (2) wafers is a silicon nitride (SiN) or a silicon carbonitride (SiCN).

8. 3D microelectronic structure according to any one of the claims-

9. indications 1 to 7, wherein the substrate of the upper wafer (1) and / or the substrate of the lower wafer (2) each comprise an active zone with active elements in the upper part of said substrate, and wherein: • the connecting pads of the first type of the interconnection structure of each of the upper (1) and lower (2) plates are electrically isolated from the active elements of the active zone of the substrate of said plate, whereas, • at least some of the bonding pads of the second type of the interconnection structure of the upper wafer (1) and / or of the lower wafer (2) are electrically coupled to at least one of the active elements of the active zone of the substrate of said wafer. Method for producing a three-dimensional, 3D, microelectronic structure according to any one of claims 1 to 8, comprising the hybrid bonding of an upper wafer (1) onto a lower wafer (2) after vertically turning over said upper wafer (1), characterized in that the prior production of the interconnection structure of each of the lower (1) and upper (2) wafers comprises the formation of a vertical stack of at least two interconnection levels directly superimposed above the substrate of said wafer, namely, respectively: • a horizontal interconnection level (MX), with horizontal metallization elements (15; 25) formed in the dielectric material of a corresponding hybrid layer; and, directly above said horizontal interconnection level (MX), • a higher interconnection level (HBM) with metal bonding pads (17b, 17c) formed in the dielectric material of a corresponding hybrid layer, and adapted to cooperate with corresponding metal bonding pads (27b, 27c) of the other wafer, for hybrid bonding of the upper wafer (1) on the lower wafer (2), said method being further characterized in that: • the respective metal bonding pads (17b, 17c; 27b, 27c) of the upper metallization level (HBM) of the interconnection structure of each of the upper (1) and lower (2) plates are produced with a substantially homogeneous distribution on the upper surface of said upper metallization level (HBM), and with a bonding pitch, defined as the maximum spacing between horizontally adjacent bonding pads in the plane of said upper surface, which is less than a determined associated threshold; • among the respective metal connecting pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) plates, connecting pads of a first type (17b; 27b) are each produced with electrical insulation from any horizontal metallization element (15; 25) of the horizontal interconnection level (MX) of the interconnection structure of said plate; • among the respective connecting pads (17b, 17c; 27b, 27c) of each of the upper (1) and lower (2) plates, in addition, connecting pads of a second type (17c; 27c) are each produced in electrical continuity with at least one underlying horizontal metallization element (15; 25) formed in the horizontal interconnection level (MX) of the interconnection structure of said plate.

10. A method according to claim 9, wherein forming the upper interconnection level (HBM) of the interconnection structure of each of the upper (1) and lower (2) wafers comprises: • the deposition (41) of a passivation film (16; 26) of electrically insulating material which covers a hybrid layer (14; 24) of dielectric material comprising horizontal metallization elements (15; 25) of the horizontal metallization level (MX) of the wafer; • the formation of a layer (17; 27) of dielectric material as well as a first etching by photolithography (41, 42), to etch said layer of dielectric material with a stop on the passivation film (16; 26) of the metallization level horizontal (MX) in order to form patterns in said layer (17; 27) of dielectric material corresponding to the metal bonding pads (17b, 17c; 27b, 27c) of the upper metallization level (HBM) of the wafer; then, • a second etching by photolithography (43, 44, 45), to etch the passivation film (16; 26) of the horizontal metallization level (MX) in order to open said film in only a part of the patterns previously formed in the layer (17; 27) of dielectric material which correspond to the metal bonding pads of the second type (17c; 27c) of the upper metallization level (HBM) of the wafer; then, • the filling (47), with metal, simultaneously of all the patterns previously formed in the layer (17; 27) of dielectric material, namely both the patterns corresponding to the metal bonding pads of the first type (17b; 27b) and the patterns corresponding to the metal bonding pads of the second type (17c; 27c) of the upper metallization level (HBM) of the wafer.

11. Method according to claim 10, in which the patterns in the layer (17; 27) of dielectric material corresponding to the metal bonding pads (17b, 17c; 27b, 27c) of the upper metallization level (HBM) of the wafer are filled with metal by electrochemical deposition.

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