DOUBLE SUPERNETWORKS OBTAINED BY LAYER TRANSFER, STRUCTURE AND MANUFACTURING METHOD

Abstract

A method (500) of manufacturing a structure comprising a stack of superlattices, comprising the steps of forming (510Car) a first superlattice (Stck1) on a first substrate; forming (520Don) a seed layer (Init) of a second superlattice (Stck2) on a second substrate; forming (550Don) a weakening plane (Imp) in the second substrate; assembling (560) the seed layer (Init) to the first superlattice (Stck1) at a dielectric separation layer which separates and keeps the first superlattice (Stck1) and the seed layer (Init) fixed to each other; removing (570A) a portion of the second substrate by fracturing the second substrate at the weakening plane (Imp) after the assembling step (560); releasing (570B) the seed layer (Init) after the step (570A) of fracturing the second substrate; and forming (580) the second superlattice (Stck2) on the released seed layer (Init). Figure to be published with the abstract: Fig. 5

Description

Title of the invention: DOUBLE SUPERNETWORKS OBTAINED BY LAYER TRANSFER, STRUCTURE AND MANUFACTURING METHOD TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates generally to superlattices, consisting of at least one periodic stack of thin layers, and particularly to superlattices including layers of semiconductor materials. More particularly, the invention relates to double superlattices. TECHNOLOGICAL BACKGROUND

[0002] Superlattices have attracted attention for their mechanical and semiconducting properties, or even for the possibility they offer of forming quantum dots.

[0003] They are also used for the development of transistors called nanosheet transistors, also called Nanosheet transistors or GAAFET for Gate-all-around Field-Effect Transistors in English terminology, whose conduction channels are formed from a stack of layers of nanometric thickness each surrounded by a gate metal, as described in patents US 10,249,739 B2 and US 11,018,222 Bl. These are semiconductor structures with an enveloping gate, or GAA for Gate-All-Around in English terminology.

[0004] This principle has been adopted to form so-called CFET transistors, for Complementary Field Effect Transistor in English terminology, having a three-dimensional structure formed using a pair of stacked superlattices: a first superlattice formed on a substrate is used to form an n-type transistor while a second superlattice formed on the first superlattice is used to form a p-type transistor, or vice versa. This three-dimensional structure is advantageous in terms of integration compared to conventional approaches used to implement CMOS technology, which usually uses p-type transistors and n-type transistors manufactured side-by-side in the same plane.In particular, the CFET approach makes it possible in principle to halve the size of a pair of p- and n-type transistors, or to shorten the connections between the two transistors and therefore to reduce the electrical resistance of the corresponding connections. This approach is described for example in documents US 2019 / 0319095 Al, US 2021 / 0104523 Al, and US 2023 / 0326925 AL.

[0005] Whether it is Nanosheet transistors or CFET transistors, the manufacturing processes considered involve the manufacturing of super networks comprising em stacks of two alternating types of materials: one is intended to form the channel regions of the transistors, the other to form sacrificial layers intended to be removed to be replaced by a gate dielectric and gate metal structure during the fabrication of the transistors.

[0006] The manufacture of CFET transistors requires stacking transistors of two types, n-type and p-type, one on top of the other. Two approaches are possible.

[0007] The first approach is called "sequential", in the sense that the transistors of the two types are formed sequentially, during distinct steps. In this approach, a semiconductor structure made of silicon or other semiconductor material, or a superlattice intended to form second Nanosheet transistors, is transferred onto a semiconductor substrate already carrying, for example, first Nanosheet transistors. In a first step, the first transistors are formed on the substrate, then the semiconductor structure is transferred onto it, in which the second transistors are then formed. The thermal budget for the process of transferring the semiconductor structure and for forming the second transistors is limited by the need not to degrade the first transistors.Furthermore, the alignment control of the second transistors with the first transistors must be extremely strict and specific electrical contact structures between the two stages must be provided.

[0008] The second approach is called "monolithic", in the sense that the first and second transistors are formed on the same substrate, at least part of the manufacturing steps being applied simultaneously to all of the layers in which the first and second transistors are formed. Reference may be made to document US 2019 / 0319095 AL One of the main advantages of this approach is the self-alignment of the second transistors on the first transistors, which allows a higher density of transistors on the substrate, and reduces the parasitic capacitances and resistances between the first and second transistors.

[0009] The monolithic approach requires thicker superlattices as a starting structure than the sequential approach, since these superlattices form the basic structure of two stacked transistors manufactured simultaneously. Superlattices are generally manufactured by epitaxy. However, the number of stackable layers for the formation of these superlattices is limited by the critical epitaxy thickness, thickness beyond which the quality of the deposited layers degrades due to elastic relaxation and / or plastic relaxation phenomena. The monolithic approach is close to and could require exceeding the critical epitaxy thickness.

[0010] Furthermore, the monolithic approach is technologically more complex to implement than the sequential approach, in particular for the formation of a dielectric separation layer between the first transistors and the second transistors. This promotes the integration of the internal spaces of the structure and the formation of the metal layers for the sources and drains of the transistors. The vertical distance between the first transistors and the second transistors can be reduced to the thickness of the dielectric layer, with positive effects on the reduction of parasitic capacitances and resistances between the first and second transistors. However, obtaining such a dielectric layer requires a complex procedure and the use of a sacrificial layer removed so as to leave space for the dielectric layer. This sacrificial layer associated with the dielectric separation layer must be compatible with a sacrificial layer intended to form a space for receiving the dielectric and gate metal layers.Thus, the two sacrificial layers used must be able to be selectively attacked with respect to each other and with respect to the semiconductor material forming the conduction channel of the transistors. For example, silicon is used for the channel, and silicon alloyed with different percentages of germanium for the sacrificial layers. From a technical point of view, although such structures can be used, obtaining them remains complex and delicate.

[0011] One approach is to form two superlattices independently of each other on two separate substrates and then transfer one onto the other using a layer transfer technology such as the so-called "Smart-Cut" method. One possible implementation of this approach is to (a) form a weakening plane within one of the two substrates by ion implantation of light species through the superlattice formed on this substrate, (b) assemble the two superlattices to each other using a direct contact bonding process such as molecular bonding, and then (c) fracture the implanted substrate at the weakening layer. A disadvantage of this approach is that it generally requires at least one heat treatment to heal the transferred layers damaged by the transfer process, in particular the ion implantation step.This heat treatment has a negative influence on superlattices due to the fact that it causes the diffusion of germanium ions into the silicon.

[0012] Thus, there is a need for a method of manufacturing superlattices or an assembly of superlattices making it possible to exceed the critical epitaxy thickness, while limiting the damage inflicted by the method on the layers forming the superlattices. Statement of the invention

[0013] The applicant's objective is to provide a method for manufacturing a structure capable of facilitating the integration and production of Nanosheet transistors, and more specifically CFET transistors, i.e. p-type transistors and superimposed n-type transistors. This manufacturing method must preferably be particularly suitable for the monolithic approach to CFET transistor manufacturing.

[0014] To achieve this aim, one aspect of the invention is a method of manufacturing a structure comprising a stack of superlattices, the method comprising the steps of forming a first superlattice on a first substrate, by stacking a plurality of first channel layers alternating with a plurality of first sacrificial layers; forming a seed layer of a second superlattice on a second substrate; forming a weakening plane of the second substrate by implanting ions of a light species into the second substrate; assembling the seed layer to the first superlattice at a dielectric separation layer which separates and keeps the first superlattice and the seed layer fixed to each other; removing a portion of the second substrate by fracturing the second substrate at the weakening plane, and removing this portion from the second substrate, after the assembly step;releasing the seed layer after the fracturing step of the second substrate; and forming the second superlattice on the released seed layer, by stacking a plurality of second channel layers alternating with a plurality of second sacrificial layers.;

[0015] A first advantage of the method is to provide a stack of superlattices which can be either identical or distinct in composition and / or orientation.

[0016] A second advantage of the method is the possibility of exceeding the critical epitaxy thickness for the structures obtained, which limits the number and thickness of layers that can be epitaxied on top of each other without losing quality in the crystalline structures of these layers.

[0017] A third advantage of the method lies in the provision within the stack of a separation layer between two superlattices, this layer being able to have structural characteristics incompatible with conventional methods for forming superlattices. Indeed, superlattices are conventionally formed by successive depositions of layers by epitaxy. However, with the present method, the separation layer can be made of a dielectric such as a nitride or an oxide which can be amorphous, incompatible with the formation by epitaxy of semiconductor layers of good crystalline quality on the surface of this amorphous layer: deposition by epitaxy on the contrary requires a crystalline base layer.The present invention thus makes it possible to use any type of dielectric, for example SiN, SiCN, or even SiO2, which can be chosen according to its own dielectric characteristics and its compatibility with the steps planned for the manufacture of transistors based on the stacking of super networks.

[0018] A fourth advantage of the method is a comparative advantage over an approach that would involve transferring the second superlattice from a substrate on which it would be independently formed to the first lattice by the Smart-Cut method. In such a situation, a healing heat treatment of the transferred layer may be necessary, but is not applicable in the present method. Thus, the present method limits the potential negative impacts of a heat treatment on the superlattices and / or an accompanying structure.

[0019] A fifth advantage arises from the intended applications for this superlattice stack, which is the formation of CFET transistors. The dielectric separation layer can be configured to perform an electrical insulation function between the stacked transistors, but also serve as etch stop layers for differentiated treatments between the transistors or the integration of such structures on the back face of the carrier substrate.

[0020] Thus, the manufacturing method according to the invention is suitable for the production of structures which can serve as the basis for a monolithic method for producing an electronic circuit integrating CFET transistors.

[0021] According to additional non-limiting characteristics of the method according to the invention, considered individually or according to any technically feasible combination:

[0022] - the separation layer can be continuously formed in a plane parallel to a surface of the first substrate on which the first superlattice is formed;

[0023] - the first channel layers and the second channel layers may each be formed of a semiconductor material, and the first sacrificial layers and the second sacrificial layers may each be formed of a material capable of exhibiting a faster etch rate than the first channel layers and the second channel layers, respectively;

[0024] - the first channel layers and the second channel layers may each be formed of silicon, and the first sacrificial layers and the second sacrificial layers may each be formed of an alloy of silicon and germanium;

[0025] - the method may comprise the steps of: forming a first layer of re covering the first superlattice before the attaching step; and, forming a second covering layer of the primer layer before the attaching step; wherein the attaching step comprises contacting the first covering layer with the second covering layer, the first covering layer and the second covering layer together forming the separation layer;

[0026] - the first covering layer and the second covering layer may each comprising silicon and at least one of the first capping layer and the second capping layer may be formed of an oxide;

[0027] - at least one of the first covering layer and the second covering layer covering formed from an oxide can be formed by a step of forming a silicon layer followed by a step of oxidizing this silicon layer;

[0028] - the method may further comprise a step of forming at least one layer stopping etching on the second substrate before the formation of the primer layer;

[0029] - the at least one etch stop layer may be formed from a layer of the same material as the second sacrificial layers and a layer of the same material as the second channel layers. BRIEF DESCRIPTION OF THE FIGURES

[0030] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0031] [Fig.l] [Fig.l] illustrates a manufacturing method according to the invention;

[0032] [Fig.2] [Fig.2] illustrates a continuation of the method of [Fig.l];

[0033] [Fig.3] [Fig.3] illustrates variants of structures that can be obtained by the method of figures 1 and 2;

[0034] [Fig.4] [Fig.4] illustrates variations of the separation layers of [Fig.3]; and

[0035] [Fig.5] [Fig.5] is a diagram summarizing the manufacturing process of Figures 1 and 2. DETAILED DESCRIPTION OF THE INVENTION

[0036] Embodiment

[0037] One embodiment of the present invention is described by means of Figures 1 to 5 and the associated description below.

[0038] [Fig.3] illustrates in (A) a Strc structure formed from a carrier substrate Car, a first Stckl superlattice, a separating Sep layer, and a second Stck2 superlattice, stacked in that order. The first Stckl superlattice comprises a plurality of first Chl layers stacked alternately with a plurality of first Sacl layers, preferably such that each first Chl layer is interposed between and in direct contact with two of the first Sacl layers. The second Stck2 superlattice comprises a plurality of second Ch2 layers stacked alternately with a plurality of second Sac2 layers, preferably such that each second Ch2 layer is interposed between and in direct contact with two of the second Sac2 layers.

[0039] The first Chl layers and the second Ch2 layers are layers formed of at least one semiconductor material for forming channel regions of transistors and may be referred to as the first channel Chl layers and the second channel Ch2 layers, respectively. These channel layers may be formed of the same material, or of different materials.

[0040] The first Sacl layers and the second Sac2 layers are layers formed from at least one material capable of exhibiting faster etching rates than the first Chl layers and the second Ch2 layers, and may be designated as the first sacrificial Sacl layers and the second sacrificial Sac2 layers, respectively. These sacrificial layers may be formed from the same material, or from different materials. In particular, the Sacl layers may have a SiiXGex composition and the Sac2 layers may have a Sii yGey composition where x and y represent the proportions of germanium in the Sacl and Sac2 layers, respectively, with x being different from or equal to y. These Sacl and Sac2 layers of SiGe alloy may be associated with Chl and Ch2 layers of silicon, thanks to the epitaxial growth compatibility of these two materials which have a fairly close lattice parameter. The proportions x and y are preferably less than 40%, for example between 15% and 35%.

[0041] The second layers Sacl and Sac2 are intended to serve as sacrificial layers in a procedure for forming Nanosheet transistors, during which the layers Sacl and Sac2 are removed by etching, which may be chemical, so as to obtain a structure of floating ribbons formed of the layers Chl and Ch2. These floating ribbons will subsequently be surrounded by a gate dielectric layer and a gate metal so as to form Nanosheet transistors.

[0042] Figures 1, 2 and 5 illustrate a method 500 for manufacturing the Strc structure, which is advantageously based on the separate manufacturing of a first superlattice Stckl and a primer layer Init of a second superlattice Stck2 on two respective substrates, then the transfer of the primer layer of the second superlattice Stck2 onto the first superlattice Stckl. The Strc structure is then completed by manufacturing the second superlattice Stack 2 by stacking successive layers on the primer Init. [Fig.5] represents a diagram schematizing the steps of the manufacturing method 500.

[0043] [Fig.l] illustrates in (A) the formation of the first superlattice Stckl on a carrier substrate Car, during a step 510Car- In the context of this example, the carrier substrate Car is made up of a monocrystalline silicon wafer.

[0044] On a surface SCar of the substrate Car, Chl layers of silicon Si of 5 to 15 nm thickness, preferably 7 to 10 nm thickness, are grown by epitaxy, alternating with Sacl layers of a first alloy of silicon and germanium of formula Sii_xGex of 5 to 10 nm thickness, preferably 6 to 9 nm thickness, and where x represents the percentage of germanium in the alloy, preferably starting and ending with a Sacl layer. On the last Sacl layer, a covering layer Capl is formed, during a step 520Car, here formed of silicon Si and having the function of preventing the oxidation of the last Sacl layer. The Capl layer may have a thickness of between 1 and 2 nm.

[0045] [Fig.l] illustrates in (B) the formation of the primer layer Init and associated layers on a donor substrate Don, during steps 510Don to 530Don- In the In this example, the donor substrate Don consists of a monocrystalline silicon wafer.

[0046] On a surface SDon of the substrate Don, the primer layer Init is deposited, which is here a layer of the first silicon and germanium alloy of formula Sii_xGex 5 to 10 nm thick, preferably 6 to 9 nm thick, during a step 520Don. On this layer Init, a covering layer Cap2, made of silicon, is formed during a step 530Don. The function of the layer Cap2 is to prevent the oxidation of the layer Init, and it is preferentially configured to be oxidized subsequently to form the bonding interface. The thickness of the layer Cap2 depends on the thickness of the future targeted oxidized layer. In other words, by aiming for an oxide layer with a thickness of between 10 and 35 nm, the layer Cap2 in this case must have a thickness of between approximately 4 and 16 nm.This Cap2 layer is optional, its interest depending on the ease of oxidization of the material constituting the last layer of the second Stck2 superlattice and the interest in integrating it into a dielectric separation layer between the two superlattices.

[0047] Optionally, before the formation of the primer layer Init, a layer Stp of the first silicon and germanium alloy of formula Si|XGcx with a thickness of between 5 and 10 nm can be formed on the donor substrate Don, then a protective layer Cap2' of silicon with a thickness of between 1 and 5 nm, during a step 510Don- These two layers are etch stop layers and are intended to protect the integrity of the primer layer Init during the manufacturing steps following the fracture of the donor substrate described later and illustrated in (B) and (C) of [Fig.2],

[0048] [Fig. 1] illustrates in (C) an oxidation of the Cap2 layer of silicon Si to form a covering layer 0x2 of silicon oxide SiO2 of 10 to 35 nm thickness, during an oxidation step 540Don.

[0049] The temperature and the oxidation duration used are limited to avoid exceeding the authorized thermal budget to avoid or at least limit the diffusion of germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thicknesses.

[0050] [Fig.l] also illustrates in (C) an implantation of light species such as hydrogen, helium, or a combination of such species in the donor substrate Don through the second superlattice Stck2 and the covering layer 0x2, so as to form an embrittlement plane lmp in the donor substrate Don, during a step 550Don-

[0051] Following the formation of the weakening plane lmp, the donor substrate Don is turned over and the oxide layer 0x2 is brought into intimate contact with the silicon layer Capl and is assembled there, for example by molecular bonding or any other assembly technique by bringing into direct contact surfaces of elements to be assembled, so as to obtain the structure illustrated in (A) of [Fig.2], during an assembly step 560. The separation layer Sep is formed at this step by bonding the last layers formed respectively on the carrier substrate Car and on the donor substrate Don, and corresponds to the assembly formed by the layers separating the first superlattice Stckl and the second superlattice Stck2, the layers Capl and 0x2 in the present embodiment, as illustrated by [Fig.3]. This separation layer Sep preferably completely overlaps the donor substrate Don. In addition, the separation layer Sep is continuously formed in a plane parallel to the surface SCar of the carrier substrate Car supporting the first superlattice Stckl.Even if the separation layer does not strictly overlap the entire carrier substrate, it is at least formed continuously over an area intended to form an assembly of semiconductor components such as transistors, possibly an assembly of CFET transistors.

[0052] At this stage of the manufacturing, the primer layer Init is sandwiched between the carrier substrate Car and the donor substrate Don. It is appropriate to release this primer layer Init in order to make it accessible. This release operation 570 is carried out in two successive steps 570A and 570B. Step 570A here consists of removing the majority of the donor substrate while step 570B consists of releasing the primer layer Init by eliminating the remains of the donor substrate.

[0053] [Fig.2] illustrates in (B) the fracture of the donor substrate Don at the level of the weakening plane lmp obtained by ion implantation, so that a part Donb is removed from the structure illustrated in (A) while a part Dona remains fixed there, during the fracture and removal step 570A. This fracture can be obtained by heat treatment, possibly assisted by a mechanical stress to initiate the fracture, according to conventional layer transfer techniques well known in the field of microelectronics.

[0054] Preferably, the carrier substrates Car and donor Don respectively comprising the first supernetwork Stckl and the primer layer Init are substantially identical. This advantageously makes it possible to easily produce them on a large scale, thus facilitating their industrialization. Furthermore, the use of substantially identical carrier and donor substrates advantageously makes it possible to have a symmetrical assembled structure having similar thermal expansion coefficients, which advantageously avoids problems of mechanical deformation following the bonding steps and future heat treatments.

[0055] Following assembly and fracture of the donor substrate, a heat treatment may be applied to consolidate the assembly and cure the assembled layers. The temperature and duration of the heat treatment are limited to avoid exceeding the permitted thermal budget to avoid or at least limit diffusion. germanium from one layer to another of the superlattices, and in particular the contamination of the channel layers by germanium over their entire thicknesses. The heat treatment may typically consist of an annealing of 2 hours or less at a maximum temperature of 750°C, and preferably less than 700°C.

[0056] An alternative to the formation of a weakening plane and the fracture of the donor substrate Don at this plane may consist of thinning the donor substrate Don after its assembly, for example by etching, grinding and / or chemical mechanical polishing (CMP). This thinning may be used to completely remove the second substrate Don if it is pushed for example up to the stop layer Stp.

[0057] [Fig.2] illustrates in (C) the structure illustrated in (B) after it has been subjected to mechanical and / or chemical attacks to eliminate the Dona portion of the donor substrate Don, the etch stop layer Stp, and the protective layer Cap2' during step 570B. Thus, the primer layer Init is released during this step, and accessible for the rest of the manufacturing process.

[0058] Then, the second superlattice Stck2 is formed. First of all, one begins by eliminating, within a thin-film deposition frame, any native oxide from the surface of the Init layer, thanks to the “in-situ” etching function available in a large number of epitaxy frames, for example by using HF gas. This operation makes it possible to clean the Init layer and to guarantee the quality of its surface in order to ensure the quality of the growth of the layers deposited there. The second superlattice Stck2 is then formed directly on the seed layer Init, during an epitaxy step 580, and by epitaxial growth, of the Ch2 layers alternating with Sac2 layers. The operation of cleaning the Init layer prior to the layer depositions is conventional and is considered to be part of the step of forming the Ch2 and Sac2 layers by epitaxy.Alternatively, other known cleaning methods could be considered, such as complete oxidation of the Cap2' layer and its removal by HF directly in the frame. The key is to obtain a clean, non-oxidized surface before proceeding with the deposition of thin layers on this surface, whether the deposition sequence is started with a Sac2 layer or a Ch2 layer.

[0059] The Ch2 layers are preferably made of silicon Si and have a thickness of 5 to 15 nm thick, preferably 7 to 10 nm thick, and the Sac2 layers are formed from the first alloy of silicon and germanium of formula Sii_xGex, 5 to 10 nm thick, preferably 6 to 9 nm thick, preferably in such a way that each Ch2 layer is interposed between and in direct contact with two of the first Sac2 layers, the seed layer Init being considered as one of the Sac2 layers. Thus, one can either grow a layer of silicon Ch2 directly on the primer layer Init which is here a layer of the first alloy of silicon and germanium of formula Sii_xGex, or start by forming a layer Sac2 of the first germanium alloy directly on the primer layer Init then form a layer Ch2 of silicon on it, then continue the formation of the layers Ch2 and Sac2 alternately.

[0060] This step 580 conditions the characteristics of the primer layer Init: this primer layer Init is of a chemical nature and crystalline structure suitable for allowing the formation of the second superlattice Stck2 by successive growths of layers by epitaxy. In the present case, the second superlattice being formed of an alternation of layers Ch2 and Sac2, it is appropriate to form an Init layer of one of these two types of layers. In the present case, it was chosen to form an Init layer of a silicon and germanium alloy of formula Sii_xGex. It is also possible to form the Init layer of another layer capable of forming a sacrificial layer with respect to the layers Ch2, that is to say layers likely to have faster etching speeds than the second layers Ch2.Other alternatives exist, such as forming an Init layer of silicon, or other materials favorable to the epitaxial formation of a layer of silicon Si or a Sii_xGex alloy.

[0061] The formation of the Stck2 superlattice after the transfer step advantageously allows it to avoid a heat treatment intended to cure the layers of the superlattice from the effects of ion implantation. This type of healing heat treatment may prove essential for semiconductor layers serving as an active layer in a transistor. Such a heat treatment can sometimes be implemented at a fairly high temperature, which can cause the diffusion of the germanium present in the adjacent layers into all of the channel layers.

[0062] The structure at (A) of [Fig.3] shows the structure Strc formed of the carrier substrate Car, the first superlattice Stckl, the capping layer Capl formed of silicon, the 0x2 layer of silicon oxide, and the seed layer Init, stacked in this order. The capping layer Capl and the 0x2 layer of silicon oxide form a dielectric separation layer Sep between the first superlattice Stckl and the second superlattice Stck2. The separation layer is considered a dielectric layer in that it is formed at least in part of a material considered to be dielectric, such as silicon nitride, silicon carbide nitride, or silicon oxide. This structure is ready to be subjected to a monolithic process for forming CFET transistors.

[0063] The figures bear the indications “Si” or “SiGe” at the locations of certain layers, and in particular those forming the superlattices Stckl and Stck2, in order to increase their readability by indicating their compositions for a given example. These indications are not, however, to be interpreted as limiting the nature of the layers thus annotated. Other materials, and in particular those cited in this description, may be used to form these layers.

[0064] [Fig.3] illustrates in (A') and in (A”) structures Strc' and Strc”, respectively, with possible variations Sep' and Sep” of the separation layer Sep of the structure Strc. In (A), the separation layer Sep is formed by bonding the covering layer 0x2, formed of oxide, to the covering layer Capl, constituting respectively the last layers formed on the donor substrate Don and on the carrier substrate Car.

[0065] A first variation illustrated in (A') consists of forming a silicon oxide layer Oxl as the last layer formed on the carrier substrate Car and forming a silicon covering layer Cap2 as the last layer formed on the donor substrate Don. Thus, the separation layer Sep' is formed by the assembly by molecular bonding of the layer Oxl with the layer Cap2.

[0066] A second variation illustrated in (A”) consists of forming two layers of silicon oxide as the last respective layers formed on the substrates Car and Don. Thus, the separation layer Sep” is formed by the assembly by molecular bonding of these two layers of silicon oxide, finally forming only one layer Ox of silicon oxide.

[0067] The separation layer Sep, which is also the layer linking the two superlattices to each other, is not limited to being formed from crystalline silicon and / or amorphous silicon oxide obtained by oxidation of silicon. Thus, although [Fig.l] illustrates in (A) and (B) a method in which the oxide layer 0x2 is formed by the oxidation of a silicon layer, the layer 0x2 could be formed by direct deposition of a silicon oxide layer. This remark applies to the variations illustrated in (A') and (A”) of [Fig.3] for the Oxl layer of (A') and to the oxide layers forming the Ox layer of (A”).

[0068] The separation layer may also be composed of layers formed from amorphous silicon or other materials as long as these are compatible with the superlattice processing method envisaged subsequently. Thus, in general, dielectric, semiconductor or metallic materials may be used to form the layers composing the separation layer, the main constraint being that these materials must be in the form of layers of sufficiently high flatness and sufficiently low roughness to be assembled by a direct bonding method such as molecular bonding. In the case where the superlattices are intended to form CFET transistors, dielectric materials and / or semiconductor materials will preferably be used. For example, it is possible use one or a combination of materials selected from silicon nitride (SiN), silicon carbide nitride (SiCN), an oxide thereof (SiON, SiCNOJ, or silicon oxide (SiO2) deposited or formed by a low-temperature oxidation method. Dielectric materials known as "high k" materials in English terminology, such as HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, their alloys or their alloys with silicon can also be used. More generally, any type of dielectric material used in the semiconductor industry can be used as a dielectric layer, protective layer, hard mask (hard mask in English terminology), via coating (liners for TSVs or through-Silicon vias in English terminology).

[0069] [Fig.4] illustrates such alternatives with, in (A), a separation layer Sep formed, in this order, of separation layers Sepa, Sepb and Sepc. The molecular bonding is carried out at an interface plane Int located between the layers Sepc and Sepb, one of which is formed of silicon, amorphous silicon, or silicon oxide, the other being formed of amorphous silicon or silicon oxide. The layer Sepa may be formed of silicon nitride, silicon carbide nitride, silicon oxide or other dielectric materials. The layers Sepa and Sepb may be formed on the donor substrate Don instead of the layer 0x2 and the layer Sepc may be formed on the carrier substrate Car instead of the layer Capl. Alternatively, the layers Sepa and Sepb may be formed on the donor substrate Car instead of the layer Capl and the layer Sepc may be formed on the donor substrate Don instead of the layer 0x2.

[0070] The configuration illustrated in (B) of [Fig.4] is different from the configuration illustrated in (A) in that it further comprises a separation layer Sepd formed on the same side of the interface plane Int as the layer Sepc, and may be formed of silicon nitride, silicon carbide nitride, silicon oxide or other dielectric materials.

[0071] The separation layers of the variants illustrated in [Fig.4] constitute MDLs, or Multiple Dielectric Layers in English terminology, and can be used to improve molecular bonding and adhesion strength for subsequent manufacturing steps.

[0072] The manufacturing method illustrated by Figures 1 and 2 makes it possible to obtain a superposition of two superlattices. In addition, the method can be repeated to stack an arbitrary number of superlattices. Thus, the critical epitaxy thickness can be exceeded: each of the superlattices taken individually can respect this thickness so as to be formed of layers of high quality, and their stacking allows an assembly of superlattices exceeding the critical thickness while maintaining the quality of the layers composing them.

[0073] The formation by epitaxy of the layers constituting the superlattices involves the reproduction of the crystalline structure from one layer to another, so that the Si layers and the SiGe layers formed sequentially one after the other by epitaxy have the same crystalline structure. Ordinarily, it is not possible to epitaxy a semiconductor layer of acceptable characteristics with a view to forming transistors on an amorphous layer such as a dielectric layer, and more particularly an oxide layer. Indeed, the latter does not constitute a suitable basis for the epitaxy of a high-quality crystalline semiconductor layer. The separation layer obtained by the method according to the invention makes it possible to position a dielectric layer between two superlattices formed from semiconductor layers of sufficient quality to produce transistors for commercial applications.

[0074] Furthermore, the separation layer can be adapted (composition, thickness of the layer(s) forming it) to the intended use of the stacked superlattices. It is thus possible to ensure a desired electrical insulation between the two superlattices Stckl and Stck2 by modulating, for example, the thickness of the Cap2 layer which, once oxidized into a 0x2 layer, forms a high-quality dielectric layer of chosen thickness and covering the entire structure, an entire wafer when the substrates are wafers.

[0075] The separation layer is formed continuously in a plane parallel to the upper surface of the substrate supporting it, covering substantially the entire surface of the substrate. Such a geometry contrasts with the situation found in CFET-type structures, in which a dielectric layer separating the n-type transistors and the p-type transistors follows the reliefs formed by the structures resulting from the formation of the transistors located between the substrate and this dielectric layer, and may be discontinuous.

[0076] Thus, the separation layer according to the invention may be of high quality, of chosen thickness, with in addition good uniformity of thickness, and continuous over a portion of interest or over substantially the entire surface of a substrate, which makes it suitable for serving as an etch stop layer, during the manufacturing process of the different transistors, or for differentiated treatment between the transistors formed in the first super network and the transistors formed in the second super network. Furthermore, by using a Car substrate of SOI type, it is also possible to produce a power supply network on the back face of the device (called BSPDN for BackSide Power Delivery Network in English terminology), using the BOX as an etch stop layer. A portion of interest may consist of a surface of a substrate intended to require the presence of the separation layer.

[0077] The carrier substrate Car and the donor substrate Don may comprise any semiconductor material. In addition to silicon, the semiconductor material may be germanium (Ge), a silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors or II-VI compound semiconductors, or SOI type substrates for Silicon-On-Insulator in English terminology, and more generally any type of semiconductor substrate comprising a buried or surface layer of dielectric material. Such a dielectric layer can serve as an etch stop layer for the formation of structures on the rear face (on the side of the carrier substrate Car) of the structure obtained by the method described in figures 1 and 2, or, for the case where it is located on the surface, as insulation in order to prevent the so-called "latch-up" phenomenon of an integrated circuit manufactured on the basis of this structure.

[0078] The Chl and Ch2 layers may be formed, for example, from silicon or a III-V type semiconductor compound. The Sacl and Sac2 layers may be formed, for example, from silicon and germanium alloys generically designated SiGe. The Chl and Ch2 layers may be of the same composition in both Stckl and Stck2 superlattices, and similarly, the Sacl and Sac2 layers may be of the same Sii_xGex composition in both Stckl and Stck2 superlattices. This latter point makes it possible to eliminate the Sacl and Sac2 sacrificial layers during the same step.

[0079] Alternatively, the Stckl and Stck2 superlattices may be of different natures and / or orientations. The orientation of the second superlattice relative to the first superlattice is defined during the assembly step. The Sacl (and Chl) layers on the one hand and the Sac2 (and Ch2) layers on the other hand may have different orientations, for example with crystallographic axes offset by 45°. It is also possible to consider the use of strained silicon, silicon and germanium alloys SiGe or germanium for the channel layers of one or other of the two superlattices or for both. When the two superlattices comprise silicon and germanium alloys, the proportions of germanium in the alloy may be the same or different for the two superlattices. It is of course appropriate to adapt the nature and characteristics of the Sacl and Sac2 sacrificial layers to those of the Chl and Ch2 layers.Also, it is appropriate to adapt the nature and crystallographic structure of the Init seed layer to the characteristics of the Sac2 and Ch2 layers in order to guarantee adequate epitaxial growth of these layers.

[0080] Similarly, the numbers of channel layers and sacrificial layers in the two superlattices may be the same, respectively, or may be different.

[0081] The embodiment described above relates to an association of supernetworks intended to form transistors, and more specifically Nanosheet or CFET transistors. The scope of the invention, however, extends beyond this field, and includes the combination of superlattices in general, not only in the field of semiconductors.

[0082] The invention is not limited to the embodiment described above and variations may be made thereto without departing from the scope of the invention as defined by the claims.

Claims

Claims

1. Method (500) for manufacturing a structure (Strc, Strc', Strc”) comprising a stack of superlattices, comprising the steps of: - forming (510Car) a first superlattice (Stckl) on a first substrate (Car), by stacking a plurality of first channel layers (Chl) alternating with a plurality of first sacrificial layers (Sacl); - forming (520Don) a seed layer (Init) of a second superlattice (Stck2) on a second substrate (Don); - forming (550Don) a weakening plane (lmp) of the second substrate (Don) by implantation of ions of a light species in the second substrate (Don); - assembling (560) the seed layer (Init) to the first superlattice (Stckl) at a dielectric separation layer (Sep, Sep', Sep”) which separates and keeps fixed to each other the first superlattice network (Stckl) and the bootstrap layer (Init);- removing (570A) a portion (Donb) of the second substrate (Don) by fracturing the second substrate (Don) at the weakening plane (lmp), and removing this portion (Donb) from the second substrate (Don), after the assembly step (560); - releasing (570B) the primer layer (Init) after the step (570A) of fracturing the second substrate (Don); and - forming (580) the second super network (Stck2) on the released primer layer (Init), by stacking a plurality of second channel layers (Ch2) alternating with a plurality of second sacrificial layers (Sac2).;

2. The method according to claim 1, wherein the separation layer (Sep, Sep', Sep”) is continuously formed in a plane parallel to a surface (SCar) of the first substrate (Car) on which the first superlattice (Stckl) is formed.

3. The method of claim 1 or 2, wherein: - the first channel layers (Chl) and the second channel layers (Ch2) are each formed of a semiconductor material, and - the first sacrificial layers (Sacl) and the second sacrificial layers (Sac2) are each formed of a material capable of exhibiting a faster etching rate than the first channel layers (Chl) and the second channel layers (Ch2), respectively.

4. The method according to any one of the preceding claims 1 to 3, wherein: - the first channel layers (Chl) and the second channel layers (Ch2) are each formed of silicon, and - the first sacrificial layers (Sacl) and the second sacrificial layers (Sac2) are each formed of an alloy of silicon and germanium.

5. The method according to any one of claims 1 to 4, comprising the steps of: - forming (520Car) a first covering layer (Capl, Oxl) of the first superlattice (Stckl) before the fixing step (560); and - forming (530Don) a second covering layer (Cap2, 0x2) of the primer layer (Init) before the fixing step (560); wherein the fixing step (560) comprises contacting the first covering layer (Capl, Oxl) with the second covering layer (Cap2, 0x2), the first covering layer (Capl, Oxl) and the second covering layer (Cap2, 0x2) together forming the separation layer (Sep, Sep', Sep”).

6. The method of claim 5, wherein the first capping layer (Capl) and the second capping layer (Cap2) each comprise silicon and at least one of the first capping layer (Oxl) and the second capping layer (Ox2) is formed of an oxide.

7. The method according to claim 6, wherein at least one of the first covering layer and the second covering layer formed of an oxide is formed by a step of forming (530Don) a silicon layer (Cap2) followed by a step of oxidizing (540Don) this silicon layer.

8. The method according to any one of claims 1 to 7, further comprising a step of forming (510Don) at least one etch stop layer (Stp, Cap2') on the second substrate (Don) before forming the primer layer (Init).

9. The method according to claim 8, wherein the at least one etch stop layer is formed of a layer (Stp) of the same material as the second sacrificial layers (Sac2) and a layer (Cap2') of the same material as the second channel layers (Ch2).

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