SINGLE-PHOTON AVALANCHE DIODE INCLUDING A CAPACITIVE PASSIVATION STRUCTURE

Abstract

One aspect of the invention relates to a single-photon avalanche diode (3) comprising: a semiconductor substrate (30) doped with a first conductivity type and having a first face (30a) and a second face (30b) opposite the first face; a semiconductor region (31) doped with a second conductivity type opposite the first conductivity type, extending in the semiconductor substrate (30) from the first face (30a) towards the second face (30b); anda capacitive passivation structure (32) disposed within a first trench (33) extending into the semiconductor substrate (30) from the first face (30a) toward the second face (30b), the capacitive passivation structure (32) extending in contact with the semiconductor region (31) and being configured to form a first electric charge accumulation layer in the semiconductor region (31) at the interface with the first trench (33).Figure to be published with the abstract: Figure 3.

Description

Title of the invention: SINGLE PHOTON AVALANCHE DIODE COMPRISING A CAPACITIVE PASSIVATION STRUCTURE TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of single photon avalanche diodes, also called SPAD (for “single photon avalanche diode” in English). TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] A single-photon avalanche diode (SPAD) is a photodiode comprising a PN junction reverse-biased at a voltage greater than its breakdown voltage. When no electrical charge is present in the depletion region (also called the space charge region) of the PN junction, the photodiode is in a pseudostable, non-conducting state. When an electrical charge generated by the absorption of a photon is injected into the depletion region, if the speed of movement of this charge in the depletion region is sufficiently high, i.e., if the electric field in the depletion region is sufficiently intense, the photodiode enters avalanche mode. A single photon is thus capable of generating a measurable electrical signal, and this in a very short period of time.

[0003] SPADs have high detection sensitivity and a very short response time which make them excellent candidates for measuring time of flight in telemetry, facial recognition and LiDAR (Light Detection And Ranging) applications. They can detect very low intensity radiation and are also used for single photon detection and photon counting.

[0004] The PN junction is typically formed between a substrate doped with a first type of conductivity and a localized region (in the substrate) doped with a second, opposite conductivity type. A problem that arises in SPADs with a horizontal PN junction (i.e., parallel to the front and back faces of the substrate) is that of collecting photogenerated charges deep in the substrate, at a distance far from the avalanche zone of the photodiode (i.e., the part of the depletion zone in which the electric field is sufficiently intense for the avalanche to be triggered by a single charge). Indeed, beyond a certain distance from the PN junction, the electric field resulting from the reverse bias of the PN junction is canceled or strongly attenuated, and no longer allows the photogenerated charges to be driven towards the avalanche zone. Only random diffusion in the substrate is then likely to drive the photogenerated charges towards the zone avalanche, with a significant probability that the photogenerated charges will never reach the avalanche zone or will reach it with a significant delay. This problem arises in particular when it is desired to collect photogenerated charges under the effect of long wavelength radiation, for example radiation with a wavelength between 750 and 1200 nm in silicon.

[0005] [Fig.l] is a schematic sectional view of a SPAD type photodiode 1 described in international application WO2018 / 050996A1.

[0006] The photodiode 1 comprises a substrate 10 made of P-type doped silicon and a localized region 11 made of N-type doped silicon, extending through the substrate 10, in a substantially vertical direction, that is to say substantially perpendicular to the upper face 10a of the substrate 10. The localized region 11 is for example in the form of a tube with a substantially vertical central axis. The substrate 10 and the localized region 11 respectively form the anode and the cathode of the photodiode 1. An avalanche zone of the photodiode 1 is located at the PN junction formed between the substrate 10 and the lateral surfaces of the localized region 11. This avalanche zone extends in the substrate 10 in a substantially vertical direction. This configuration makes it possible to efficiently collect photogenerated charges deep in the substrate 10.

[0007] The photodiode 1 further comprises: • a lightly doped P-type layer 12 (P doping), with a doping level lower than that of the substrate 10, covering the lower face 10b of the substrate 10; • a P-type doped support layer 13, with a doping level higher than that of the lightly doped P layer 12, covering the lightly doped P layer 12; and • a lightly doped region of type N 14 (N ), with a doping level lower than that of the localized region 11, laterally surrounding the upper part 11a of the localized region 11.

[0008] The lightly doped P layer 12 and the lightly doped N region 14 decrease the electric field at the upper and lower parts of the PN junction (by their lower doping level) and therefore reduce the risk of untimely triggering of the avalanche due to the charges generated by the surface defects of the silicon.

[0009] The localized region 11 is formed by etching a trench 15 from the upper face 10a of the substrate 10, this trench 15 passing through the lightly N-doped region 14, the substrate 10 and interrupting in the lightly P-doped layer 12, then by filling the trench 15 with an N-type doped polycrystalline silicon.

[0010] However, the surfaces delimiting the trench 15 have numerous defects caused by the etching, which generate a dark current in the presence of a field electric.

[0011] Furthermore, US patent 11387379B2 describes an avalanche photodetector for the detection of single photons whose detection principle does not rely on a PN junction. This photodetector is supposed not to suffer from the disadvantages of PN junction SPADs, such as the high dark current caused by silicon defects.

[0012] [Fig.2] is a schematic sectional view of the avalanche photodetector 2 described in this patent. The photodetector 2 comprises a P-type doped semiconductor substrate 20 and a peripheral structure 21 called CDTI (for “Capacitive Deep Trench Isolation” in English), extending through the semiconductor substrate 20 and surrounding an active region of the semiconductor substrate 20 intended for the absorption of photons. The CDTI peripheral structure 21 forms a vertical gate structure. It is formed by etching a trench 22 in the substrate 20, coating the side walls of the trench 22 with a layer of insulating material 210 (such as a thermal oxide) and then filling the remainder of the trench 22 with a conductive material 211 (such as polycrystalline silicon).

[0013] The CDTI peripheral structure 21 allows the formation of an electron accumulation layer in the P-doped semiconductor substrate 20, at the interface with the insulating material layer 210. In other words, it allows the formation of an inversion layer of the doping type, as in the channel region of a MOS transistor. This inversion layer is the origin of an electric field E which attracts an electron (photogenerated by the absorption of an hv photon) towards the interface between the insulating material layer 210 and the semiconductor substrate 20. This electron collides with the atoms of the semiconductor substrate 20, which releases other electrons and causes the avalanche effect.

[0014] The electron accumulation layer, or doping type inversion layer, is equivalent to a thin, heavily N-doped layer. The electric field E near the interface is therefore high and abrupt, so much so that it causes the appearance of a parasitic current by band-to-band tunneling. Now this parasitic current by tunneling considerably increases the dark current of the photodetector. Summary of the invention

[0015] There is therefore a need to provide a device for detecting a single photon which has a low dark current.

[0016] According to a first aspect of the invention, this need is tended to be satisfied by providing a single-photon avalanche diode comprising: • a semiconductor substrate doped with a first conductivity type and having a first face and a second face opposite the first face; • a semiconductor region doped with a second conductivity type opposite to the first conductivity type, extending in the semiconductor substrate from the first face towards the second face; and • a capacitive effect passivation structure disposed within a first trench which extends into the semiconductor substrate from the first face towards the second face, the capacitive effect passivation structure extending in contact with the semiconductor region and being configured to form a first layer of accumulation of electrical charges in the semiconductor region at the interface with the first trench.

[0017] The first electric charge accumulation layer formed in the semiconductor region makes it possible to passivate the surface defects created by the etching of the first trench and to suppress any electric field at the interface with the first trench. Thus, these defects do not generate dark current.

[0018] Preferably, the capacitive passivation structure comprises a first dielectric layer and a first electrically charged layer separated from the semiconductor region by the first dielectric layer.

[0019] Alternatively, the capacitive passivation structure comprises a first dielectric layer and an electrode separated from the semiconductor region by the first dielectric layer.

[0020] In first and second embodiments, the diode further comprises a peripheral insulation structure defining an active region of the semiconductor substrate, the peripheral insulation structure extending into the semiconductor substrate from the first face toward the second face.

[0021] Advantageously, the peripheral insulation structure is arranged inside a second trench and configured to form a second layer of accumulation of electric charges in the semiconductor substrate at the interface with the second trench.

[0022] The peripheral insulation structure preferably comprises a second dielectric layer and a second electrically charged layer separated from the active region of the semiconductor substrate by the second dielectric layer.

[0023] It may further comprise a layer of opaque material separated from the active region of the semiconductor substrate by the second electrically charged layer and the second dielectric layer.

[0024] In a third embodiment, the capacitive effect passivation structure surrounds the semiconductor region which itself surrounds an active region of the semiconductor substrate.

[0025] According to a development of this third embodiment, the step structure- capacitive effect sivation includes a layer of opaque material.

[0026] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the diode according to the first aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: • the semiconductor region surrounds the passivation structure by capacitive effect; • the diode further comprises a contact area of ​​the semiconductor region; • the contact area is arranged on the passivation structure by capacitive effect in the first trench; • the contact area extends into the semiconductor region; • the diode further comprises a contact pad electrically connected to the region semiconductor by the contact area; • the diode further comprises a first electric field reduction layer arranged on the first face of the semiconductor substrate; and • the diode further comprises a second electric field reduction layer arranged on the second face of the semiconductor substrate.

[0027] A second aspect of the invention relates to a method of manufacturing a single-photon avalanche diode, comprising the following steps: • etching a first trench in a semiconductor substrate doped with a first conductivity type and having a first face and a second face opposite the first face, the first trench extending from the first face towards the second face; • forming a semiconductor region doped with a second conductivity type opposite to the first conductivity type, the semiconductor region being delimited in part by the first trench and extending into the semiconductor substrate from the first face towards the second face; and • forming a capacitive passivation structure in the first trench, the capacitive passivation structure being configured to form a first electric charge accumulation layer in the semiconductor region at the interface with the first trench.

[0028] In one embodiment, the formation of the semiconductor region comprises the following substeps: • epitaxially forming a doped semiconductor layer on a lateral surface of the first trench, the doped semiconductor layer comprising doping impurities; and • perform diffusion annealing to laterally diffuse the doping impurities from the doped semiconductor layer into the semiconductor substrate.

[0029] In an alternative implementation, the semiconductor region is formed by gas-phase diffusion doping, from a lateral surface of the first trench. BRIEF DESCRIPTION OF THE FIGURES

[0030] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended figures, among which: • [Fig.l], previously described, schematically represents a single-photon avalanche diode according to the prior art; • [Fig.2], previously described, schematically represents an avalanche photodetector according to the prior art; • [Fig.3] is a schematic sectional view of a single-photon avalanche diode according to a first embodiment of the invention; • [Fig.4] schematically represents the behavior of the diode of [Fig.3] under reverse bias; • [Fig.5] is a schematic sectional view of a single-photon avalanche diode according to a second embodiment of the invention; • [Fig.6] is a schematic sectional view of a single-photon avalanche diode according to a third embodiment of the invention; • [Fig.7] is a schematic and partial top view of a photodetector comprising a plurality of single-photon avalanche diodes; • Figures 8A to 81 represent steps of a manufacturing method of the single-photon avalanche diode according to [Fig.3].

[0031] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0032] In the following description, the terms "front", "rear", "upper", "lower", "above", "below", "horizontal", "vertical", "lateral", etc. used to qualify the position or orientation of certain elements refer to the orientation of Figures 3 to 6 and 8A-8I. Furthermore, unless otherwise specified, the expressions "approximately", "substantially" and "of the order of" mean to within 5%, or, when they relate to absolute or relative angles or angular orientations, to within 5 degrees.

[0033] Figures 3, 5 and 6 show in schematic sectional view different modes of production of a single-photon avalanche diode 3. The single-photon avalanche diode 3 may be indifferently called “diode 3”, “SPAD 3” or “photodiode 3”.

[0034] In a manner common to all these embodiments, the diode 3 comprises: • a semiconductor substrate 30 doped with a first type of conductivity, having a first face 30a and a second face 30b opposite the first face 30a; • a semiconductor region 31 doped with a second type of conductivity opposite to the first type of conductivity, extending in the semiconductor substrate 30 from the first face 30a towards the second face 30b; • a capacitive effect passivation structure 32 extending in the semiconductor substrate 30 from the first face 30a towards the second face 30b, in contact with the semiconductor region 31.

[0035] The semiconductor substrate 30 (hereinafter simply referred to as “substrate 30”) and the semiconductor region 31 are preferably formed from the same semiconductor material, for example silicon.

[0036] The first and second faces 30a-30 of the substrate 30 extend along substantially parallel planes. The first face 30a corresponds (in the orientation of the figures) to the front or upper face of the substrate 30, while the second face 30b corresponds to its rear or lower face. The thickness of the substrate 30 may be between 1 μm and 25 μm, preferably between 5 μm and 20 μm.

[0037] The semiconductor region 31 preferably extends in a direction substantially perpendicular to the first face 30a. It advantageously passes through the substrate 30 (in other words, it extends over the entire thickness of the substrate 30).

[0038] The semiconductor region 31 is a so-called “localized” region, because it occupies only a part of the volume of the substrate 30. It has a lateral surface 31c of which at least a part is in contact with the substrate 30, thus obtaining a PN junction which extends deep into the substrate. The PN junction preferably extends in a direction substantially perpendicular to the first face 30a.

[0039] When the substrate 30 is P-type doped and the semiconductor region 31 is N-type doped, the substrate 30 and the semiconductor region 31 respectively form the anode and the cathode of the diode 3. Conversely, when the substrate 30 is N-type doped and the semiconductor region 31 is P-type doped, the substrate 30 and the semiconductor region 31 respectively form the cathode and the anode of the diode 3.

[0040] Diode 3 comprises a depletion zone, also called a space charge zone, which extends laterally on either side of the PN junction. The avalanche of diode 3 occurs in a so-called active part of this depletion zone.

[0041] The capacitive effect passivation structure 32 (hereinafter simply referred to as “passivation structure 62”) is disposed within a first trench 33, which partially delimits the semiconductor region 31 and which extends into the substrate 30 from the first face 30a towards the second face 30b. As described later with reference to FIGS. 8C and 8D, the first trench 33 serves to form the semiconductor region 31.

[0042] The passivation structure 32 extends in contact with the semiconductor region 31, preferably in a direction substantially perpendicular to the first face 30a of the substrate. It advantageously passes through the substrate 30 (in other words, it extends over the entire thickness of the substrate 30).

[0043] As described below in relation to [Fig. 4], the capacitive effect passivation structure 32 is configured to form a first electric charge accumulation layer in the semiconductor region 31 at the interface with the first trench 33.

[0044] In the illustrated embodiments, the diode 3 further comprises a first electric field reduction layer 34 arranged on the first face 30a of the substrate 30 (in other words on the front face) and / or a second electric field reduction layer 35 arranged on the second face 30b of the substrate 30 (on the rear face). The first and second electric field reduction layers 34-35 are each formed from a doped semiconductor material, of N or P type, which has a concentration of doping impurities (respectively of donor or acceptor type) lower than the concentration of doping impurities of the substrate 30. This semiconductor material is preferably silicon.

[0045] Preferably, the first electric field reduction layer 34 (on the front face) has the same type of conductivity as the substrate 30 (i.e. the first type of conductivity) and the second electric field reduction layer 35 (on the rear face) is of the opposite type of conductivity (i.e. the second type of conductivity).

[0046] Each of the first and second electric field reduction layers 34-35 may have a thickness of between 50 nm and 1 pm, for example equal to 1 pm.

[0047] The semiconductor region 31 may extend from the upper face of the first electric field reduction layer 34, pass through this first layer 34 and the substrate 30, and be interrupted on the upper face of the second electric field reduction layer 35 or in this second layer 35.

[0048] Similarly, the first trench 33 may extend from the upper face of the first electric field reduction layer 34, pass through this first layer 34 and the substrate 30, and be interrupted on the upper face of the second electric field reduction layer 35 or in the second layer 35.

[0049] The diode 3 further comprises at least one first contact pad 361 electrically connected electrically to the substrate 30 and at least one second contact pad 362 electrically connected to the semiconductor region 31. These contact pads 361-362 make it possible to apply electrical potentials to the substrate 30 and to the conductive region 31, and therefore to polarize the PN junction of the diode 3. They are for example made of metal (we then speak of contact metallizations).

[0050] The diode 3 may comprise several first contact pads 361 distributed so as to standardize the electrical potential applied to the substrate 30 and the collection of charge carriers, as illustrated in the sectional views of FIGS. 3 to 5. On the contrary, it may comprise only one second contact pad 362 (the semiconductor region 31 being much less extensive than the substrate 30).

[0051] Each first contact pad 361 is preferably disposed on and in contact with the upper face of the first electric field reduction layer 34.

[0052] For each first contact pad 361, a first contact area of ​​the substrate 371, preferably made of a doped semiconductor material of the same conductivity type as the substrate 30 but having a higher concentration of doping impurities, may extend from the upper face of the first electric field reduction layer 34 towards the substrate 30, in order to minimize the contact resistance (between the first contact pad 361 and the substrate 30). The first contact pad 361 is then electrically connected to the substrate 30 by the first contact area 371. It is advantageously arranged on and in contact with this first contact area 371.

[0053] The second contact pad 362 is preferably located at the same level as the first contact pad(s) 361, in other words at the upper face of the first electric field reduction layer 34 (which here coincides with the upper face of the semiconductor region 31). A second contact area 372 of the semiconductor region, preferably made of a doped semiconductor material of the same conductivity type as the semiconductor region 31 but having a higher concentration of doping impurities, is advantageously provided to reduce the contact resistance (between the second contact pad 362 and the semiconductor region 31). The second contact pad 362 is then electrically connected to the semiconductor region 31 by the second contact area 372. It is advantageously arranged on and in contact with this second contact area 372.

[0054] The position of this second contact area 372 (and therefore of the second contact pad 362) differs according to the embodiments of the diode 3. In the embodiment of [Fig. 3], the second contact area 372 is located in the first trench 33, on the passivation structure 32. The second contact area 372 and the passivation structure 32 are thus aligned. In other words, the second contact area 372 does not extend, laterally, beyond the passivation structure 32. It is then in contact with the semiconductor region 31 by its lateral surface only. In the embodiments of FIGS. 5 and 6, the second contact area 372 extends into the semiconductor region 31. It is then in contact with the semiconductor region 31 by its lateral surface, but also its lower surface.

[0055] The first and second contact areas 371-372 are preferably made of (doped) silicon.

[0056] In the absence of the first electric field reduction layer 34, the first and second contact pads 361-362 are disposed at the front face 30a of the substrate 30 (rather than at the upper face of the first electric field reduction layer 34).

[0057] In operation, the cathode of diode 3 is biased to a positive potential V+ and the anode of the photodiode is biased to a negative potential V- (via contact pads 361-362), so that the cathode-anode voltage of the diode is greater than the avalanche voltage (in absolute value). When diode 3 is thus reverse biased, an electric field appears at the PN junction.

[0058] The operation of diode 3 is described below in relation to [Fig.4]. This figure shows the diode of [Fig.3] under reverse bias, but the operation described is common to all embodiments.

[0059] In [Fig.4], the dotted lines represent equipotential lines in the structure when diode 3 is reverse biased. In this example, substrate 30 is P-doped and constitutes the anode, while semiconductor region 31 is N-doped and constitutes the cathode. The closer the equipotential lines are to each other, the stronger the electric field.

[0060] As shown in the figure, because the doping level (i.e., the concentration of doping impurities) of the first and second electric field reduction layers 34-35 is lower than the doping level of the substrate 30, the equipotential lines are less constricted at the upper (at the interface between the first layer 34 and the upper part of the semiconductor region 31) and lower (at the interface between the second layer 35 and the lower part of the semiconductor region 31) portions of the PN junction than at the central portion (at the interface between the substrate 30 and the central portion of the semiconductor region 31) of the PN junction. As a result, the electric field generated at the upper and lower portions of the PN junction is less intense than the electric field generated at the central portion of the PN junction.

[0061] The doping impurity concentrations of the substrate 30, the semiconductor region 31 and the first and second electric field reduction layers 34-35, as well as the bias voltage of the diode, are preferably chosen so that the electric field at the central portion of the PN junction is sufficiently intense so that the avalanche can be triggered by a single photo-generated charge, for example is greater than 300 kV / cm over a distance of 100 nm to 500 nm in a direction orthogonal to the PN junction, and so that the electric field at the upper and lower portions of the PN junction is sufficiently weak so that the avalanche cannot be triggered by a single photo-generated charge, for example is less than 300 kV / cm. For example, the breakdown voltage (or avalanche voltage) of the diode is between 10 V and 50 V (in absolute value), and the reverse bias voltage of the photodiode is higher than its breakdown voltage by a value between 0.5 and 10 V (in absolute values).The concentration of doping impurities of the substrate 30 is for example between 5.1016 cm 3 and 7.1017 cm 3. The concentration of doping impurities of the semiconductor region 31 is for example between 1017 cm 3 and 1019 cm 3. The concentration of doping impurities of the first and second electric field reduction layers 34-35 is for example less than 5.1016 cm 3.

[0062] The first and second electric field reduction layers 34-35 reduce the risk of untimely triggering of the avalanche at the ends of the PN junction, this risk being linked to edge effects such as the presence of defects on the surface of the semiconductor material. These layers are however optional, other solutions may be provided to control the risk of untimely triggering of the avalanche linked to edge effects, for example by varying the shape of the upper and lower ends of the semiconductor region 31, or by reducing the doping level of the semiconductor region 31 at its upper and lower ends.

[0063] The passivation structure 32 makes it possible to passivate the defects caused by the etching of the first trench 33, by forming a first layer of accumulation of electric charges in the semiconductor region 31, at the interface with the first trench 33. These electric charges have a polarity corresponding to the type of conductivity of the semiconductor region 31, i.e. the second type of conductivity. It is therefore a true accumulation layer, and not an inversion layer as in the avalanche photodetector of the prior art. In the example illustrated by [Fig.4], the semiconductor region 31 is N-doped and the accumulated charges are therefore electrons.

[0064] The electrical charges come from the surface contact. The accumulation layer allows good electrical continuity between the contact and the rest of the semiconductor region 31 to ensure static but also dynamic balance during avalanche phases.

[0065] The defects are rendered inactive and the electric field at the first trench 33 is reduced. The dark current of diode 3 is therefore reduced compared to a diode without a capacitive passivation structure, like that of [Fig. 1].

[0066] The first trench 33 has a bottom and a peripheral lateral surface. The bottom of the first trench 33 is here formed by the second electric field reduction layer 35. The peripheral lateral surface of the first trench 33 is formed, at least in part, by the semiconductor region 31.

[0067] However, in the embodiments of Figures 3, 5 and 6, the semiconductor region 31 and the first trench 33 are arranged so that the peripheral lateral surface of the first trench 33 is entirely constituted by the semiconductor region 31.

[0068] The peripheral lateral surface of the first trench 33 is thus passivated, at least in part, thanks to the first charge accumulation layer. In addition to reducing the dark current, this passivation makes it possible to bring the PN junction closer to the first trench 33 (without risk of activating the defects) and therefore, more generally, to reduce the lateral dimensions of the diode 3. This reduction in the size of the diode 3 proves to be particularly interesting with a view to forming a photodetector comprising a matrix of diodes.

[0069] The passivation structure 32 may occupy the entirety of the first trench 33, as in the embodiments of FIGS. 5 and 6, or only a portion of the first trench 33, as in the embodiment of [Fig. 3] (where the second contacting zone 372 occupies the upper portion of the first trench 33).

[0070] The passivation structure 32 can adopt different configurations.

[0071] In the embodiment of [Fig.3], the passivation structure 32 comprises a first dielectric layer 321 and a first electrically charged layer 322 separated from the semiconductor region 31 by the first dielectric layer 321.

[0072] The first dielectric layer 321 covers the peripheral lateral surface of the first trench 33 and, advantageously, the bottom of the first trench 33. It is preferably formed from an oxide, for example silicon dioxide (SiO2).

[0073] The first charged layer 322 contains electrical charges of polarity opposite to those desired in the semiconductor region 31. It is preferably formed of a dielectric material, for example silicon nitride (Si3N4) in the case of a positively charged layer, alumina (A12O3) or tantalum pentoxide (Ta2O5) in the case of a negatively charged layer. The surface density of electrical charges of the first charged layer 322 at the interface with the first dielectric layer 321 is preferably greater than 1012 cm 2.

[0074] The first charged layer 322 advantageously occupies the remaining part of the first trench 33. It thus constitutes the heart of the passivation structure 32, whereas the first dielectric layer 321 constitutes the envelope of the passivation structure 32.

[0075] An advantage of this embodiment is that the passivation structure 32 does not require electrical contact on the front face of the substrate 30, which makes it possible to form instead the second contact pad 362 and the second contact making zone 372 (see [Fig. 3]). The diode 3 can then have a symmetrical configuration with respect to the passivation structure 32. Forming the second contact making zone 372 in the first trench 33 limits the extent of the contacts on the useful surface of the diode 3, which tends to avoid electric field peaks and therefore untimely triggering of the avalanche on the surface.

[0076] In the embodiment of [Fig. 5], the passivation structure 32 comprises the first dielectric layer 321 described previously and an electrode 322' separated from the semiconductor region 31 by the first dielectric layer 321, in the manner of a MOS (metal-oxide-semiconductor) gate structure. The electrode 322' is an electrically conductive layer, for example made of doped polycrystalline silicon or metal. In a manner similar to the embodiment of [Fig. 3], the first dielectric layer 321 and the electrode 322' may respectively constitute the envelope and the core of the passivation structure 32.

[0077] During operation of the diode 3, a voltage is applied between the electrode 322' and the semiconductor region 31 (in addition to the bias voltage of the PN junction) in order to form the first charge accumulation layer. To do this, the diode 3 comprises a third contact pad 363 electrically connected to the electrode 322' of the passivation structure 32. This third contact pad 363 is preferably arranged on and in contact with the upper face of the electrode 322'. It is advantageously located at the same level as the first and second contact pads 361-362.

[0078] In a manner common to the embodiments of Figures 3 and 5, the semiconductor region 31 is ring-shaped (or tube-shaped) and the passivation structure 32 occupies the interior space of this ring. In other words, the semiconductor region 31 surrounds the passivation structure 32. The interior lateral surface of the semiconductor region 31, in contact with the passivation structure 32, is therefore peripheral. The ring formed by the semiconductor region 31 preferably has a rectangular section (in the section plane of the figures) and a central axis substantially perpendicular to the first face 30a.

[0079] Furthermore, the semiconductor region 31 and the passivation structure 32 are themselves surrounded by a region 30' called the active region of the substrate 30. The lateral surface 31c of the semiconductor region 31, external and in contact with the active region 30' of the substrate 30, is therefore peripheral. The active region 30' of the substrate 30 is intended to the absorption of photons.

[0080] The semiconductor region 31 and the passivation structure 32 are advantageously arranged in the center of the active region 30' of the substrate 30.

[0081] Furthermore, the diode 3 advantageously comprises a peripheral insulation structure 38 delimiting the active region 30' of the substrate 30. The peripheral insulation structure 38 extends in the substrate 30 from the first face 30a towards the second face 30b, preferably in a direction substantially perpendicular to the first face 30a. It advantageously passes through the substrate 30.

[0082] The peripheral insulation structure 38 may also extend through the first electric field reduction layer 34 and / or the second electric field reduction layer 35, as illustrated in the figures.

[0083] The peripheral insulation structure 38 is advantageously arranged inside a second trench 39 and configured to form, by capacitive effect, a second layer of accumulation of electric charges in the substrate 30, at the interface with this second trench 39. Thus, the defects generated by the etching of the second trench 39, for the purposes of electrical and / or optical insulation of the diode 3, are passivated. In the example illustrated by [Fig.4], the substrate 30 is P-doped, the accumulated charges are therefore holes.

[0084] Such a peripheral isolation structure 38 may be called a capacitive deep trench isolation structure or CDTI structure (for “capacitive deep trench isolation” in English).

[0085] Similarly to the passivation structure 32, the peripheral insulation structure 38 may comprise: • a second dielectric layer 381 (preferably made of an oxide such as SiO 2); and • a second electrically charged layer 382 (preferably made of a dielectric such as Si3N4, Al2O3 or Ta2O5) or a second electrode 382' (made of metal or doped polysilicon) separated from the active region 30' of the substrate 30 by the second dielectric layer 381.

[0086] The second trench 39 has an annular shape (to surround the active region 30' and the semiconductor region 31). The second dielectric layer 381 covers a peripheral lateral surface of the second trench 39, formed by the active region 30' of the substrate 30. The second electrically charged layer or the second electrode occupies all or part of the remainder of the second trench 39.

[0087] The peripheral insulation structure 38 may further comprise a layer of opaque material 383 separated from the active region 30' by the second electrically charged layer 382 or the second electrode 382' and the second dielectric layer 381. This layer of opaque material 383, preferably made of metal, makes it possible to make opaque the peripheral isolation structure 38, thus preventing photons emitted in the avalanche zone of the diode 3 from propagating to one or more neighboring diodes 3 and triggering an avalanche there. Thus, the peripheral isolation structure 38 is configured to reduce optical crosstalk, in addition to limiting leakage of electrical charges (electrical isolation). A layer of opaque material designates a layer whose transmission factor is less than 20% for wavelengths between 400 nm and 1100 nm.

[0088] Alternatively, the peripheral isolation structure 38 may be a deep trench isolation structure, or DTI structure (for “deep trench isolation” in English), in other words a structure devoid of the functions of passivation of the sides of the diode 3 by capacitive effect and of limitation of optical crosstalk.

[0089] [Fig.6] represents an embodiment of the diode 3 in which the structure of capacitive passivation 32 (arranged inside the first trench 33) and the semiconductor region 31 both have an annular (or tubular) shape. The passivation structure 32 surrounds the semiconductor region 31 which itself surrounds the active region 30' of the substrate 30. In other words, the passivation structure 32 is not located in the center of the diode 3, but at its periphery. The passivation structure 32 is then referred to as peripheral.

[0090] The peripheral passivation structure 32 may comprise, in a manner analogous to the embodiment of [Fig. 3], the first dielectric layer 321 and the first electrically charged layer 322 (separated from the semiconductor region 31 by the first dielectric layer 321). Advantageously, it further comprises a layer of opaque material 323 separated from the semiconductor region 31 by the first electrically charged layer 322 and the first dielectric layer 321, to reduce optical crosstalk with one or more neighboring diodes.

[0091] The peripheral passivation structure 32 may alternatively comprise the first dielectric layer 321 and the first electrode 322', as in the embodiment of [Fig.5]. Optical crosstalk between neighboring diodes is then reduced by choosing an opaque (conductive) material (such as a metal) to form the first electrode 322'.

[0092] In both cases, the peripheral passivation structure 32 then fulfills the function of electrical insulation of the peripheral insulation structure 38 described in relation to FIGS. 3 and 5 and, advantageously, the function of limiting optical crosstalk (in the presence of a layer of opaque material).

[0093] This embodiment has the advantage of only having to form one (annular) trench, instead of two.

[0094] The diode 3 may here comprise only a single first contact pad 361 electrically connected to the substrate 30, preferably via a first zone of contact point 371. This first contact pad 361 is advantageously located in the center of the upper face of the diode 3 (upper face of the first electric field reduction layer 34 or upper face of the active portion of the substrate 30).

[0095] Several diodes 3 according to any one of the embodiments described above can be combined in a photodetector, in the form of a matrix. Each diode 3 then forms a pixel of the matrix, called a SPAD pixel. The different diodes 3 share the same substrate 30. Each diode 3 comprises an active region 30' of the substrate 30, a semiconductor region 31 in contact with this active region 30' (thus forming the PN junction) and a capacitive effect passivation structure 32. The active region 30' of the substrate 30 is delimited either by the peripheral insulation structure 38 of FIGS. 3 and 5, or by the peripheral passivation structure 32 of [Fig. 6]. Two neighboring pixels (in a row or a column of the matrix) can share a portion of the opaque material layer 323, 383 fulfilling the optical insulator function.

[0096] [Fig.7] represents, in top view, an example of a photodetector comprising a matrix of 3 diodes or SPAD pixels, here 4 in number. The diodes 3 are in this example in the configuration described in relation to [Fig.3]. The active region 30' preferably has a square shape in top view and measures for example between 2 pm and 6 pm on each side. Each diode 3 comprises four first semiconductor zones 731 (and four first contact pads) located in the four corners of the active region 30', in order to standardize the electric field and the collection of charges.

[0097] In addition to the diode matrix 3, the photodetector may comprise a circuit for biasing the diodes 3 (at a voltage higher than their avalanche voltage), a reading circuit configured to detect the avalanche of one or more diodes 3 (and in particular a voltage pulse generated at the output of the diode), as well as a quenching circuit having the function of interrupting the avalanche of the diode(s) once it has been triggered. These additional circuits have not been shown in the figures and will not be detailed, the embodiments of the diode described above being compatible with the additional circuits equipping known SPAD photodetectors.

[0098] For diodes 3 according to [Fig.3] or [Fig.5], the reading circuit and the extinction circuit are advantageously electrically connected to the second contact pad 362 (or to the second contact making zone 372) of each diode 3, and therefore to the semiconductor region 31, because the semiconductor region 31 constitutes the electrode which has the lowest capacitance, due to its smaller surface area in relation to the other electrode or doping zones of the diode. For diodes 3 according to [Fig.6], the reading circuit and the extinction circuit are advantageously electrically connected to the first contact pad 361 (or to the first contact area 371) of each diode 3.

[0099] The ancillary circuits of the photodetector can be assembled in an integrated circuit in CMOS technology (for “complementary metal oxide semiconductor” in English). This integrated circuit is advantageously glued to the diode matrix 3, preferably on the front face of the substrate 30 (for illumination of the diodes on the rear face).

[0100] A method of manufacturing the diode 3 will now be described. Figures 8A to 81 schematically represent in sectional view the steps S1 to S9 of a preferred embodiment of the manufacturing method making it possible to obtain the diode 3 of [Fig.3].

[0101] [Fig.8A] represents a step S1 of etching the first trench 33 in the substrate 30, through an etching mask 80. The first trench 33 has for example a diameter between 250 nm and 1 pm and a depth between 5 pm and 25 pm. The etching mask 80 is preferably a hard mask, for example made of oxide.

[0102] The first trench 33 is preferably etched from the upper face of a stack comprising the first electric field reduction layer 34, the substrate 30 and the second electric field reduction layer 35 (not shown). The stack may also comprise a support layer / substrate (not shown), from which the other layers 34, 30, 35 are formed, for example by epitaxy. The first trench 33 passes through the first electric field reduction layer 34, the substrate 30 and is interrupted on or in the second electric field reduction layer 35.

[0103] Steps S2 and S3 of FIGS. 8B and 8C relate to the formation of the semiconductor region 31, from the first trench 33.

[0104] In step S2 of [Fig.8B], a doped semiconductor layer 81 (of the second conductivity type) is formed by epitaxy on at least part of the peripheral lateral surface of the first trench 33, and preferably on the entire peripheral lateral surface of the first trench 33. Advantageously, the etching mask 80 is kept at this step to prevent the growth of the doped conductive layer 81 on the upper face of the stack (this is then referred to as selective epitaxy). The doped semiconductor layer 81 has, for example, a thickness of between 50 nm and 200 nm. Its concentration of doping impurities is advantageously less than 5.1019 cm 3 to avoid obtaining too strong an electric field in the PN junction.

[0105] Then, in step S3 of [Fig.8C], diffusion annealing is performed to diffuse the doping impurities of the doped semiconductor layer 81 laterally in the substrate 30, thus obtaining the semiconductor region 31. Preferably, the doping impurities are diffused over a distance d of between 100 nm and 1 pm, this distance being measured from the peripheral lateral surface of the first trench 33.

[0106] Thus, when the doped semiconductor layer 81 covers the entire peripheral lateral surface of the first trench 33, the semiconductor region 31 is in the form of a ring around the first trench 33 (this ring having a section of width l=d between 100 nm and 1 pm).

[0107] Diffusion annealing is preferably carried out at a temperature between 800°C and 1100°C. Its duration may be between 10 s and 90 min.

[0108] The diffusion annealing has the effect of smoothing the doping of the semiconductor region 31 to soften the electric field (thus avoiding the band-to-band tunnel effect) and of moving the depletion zone of the PN junction away from the etching zone of the first trench 33.

[0109] In an alternative implementation of steps S2 and S3, the semiconductor region 31 is formed by gas-phase diffusion doping, from the lateral surface of the first trench 33.

[0110] [Fig.8D] represents an optional step S4 of the manufacturing method, consisting in forming, at the interface between the semiconductor region 31 and the first trench 33, an additional doped semiconductor layer 82 (called interface layer), in order to reinforce the passivation of the defects caused by the etching of the first trench 33 (said passivation being obtained by the first charge accumulation layer formed thanks to the passivation structure 32). The additional doped conductive layer 82 has for example a thickness of between 25 nm and 200 nm. Its concentration of doping impurities is advantageously greater than or equal to 5.1018 cm3.

[0111] Steps S5 and S6 of FIGS. 8E and 8F relate to the formation of the capacitive effect passivation structure 32.

[0112] In step S5 of [Fig.8E], the first dielectric layer 321 is formed on said at least part of the peripheral lateral surface of the first trench 33, and preferably on the entire peripheral lateral surface of the first trench 33. The first dielectric layer 321 is preferably formed by thermal oxidation of the material of the semiconductor region 31. Its thickness is for example between 1 nm and 5 nm.

[0113] Then, in S6 (cf. [Fig.8F]), the remaining part (the core) of the first trench 33 is filled with an electrically charged material to form the first charged layer 322. The technique used may be atomic layer deposition (or ALD), which is a conformal deposition technique.

[0114] After removal of the etching mask 80, the passivation structure 32 is finished and can be used as is. The method then subsequently comprises a step of forming the second contact zone 372 in the semiconductor region 31.

[0115] It is however possible to go further in the integration to minimize the surface area occupied on the surface of the diode, by forming the second contact zone 372 in the first trench 33.

[0116] Steps S7 to S9 of figures 8G to 81 thus relate to the formation of the second contact zone 372 at the top of the first trench 33.

[0117] After step S6 of filling the first trench 33 with the electrically charged material, the method comprises a step S7 represented by [Fig.8G] and consisting of etching an upper portion of the first charged layer 322 (this is called partial withdrawal, or “recess” in English). The etched portion of the first charged layer 322 may have a thickness of between 50 nm and 200 nm. The etching of the first charged layer 322 is preferably selective with respect to the first dielectric layer 321.

[0118] Then, in S8 (cf. [Fig.8H]), the first dielectric layer 321 is etched in the upper part of the first trench 33, until exposing (a part of) the lateral surface of the semiconductor region 31. The etching of the first dielectric layer 321 is preferably selective with respect to the semiconductor region 31. Advantageously, the hard mask 80 is removed simultaneously (the first dielectric layer 321 and the hard mask 80 may in particular both be made of an oxide, such as SiO2).

[0119] Finally, in S9 (cf. [Fig.81]), a doped semiconductor material (such as doped polycrystalline silicon) is deposited in the upper part of the first trench 33 (emptied of the electrically charged material), so as to plug the first trench 33 and form the second contacting zone 372. The doped semiconductor material can be deposited so as to form a flat surface with the upper face of the stack (or the upper face of the substrate, in the absence of the first electric field reduction layer 34). Alternatively, the deposition can form an excess thickness on the upper face of the stack, in which case a planarization operation (for example by chemical-mechanical polishing) is implemented to obtain a flat surface with the upper face of the stack.

[0120] The diode 3 of [Fig.5] may be manufactured by replacing the electrically charged material with an electrically conductive material (e.g., metal, doped polysilicon) to form the electrode 322' in step S6 of [Fig.8F] and omitting subsequent steps S7-S9. As a replacement, the method will include a step of forming the second contacting area 372 in the semiconductor region 31, by example by implantation of doping impurities.

[0121] The semiconductor region 31 and the capacitive effect passivation structure 32 (obtained using any of the methods described above) together form a structure known as a diffused capacitive deep trench or CDTC (for “diffused capacitive deep trench” in English).

Claims

Claims

1. A single-photon avalanche diode (3) comprising: - a semiconductor substrate (30) doped with a first conductivity type and having a first face (30a) and a second face (30b) opposite the first face; - a semiconductor region (31) doped with a second conductivity type opposite the first conductivity type, extending in the semiconductor substrate (30) from the first face (30a) towards the second face (30b);and - a capacitive effect passivation structure (32) arranged inside a first trench (33) which extends in the semiconductor substrate (30) from the first face (30a) towards the second face (30b), the capacitive effect passivation structure (32) extending in contact with the semiconductor region (31) and being configured to form a first electric charge accumulation layer in the semiconductor region (31) at the interface with the first trench (33).;

2. The diode (3) of claim 1, wherein the capacitive passivation structure (32) comprises a first dielectric layer (321) and a first electrically charged layer (322) separated from the semiconductor region (31) by the first dielectric layer (321).

3. The diode (3) of claim 1, wherein the capacitive passivation structure (32) comprises a first dielectric layer (321) and an electrode (322') separated from the semiconductor region (31) by the first dielectric layer (321).

4. A diode (3) according to any one of claims 1 to 3, further comprising a peripheral insulation structure (38) delimiting an active region (30') of the semiconductor substrate (30), the peripheral insulation structure (38) extending into the semiconductor substrate (30) from the first face (30a) towards the second face (30b).

5. A diode (3) according to claim 4, wherein the peripheral insulation structure (38) is disposed within a second trench (39) and configured to form a second electric charge accumulation layer in the semiconductor substrate (30) at the interface with the second trench (39).

6. The diode (3) of claim 5, wherein the peripheral insulation structure (38) comprises a second dielectric layer (381) and a second electrically charged layer (382) separated from the active region (30') of the semiconductor substrate (30) by the second dielectric layer (381).

7. The diode (3) of claim 6, wherein the peripheral insulation structure (38) further comprises a layer of opaque material (383) separated from the active region (30') of the semiconductor substrate (30) by the second electrically charged layer (382) and the second dielectric layer (381).

8. Diode (3) according to any one of claims 1 to 7, in which the semiconductor region (31) surrounds the capacitive passivation structure (32).

9. Diode (3) according to any one of claims 1 to 3, in which the capacitive effect passivation structure (32) surrounds the semiconductor region (31) which itself surrounds an active region (30') of the semiconductor substrate (30).

10. Diode (3) according to claim 9, in which the capacitive effect passivation structure (32) comprises a layer of opaque material (323).

11. A diode (3) according to any one of claims 1 to 10, further comprising a contacting area (372) of the semiconductor region (31), the contacting area (372) being arranged on the capacitive passivation structure (32) in the first trench (33).

12. A method of manufacturing a single-photon avalanche diode (3), comprising the following steps: - etching a first trench (33) in a semiconductor substrate (30) doped with a first conductivity type and having a first face (30a) and a second face (30b) opposite the first face, the first trench extending from the first face towards the second face; - forming a semiconductor region (31) doped with a second conductivity type opposite the first conductivity type, the semiconductor region (31) being delimited in part by the first trench (33) and extending into the semiconductor substrate (30) from the first face (30a) towards the second face (30b); - forming a capacitive effect passivation structure (32) in the first trench (33), the capacitive effect passivation structure (32) being configured to form a first electric charge accumulation layer in the semiconductor region (31) at the interface with the first trench (33).

13. The method of claim 12, wherein forming the semiconductor region (31) comprises the following substeps: - epitaxially forming a doped semiconductor layer (81) on a lateral surface of the first trench (33), the doped semiconductor layer (81) comprising doping impurities; and - performing diffusion annealing to laterally diffuse the doping impurities from the doped semiconductor layer (81) into the semiconductor substrate (30).

14. The method of claim 12, wherein the semiconductor region (31) is formed by gas-phase diffusion doping from a side surface of the first trench (33).

Images