Electronic chip manufacturing process

Abstract

Method for manufacturing electronic chips. This description relates to a method for manufacturing a passivated-sidewall electronic chip from a semiconductor substrate (110) having one face covered by connection pads (107) and in which chips are formed. The method comprises the following steps: - forming trenches or cavities between the chips, - depositing an insulating material (121) in the trenches or cavities, - separating the chips by cutting at least the insulating material (121). Figure for the abstract: Fig. 1C

Description

Title of the invention: Method for manufacturing electronic chips technical field

[0001] This description relates to the field of CSP ('Chip-Scale Package') type chips. It relates more particularly to a method for manufacturing bare chips ("bare dice" or "bare chip"). Previous technique

[0002] Bare chips comprise a substrate, made of a semiconductor-conductive material, in which electronic circuits have been fabricated. The substrate is covered by connection pads to allow the chip to be assembled, for example, with a printed circuit board. During chip assembly, the connection pads are soldered or brazed to traces or metallic elements of the printed circuit board. However, during assembly, the solder sometimes migrates up the sides of the chip. Since the sides of the chip are made of a semiconductor material, this can lead to a loss of electrical performance (short circuit, leakage current, etc.). Therefore, there is a need to prevent such phenomena.

[0003] Such chips are particularly interesting in many industrial fields, for example, in the automotive field. Summary of the invention

[0004] There is a need to improve at least in part certain aspects of known methods for manufacturing electronic chips. This goal is achieved by a method for manufacturing an electronic chip with passivated sides from a semiconductor substrate, one face of which is covered by connection pads and in which chips are formed, the method comprising the following steps: - forming trenches or cavities between the chips, - depositing an insulating material in the trenches or cavities, - separating the chips by cutting at least the insulating material.

[0005] According to a particular embodiment, trenches are formed, the trenches going from the first face of the substrate to a second face of the substrate.

[0006] According to a particular embodiment, cavities are formed by partially cutting the substrate from the first face, the depth of the cavities preferably being between 10 and 75% of the thickness of the substrate.

[0007] According to a particular embodiment, the width of the trenches or cavities is between 20 and 80 pm.

[0008] According to a particular embodiment, before the chip separation step, the process includes a step in which the substrate is thinned from a second face until the cavities are reached.

[0009] According to a particular embodiment, the insulating material comprises a polymer or a resin, preferably an epoxy or phenolic resin, and electrically insulating charges, for example alumina or silica particles.

[0010] According to a particular embodiment, the insulating material is deposited by inkjet printing.

[0011] This goal is also achieved by an electronic chip with passivated sides comprising a semiconductor substrate, having a first face covered by connection areas, a second face and sides, at least a part of the sides being formed of a layer of insulating material extending from the first face of the substrate.

[0012] According to a particular embodiment, the layer of insulating material goes from the first face to the second face.

[0013] According to a particular embodiment, a notch starting from the first face of the substrate is formed in the sides, the notch being filled by the layer of insulating material. Brief description of the drawings

[0014] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0015] [Fig.1A], [Fig.1B], [Fig.1C] and [Fig.1D] represent cross-sectional views illustrating steps in a manufacturing process for an electronic chip with passivated sidewalls according to a particular embodiment;

[0016] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] represent cross-sectional views illustrating steps in a manufacturing process for an electronic chip with passivated sidewalls according to another particular embodiment;

[0017] Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D and Fig. 3E represent cross-sectional views illustrating steps in a manufacturing process for an electronic chip with passivated sidewalls according to another particular embodiment. Description of the implementation methods

[0018] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0019] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0020] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0021] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0022] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0023] We will now describe in more detail the manufacturing process of an electronic chip (“bare dice” or “bare chip”) with passivated sidewalls by referring to figures IA to 1D, 2A to 2D and 3A to 3E.

[0024] The process comprises the following steps: a) provide a semiconductor substrate 110 of which a first face 111 is covered by connection areas 107 and in which chips 100 are formed (figures IA, 2A, 3A), b) form trenches or cavities 120 in the substrate 110 between the chips 100 (figures IB, 2B, 3B), c) deposit an insulating material 121 in the trenches or in the cavities 120 (figures IC, 2C, 3C), - possibly, perform a thinning step of substrate 110 on the back face ([Fig.3D]), d) separate the chips 100 by cutting through the layer of insulating material 121 (figures 1D, 2D, 3E).

[0025] With such a process, the sides 113 of the chips 100 obtained are passivated by means of an insulating layer 121. Potential contamination (due to a deficient assembly with the card) is thus avoided and there is no degradation of electrical performance.

[0026] In step a), the fabrication of the discrete component(s) and / or integrated circuit(s) is completed. The chips 100 are formed in the same substrate 110, and have not yet been individualized.

[0027] The substrate 110 comprises a first face 111 (upper face or front face or active face) and a second face 112 (lower face or rear face). The two Faces 111 and 112 are parallel to each other. They are connected to each other by lateral walls.

[0028] The substrate 110 is, for example, a semiconductor substrate, for example made of silicon. It can also be made of SiC.

[0029] The substrate 110 has, for example, a thickness between 100 and 900 pm, preferably between 300 and 900 pm, for example a thickness of about 725 pm.

[0030] One or more connection areas 107 (also called electrical contacts) are formed on the upper surface 111 of the substrate 110 of the electronic chip 100 and allow it to be connected to other elements (chips or printed circuit boards for example). Preferably, there are at least two connection areas.

[0031] The electrical connection pads 107 are, for example, at a distance of 10 to 30 pm from the side wall of the chip. The electrical connection pads 107 can be positioned on the upper face 111 of the chip 100 or be flush with the upper face 111 (i.e., level with the upper face 111 of the chip 100).

[0032] The electrical connection pads 107 are also called "UBM" (for the English expression "Under Bump Metallization"). The electrical connection pads 107 are made of a conductive material. The electrical connection pads 107 advantageously comprise at least one of the following elements: gold, titanium, nickel, copper, or tungsten. Preferably, they comprise gold.

[0033] The chip 100 may comprise one or more discrete components. The discrete component(s) may be chosen, for example, from transistors, diodes, thyristors, triacs, etc. The chip 100 may comprise one or more electronic circuits. The chip 100 allows for the implementation of various electronic functions.

[0034] The substrate provided in step a) is positioned on a support 200. The support 200 is adhesive.

[0035] In step b), the substrate 110 is cut at least partially between the chips 100 to form either cavities or trenches. The cavities or trenches 120 define the lateral contours of the chips 100. More specifically, the cavities or trenches 120 extend from the upper face 111 of the substrate 110.

[0036] According to a first embodiment, for example shown in Figures 1B and 3B, cavities 120 are formed. They have a depth less than the thickness of the substrate 110.

[0037] The depth of the cavities 120 is, for example, between 10 and 300 pm, preferably between 20 and 250 pm.

[0038] The depth of the cavities 120 is preferably between 10 and 75% of the thickness of the substrate 110. The depth of the trenches is adjustable according to the needs of the application.

[0039] The width of the cavities 120 is, for example, between 20 and 80 pm.

[0040] The bottom of the cavities can be flat or concave.

[0041] According to a second embodiment, for example shown in [Fig.2B], the trenches go all the way through the substrate 110, that is to say that the substrate 110 is cut from the first face 111 to the second face 112.

[0042] The width of the trenches 120 is, for example, between 20 and 80 pm.

[0043] This step b) is carried out using a cutting or engraving device. The cutting device is, for example, a mechanical cutting / engraving tool such as a saw, or a laser engraving tool. In a preferred embodiment, the cutting / engraving device is a laser.

[0044] To create trenches that pass completely through the substrate 110, it is possible to first perform a laser-induced dislocation cutting step (known as 'stealth diking') followed by an expansion step. The 'stealth diking' step involves using a specific laser to generate dislocations within the silicon substrate, in the cutting paths. These dislocations are defects present in the substrate's thickness which, under mechanical stress, allow the chips to be separated. The adhesive support 200 is then simply stretched to separate the chips and allow the insulating material to be deposited.

[0045] During step c), the trenches or cavities 120 are filled with an insulating material 121 from the front face 111.

[0046] The insulating material 121 is preferably deposited by inkjet printing using a nozzle 300. Several passes of the nozzle may be necessary to fill the trenches or cavities 120.

[0047] The insulating material is an electrically insulating material. More specifically, the insulating material comprises a base material (polymer or resin) and, preferably, electrically insulating particles. The resin is selected from the group comprising: epoxy resins, phenolic resins, and acrylic resins. The base material may be polyvinylpyrrolidone (PVP), a silicone (also called polysiloxane), a polyamic acid, or tripropylene glycol diacrylate (TPGDA). The particles are, for example, oxide particles, and in particular alumina or silica particles.

[0048] Preferably, the resin is a thermosetting or photosensitive (UV) resin. Such resins are very stable and resistant to many chemicals.

[0049] The polymerization of the resin is, for example, a UV polymerization step. It can also be carried out by heating or any other polymerization method chosen according to the nature of the material used.

[0050] An annealing step can be carried out after step c).

[0051] The process may also include a thinning step on the back face ([Fig. 3D]). This step is preferably carried out after step c). For this purpose, the structure is inverted and fixed by its front face 111 onto a support 201. The support 201 is, for example, a strip of adhesive tape. The structure is then thinned from its back face 112 so that the substrate 110 has its final thickness. When cavities have been formed in step b), the thinning step is preferably carried out in such a way as to thin the substrate 110 down to the cavities 120.

[0052] In step d), the chips 100 are separated. This singulation step can be carried out by cutting through the insulating material 121 ([Fig. 3E]) and, if necessary, also by cutting through the substrate 110 (Figures 1D, 2D). The cutting line is centered with respect to the cavities / trenches.

[0053] The cutting device is, for example, a mechanical engraving tool such as a saw, or a laser engraving tool. In a preferred embodiment, the cutting device is a laser.

[0054] The trench made in step d) has a width less than the trench or cavity made in step b). The trench is centered on the cavity made in step b).

[0055] At the end of the process, the resulting chips 100 have passivated sides 113. The passivation is due to the presence of the insulating material layer 121. The soldering materials do not wet the insulating material 121.

[0056] According to a first embodiment, only a portion of the flank 113 is passivated ([Fig. 1D]). The flanks comprise a first portion formed in the substrate 110, made of semiconductor material, and a second portion made of insulating material 121. The insulating material 121 is housed in a notch formed in the substrate 110. The notch is positioned at the intersection of the first face 111 and the flank 113. The notch extends from the first face 111 to the second face 112 in a plane perpendicular to both the first and second faces 112. A portion of the flank 113 is formed of insulating material 121, and a portion of the first face 111 is formed of insulating material 121.

[0057] According to a second variant, the entire flank 113 is passivated 2D, 3E).

[0058] With such a process the height of the sides 113 covered by the insulating material 121 can be easily adapted.

[0059] The chips 100 can then be fixed to an external device, for example, a printed circuit board or other component, by their upper face 111.

[0060] For this purpose, a soldering material is positioned between the chip 103 and the external device. During soldering, even if the soldering material rises along the wettable sides 113 of the chips 100, they will function correctly.

[0061] Such CSP-type electronic chips find applications in many industrial fields, and in particular, in the field of telephony, in the automotive field or the medical field.

[0062] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0063] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing electronic chips (100) with passivated flanks from a semiconductor substrate (110) having a first face (111) covered by connection pads (107) and in which chips (100) are formed, the method comprising the following steps: - forming cavities (120) between the chips (100), - depositing an insulating material (121) in the cavities (120), - separating the chips (100) by cutting through the insulating material (121) and the substrate (110), thereby only a part of the flanks (113) of the chips (100) is passivated, the flanks (113) comprising a first part formed in the substrate (110) and a second part formed of a layer of insulating material (121) extending from the first face (111) of the substrate (110).

2. A method according to claim 1, wherein cavities (120) are formed by partially cutting the substrate (110) from the first face (111), the depth of the cavities (120) preferably being between 10 and 75% of the thickness of the substrate (110).

3. A method according to any one of the preceding claims, wherein the width of the trenches or cavities (120) is between 20 and 80 pm.

4. A method according to any one of the preceding claims, wherein, prior to the chip separation step (100), the method comprises a step in which the substrate (110) is thinned from a second face (112) until the cavities (120) are reached.

5. A method according to any one of the preceding claims, wherein the insulating material (121) comprises a polymer or resin, preferably an epoxy or phenolic resin, and electrically insulating charges, for example, alumina or silica particles.

6. A method according to any one of the preceding claims, wherein the insulating material (121) is deposited by inkjet printing.

7. Electronic chip (100) with passivated sides comprising a semiconductor substrate (110), having a first face (111) covered by connection areas (107), a second face (112) and flanks (113), only a part of the flanks (113) of the electronic chip (100) being passivated, the flanks (113) comprising a first part formed in the substrate (110) and a second part formed of a layer of insulating material (121) extending from the first face (111) of the substrate (110).

8. Electronic chip (100) according to claim 7, wherein a notch starting from the first face (111) of the substrate (110) is formed in the sides (113), the notch being filled by the layer of insulating material (121).

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