Inductance

Abstract

Inductance The present description relates to an inductance (100) arranged in a stack of insulating and conductive levels, comprising: in a first zone of the stack, at least first (101) and second (102) turns arranged respectively in two distinct conductive levels of the stack; and in a second zone of the stack, at least third (103) and fourth (104) turns arranged respectively in two distinct conductive levels of the stack, in which the first, second, third and fourth turns are connected in series between first and second ends of the inductance, so that a current applied between the first and second ends of the inductance flows in a first direction of rotation in the first (101) and second (102) turns and in a second direction of rotation opposite to the first direction in the third (103) and fourth (104) turns. Figure for abstract: Fig. 2

Description

Title of the invention: Inductance Technical field

[0001] The present description relates generally to integrated electronic circuits and more particularly to an inductance structure formed on a substrate. Prior art

[0002] An induction coil or inductance is an electronic component comprising one or more conductive loops or turns connected in series between two connection terminals also called ends of the inductance. The inductance value, expressed in Henry, represents the capacity of the inductance to store energy in the form of a magnetic field when an electric current passes through it. The inductance value is higher the higher the number of turns of the inductance.

[0003] In microelectronics, the turns of an induction coil are materialized by conductive tracks in a stack of conductive and insulating levels coating a substrate.

[0004] The magnetic field generated by an inductor can cause unwanted coupling with neighboring electronic components. To limit this phenomenon, a planar eight-shaped inductor configuration has been proposed, making it possible to reduce the magnetic field seen by neighboring components. However, this solution requires a relatively large surface area.

[0005] There is therefore a need to design compact inductors with configurations that make it possible to reduce parasitic mutual inductance, i.e. coupling with other devices, while having a significant self-inductance. Summary of the invention

[0006] For this, one embodiment provides an inductance arranged in a stack of insulating and conductive levels, comprising: - in a first zone of the stack, at least first and second turns arranged respectively in two distinct conductive levels of the stack; and - in a second zone of the stack, at least third and fourth turns arranged respectively in two distinct conductive levels of the stack, wherein the first, second, third and fourth turns are connected in series between first and second ends of the inductor, such that a current applied between the first and second ends of the inductor flows in a first direction of rotation in the first and second turns and in a second direction of rotation opposite to the first direction in the third and fourth turns.

[0007] According to one embodiment, the first and fourth turns are in the same first conductive level and the second and third turns are in the same second conductive level, the first and second conductive levels being distinct.

[0008] According to one embodiment, the second turn and the third turn are joined and together define a conductive track having a figure-of-eight shape.

[0009] According to one embodiment, the first, second, third and fourth turns are connected in series, in this order, between the first and second ends of the inductor.

[0010] According to one embodiment, the first end of the inductor is connected to a first connection terminal of the inductor by at least one conductive track located in a third conductive level.

[0011] According to one embodiment, the first connection terminal of the inductor is arranged in the first conductive level.

[0012] According to one embodiment, the second end of the inductor is connected to a second connection terminal of the inductor by at least one conductive track located in a third conductive level.

[0013] According to one embodiment, the second connection terminal of the inductor is arranged in the first conductive level.

[0014] According to one embodiment, the midpoint of the inductor is connected to a third connection terminal of the inductor by at least one conductive track located in a third conductive level.

[0015] According to one embodiment, the third connection terminal of the inductor is arranged in the first conductive level.

[0016] According to one embodiment, the first and second turns are superimposed, and the third and fourth turns are superimposed.

[0017] Another embodiment provides an integrated circuit, comprising at least one inductor as defined above.

[0018] Another embodiment provides a voltage controlled oscillator, comprising at least one inductor as defined above. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] schematically represents, seen from above, conductive tracks of a example of an inductor according to one embodiment;

[0021] [Fig. 2] is a three-dimensional schematic view of the stack of conductive tracks of the inductor of [Fig. 1];

[0022] [Fig. 3] is a schematic view of a cross-section of the inductance of [Fig. 1] along the axis A1 of Figures 1 and 2; and

[0023] [Fig.4] represents a schematic view of a cross-section of the inductance of [Fig.l] along axis A2 of figures 1 and 2. Description of the embodiments

[0024] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed. In particular, the methods for manufacturing the described inductors have not been detailed, the described embodiments being compatible with the usual methods for manufacturing inductors in microelectronics or these methods being within the reach of the person skilled in the art from the indications of the present description.

[0026] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0029] In the remainder of the description, inductances formed in a circuit comprising a stack of insulating and conductive levels coating a substrate are considered. Other electronic components may also be integrated into the circuit and connected to the inductance by conductive tracks of the stack. Here, a conductive level is referred to as a set of conductive tracks defined in the same layer of a conductive material, for example a metal, for example copper. A turn of an inductance corresponds to one or more conductive tracks, of the same level conductor or different conductive levels, connected to each other so as to be electrically equivalent to a single track having the shape of a loop.

[0030] [Fig.l] schematically represents, seen from above, conductive tracks of an example of an inductor 100 according to an example of an embodiment.

[0031] [Fig.2] is a three-dimensional schematic view of the stack of conductive tracks of the inductor 100 of [Fig.l].

[0032] [Fig. 3] is a schematic view of a cross-section of the inductor 100 of [Fig. 1] along the axis A1 of FIGS. 1 and 2.

[0033] [Fig.4] represents a schematic view of a cross-section of the inductor 100 of [Fig.l] along the axis A2 of figures 1 and 2.

[0034] In the example of Figures 1 to 4, the inductor 100 is formed in a stack comprising, in this order from the upper face of a substrate (not visible in the figures) three conductive levels M1, M2, M3. The substrate is for example a substrate made of a semiconductor material, for example silicon, or of a dielectric material, for example glass. The conductive levels are separated two by two by electrically insulating layers, for example silicon oxide, in which conductive vias are formed, for example metal, for example copper, making it possible to electrically connect to each other conductive tracks of the levels M1, M2, M3.

[0035] [Fig.l] comprises three views (Ml), (M2), (M3) respectively representing the conductive tracks of the inductance formed in the level Ml, the conductive tracks of the inductance formed in the level M2, and the conductive tracks of the inductance formed in the level M3.

[0036] In this example, the inductance 100 comprises four turns 101, 102, 103, 104.

[0037] Level M2 comprises turns 101 and 104 of the inductor, and level M3 comprises turns 102 and 103 of the inductor.

[0038] The turns 101 and 102 are superimposed and arranged mainly in a first zone of the stack. By superimposed turns is meant here that, seen in the stacking direction of the layers, that is to say in a direction orthogonal to the substrate, the conductive tracks constituting the turns overlap. In other words, in projection in the stacking direction of the layers, the conductive tracks constituting the turns coincide over substantially their entire surface. As a variant, the turns 101 and 102 only partially overlap. In another variant, the turns 101 and 102 do not overlap.

[0039] The turns 103 and 104 are for example also superimposed and arranged mainly in a second zone of the stack, distinct from the first zone. As a variant, the turns 103 and 104 only partially overlap. In another variant, the turns 103 and 104 do not overlap.

[0040] By zone of the stack is meant a volume extending over several levels of the stack and by two distinct zones is meant two volumes which are mainly disjoint. In other words, the turns 103 and 104 are not superimposed on the turns 101 and 102, that is to say that they do not cover the turns 101 and 102.

[0041] In the example of figures 1 to 4, the turns 101, 102, 103 and 104 are connected in series, in this order, between a first end 123 and a second end 124 of the inductance.

[0042] The turns 101 to 104 are connected so that an electric current propagating from the end 123 to the end 124 of the inductance flows first through the first turn 101 in a first direction of rotation, for example counterclockwise, then through the second turn 102 in the same first direction of rotation, then through the third turn 103 in a second direction of rotation opposite to the first direction, for example clockwise, then through the fourth turn 104 in the same second direction of rotation. The direction of flow of the electric current in the inductance 100 is represented by arrows in Figures 1 and 2.

[0043] In the example of Figures 1 to 4, the turn 101 is constituted by a conductive track formed entirely in the level M2 and comprises a first end corresponding to the end 123 of the inductance, and a second end 127. The turn 102 is constituted by a conductive track formed entirely in the level M3 and comprises a first end 137 and a second end 136. The turn 103 is constituted by a conductive track formed entirely in the level M3 and comprises a first end corresponding to the end 136 of the turn 102, and a second end 138. The turn 104 is constituted by a conductive track formed entirely in the level M2 and comprises a first end 128 and a second end 124 corresponding to the second end of the inductance.

[0044] In the example of figures 1 to 4, the inductance comprises one or more conductive vias 147 extending in the insulating level separating the levels M2 and M3 and electrically connecting the second end 127 of the first turn 101 to the first end 137 of the second turn 102. More particularly, in this example, the vias 147 are in contact, by their lower face, with the upper face of the end 127 of the turn 101, and, by their upper face, with the lower face of the end 137 of the turn 102.

[0045] In the example of Figures 1 to 4, the inductor further comprises one or more conductive vias 148 extending in the insulating level separating the levels M2 and M3 and electrically connecting the second end 138 of the third turn 103 to the first end 128 of the fourth turn 104. More particularly, in this example, the vias 148 are in contact, by their lower face, with the upper face of the end 128 of the turn 104, and, by their upper face, with the lower face from end 138 of turn 103.

[0046] In this example, the inductor 100 comprises three terminals 121, 122 and 125 for connection to an external circuit. In the example shown, the connection terminals 121, 122, 125 are formed in the level M2.

[0047] The first terminal 121 is connected to the first end 123 of the inductor by at least one conductive track 106 of the level M1. The track 106 comprises a first end 111 and a second end 113. One or more conductive vias 141 extend into the insulating level separating the levels M1 and M2 and electrically connect the first end 111 of the track 106 to the terminal 121. More particularly, in this example, the vias 141 are in contact, by their lower face, with the upper face of the end 111 of the track 106, and, by their upper face, with the lower face of the terminal 121. In addition, one or more conductive vias 143 extend into the insulating level separating the levels M1 and M2 and electrically connect the second end 113 of the track 106 to the first end 123 of the inductor.More particularly, in this example, the vias 143 are in contact, by their lower face, with the upper face of the end 113 of the track 106, and, by their upper face, with the lower face of the end 123 of the inductor.

[0048] The second terminal 122 is connected to the second end 124 of the inductor by at least one conductive track 107 of the level ML. The track 107 comprises a first end 112 and a second end 114. One or more conductive vias 142 extend into the insulating level separating the levels M1 and M2 and electrically connect the first end 112 of the track 107 to the terminal 122. More particularly, in this example, the vias 142 are in contact, by their lower face, with the upper face of the end 112 of the track 107, and, by their upper face, with the lower face of the terminal 122. In addition, one or more conductive vias 142 extend into the insulating level separating the levels M1 and M2 and electrically connect the second end 114 of the track 107 to the second end 124 of the inductance.More particularly, in this example, the vias 144 are in contact, by their lower face, with the upper face of the end 114 of the track 107, and, by their upper face, with the lower face of the end 124 of the inductor.

[0049] The third terminal 125 is connected to the common end 136 of the turns 102 and 103, defining the midpoint of the inductance, by at least one conductive track 126 of the level M2 and at least one conductive track 108 of the level ML. The terminal 125 allows, for certain applications, to use the inductance in a differential mode. The track 108 comprises a first end 115 and a second end 116. One or more conductive vias 145 extend in the insulating level separating the levels M1 and M2 and electrically connect the first end 115 of the track 108 to the terminal 125. More particularly, in this example, the vias 145 are in contact, by their lower face, with the upper face of the end 115 of the track 108, and, by their upper face, with the lower face of the terminal 125. In addition, one or more conductive vias 146 extend into the insulating level separating the levels M1 and M2 and electrically connect the second end 116 of the track 108 to a conductive track 126 of the level M2, located directly above the midpoint 136 of the inductor. More particularly, in this example, the vias 146 are in contact, by their lower face, with the upper face of the end 116 of the track 108, and, by their upper face, with the lower face of the track 126.In addition, one or more conductive vias 149 extend into the insulating level separating levels M2 and M3 and electrically connect track 126 to midpoint 136 of the inductor. More particularly, in this example, the vias 149 are in contact, by their lower face, with the upper face of track 126, and, by their upper face, with the lower face of midpoint 136.

[0050] It will be noted that in the example shown, the inductor comprises, in the level M1, two conductive tracks 106 connected in parallel between the terminal 121 and the end 123 of the inductor. Furthermore, in this example, the inductor comprises, in the level M1, two conductive tracks 107 connected in parallel between the terminal 122 and the end 124 of the inductor. Furthermore, in this example, the inductor comprises, in the level M1, two conductive tracks 108 connected in parallel between the terminal 125 and the midpoint 136 of the inductor. The embodiments described are however not limited to this particular case. As a variant, the conductive tracks 106, 107 and / or 108 may be single tracks, or each comprise a number of parallel tracks greater than two.

[0051] The path traveled by an electric current between the end terminal 121 and the end terminal 122 of the inductor is for example the following.

[0052] The electric current enters the inductor 100 through the connection terminal 121, passes through the via(s) 141, then passes through the conductive track 106, from its end 111 to its end 113. The current then flows through the via(s) 143. The current then flows through the first turn 101 of the inductor from its end 123 to its end 127. The current then flows through the via(s) 147. The current then flows through the second turn 102 of the inductor from its end 137 to its end 136 and then through the third turn 103 of the inductor from its end 136 to its end 138. The current then flows through the via(s) 148 and then flows through the fourth turn 104 of the inductor from its end 137 to its end 136. end 128 to its end 124. The current then passes through the via(s) 144 then the conductive track 107, from its end 114 to its end 112. The current then passes through the via(s) 142 and spring of inductance 100 through connection terminal 122.

[0053] An advantage of the arrangement described in relation to Figures 1 to 4 is that it makes it possible to limit the parasitic mutual inductance with neighboring components. This is linked to the fact that a portion of the turns of the inductance, turns 101 and 102 in the example shown, is traversed by a current flowing in a first direction of rotation, while another portion of turns of the inductance, turns 103 and 104 in the example shown, is traversed by a current flowing in a second direction of rotation opposite to the first direction. The parasitic mutual inductance, seen by the neighboring components, is thereby reduced, without this reducing the self-inductance value, which is linked to the total number of turns of the inductance.

[0054] Compared to a planar figure-of-eight inductor arrangement, i.e. in which all the turns of the inductor are formed mainly in the same conductive level, an additional advantage is to reduce the overall size of the inductor.

[0055] Considering identical widths and thicknesses of conductive tracks, the arrangement described in relation to Figures 1 to 4 requires between 1.6 and 1.8 times less surface area than an inductor having a planar figure-eight arrangement to obtain a substantially equal self-inductance. For example, the arrangement described in relation to Figures 1 to 4 makes it possible to produce an inductance of approximately 0.8nH over a total surface area of ​​the order of 22000pm2, compared to approximately 40000pm2 with a planar figure-eight arrangement. According to another example, the arrangement described in relation to Figures 1 to 4 makes it possible to produce an inductance of approximately 1.1nH over a total surface area of ​​the order of 31000pm2, compared to approximately 51000pm2 with an inductor having a planar figure-eight arrangement. According to another example, the arrangement described in relation to figures 1 to 4 makes it possible to achieve an inductance of approximately 1.4nH over a total surface area of ​​about 38000pm2, compared to about 63000pm2 with a planar figure-of-eight arrangement.

[0056] Another advantage of the embodiment described in relation to figures 1 to 4 is that it allows contact to be made at the midpoint of the inductance, which allows the inductance to be used in differential mode.

[0057] Inductors of the type described in relation to Figures 1 to 4 can advantageously be used in many applications, for example in voltage controlled oscillators (VCOs), for example for radio frequency signal synthesis applications, for example in radio link telecommunication devices, for example mobile phones. The reduction of the parasitic mutual inductance between the inductor and neighboring components then makes it possible to synthesize more precise and more stable reference frequencies.

[0058] More generally, such inductors can be used in any circuit capable of benefiting from a reduction in the parasitic mutual inductance between the inductor and neighboring components.

[0059] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to the person skilled in the art. In particular, the embodiments described are not limited to the example described above of an inductor with four turns made in two conductive levels. More generally, the person skilled in the art will know how to adapt the proposed solution to inductors having a number of turns greater than four and / or a number of conductive levels greater than two for the production of the turns.

[0060] Furthermore, the general shape of the turns of the inductor may be different from that shown. More generally, the turns of the inductor may have any other shape, for example a general circular, square, rectangular shape, etc.

[0061] Furthermore, the described embodiments are not limited to the particular example described in relation to FIGS. 1 to 4 in which the inductor comprises a connection terminal at its midpoint. Alternatively, the connection terminal 125 at the midpoint 136 of the inductor may be omitted, in which case the inductor comprises only two connection terminals connected respectively to its two ends.

[0062] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Inductance (100) arranged in a stack of insulating and conductive levels, comprising: - in a first zone of the stack, at least first (101) and second (102) turns arranged respectively in two distinct conductive levels (M2, M3) of the stack; and - in a second zone of the stack, at least third (103) and fourth (104) turns arranged respectively in two distinct conductive levels (M3, M2) of the stack, in which the first, second, third and fourth turns are connected in series between first (123) and second (124) ends of the inductance, so that a current applied between the first and second ends of the inductance flows in a first direction of rotation in the first (101) and second (102) turns and in a second direction of rotation opposite to the first direction in the third (103) and fourth (104) turns.

2. Inductance according to claim 1, in which the first (101) and the fourth (104) turns are in the same first conductive level (M2) and the second (102) and the third (103) turns are in the same second conductive level (M3), the first and second conductive levels being distinct.

3. An inductor according to claim 2, wherein the second turn (102) and the third turn (103) are contiguous and together define a conductive track having a figure-of-eight shape.

4. An inductor according to any one of claims 1 to 3, wherein the first (101), second (102), third (103) and fourth (104) turns are connected in series, in that order, between the first (123) and second (124) ends of the inductor.

5. Inductor according to any one of claims 1 to 4, wherein the first end (123) of the inductor is connected to a first connection terminal (121) of the inductor by at least one conductive track (106) located in a third conductive level (Ml).

6. An inductor according to claim 5, wherein the first connection terminal (121) of the inductor is arranged in the first conductive level (M2).

7. An inductor according to any one of claims 1 to 6, in wherein the second (124) end of the inductor is connected to a second (122) connection terminal of the inductor by at least one conductive track (107) located in a third conductive level (Ml).

8. Inductor according to claim 7, wherein the second terminal (122) for connecting the inductor is arranged in the first conductive level (M2).

9. An inductor according to any one of claims 1 to 8, wherein the midpoint (136) of the inductor is connected to a third connection terminal (125) of the inductor by at least one conductive track (108) located in a third conductive level (Ml).

10. An inductor according to claim 9, wherein the third terminal (125) for connecting the inductor is arranged in the first conductive level (M2).

11. An inductor according to any one of claims 1 to 10, wherein the first (101) and second (102) turns are superimposed, and wherein the third (103) and fourth (104) turns are superimposed.

12. Integrated circuit, comprising at least one inductor (100) according to any one of claims 1 to 11.

13. Voltage controlled oscillator, comprising at least one inductor (100) according to any one of claims 1 to 11.

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