Fabrication of a POI structure with a highly uniform piezoelectric layer

Abstract

The present invention relates to a method of manufacturing a piezoelectric-on-insulator, POI, structure, comprising providing a donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises or is made of one of lithium tantalate and lithium niobate, transferring a piezoelectric layer from the piezoelectric substrate to a target substrate, and polishing the transferred piezoelectric layer to the target substrate with a chemical mechanical polishing, CMP, slurry, wherein the CMP slurry consists of an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon in the range of 4 to 18. Figure for abstract: Figure 2

Description

Title of the invention: Fabrication of a POI structure with a highly uniform piezoelectric layer

[0001] The present invention relates to the method for manufacturing piezoelectric on insulator (POI) structures, in particular POI structures usable for the manufacturing of microelectronic, micromechanical and photonic devices.

[0002] In the field of microelectronics, micromechanics and photonics, POI structures are of increasing importance for example due to superior sensitivity and information propagation properties. For example, sensors such as surface acoustic wave (SAW) sensors, or bulk acoustic wave (BAW) sensors using the piezoelectric effect to convert an electrical signal into a mechanical / acoustic wave offer particularly advantageous options due to a wide variety of measurable ambient parameters, including for example temperature, pressure, strain and torque.

[0003] A typical POI structure comprises a layer of piezoelectric material, in particular a single-crystal material such as, for example, lithium niobate (LiNbO3) or lithium tantalate (LiTaO3), on a support substrate made of, for example, silicon. Various methods for forming a thin layer of piezoelectric material on the support substrate are known in the art. The application of Smart Cut™ technology has proven particularly advantageous. According to this technology (see, for example, WO 2020 / 200986 A1), light species are implanted into a piezoelectric substrate formed on a support substrate to form a weakened region in the piezoelectric substrate, and then the piezoelectric substrate is bonded to a target substrate. Via fracturing at the weakened region, the thin layer of piezoelectric material can be obtained on the support substrate.The transferred piezoelectric material layer is subjected to an annealing process and then to a polishing process, in particular via chemical mechanical polishing, CMP, with the aim of improving the crystal quality and achieving the desired thickness uniformity of a monodomain layer of piezoelectric material with substantially all dipole moments aligned parallel to each other in a given direction.

[0004] However, despite recent technical progress, there is a risk that the thickness uniformity obtained from the transferred piezoelectric material layer may not be high enough to meet current application requirements.

[0005] Therefore, an object of the present invention is to provide a technique for manufacturing a POI structure (based on Smart Cut™ technology) with high thickness uniformity of the piezoelectric material layer.

[0006] The present invention achieves this object by providing a method of manufacturing a piezoelectric on insulator, POI, structure, comprising the steps of:

[0007] providing a donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises or consists of one of lithium tantalate (LiTaO3) and lithium niobate (LiNbO3);

[0008] transferring a piezoelectric layer from the piezoelectric substrate to a target substrate (e.g., a silicon substrate); and

[0009] polishing the transferred piezoelectric layer to the target substrate with a chemical mechanical polishing, CMP, slurry, wherein the CMP slurry consists of an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon in the range of 4 to 18.

[0010] The polishing step may be preceded by an annealing step in order to increase the crystalline quality and to consolidate the bonding between the piezoelectric layer and the target substrate. The amorphous silicon used for the CMP suspension may comprise or consist of precipitated amorphous silicon particles with diameters in the range of 40 to 60 nm.

[0011] It is known in the prior art to polish the transferred piezoelectric layer in order to remove a multi-domain top layer comprising a plurality of regions having different polarities and to increase the surface quality (reduce roughness) and thickness uniformity. However, in the prior art, a CMP slurry consisting of an aqueous suspension of amorphous silicon with a much higher weight percentage of the amorphous silicon, namely in the range of 25 to 35, is used for the polishing process of the transferred piezoelectric layer. The inventors of the present invention have surprisingly discovered that polishing the transferred piezoelectric layer with a significantly lower concentration of amorphous silicon in the CMP slurry results in better polishing results in terms of thickness uniformity of the finally obtained single-domain piezoelectric layer.

[0012] Other parameters of the entire manufacturing process may be chosen as is done in a customary manner known to those skilled in the art (see, however, the description below). Depending on the actual choice of the piezoelectric material and the values ​​of the other parameters, a weight percentage of the amorphous silicon in the range of 4 to 13, in particular 5 to 7, may be advantageous with respect to the resulting thickness uniformity of the finally obtained transferred piezoelectric layer.

[0013] According to one embodiment, the step of providing the donor substrate (pseudodonor, PSD) comprises bonding a block of piezoelectric material to a support substrate (manipulator) via a bonding layer, grinding and polishing the block of piezoelectric material to obtain the piezoelectric substrate and implanting a species (e.g. hydrogen) into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate. Thus, a donor substrate suitable for providing a high-quality piezoelectric layer on top of the weakened layer can be reliably manufactured. Bonding of the block of piezoelectric material to the support substrate can be promoted by a dielectric bonding layer, for example a photo (UV) polymer layer or a layer made of or comprising silicon oxide and / or silicon nitride.

[0014] The step of transferring the piezoelectric layer to the target substrate may comprise bonding the donor substrate to the target substrate (on the piezoelectric substrate side) and fracturing the piezoelectric substrate at the weakened layer in an annealing process. Thus, the piezoelectric layer can be reliably transferred to the target substrate without too heavy a defect. Additional post-processing (annealing and polishing) is, however, still required, as described above. It should be noted that naturally occurring silicon oxide may be present between the transferred piezoelectric layer and the target substrate. Furthermore, a dielectric bonding layer may be formed on or above a surface of the target substrate prior to transfer of the piezoelectric layer to that surface.This dielectric assembly layer may be made of or include silicon oxide and / or silicon nitride, or a stack of layers composed of these materials. Further, depending on the actual application, a charge trapping layer may be formed on or above a surface of the target substrate prior to transfer of the piezoelectric layer to this surface. The charge trapping layer may be made of or include polycrystalline silicon.

[0015] For the polishing process, the target substrate with the transferred piezoelectric layer is positioned on a rotating head and brought into contact with a rotating polishing pad. According to particular embodiments, the head is rotated 80 to 120 revolutions per minute (rpm), and the polishing pad is rotated in the same direction as the head at a different speed relative to the head in the range of 90 to 130 rpm. These parameter ranges may prove advantageous in terms of thickness uniformity of the resulting polished piezoelectric layer.

[0016] According to another embodiment, the wafer pressure applied to the target substrate to press it against a polishing pad is not greater than 20.68 kPa (3 psi) or less than 18.96 kPa (2.75 psi), for example in the range of 17.24 kPa (2.5 psi) to 20.68 kPa (3 psi). For example, the ratio of the wafer pressure to the ring pressure used to hold the target substrate in place in a ring retainer during the polishing process is in the range of 1:2 to 5:3. These parameter ranges can prove advantageous in terms of thickness uniformity of the resulting polished piezoelectric layer, especially in combination with the parameter ranges mentioned above.

[0017] According to another embodiment, the flow rate of the CMP suspension is less than 250 ml / minute or 200 ml / minute or 150 ml / minute, or is in the range of 150 ml / minute to 250 ml / minute. These parameter ranges may prove advantageous in terms of thickness uniformity of the resulting polished piezoelectric layer, particularly in combination with the parameter ranges mentioned above.

[0018] Further, a POI structure is provided, comprising a piezoelectric layer formed on or above a target substrate and obtainable by the method according to a certain of the examples described above, wherein the piezoelectric layer has a thickness uniformity (thickness range across the diameter of the layer) of less than 50 nm, in particular less than 20 nm. Further, a microelectronic, micromechanical or photonic device is provided, or a microelectromechanical system (MEMS) comprising such a POI structure.

[0019] Additional features and advantages of the present invention will be described with reference to the drawings. In the description, reference is made to the accompanying drawings, which are intended to illustrate preferred embodiments of the invention. It should be understood that such embodiments do not represent the full scope of the invention.

[0020] [Fig.l] illustrates the steps of a method of manufacturing a POI structure according to an embodiment of the present invention.

[0021] [Fig.2] illustrates the technical effect of obtaining a piezoelectric layer highly uniform resulting from a method of manufacturing a POI structure according to an embodiment of the present invention.

[0022] A method of manufacturing a POI structure is provided herein, comprising a target substrate on which a piezoelectric layer with high thickness uniformity is formed. The high thickness uniformity results from a polishing step performed with a relatively highly dilute aqueous suspension of amorphous silicon. The method utilizes Smart Cut™ technology.

[0023] [Fig.l] illustrates steps of a method of manufacturing a POI structure according to an embodiment of the present invention. The method is similar to a method described in WO 2020 / 200986 A1, but differs therefrom by the inventive method of polishing the transferred piezoelectric layer.

[0024] As shown in step i) of [Fig.l], a donor substrate 1 is provided, which comprises a piezoelectric substrate 1a formed on a support (manipulator) substrate 1b. The piezoelectric substrate 1a is made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3). The support substrate 1b may be made of a material (or a plurality of materials) having a coefficient of thermal expansion close to that exhibited by a target substrate 7, i.e., the coefficient of thermal expansion of the support substrate 1b differs from that of the target substrate 7 by less than the difference in the coefficient of thermal expansion of the piezoelectric substrate 1a and that of the target substrate 7. The support substrate 1b and the target substrate 7 may have identical coefficients of thermal expansion and both substrates may, for example, be made of or comprise silicon.Additionally, both substrates can have similar thicknesses.

[0025] In order to obtain the donor substrate 1, a solid block of piezoelectric material may first be attached to the support substrate 1b, for example using a molecular adhesion bonding technique. The bonding may be promoted by a dielectric bonding (adhesion) layer (not shown in [Fig.l]), for example a photo (UV) polymer layer or a layer made of or comprising silicon oxide and / or silicon nitride. The bonding process may comprise the application of a low-temperature heat treatment (for example at a temperature between 50 and 300°C, typically 100°C) to sufficiently enhance the bonding energy to enable the following thinning step. Then, the piezoelectric substrate 1a is formed by thinning, for example by chemical-mechanical grinding and / or polishing.

[0026] The thinning step is carried out in such a way that the piezoelectric substrate 1a has a sufficiently low thickness so that the stresses generated during the heat treatment applied in a subsequent treatment step are reduced. On the other hand, the thickness must be sufficiently high to provide the piezoelectric layer 3 which is to be transferred to the target substrate 7 or to provide a plurality of such layers which are to be transferred one after the other in multiple transfer steps (after respective regeneration of the donor substrate 1) to respective target substrates. The thickness of the piezoelectric substrate 1a may for example be between 5 and 400 pm, for example 20 pm or 100 pm.

[0027] Hydrogen (optionally supplemented with helium) is implanted ii) into the piezoelectric substrate 1a through the exposed surface 4 to generate a weakened layer 2 which marks the separation of the piezoelectric layer 3 from the remaining part 5 of the donor substrate 1. The nature and dose of the implanted species and the implantation energy can be chosen depending on the thickness of the piezoelectric layer 3 which is to be transferred to the target substrate 7 and the physico-chemical properties of the piezoelectric layer 3. chemical properties of the piezoelectric substrate 1a. For example, for a lithium tantalate substrate, a hydrogen ion dose of between 1016 and 5«1017 at / cm2 with an energy of between 30 keV and 300 keV can be implanted to delimit the piezoelectric layer 3 with a thickness of 200 nm to 2000 nm, for example.

[0028] According to the method illustrated in [Fig.2], the implantation step ii) is followed by the step of attaching iii) the donor substrate 1 to the support substrate 7 on the side of the piezoelectric substrate 1a by molecular adhesion and / or electrostatic bonding. A dielectric assembly layer 7b may be provided between the piezoelectric substrate 1a of the donor substrate 1 and the target substrate 7. The dielectric assembly layer 7b may comprise an oxide and may be made of or comprise silicon oxide and / or silicon nitride or a stack of layers composed of these materials. Furthermore, a charge trapping layer, for example made of or comprising polycrystalline silicon, may be formed on or above the target substrate 7 in order to improve the electrical resistivity thereof if this is desired by an actual application.

[0029] The piezoelectric layer 3 is then detached from the remaining portion 5 of the donor substrate 1 to obtain iv) a POI structure 9 comprising the target substrate 7, the dielectric assembly layer 7b (if any) and the piezoelectric layer 3. Detachment at the weakened layer 2 is facilitated by heat treatment in a temperature range of about 100°C to 600°C to allow transfer of the piezoelectric layer 3 to the target substrate 7. Alternatively or additionally, detachment at the weakened layer 2 may be facilitated by the application of a blade or jet of gaseous or liquid fluid, or any other mechanical force applied to the weakened layer 2.

[0030] A post-treatment of the transferred piezoelectric layer 3 is necessary to obtain a transferred piezoelectric layer 3 having a satisfactory single-domain crystalline and surface quality (reduced roughness) and a thickness uniformity as required by real applications. The post-treatment comprises a heat treatment v) of the piezoelectric layer 3 for example at approximately 500°C in a neutral atmosphere or an atmosphere comprising oxygen. This heat treatment makes it possible to treat crystalline defects present in the piezoelectric layer and consolidates the bonding between the piezoelectric layer 3 and the target substrate 7.However, the heat treatment causes diffusion of the hydrogen contained in the piezoelectric layer 3, in particular in its upper part (with a thickness of about 50 nm or less, for example), and consequently the generation of a plurality of ferroelectric domains giving the upper part a multi-domain character. In fact, the hydrogen implanted in the piezoelectric substrate during the step of defining the piezoelectric layer. 3 above the weakened layer 2 is distributed in this substrate according to a profile having a concentration peak at the weakening plane 2. After fracturing at the weakened layer 2, the piezoelectric layer 3 transferred to the target substrate 7 therefore has a significant concentration of hydrogen and the heat treatment leads to the generation of multiple domains, i.e. a plurality of regions having different polarities. The performance of devices which are intended to be formed on / in the piezoelectric layer 3 would be strongly affected by such multiple domains.

[0031] In order to remove the multiple upper domains and increase the surface quality and thickness uniformity of the transferred piezoelectric layer 3, the post-processing comprises polishing the exposed surface of the piezoelectric layer 3 (see step vi) in [Fig.l]). For example, 100 to 300 nm of the upper portion of the piezoelectric layer 3 may be removed by the polishing process to achieve a predetermined target thickness, for example, about 600 nm.

[0032] According to the invention, the piezoelectric layer 3 is polished by CMP using a relatively highly diluted CMP suspension. Typically, an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon of 25 to 35 is used for the post-treatment CMP step following the thermal annealing of the transferred piezoelectric layer. According to the invention, an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon in the range of only 4 to 18, in particular in the range of 4 to 13, more particularly in the range of 5 to 7, is used as the CMP suspension. Further parameters of the entire manufacturing process can be chosen in a typical manner that is known to those skilled in the art.A single-domain piezoelectric layer, in which substantially all dipole moments are aligned parallel to each other in a given direction, can thereby be formed on the target substrate 7, providing both the required thickness uniformity and surface and crystal qualities.

[0033] For the polishing process, the target substrate 7 with the transferred piezoelectric layer 3 is positioned on a rotating head and brought into contact with a rotating polishing pad. It may be preferred to use a “single-zone” head with a single holding ring retainer rather than a “multi-zone” head which has multiple ring retainers with varying pressures applied. For example, during the polishing process, the head is rotated 80 to 120 revolutions per minute (rpm) and the polishing pad is rotated in the same direction as the head at a different speed compared to the head in the range of 90 to 130 rpm. For example, the head may be rotated at 75 rpm, and the polishing pad may be rotated at 100 rpm. The speed of a Reconditioning brush can be chosen similar to that of the polishing head or pad.

[0034] The wafer pressure applied to the target substrate to press it against the polishing pad may be chosen to be no greater than 20.68 kPa (3 psi) or less than 18.96 kPa (2.75 psi), for example in the range of 17.24 kPa (2.5 psi) to 20.68 kPa (3 psi). For example, the ratio of wafer pressure to ring pressure used to hold the target substrate in place in a ring retainer during the polishing process is in the range of 1:2 to 5:3. The flow rate of the CMP slurry may be chosen to be less than 250 ml / minute or 200 ml / minute or 150 ml / minute, or may be chosen in the range of 150 ml / minute to 250 ml / minute.

[0035] The CMP suspension used according to the invention can be prepared by diluting a commercially available CMP suspension. For example, Klebosol® 30HB50 can be diluted with water to obtain a CMP suspension with a weight percentage of amorphous silicon in the range of 4 to 18, particularly in the range of 4 to 13, more particularly in the range of 5 to 7. Klebosol® 30HB50 has amorphous silicon for 25 to 35% by weight, and an average diameter of the precipitated amorphous silicon particles of 50 nm. Assuming a dilution of 35% by weight of amorphous silicon by adding 1 part of water to 1 part of Klebosol® 30HB50 (1:1 dilution), the result is a CMP suspension containing 17.5% by weight of amorphous silicon.A 1:4 dilution of Klebosol® 30HB50 having 25% by weight amorphous silicon gives a CMP suspension having 5% by weight amorphous silicon and a 1:4 dilution of Klebosol® 30HB50 having 35% by weight amorphous silicon gives a CMP suspension having 7% by weight amorphous silicon.

[0036] [Fig.2] illustrates examples of results for the obtained thickness uniformity (thickness range) of the piezoelectric layer of the POI structure after CMP of the piezoelectric layer made of lithium tantalate with a CMP suspension obtained by diluting Klebosol® 30HB50 with dilutions from 1:1 to 1:6. The abscissa represents the diameter of the piezoelectric layer in mm and the ordinate represents the thickness of the piezoelectric layer (LTO) in nm. Thickness profiles are shown for dilutions of Klebosol® 30HB50 with water of 1:1, 1:2, 1:3, 1:3.5, 1:4, 1:5 and 1:6. Other polishing parameters were chosen within the ranges described above.

[0037] It can be seen that for the dilutions of 1:5 and 1:6, the edge suppression is considerably increased, resulting in a piezoelectric layer thickness range of 147.844 nm and 180.313 nm, respectively. However, for the other dilutions, at least fairly satisfactory results could be obtained. The range thickness range observed across the layer diameter for the 1:1 dilution is 61.879 nm. Excellent results can be obtained for the other dilutions shown. The thickness range observed across the layer diameter for the 1:2 dilution is 36.82 nm, the thickness range observed across the layer diameter for the 1:3 dilution is 24.573 nm, the thickness range observed across the layer diameter for the 1:3.5 dilution is 23.186 nm, and the thickness range observed across the layer diameter for the 1:4 dilution is 21.849 nm.

Claims

Claims

1. A method of manufacturing a piezoelectric-on-insulator, POI, structure (9), comprising the steps of providing a donor substrate (1) comprising a piezoelectric substrate (1a), wherein the piezoelectric substrate (1) comprises or consists of one of lithium tantalate and lithium niobate; transferring a piezoelectric layer (3) from the piezoelectric substrate to a target substrate (7); and polishing the transferred piezoelectric layer (3) to the target substrate (7) with a chemical mechanical polishing, CMP, slurry, wherein the CMP slurry consists of an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon in the range of 4 to 18.

2. The method of claim 1, wherein the CMP suspension consists of an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon in the range of 4 to 13, in particular 5 to 7.

3. The method of claim 1 or 2, wherein the amorphous silicon comprises or consists of precipitated amorphous silicon particles with diameters in the range of 40 to 60 nm.

4. The method according to any one of the preceding claims, wherein the step of providing the donor substrate (1) comprises bonding a block of piezoelectric material to a support substrate (1b) via a bonding layer, grinding and polishing the block of piezoelectric material to obtain the piezoelectric substrate (1a), and implanting a species into the piezoelectric substrate (1a) to obtain a weakened layer (2) in the piezoelectric substrate (1a).

5. The method according to claim 4, wherein the step of transferring the piezoelectric layer (3) to the target substrate (7) comprises bonding the donor substrate (1) to the target substrate (7) and fracturing the piezoelectric substrate (1a) at the weakened layer (2).

6. The method according to any one of the preceding claims, further comprising performing an annealing treatment of the piezoelectric layer (3) transferred to the target substrate (7) before polishing the piezoelectric layer (3).

7. The method according to any one of the preceding claims, wherein the polishing comprises rotating the target substrate between 80 and 120 revolutions per minute and a polishing pad in the same direction as the head and in contact with the piezoelectric layer (3) at a different speed relative to the head of 90 to 130 revolutions per minute.

8. The method according to any one of the preceding claims, wherein the polishing comprises applying a wafer pressure to the target substrate (7) to press it against a polishing pad, which is not more than 20.68 kPa or less than 18.96 kPa, particularly in the range of 17.24 kPa to 20.68 kPa.

9. The method of any preceding claim, wherein the polishing comprises applying the CMP slurry to a polishing pad at a flow rate of less than 250 ml / minute or 200 ml / minute or 150 ml / minute, or in the range of 150 ml / minute to 250 ml / minute.

10. Piezoelectric-on-insulator, POI, structure (9) comprising a piezoelectric layer (3) formed on or above a target substrate (7) and obtainable by the method according to any one of the preceding claims, wherein the piezoelectric layer (3) has a thickness uniformity of less than 50 nm, in particular less than 20 nm.

11. Microelectronic, micromechanical or photonic device, or microelectromechanical system comprising the POI structure (9) according to claim 10.

Images