Integrated circuit comprising at least two power domains capable of being placed in a retention state, and corresponding nested power management method.

Abstract

The integrated circuit comprises a logic part (LG) capable of being powered by a main supply voltage (V11), comprising a first always-active power supply domain (PD0), and at least two power supply domains capable of being deactivated in a retention state (PD1, PD2). The logic part (LG) comprises auxiliary power supply lines (LGN) configured to power each deactivated power supply domain placed in the retention state (PD1, PD2) with the supply voltage (V11_0) of the first always-active power supply domain (PD0). Figure for abstract: Fig 1

Description

Title of the invention: Integrated circuit comprising at least two power supply domains capable of being placed in a retention state, and corresponding nested power supply management method.

[0001] Embodiments and implementations relate to integrated circuits, in particular comprising power supply domains capable of being deactivated and placed in a retention state, as well as nested management of the corresponding power supply.

[0002] Indeed, integrated circuits offer the possibility of a low-power mode, in which energy consumption is reduced and tends to be minimized.

[0003] Typically, portions of the integrated circuit may be disabled, particularly within a logic portion, in order to limit the consumption of the circuit, and also limiting certain functionalities of the circuit.

[0004] The logic part of the circuit corresponds for example to the “core” of a processor, usually comprising synchronous (or “dynamic”) devices clocked on clock edges, such as combinational logic gates and flip-flops; and sequential (or “static”) devices clocked on clock levels, such as latches or registers.

[0005] Conventionally, to provide operation in low power mode, an always-on power domain and a power domain that can be deactivated and placed in a retention state are provided.

[0006] A power supply domain corresponds for example to a set of circuits or functionalities using the same power supply in normal operation, and being switched on or off at the same time.

[0007] In the retention state, the states (i.e., the contained data) of the sequential / static elements of the deactivated power supply domain are advantageously retained by a retention circuit (e.g., of the latch type), while the synchronous / dynamic logic elements and the combinational / dynamic logic elements are switched off.

[0008] However, in conventional low-power modes, the always-on power supply domain continues its normal consumption, notably undergoing current leaks, and in a manner substantially proportional to the size of the always-on power supply domain (i.e., substantially the quantity of functionalities remaining active).

[0009] However, conventionally, the size of the always-active power supply domain is limited in reduction material, due to the need for a minimum of control elements to "wake up" the deactivated power supply domain placed in the retention state.

[0010] Thus, in this type of integrated circuit, there is a need to further reduce the consumption in the low consumption mode, in particular in terms of current leakage, while retaining the retention functionality, i.e. the retention of the static data of the domain placed in the retention state.

[0011] According to one aspect, there is provided in this regard an integrated circuit comprising a logic part comprising a first power supply domain called always-on (known to those skilled in the art by the English term "always on power domain") capable of being powered by a power supply voltage, and at least two power supply domains capable of being deactivated (i.e. for example disconnected from the power supply voltage) and placed in a retention state, in which the logic part comprises auxiliary power supply lines configured to power retention means (for example retention flip-flops or latches) of each power supply domain deactivated and placed in the retention state, with said power supply voltage of the first power supply domain always-on.

[0012] In other words, the integrated circuit according to this aspect can offer several degrees of low consumption, by deactivating a selection of one or more of said domains, the latter, placed in the retention state, all being powered by the always active power supply domain.

[0013] Consequently, it can be considered that the power supply domain containing the control elements making it possible to "wake up" the other power supply domain deactivated and placed in the retention state, which is the domain always active in the conventional case, can, in the integrated circuit according to this aspect, also be deactivated and placed in the retention state.

[0014] Thus, the integrated circuit according to this aspect makes it possible, for example, to design the first always-active power supply domain with a size and functionality much smaller than the conventional case, comprising, for example, only auxiliary power supply elements and possibly control elements (in small quantity), capable of waking up the power supply domain containing the control elements (in larger quantity) making it possible to “wake up” the other power supply domain, so that the consumption of the circuit is also lower.

[0015] According to one embodiment, said power supply domains capable of being deactivated and placed in the retention state are organized in hierarchical ranks, so that control means, configured to control the deactivation and the placement in the retention state or not of respectively each domain of rank N, belong to the domain of rank N1; the control means configured to command the deactivation and placement in the retention state or not of the lowest ranking domain belonging to another power domain.

[0016] In other words, in this organization, the power supply domains are "nested" from one to the other (N; N1), particularly from the point of view of the functionality of management and control of the deactivation and placement in the retention state, as well as of the functionality of management and control of the respective "wake-up", i.e. the reactivation in the operating state of the respective domain.

[0017] According to one embodiment, the other power supply domain is the first always-active power supply domain, or is another always-active power supply domain powered by another main supply voltage.

[0018] According to one embodiment, the logic part is configured to deactivate and place in the retention state the power supply domain of rank N, by a sequence comprising deactivations and placements of each power supply domain of higher rank in the retention state, successively by decreasing ranks.

[0019] According to one embodiment, the logic part is configured to reactivate and place out of the retention state the power supply domain of rank N, by a sequence comprising reactivations and placement out of the retention state of each power supply domain of lower rank, successively by increasing ranks.

[0020] According to another aspect, there is also provided a method for managing the power supply of an integrated circuit provided with a logic part comprising a first power supply domain called always active powered by a supply voltage, and at least two power supply domains capable of being deactivated and placed in a retention state, in which the method comprises a power supply of each power supply domain deactivated and placed in the retention state with the supply voltage of the first power supply domain always active.

[0021] For example, the method includes disconnecting each power supply domain in the retention disabled state from the supply voltage.

[0022] According to one embodiment, said power supply domains capable of being deactivated and placed in the retention state are organized in hierarchical ranks, so that each domain of rank J is deactivated and placed in the retention state or not, by commands from control means belonging to the domain of rank J1; the lowest rank domain being deactivated and placed in the retention state or not by commands from control means belonging to another power supply domain.

[0023] According to one embodiment, the other power supply domain is the first always-active power supply domain, or is another always-active power supply domain powered by another main supply voltage.

[0024] According to one embodiment, the method comprises a deactivation and a placing a power supply domain of rank J in the retention state, by a sequence comprising deactivations and placing each power supply domain of higher rank in the retention state, successively by decreasing ranks.

[0025] According to one embodiment, the method comprises a reactivation and placement out of the retention state of a power supply domain of rank J, by a sequence comprising reactivations and placement out of the retention state of each power supply domain of lower rank, successively by increasing ranks.

[0026] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and the appended drawings, in which the figures:

[0027] [Fig.l] ;

[0028] [Fig.2] ;

[0029] [Fig.3] ;

[0030] [Fig.4] ;

[0031] [Fig.5] illustrate embodiments and implementations of the invention.

[0032] [Fig.l] illustrates an example of an integrated circuit CI in a running state (usually "run" in English) MD_RN. The integrated circuit CI is for example a microcontroller, comprising a logic part LG, for example the heart of a central computing unit. The logic part LG is subdivided into power supply domains PD0, PDI, PD2, PD33.

[0033] Each power supply domain PD0, PDI, PD2, PD33 corresponds for example to a set of circuits or functionalities of the logic part LG using the same power supply VI1, V33 in normal operation, and being switched on or off at the same time.

[0034] In this example a first supply voltage V33, usually designated VDD, is supplied to the integrated circuit CI, for example from an external source.

[0035] From the voltage V33, an LDO / SMPS voltage regulator is configured to generate a voltage Vil adapted to the domains PD0, PDI, PD2 of the logic part LG.

[0036] Another domain PD33 may be provided to be powered directly by the voltage V33 (VDD), for example a domain implementing “analog” functionalities of the input-output interface type.

[0037] For example, the voltage V33 may be substantially 3.3V, while the regulated supply voltage Vil, which will be called the main supply voltage, may be substantially 1.1V or lower, for example 0.9V.

[0038] The logic part LG comprises a first always-active power supply domain PD0, and (at least) two power supply domains capable of being deactivated and placed in a retention state PDI, PD2. The power supply domain PD33 may optionally he too must always be active.

[0039] By "disabled" is meant for example that the supply domains PDI, PD2 are disconnected from the main supply voltage Vil (see figures 2 and 3), usually by means of switch circuits SWO, SW1, SW2 connected between the voltage regulator LDO / SMPS and the respective supply domains of the logic part LG.

[0040] In the retention state, the states (i.e. the contained data) of the sequential elements, for example of the lock type, of the deactivated power supply domain PDI, PD2 are advantageously preserved by retention means, while the synchronous / dynamic logic elements are deactivated.

[0041] The retention means, conventional and known per se, may for example comprise an additional sequential / static circuit, for example of the lock type, configured to be in the same state (contain the same data) as a functional sequential device, and to be powered by an auxiliary power supply line LGN when the PDI, PD2 domain is deactivated.

[0042] In other words, said PDI, PD2 domains capable of being deactivated and placed in the retention state, comprise retention means configured to retain a static state contained in the sequential elements of the respective PDI, PD2 domain; the auxiliary power supply lines being configured to supply the retention means of said power supply domains.

[0043] Thus, the logic part LG comprises in this regard auxiliary supply lines LGN configured to supply each deactivated supply domain in the retention state PDI, PD2 with the supply voltage V11_0 of the first still active supply domain PD0.

[0044] Therefore, the integrated circuit CI benefits from several degrees of low consumption MD_LP1, MD_LP2 (see figures 2 and 3), by offering the possibility of deactivating and placing in the retention state a selection of one or more of said domains PDI, PD2, powered by the always active power supply domain PD0.

[0045] These latter may be designated “first domain in retention state” PDI (which will be duly distinguished from the “first” domain always active PD0, even in the absence of the mention “in retention state”), and “second domain in retention state” PD2.

[0046] We now refer to [Fig.2].

[0047] [Fig.2] illustrates the integrated circuit of [Fig.l], in a low power mode MD_LP1.

[0048] In the low power mode MD_LP1, the second domain PD2 is deactivated and placed in the retention state, while the first retention state domain PDI is kept in the on state, powered by the main supply voltage VIL

[0049] The second domain PD2 is no longer supplied by the main supply voltage VI1 and is, for example, disconnected from the LDO / SMPS regulator by the respective open switching circuit SW2.

[0050] The retention means of the second domain PD2 are supplied, via the auxiliary supply lines LGN, with the supply voltage Vll_0 of the first still active supply domain PD0.

[0051] For example, the main supply voltage Vil supplied to the first always-on domain PD0 and to the first domain PDI, can be lowered to 0.7V in the low power mode MD_LP1.

[0052] In order to implement the deactivation and retention functionality of the second power domain PD2, commands ISL_V11_2, SV_V11_2, RSTR_V11_2 are initiated in an active power domain PDI.

[0053] The first retention state domain PDI comprises control means PwrCtrl_V 11_1, configured to control the deactivation and placement in the retention state of the second retention state domain PD2; as well as the reactivation or waking up of the second domain PD2 in the operating state, i.e. placed out of the deactivated retention state.

[0054] The control means PwrCtrl_V 11_1 are for example incorporated within a control automaton of the FSM state machine type of the first PDI domain, and are configured to generate at least: an isolation control signal ISL_V 11_2 capable of controlling the isolation of the retention circuits of the retention means of the second domain PD2; a backup signal SV_V 11_2 capable of controlling a capture of the current static state in the second domain PD2, by the retention means, which will be retained during the retention state; a recovery signal RSTR_V 1_2 capable of commanding a return to the operating state, i.e. a wake-up from the retention state of the second PD2 domain.

[0055] We now refer to [Fig.3].

[0056] [Fig. 3] illustrates the integrated circuit of Figures 1 and 2, in a very low power mode MD_LP2 consumption.

[0057] In the very low power mode MD_LP2, the second PD2 domain is deactivated and placed in the retention state, and the first PDI domain is also deactivated and placed in the retention state.

[0058] The first domain DPI and the second domain PD2 are no longer supplied by the main supply voltage Vil and are for example disconnected from the LDO / SMPS regulator by the respective open switching circuits SW1, SW2.

[0059] The retention means of the first domain PDI and of the second domain PD2 are supplied, via the auxiliary supply lines LGN, with the voltage V11_0 power supply of the first always-active power domain PDO.

[0060] For example, the main supply voltage Vil supplied to the first always-on domain PDO can be lowered to 0.66V in the very low power mode MD_LP2.

[0061] Analogously to the second domain PD2, in order to implement the deactivation and retention functionality of the first power domain PDI, commands ISL_V 11_2, SV_V 11_2, RSTR_V 11_2 are initiated in an active power domain PD33 (or PDO).

[0062] Thus, control means PwrCtrl_V33 are configured to control the deactivation in the retention state of the first PDI domain; as well as the reactivation or the awakening of the first PDI domain in the operating state, that is to say outside the deactivated retention state.

[0063] The control means PwrCtrl_V33 are for example incorporated within a control automaton of the FSM state machine type of an always-active power supply domain. This always-active power supply domain can be for example the power supply domain PD33 powered by the external voltage V33 (VDD); or, alternatively, the first always-active power supply domain PDO.

[0064] The PwrCtrl_V33 control means are also configured to generate at least: an isolation control signal ISL_V11_1 capable of controlling the isolation of the retention circuits of the retention means of the first PDI domain; a save signal SV_V11_1 capable of commanding a capture of the current static state in the first PDI domain, by the retention means, which will be retained during the retention state; a recovery signal RSTR_V1_1 capable of commanding a return to the running state, i.e. a wake-up from the retention state of the first PDI domain.

[0065] In summary, with N=2 in Figures 1, 2 and 3, the power domains capable of being deactivated and placed in the retention state PDI, PD2 are organized in N hierarchical ranks.

[0066] The hierarchy is made so that control means PwrCtrl_V 11_J-1, configured to control the deactivation and the placement in the retention state and the reactivation out of the retention state, of respectively each domain of rank J (PD2, for J=N=2), belong to the domain of lower rank J1 (PDI, for J=N=2).

[0067] The control means PwrCtrl_V33 configured to control the deactivation and placement in the retention state and the reactivation out of the retention state of the lowest ranking domain PDI, belong to another power supply domain, either the first always active power supply domain PDO, or the other always active power supply domain PD33 powered by voltage V33, i.e. another main supply voltage.

[0068] The integrated circuit CI described in relation to figures 1, 2 and 3 makes it possible, for example, to design the first always-on power supply domain PDO with minimal size and functionality, so as to have extremely low energy consumption, in particular in the very low consumption mode MD_LP2.

[0069] The domain capable of being deactivated and placed in the lowest rank retention state PDI, can also be designed with a size tending to be minimized, so as to have reduced energy consumption, in particular for the low consumption mode MD_LP1.

[0070] For example, the second retention state domain PD2 may comprise the vast majority of the functionalities of the logic part LG powered by the main supply voltage VI1; while the first retention state domain PDI may comprise only a few functionalities of the logic part, and the function of the control means PwrCtrl_Vll_l.

[0071] The functionalities implemented by the first PDI domain may be functionalities relating to the awakening of the second PD2 domain, for example originating from digital or software means, for example originating from decoding operations of information communicated on a data bus.

[0072] The functionalities of the second domain PD2 can for example represent more than 95% of the logic part supplied by the main supply voltage Vil, for example 97.5%.

[0073] The functionalities of the first PDI domain may represent less than 5% of the logic part (powered by the main supply voltage Vil), for example 2.4%.

[0074] The first always-active domain PDO may represent a marginal portion of the logic part supplied by the main supply voltage Vil, for example 0.1%. For example, the functionality of the first always-active domain PDO may include only the transmission of the supply voltage V11_0 on the auxiliary supply lines LGN.

[0075] Furthermore, given the small amount of functionality of the first PDI domain, the control means PwrCtrl_V33 controlling the retention state of the first PDI domain are made proportionally in small quantity. Their consumption in working state is also proportionally low.

[0076] Thus, the control means PwrCtrl_V33 provided for controlling the retention state of the first domain PDI, have a consumption much lower than the consumption of the control means PwrCtrl_Vll_l provided for controlling the retention state of the second domain PD2.

[0077] This applies both in the case where the control means PwrCtrl_V33 are implemented in the always active domain PD33 powered by an external supply voltage V33; and in the case where they are implemented in the always active domain PDO powered by the main supply voltage Vil.

[0078] Consequently, in the very low consumption mode MD_LP2, the deactivation in the retention state of the first PDI domain offers a concrete and non-negligible gain, on the reduction of consumption, compared to the low consumption mode MD_LP1.

[0079] [Fig.4] illustrates a procedure 400 for deactivating the power supply domain PDJ of rank J, implemented in a method for managing the power supply of the integrated circuit CI described previously in relation to FIGS. 1 to 3.

[0080] The power supply management method firstly comprises a power supply 402 of the logic part LG of the integrated circuit with a main supply voltage VIL

[0081] And, to implement a deactivation 406 of a power supply domain of rank J in the retention state, the procedure 400 comprises a sequence of successive deactivations and placements in the retention state 404 of each power supply domain of higher rank, by decreasing ranks N ... J.

[0082] Thus, to deactivate the PDJ domain (with 1 <J<N) on commence par désactiver le domaine PDN de rang N le plus grand dans une étape 404.

[0083] Step 404 thus comprises a generation of control signals placing the PDN domain in the retention state, and initiated in the lower-ranking domain PDN-1.

[0084] The PDN domain is disconnected from the main supply voltage VI1, and the PDN retention means are powered by the voltage V11_0 of the still active supply domain PDO.

[0085] Optionally, the main supply voltage Vil (supplying the always active supply domain PDO) can be reduced, for example, from VI 1 = 0.9V to Vll = 0.7V.

[0086] This step is implemented for all domains N... J of rank higher than J.

[0087] Then, the domain PDJ of rank J (with 1 <J<N) est désactivé dans une étape 406.

[0088] Step 406 thus comprises a generation of the control signals placing in the retention state of the PDJ domain, and initiated in the lower ranking PDJ-1 domain.

[0089] The PDJ domain is disconnected from the main supply voltage VI1, and the PDJ retention means are powered by the voltage V11_0 of the still active supply domain PDO.

[0090] Optionally, the main supply voltage Vil (supplying the always active supply domain PDO) can be reduced, for example, we go from VI l=0.9V to Vll=0.7V.

[0091] Beyond the domain of rank J, the lowest rank PDI domain can be deactivated, in a step 408, after having deactivated any domains of rank between J and 1 (J...1).

[0092] From another point of view, before deactivating the lowest ranking PDI domain, steps 404-406 are implemented as described above, with J=2.

[0093] The lowest ranking PDI domain is deactivated and placed in the retention state in a step 408, comprising a generation of the control signals placing the PDJ domain in the retention state, and initiated in the still active PD33 domain.

[0094] The PDI domain is disconnected from the main supply voltage VI1, and the PDI retention means are powered by the voltage V11_0 of the still active supply domain PD0.

[0095] Optionally, the main supply voltage Vil (supplying the always active supply domain PD0) can be reduced, for example, from VI l=0.7V to VI 1=0.66V.

[0096] It will be noted that with N=2 and J=1, the implementation of the method 400 is illustrated by the sequence of figures 1, 2 and 3.

[0097] [Fig.5] illustrates a procedure 500 for reactivating the power supply domain PDJ of rank J, implemented in a method for managing the power supply of the integrated circuit CI described previously in relation to FIGS. 1 to 3.

[0098] The power supply management method firstly comprises a power supply 502 of the logic part LG of the integrated circuit with a main supply voltage VIL

[0099] And, to implement a reactivation 506 of a power supply domain of rank J out of the retention state, the procedure 500 comprises a sequence of successive reactivations and placements out of the retention state 504 of each power supply domain of lower rank, by increasing ranks 1 ... J.

[0100] Thus, to reactivate the PDJ domain (with 1 <J<N) on commence par réactiver le domaine PDI de rang le plus bas dans une étape 504, si ce domaine était désactivé.

[0101] Step 504 thus comprises a generation of the wake-up control signals outside the retention state of the PDI domain, initiated in the still active domain PD33.

[0102] The PDI domain is reconnected to the main supply voltage Vil which supplies all the functionalities of the PDI domain.

[0103] Optionally, the main supply voltage Vil can be increased, for example, from VI 1 = 0.66V to VI 1 = 0.7V.

[0104] All the domains of rank between 1 and J are reactivated, by successive steps 506 each comprising a generation of the wake-up control signals outside the retention state of the PDJ domain, initiated in the lower rank domain PDJ- 1.

[0105] The PDJ domain is reconnected to the main supply voltage Vil, which powers all the functionalities of the PDJ domain.

[0106] Optionally, the main supply voltage Vil can be increased, for example, from VI 1 = 0.7V to VI 1 = 0.9V.

[0107] Similarly, to reactivate the highest rank PDN domain in step 508, all the domains of rank between J and N are reactivated, by successive steps 506 each comprising a generation of wake-up signals outside the retention state of the PDJ domain, initiated in the lower rank domain PDJ-1.

[0108] In step 508 the PDN domain is reconnected to the main supply voltage Vil, which supplies all the functionalities of the PDN domain.

[0109] Optionally, the main supply voltage Vil can be increased, for example, from VI 1 = 0.7V to VI 1 = 0.9V.

Claims

Claims

1. Integrated circuit comprising a logic part (LG) comprising a first power supply domain called always active (PDO) capable of being powered by a power supply voltage (V1l_0), and at least two power supply domains capable of being deactivated and placed in a retention state (PDI, PD2), in which the logic part (LG) comprises auxiliary power supply lines (LGN) configured to power retention means of each power supply domain deactivated and placed in the retention state (PDI, PD2) with said power supply voltage (Vll_0) of the first power supply domain always active (PDO).

2. Integrated circuit according to claim 1, wherein said power supply domains capable of being deactivated and placed in the retention state (PDI, PD2) are organized in hierarchical ranks, so that control means (PwrCtrl_Vll_l), configured to control the deactivation and the placement in the retention state or not of respectively each domain of rank J (PD2), belong to the domain of lower rank Jl (PDI); the control means (PwrCtrl_V33) configured to control the deactivation and the placement in the retention state or not of the domain of the lowest rank (PDI) belonging to another power supply domain (PD33, PDO).

3. An integrated circuit according to claim 2, wherein the other power supply domain is the first always-on power supply domain (PDO), or is another always-on power supply domain (PD33) supplied by another main supply voltage (V33).

4. Integrated circuit according to one of claims 2 or 3, in which the logic part (LG) is configured to deactivate and place in the retention state the power supply domain of rank J (PDI), by a sequence comprising deactivations and placements in the retention state of each power supply domain of higher rank (PD2), successively by decreasing ranks (N ... J).

5. Integrated circuit according to one of claims 2 to 4, in which the logic part (LG) is configured to reactivate and place out of the retention state the power supply domain of rank J (PD2), by a sequence comprising reactivations and placements out of the retention state of each power supply domain of lower rank (PDI), successively by increasing ranks (1 ... J).

6. Method for managing the power supply of an integrated circuit (IC) provided with a logic part (LG) comprising a first power supply domain called always active (PDO) supplied by a supply voltage (Vll_0), and at least two power supply domains capable of being deactivated and placed in a retention state (PDI, PD2), in which the method comprises supplying retention means of each power supply domain deactivated and placed in the retention state (PDI, PD2) with the supply voltage (Vll_0) of the first power supply domain always active (PDO).

7. Method according to claim 6, wherein said power supply domains capable of being deactivated and placed in the retention state (PDI, PD2) are organized in hierarchical ranks, so that each domain of rank J (PD2) is deactivated and placed in the retention state or not, by commands (ISL_V 11_2, SV_V 11_2, RSTR_V 11_2) coming from the domain of lower rank J1 (PDI); the lowest rank domain (PDI) being deactivated and placed in the retention state or not by commands (ISL_V 11_2, SV_V 11_2, RSTR_V 11_2) coming from another power supply domain (PD33, PDO).

8. The method of claim 7, wherein the other power supply domain is the first always-on power supply domain (PDO), or is another always-on power supply domain (PD33) powered by another main supply voltage (V33).

9. Method according to one of claims 7 or 8, comprising a deactivation and a placement in the retention state of a power supply domain of rank J (PDI), by a sequence comprising deactivations and placements in the retention state of each power supply domain of higher rank (PD2), successively by decreasing ranks (N ... J).

10. Method according to one of claims 7 to 9, comprising a reactivation and a placement out of the retention state of a power supply domain of rank J (PD2), by a sequence comprising reactivations and placements out of the retention state of each power supply domain of lower rank (PDI), successively by increasing ranks (1 ... J).

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