Phase change memory device with improved temperature resistance

Abstract

Title: Phase change memory device with improved temperature resistance The invention relates to a phase change memory device (1) comprising a memory point (1000), the latter comprising a metal layer (300) forming a heating element (3000), a memory layer (700) based on a phase change material and an upper electrode (800). The device further comprises a first encapsulation layer (400) extending from a first main flank (303) of the metal layer and having a doped portion (450) based on at least one first doping species. The doped portion (450) extends from the first main flank (303) of the metal layer (300). Figure for abstract: Fig. 23B

Description

Title of the invention: Phase change memory device with improved temperature resistance Technical field

[0001] The present invention relates to the field of phase change memory devices. It finds a particularly advantageous application in memory devices whose memory point architecture includes a heating element underlying the memory layer. STATE OF THE ART

[0002] Memory devices represent crucial issues in many applications, for example for the type of memory commonly referred to as Storage Class Memory (SCM), embedded memories for automobiles, or neuromorphic applications. In this context, resistive memories represent very good candidates to support or replace Flash memory. Resistive memories indeed have significant advantages in terms of speed and scaling, i.e. the reduction of the dimensions of the memory unit cell, and of the distance between two memory points, which has the effect of increasing the density of memory points in the memory matrices.Among resistive memories, phase change memories (commonly abbreviated PCM) represent the most mature non-volatile resistive memory technology and are at an advanced stage of development and production.

[0003] Phase change memories typically comprise two programming states obtained from a layer based on a phase change material forming a so-called “memory” layer and having an amorphous state and a crystalline state. a. "RESET" programming or equivalently HRS, from the English High Resistive State (which can be translated as high resistivity state), which is based on the melting of all or part of the chalcogenide layer, during an electrical pulse allowing the melting temperature of the material to be reached by Joule effect. The molten part of the chalcogenide material is then frozen in an amorphous state by sudden cooling, obtained by rapid reduction of the current. The amorphous state of the chalcogenide material is very poorly electrically conductive. Reset programming allows the information "0" to be stored, with the storage of a high resistance in the PCM device. b. “SET” programming or equivalently LRS, from the English Low Resistive State (which can be translated as low resistivity state), which is based on partial or total melting of the chalcogenide material during an electrical pulse. The chalcogenide material is then crystallized by gradual cooling obtained by gradually reducing the current. The crystalline state of the chalcogenide material is a better electrical conductor than the amorphous state. The set programming allows the information "1" to be stored, with the storage of a low resistance in the PCM device.

[0004] The work of optimizing memories of this type is currently focused, among other things, on reducing the drift of the "SET" state and on reducing the size of the memory point. However, the vertical extension of the unit PCM cell is a non-negligible parameter given its impact on the passive resistance of the vertical metal connections in the metal vias of the devices integrated at the same level. In the most widespread integration of PCM cells, a significant part of the vertical dimension of the PCM cell corresponds to the heating element (commonly referred to by the English term "heater") located under the phase change material. This heating element is at the heart of the operation of the PCM cell: when a current flows through it, it emits heat by the Joule effect, propagating in the memory layer and modifying the state of the phase change material.Depending on the amount of heat emitted by the heating element, the memory layer switches from the "SET" state to the "RESET" state, or vice versa.

[0005] The performance of the resistive heating element is first of all very sensitive to its dimensions. In particular, a fairly thin heating element (a few nanometers or tens of nanometers thick) is preferred in order to maximize the Joule effect occurring within it. In this way, the control of the state of the memory layer and therefore the performance of the device are improved.

[0006] The performance of the resistive heating element is also very sensitive to the properties of the material that composes it. However, the deposition processes for producing the heating element with the preferred dimensions mentioned above (chemical vapor deposition, alternating flow chemical deposition) impose limits in terms of composition of the heating element. This is due to various parameters, in particular the precursors used, the reactivity of the elements involved or the temperature at which these deposition processes must be carried out. Thus, the range of materials that can be considered for the heating element is restricted, and the latter do not have the most advantageous physical properties for the operation of the memory point. In particular, the materials that can be deposited by the processes mentioned above do not have optimal stability at the operating temperatures of the memory point.Thus, there is a need to improve the thermal properties of the memory point, while maintaining a heating element having di- . dimensions promoting the performance of the device. SUMMARY

[0007] To achieve this objective, a first aspect of the invention relates to a phase change memory device comprising a memory point, the memory point comprising: a. a metallic layer based on a metallic material and forming a heating element, b. a memory layer based on a phase change material, the phase change material being configured such that the memory layer selectively transitions from a first resistive state (LRS) having a first resistivity to a second resistive state (HRS) having a second resistivity greater than the first resistivity, c. an upper electrode.

[0008] The heating element is intended to receive an electric current making it possible to produce heat by Joule effect and to transfer a portion of this heat to the memory layer so as to selectively pass the memory layer from one of the first resistive state (LRS) and the second resistive state (HRS) to the other of the first resistive state (LRS) and the second resistive state (HRS). According to one embodiment, the heating element can also selectively pass the memory layer from the first resistive state (LRS) or from the second resistive state (HRS) to a third resistive state having a third resistivity, different from the first resistivity and from the third resistivity, and vice versa. Generally, the heating element can be configured to be able to selectively place the memory layer in N levels, with N an integer greater than or equal to 2, each level being characterized by a different resistivity.When N is strictly greater than 2, the memory device is called multi-level and allows more information to be coded at the same memory point. This can, for example, allow the creation of artificial neural networks.

[0009] The heating element has a first main flank and a second main flank, opposite each other.

[0010] The memory device further comprises a first encapsulation layer extending from the first main flank of the metal layer. The first encapsulation layer has a portion, called doped, having doping based on at least one species, called first doping species, the doped portion extending from the first main flank of the metal layer.

[0011] The doping of the first encapsulation layer makes it possible to improve the thermal resistivity of the memory point. In particular, this doping makes it possible to reduce the value of the thermal transfer coefficient of the first encapsulation layer, which makes it possible a certain thermal confinement of the heating element, less dissipation of heat from the heating element to regions of the device other than the memory layer, and therefore a reduction in the energy required for programming the "RESET" state. The doping of the first encapsulation layer thus makes it possible to use materials allowing the formation of a memory layer with advantageous dimensions as mentioned above, while guaranteeing a very good ratio between the energy used to heat the heating element and the energy actually transmitted to the memory layer. The invention therefore makes it possible to achieve the objective set out above, namely to improve the thermal properties of the memory point, which leads to an improvement in its performance. The thermal confinement effect of the heating element is furthermore further improved when the device comprises a second encapsulation layer, also doped.

[0012] The presence of the first encapsulation layer also makes it possible to limit damage to the metal layer due to potential exposure to air. With this in mind, it is advantageous to provide for the first encapsulation layer to be deposited in a conforming manner on the metal layer.

[0013] Preferably, the metal layer is also doped, for example with the same doping species as the first encapsulation layer. Doping the metal layer makes it possible to modify its stoichiometry and atomic structure as well as to add new chemical elements therein. Furthermore, doping the metal layer makes it possible to obtain very good temperature resistance of the heating element, which makes it possible to improve the performance of the memory device.

[0014] Furthermore, by improving the temperature resistance through doping, the number of materials that can be used to form the heating element is increased. Materials that previously were not good candidates for the production of the heating element due to their poor temperature resistance, but which had other advantageous physical properties, can be used. Indeed, the implantation makes it possible to compensate for this poor natural temperature resistance and thus to give the heating element a satisfactory temperature resistance or even a higher one than what would have been obtained by the use of materials that naturally have a correct temperature resistance but have not been doped.

[0015] Furthermore, doping the metal layer makes it possible to give the latter better resistivity, which is very advantageous for enabling a strong Joule effect at the level of the heating element and therefore better control of the state of the memory layer.

[0016] A second aspect of the invention relates to a method of manufacturing a phase change memory device comprising a memory point, the method comprising the following steps: a. provide a set comprising at least: i. a metal layer based on a metallic material and intended to form a heating element for the memory point, the metal layer having a first main flank, ii. a first encapsulation layer (400) extending from the first main flank (303) of the metal layer (300), b. implanting a species called the first doping species in a portion (450), called doped, of the first encapsulation layer (400), the doped portion (450) extending from the main flank (303) of the metal layer (300), c. forming against one face of the metal layer a stack comprising: i. a layer called a memory layer based on a phase change material, thermally coupled with the metal layer so that heat produced by the Joule effect by the metal layer is transferred to the memory layer, ii. an upper electrode.

[0017] Preferably, the method also comprises a step of doping the metal layer, for example with the same doping species as the first encapsulation layer. The implantation of the metal layer, and therefore of the heating element, allows not only a modification of its composition but also its amorphization. Indeed, the methods generally used for the formation of the metal layer (in particular chemical deposition by alternating flow, which makes it possible to obtain very thin layers) operate by saturating the structure by one face, layer after layer. Planes are thus obtained in an ordered stack, which constitutes an easy conduction path for the current to follow. As it is, the resistivity of the heating element is therefore low. Consequently, the Joule effect is not very significant, which is unfavorable for the operation of the memory point.By implementing the heating element, this stack is disordered, which makes it possible to increase the resistivity of the heating element, therefore increasing the Joule effect, and finally improving the programming control and increasing the performance of the memory point.

[0018] Preferably, the step of implanting the metal layer is carried out through the first encapsulation layer. Carrying out the implantation through the first encapsulation layer makes it possible to transfer species from the first encapsulation layer into the metal layer. This transfer is particularly favorable when the transferred species can contribute to an increase in the resistivity and the temperature resistance of the metal layer, which is particularly the case when the first encapsulation layer comprises silicon and / or nitrogen. The implantation thus allows an increase in the resistivity and a increase in the temperature resistance of the metal layer not only through the implantation of the doping species but also through the implantation of one or more species coming from the first encapsulation layer.

[0019] It should be noted that the implementation of the first encapsulation layer (and possibly the memory layer) is compatible with all PCM architectures integrating a heating element underlying the memory layer. Furthermore, the additional cost of this step is low, for a high gain in performance of the memory device.

[0020] The advantages provided by the memory device according to the invention apply mutatis mutandis to the method according to the invention, and vice versa. BRIEF DESCRIPTION OF THE FIGURES

[0021] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0022] [Fig-1] [Fig.l] represents a cross-sectional view illustrating according to a example the location of a PCM device between the metal levels at the end of the manufacturing line (commonly referred to in English as "back-end of line", or simply "back-end").

[0023] [Fig.2] [Fig.2] represents a perspective diagram of a memory point according to a example of realization.

[0024] [Fig.3A] Figures 3A to 23B illustrate an embodiment of the method according to the invention.

[0025] [Fig.3B]

[0026] [Fig.4A]

[0027] [Fig.4B]

[0028] [Fig.5A]

[0029] [Fig.5B]

[0030] [Fig.6A]

[0031] [Fig.6B]

[0032] [Fig.7A]

[0033] [Fig.7B]

[0034] [Fig. 8 A]

[0035] [Fig.8B]

[0036] [Fig.9A]

[0037] [Fig.9B]

[0038] [Fig.lOA]

[0039] [Fig.lOB]

[0040] [Fig. 11 A]

[0041]

[0042]

[0043]

[0044]

[0045]

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

[0057]

[0058]

[0059]

[0060]

[0061]

[0062]

[0063]

[0064]

[0065]

[0066] [Fig.llB] [Fig.l2A] [Fig.l2B] [Fig.l3A] [Fig.l3B] [Fig.l4A] [Fig.l4B] [Fig.l5A] [Fig.l5B] [Fig.l6A] [Fig.lôB] [Fig.l7A] [Fig.l7B] [Fig.l8A] [Fig.l8B] [Fig.l9A] [Fig.l9B] [Fig.20A] [Fig.20B] [Fig.21A] [Fig.21B] [Fig.22A] [Fig.22B] [Fig.23A] [Fig.23B] [Fig.24] [Fig.24] represents the result of a simulation of the carbon implantation of a SiN / TiN / SiN tri-layer.

[0067] [Fig.25A] Figures 25A to 25D are sectional views of embodiments of the device according to the invention in which the memory point has different structures.

[0068]

[0069]

[0070]

[0071] [Fig.25B] [Fig.25C] [Fig.25D] The drawings are given as examples and are not limiting of the invention.They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily on the scale of practical applications. In particular, the dimensions and relative dimensions of the layers are not representative of reality. DETAILED DESCRIPTION

[0072] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0073] According to one example, the first encapsulation layer is based on at least one of the following materials: SiN, SiCN, SiC.

[0074] According to one example, the concentration of first dopant species in the doped portion of the first encapsulation layer is greater than or equal to 5.1020 atoms / cm3, preferably greater than or equal to 1.1021 atoms / cm3. Typically, the concentration of first dopant species in the doped portion of the first encapsulation layer is less than or equal to 1.1022 atoms / cm3.

[0075] According to one example, the first encapsulation layer has a thickness e400 taken in a direction perpendicular to the first main flank of the metal layer, the doped portion extending over a thickness e450 in this same direction within the first encapsulation layer, with e450 > 0.05*e400, preferably e450 > 0.10*e400.

[0076] According to one example, the first encapsulation layer has a thickness e400 taken in a direction perpendicular to the first main flank of the metal layer, the doped portion extending over a thickness e450 in this same direction within the first encapsulation layer, with e450 < 0.5*e400, preferably e450 < 0.3*e400. The remainder of the first encapsulation layer (which may be designated the undoped portion) is preferably less doped than the doped portion. The so-called undoped portion is preferably doped at a concentration strictly less than 5.1020 atoms / cm3. This guarantees that a significant portion of the encapsulation layer is less doped than the doped portion. In this way, the doped portion of the encapsulation layer ensures thermal confinement of the metal layer while the undoped portion ensures protection of the metal layer. The thickness e450 of the doped portion in the encapsulation layer can be controlled by means known to those skilled in the art during implantation of the encapsulation layer (modulation of the implantation energy, the implantation angle, etc.).

[0077] According to one example, the metal layer has a thickness e300 between its first main flank and its second main flank, with e300 <10 nm. This makes it possible to maximize the Joule effect occurring in the metal layer and thus to improve the control of the state of the memory layer.

[0078] According to a preferred embodiment, the metal layer has a doping based on a second doping species, preferably identical to the first doping species. It is also conceivable that the metal layer has a doping based on of a second doping species distinct from the first doping species, and a doping based on the first doping species. Whether the second doping species is identical or not to the first doping species, the concentration of second doping species within the metal layer is preferably between 0% and 8%.

[0079] According to a preferred embodiment, the device further comprises a first dielectric layer extending from the second main flank of the metal layer, the first dielectric layer having a portion, called doped, having a doping based on at least one species, called third doping species, preferably identical to the first doping species, the doped portion of the first dielectric layer extending from the second main flank of the metal layer. The advantages obtained by doping the first encapsulation layer are also obtained by doping the first dielectric layer (thermal confinement of the metal layer in particular).

[0080] According to one example, the concentration of third dopant species in the doped portion of the first dielectric layer is greater than or equal to 5.1020 atoms / cm3, preferably greater than or equal to 1.1021 atoms / cm3. Typically, the concentration of third dopant species in the doped portion of the first dielectric layer is less than or equal to 1.1022 atoms / cm3.

[0081] Preferably, the third doping species is identical to the second doping species. It is also conceivable that the doped portion of the first dielectric layer has doping based on a third doping species distinct from the second doping species, and doping based on the second doping species, or even also doping based on the first doping species.

[0082] According to one example, the first encapsulation layer has a first main flank and a second main flank opposite each other, the second main flank facing the first main flank of the metal layer, the device further comprising a second encapsulation layer against the first main flank of the first encapsulation layer. The second encapsulation layer advantageously has doping, preferably based on the first doping species.

[0083] According to an example, the first dopant species is chosen from the following species: silicon, carbon, argon, nitrogen, oxygen, xenon, titanium, tantalum, tungsten, cobalt, germanium, neon and their alloys. The atomic proportions of these alloys are not necessarily fixed at 1:1. As will be described further below, distinct dopant species can be implanted during different implantation sub-steps, whether for implanting one or more of the same layer(s) or for implanting distinct layers. Argon, xenon, nitrogen, oxygen, carbon, silicon and germanium are particularly advantageous for reduce the thermal diffusion coefficient of the first encapsulation layer (and, where applicable, of the second encapsulation layer).

[0084] Preferably, the second implanted species is identical to the first implanted species. Generally, the second implanted species may be chosen from the same doping species as the first implanted species. All of these species have the effect, when implanted in the metal layer, of improving its temperature resistance.

[0085] Argon, xenon, nitrogen, oxygen, carbon, silicon and germanium are also particularly advantageous for increasing the electrical resistivity of the metal layer and thus increasing the Joule effect. Argon and xenon act in particular on the resistivity of the metal layer by modifying its structure. Their implantation in the metal layer causes amorphization which causes the resistivity to increase. Nitrogen, oxygen, carbon, silicon and germanium modify the composition of the material constituting the metal layer, which causes the resistivity to increase.

[0086] Preferably, the third implanted species is identical to the first implanted species. Generally, the third implanted species may be selected from the same doping species as the first implanted species.

[0087] According to one example, in a direction perpendicular to the first main flank of the metal layer, the memory layer has a length Lcm and the heating element has a thickness eec, with Lcm > y * eec, with y > 2, preferably y > 5, preferably y > 10.

[0088] According to one example, the metallic material is based on at least one of the following materials: TiN, TiC, TiSiN, TiSiCN, TiWN, TaN, TaCN. The atomic proportions of these alloys are not necessarily fixed at 1:1.

[0089] According to one example, the metal layer has a lower face and the device further comprises a metal via in contact with the lower face of the metal layer.

[0090] According to an advantageous embodiment of the method according to the invention, the latter further comprises a step of implanting a species called the second doping species, preferably identical to the first doping species, in the metal layer, the step of implanting the metal layer being carried out through the first encapsulation layer.

[0091] As will be seen further on, the first encapsulation layer can also serve as a protective layer during the etching of a portion of the metal layer. In this regard, it is advantageous to provide that the first encapsulation layer is deposited conformally on the metal layer.

[0092] According to one example, the first encapsulation layer has a first sidewall main and a second main flank opposite each other, the second main flank facing the first main flank of the metal layer, and the method further comprises forming a second encapsulation layer against the first main flank of the first encapsulation layer.

[0093] According to one example, the second encapsulation layer is based on at least one of the following materials: SiN, SiCN, SiC.

[0094] According to one example, the implantation of the second doping species in the metal layer is carried out through the second encapsulation layer. Carrying out the implantation of the metal layer through the second encapsulation layer has the same advantages as carrying it out through the first encapsulation layer, this time with two layers from which species can be transferred into the metal layer and increase its resistivity. Thus, it can be provided that the implantation is carried out so as to transfer into the heating element a doping species from the first encapsulation layer and a different doping species, this time from the second encapsulation layer. The properties of the heating element can be improved by the implantation of these two distinct species.To promote the transfer of doping species from the second encapsulation layer to the metal layer, it can be provided that the thickness e4Oo of the first encapsulation layer is low, for example less than or equal to 1 nm.

[0095] According to one example, the first main flank of the metal layer is not covered during the step of implanting the second doping species. The step of providing the assembly at the start of the process can thus comprise the following steps: a. Provide the metal layer, b. Implant the metal layer with the second doping species, c. Form the first encapsulation layer.

[0096] According to one example, providing the assembly comprises the following steps: a. providing a support layer having an upper face extending mainly in a plane parallel to the longitudinal plane, b. forming on a portion of the upper face of the support layer a dielectric layer, the dielectric layer having a flank preferably extending mainly in a plane parallel to the transverse plane, c. forming at least against the flank of the dielectric layer, and preferably on the upper face of the support layer, the metal layer.

[0097] Using a support layer to form the metal layer allows it to be formed more precisely. This also allows the metal layer to be shaped into the desired shape without the need for etching steps that could damage it.

[0098] According to one example, the dielectric layer comprises a first dielectric layer and a second dielectric layer, the second dielectric layer and the support layer being separated by the first dielectric layer, and the method further comprises a step of polishing an upper portion of the metal layer and the second dielectric layer, with a selective stop on the first dielectric layer. The polishing step may in particular take place before the step of forming the memory layer, and preferably after the implantation step.

[0099] In order to allow selective polishing of the second dielectric layer selectively to the first dielectric layer, these two dielectric layers are of different natures. For example, the first dielectric layer may be based on SiN and the second dielectric layer based on SiO2.

[0100] Using a support layer comprising two layers of different natures and carrying out a polishing of the metal layer stopping when the second dielectric layer is completely exhausted makes it possible to very well control the height of the metal layer. The polishing is stopped without damaging the portion of the remaining metal layer.

[0101] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0102] A layer may also be composed of several sub-layers of the same material or of different materials.

[0103] A substrate, a layer, a device, “based” on a material M, is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus a material based on an IILN material may comprise an IILN material with added dopants.

[0104] The term “selective etching with respect to” or “etching exhibiting selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching speed of the material A greater than the etching speed of the material B. The selectivity is the ratio between the etching speed of the material A and the etching speed of the material B. The selectivity between A and B is denoted SA:B.

[0105] A reference frame, preferably orthonormal, comprising the axes X, Y, Z is shown in figures 2 to 23B and 25A to 25D. The Z direction may be designated “stacking direction”.

[0106] In the present patent application, we will preferably speak of thickness for a layer and of height for a structure or a device. The height is taken perpendicular to the longitudinal plane XY. The thickness is taken in a direction normal to the main extension plane of the layer. Thus, a layer or portion of a layer typically has a thickness along Z, when it extends mainly along the longitudinal plane XY, and a projecting element, for example an isolation trench, has a height along Z. The relative terms “on”, “under”, “above”, “below”, “underlying” preferably refer to positions taken along the Z direction.

[0107] The terms “substantially”, “approximately”, “of the order of” mean, unless otherwise stated, “to within 10%, preferably to within 5%”.

[0108] A PCM device 1 is typically manufactured at the end of the manufacturing line (commonly referred to as the back-end of the line, or back-end). The PCM device 1 and its substrate may be arranged between two metal levels M of the back-end, in particular between the last two levels, for example between MN and Mx icommc illustrated in [Fig.l]. The position of the part of the device manufactured at the start of the manufacturing line (usually referred to as the front-end) is indicated by dotted lines in [Fig.l]. Integrations may more generally go up to ten metal levels or more. The term substrate does not necessarily mean a monolayer and may include a stack of layers, in particular in the context of a back-end production.

[0109] Method of manufacturing a phase change memory device

[0110] An embodiment of the method according to the invention will now be described with reference to Figures 3A to 23B. For reasons of clarity, these figures illustrate the obtaining of a single memory point. Naturally, these steps can make it possible to obtain numerous memory points simultaneously.

[0111] Furthermore, these figures illustrate the manufacture of a memory point whose structure can be described as a “WALL” structure. In this structure, the heating element, the memory layer and the upper electrode are stacked, in this order, according to the stacking direction Z. The heating element also has, in the case of this structure, a shape that is invariant according to a direction perpendicular (here Y) to the stacking direction Z (for example, the shape of a straight block or, seen in section, the shape of an “L”). The steps described below can, however, be perfectly adapted to the formation of memory points having other structures. Different examples of structures will be presented further, with reference in Figures 25A to 25D.

[0112] It should be noted that all the figures indexed “A” correspond to top views along the stacking direction Z, while all the figures indexed “B” correspond to side views.

[0113] Figures 3A and 3B illustrate the provision of a support layer 100. The support layer 100 has an upper face 101 extending mainly in a longitudinal plane XY.

[0114] The support layer 100 may correspond to a metal level of the back-end, typically the level MN.i, or to a part of this level. It may be designated the lower metal line or the lower interconnection line. It typically comprises at least one metal via 150 whose upper face 151 is preferably flush with the upper face 101 of the support layer 100. The metal via 150 may for example be tungsten-based. It has a width l150 along the first direction X, with preferably l150 > 1 nm, and preferably l150 < 500 nm.

[0115] Figures 4A and 4B illustrate the formation of a dielectric layer 200 on the upper face 101 of the support layer 100. The dielectric layer 200 typically comprises a first dielectric layer 210 and a second dielectric layer 220, the first dielectric layer 210 extending from the upper face 101 of the support layer 100 and the second dielectric layer 220 extending over the first dielectric layer 210. Preferably, the first dielectric layer 210 and the second dielectric layer 220 are in contact with each other. In this case, the upper face 211 of the first dielectric layer 210 is in contact with the lower face 222 of the second dielectric layer 220.

[0116] The dielectric layer 200, the first dielectric layer 210 and the second dielectric layer 220 respectively have a thickness e20o, e2i0 and e220 according to the stacking direction Z. As will become apparent later, the thickness e2i0 of the first dielectric layer 210 can determine the height hec of the heating element of the device 1 obtained at the end of the process. Thus, it is expected that e2i0 is substantially equal to the desired height hec for the heating element.

[0117] The dielectric layer 200 can for example be deposited over the entire support layer 100 (FIGS. 4A, 4B), then be partially etched in order to at least partially, and preferably entirely, expose the upper face 151 of the metal via 150 (FIGS. 5A, 5B).

[0118] Preferably, the etching of the dielectric layer 200 is configured to give it a flank 203 extending substantially perpendicularly, to within 30%, to the upper face 101 of the support layer 100. The first dielectric layer 210 and the second dielectric layer 220 can be etched during the same etching step, or during two successive etching steps. In both cases, preferably potentially, the sides 213, 223 thus formed in these two layers 210, 220 are in the extension of one another in the stacking direction Z. Together they form the side 203 of the dielectric layer 200.

[0119] The flank 203 of the dielectric layer 200 is ideally located in the extension of a flank 153, perpendicular to its upper face 151, of the metal via 150. The dielectric layer 200 may also be located partly above the metal via 150, in which case its flank 203 is located in advance relative to the flank 153 of the metal via 150. This advance preferably does not exceed 50 nm. The flank 203 of the dielectric layer 200 may also be located, in projection in the longitudinal plane XY, in retreat relative to the metal via 150. This may be of particular interest when it is desired that the metal via 150 connects a second heating element (the two heating elements can then be selected separately using the metal lines located above the corresponding memory points).The fact that the side 203 is set back from the metal via 150 then makes it possible to leave more space above the metal via 150 for the presence of this second heating element.

[0120] It is understood that to produce a plurality of memory points 1000, the dielectric layer 200 will be structured so as to form a plurality of flanks 203 against each of which, as will be described later, a heating element 3000 will be formed. Preferably, each of the flanks 203 will be located above a separate metal via 150.

[0121] At this stage of the process, it is possible to carry out an implantation of a third doping species in the dielectric layer 200 (implantation not shown in the figures). In particular, it is possible to implant a so-called doped portion 215 of the first dielectric layer 210 extending from the flank 203 of the latter.

[0122] Figures 6A and 6B then illustrate the formation of a metal layer 300 on the dielectric layer 200 and on the support layer 100. The metal layer 300 can be deposited, preferably in a conformal manner: a. on the upper face 201 of the dielectric layer 200, and more particularly on the upper face 221 of the second dielectric layer 220, b. against the flank 203 of the dielectric layer 200, and therefore both against the flank 213 of the first dielectric layer 210 and against the flank 223 of the second dielectric layer 220, c. on the upper face 101 of the support layer 100 and in particular on the upper face 151 of the metal via 150.

[0123] Thus, the metal layer 300 matches the shape of the dielectric layer 200. It is also preferably in contact with the upper face 151 of the metal via 150.

[0124] We thus distinguish three portions of the metallic layer 300: a. a first portion 300a extending above the plane in which the upper face 201 of the dielectric layer 200 extends, b. a second portion 300b extending above the metal via 150 and possibly, if the dielectric layer 200 is set back relative to the metal via 150, above a part of the support layer 100 not being the metal via 150 and not being covered by the dielectric layer 200, c. a third portion 300c extending above the remaining part of the support layer 100 not being the metal via and not being covered by the dielectric layer 200.

[0125] The heating element 3000 of the memory point will essentially be formed by the second portion 300b and a part of the portion 300c.

[0126] The first portion 300a and the third portion 300c each have main extension planes parallel to the longitudinal plane XY and their thickness is thus measured along the stacking direction Z. The second portion 300b has an “L” shape, composed of a portion called the main portion extending from the flank 203 of the dielectric layer 200 and a portion called the “return” 320b extending from the upper face 151 of the metal via 150. The return 320b of the second portion 300b is separated from the dielectric layer 200 by the main portion of the L. The main portion of the “L” corresponds to a wall 3000 formed by the metal layer 300 against the flank 203 of the dielectric layer 200. This wall 3000 extends in particular between a first main flank 303 and a second main flank 304 of the metal layer 300. The wall 3000 is in contact with the upper face 151 of the metal via 150.It is in particular this wall 3000 which will have the function of heating element within the memory point 1000.

[0127] The thickness of the wall 3000 is measured along the first direction X. The thickness of the return 320b of the second portion 300b is measured along the stacking direction Z.

[0128] The metal layer 300 has a thickness e300 measured along the first direction X or the stacking direction Z depending on the portion considered. In the typical case of a conformal deposition, e300 is identical in the three portions 300a, 300b, 300c of the metal layer 300. e300 is preferably less than 10 nm.

[0129] In order to obtain very good conformity of the metal layer 300, this step can be carried out by chemical deposition such as chemical vapor deposition (commonly abbreviated CVD) or atomic layer deposition (commonly abbreviated ALD). However, it is possible to use other deposition methods. will prefer deposition techniques that ensure good conformity of the 3000 wall thickness.

[0130] It should be noted that the metal layer 3000 may not be deposited on all the regions mentioned above, as long as it forms at least the wall 3000. It is conceivable that the metal layer 300 is deposited only against the flank 203 of the dielectric layer 200, and therefore, from this deposition step, only forms the wall 3000, or else only against the flank 203 and on the upper face 151 of the metal via 150 and therefore, from this deposition step, only forms the second portion 300b.

[0131] As illustrated in Figures 7A and 7B, it is possible at this stage of the method to carry out a step of implanting a second doping species in the metal layer 300 from at least its first main flank 303. This implantation step will be described in more detail later. Advantageously, the implantation extends into the first dielectric layer 210, and possibly into the second dielectric layer 220. The first dielectric layer 210 thus has a doped portion 215 extending from its flank 203. Figures 8A and 8B illustrate the doping that can be obtained in the metal layer after the implantation carried out during the step illustrated in Figure 7.

[0132] Figures 9A and 9B illustrate the formation of a first encapsulation layer 400 on the metal layer 300. This step is preferably carried out less than 24 hours after the formation of the metal layer 300. This makes it possible to avoid excessive oxidation of the metal layer 300.

[0133] The first encapsulation layer 400 is in particular deposited, preferably in a conforming manner: a. on an upper face 301a of the first portion 300a of the metal layer 300, b. against the first main flank 303 of the metal layer 300, c. on an upper face 301c of the third portion 300c of the metal layer 300.

[0134] Thus, the first encapsulation layer 400 matches the shape of the metal layer 300. It is preferably in direct contact with it.

[0135] Three portions of the first encapsulation layer 400 are thus distinguished: a. a first portion 400a extending above the plane in which the upper face 301a of the first portion 300a of the metal layer 300 extends, b. a second portion 400b extending above, in the stacking direction Z, the return 320b of the second portion 300b of the metal layer 300, and, in the first direction X, next to the first main flank 303 of the metal layer 300, c. a third portion 400c extending above the third portion 300c of the metal layer 300.

[0136] The first encapsulation layer 400 has a thickness e400 measured along the first direction X or the stacking direction Z depending on the portion considered. In the typical case of a conformal deposition, e400 is identical in the three portions 400a, 400b, 400c of the first encapsulation layer 400. e400 is typically greater than 5 nm, and preferably less than 30 nm.

[0137] Again, a deposition technique guaranteeing good conformity of the first encapsulation layer 400 (CVD, ALD) will be preferred.

[0138] The second portion 400b of the first encapsulation layer 400 has a step shape. This step notably comprises an “L”-shaped part consisting of: a. of a main portion 410b extending between a first main flank 403 and a second main flank 404 of the first encapsulation layer 400, the second main flank 404 of the first encapsulation layer 400 being located opposite the first main flank 303 of the metal layer 300, b. of a return 420b located above, in the stacking direction Z, the return 320b defined by the second portion 300b of the metal layer 300, this return 420b being separated from the wall 3000 by the main portion 410b of the “L”.

[0139] As illustrated in Figures 10A and 10B, it is possible at this stage of the method to carry out a step of implanting a first doping species in at least a portion of the main portion 410b of the “L” of the first encapsulation layer 400. This implantation is carried out at this stage of the method from at least the first main flank 403 of the first encapsulation layer 400. Preferably, the implantation of the first species extends into the metal layer 300. Advantageously, it also extends into the dielectric layer 200, and in particular into a doped portion 215 of the first dielectric layer 210. This implantation step will be described in more detail later. Figures 11A and 11B illustrate the doping that can be obtained in the metal layer after the implantation carried out during the step illustrated in Figure 10.

[0140] Figures 12A and 12B then illustrate a step of partial removal, typically by etching, of the first encapsulation layer 400 and of the metal layer 300. Advantageously, during this step, the following are removed: a. the first portion 400a of the first encapsulation layer 400 and the first portion 300a of the metal layer 300, b. the return 420b of the second portion 400b of the first encapsulation layer 400 as well as the portion of the return 320b of the second underlying portion 320b according to the stacking direction Z. This withdrawal makes it possible to make part of the upper face 151 of the metal via 150 visible. c. the third portion 400c of the first encapsulation layer 400 and the third portion 300c of the metal layer 300.

[0141] This removal can be carried out using a reaction ion etching process (commonly abbreviated RIE, from the English “Reactive-Ion Etching”). Anisotropic etching conditions will be favored in order to preferentially etch the portions of layers whose main extension plane is parallel to the longitudinal plane XY while retaining the main portion 410b of the first encapsulation layer 400.

[0142] As illustrated in Figures 13A and 13B, it is possible at this stage of the method to carry out a step of implanting a doping species in the first encapsulation layer 400, preferably also in the metal layer 300 and preferably also in the dielectric layer 200. This implantation step will be described further. Figures 14A and 14B illustrate the doping that can be obtained in the metal layer after the implantation carried out during the step illustrated in Figure 13. The doping species implanted during this step can be the first doping species, the second doping species, the third doping species or a distinct doping species.

[0143] Figures 15A and 15B illustrate the optional formation of a second encapsulation layer 500 on the metal layer 300. The second encapsulation layer 500 is in particular deposited, preferably in a conformal manner: a. on the upper face 201 of the support layer 200, b. against the first main flank 403 of the first encapsulation layer 400, c. on the visible portion of the upper face 151 of the metal via 150 and on the upper face 101 of the support layer 100.

[0144] Three portions of the second encapsulation layer 500 are thus distinguished: a. a first portion 500a extending above, in the stacking direction Z, the plane in which the upper face 201 of the dielectric layer 200 mainly extends, b. a second portion 500b extending in particular, along the first direction X, next to the main portion 410b of the first encapsulation layer 400 and next to the return 320b of the metal layer 300. The second portion 500b is preferably in direct contact with the main portion 410b of the first encapsulation layer 400 and with the return 320b of the metal layer 300. This second portion 500b also preferably extends from the portion of the upper face 151 of the metal via 150 made apparent during the removal step illustrated in Figure 12. It may also be in contact with a portion of the support layer 100 not being the metal via 150, as illustrated in [Fig.15B]. c. a third portion 500c extending above a portion of the support layer 100 not being covered by the support layer 200 and preferably not being the metal via.

[0145] The second encapsulation layer 500 has a thickness e500 measured along the first direction X or the stacking direction Z depending on the portion considered. In the typical case of a conformal deposition, e500 is identical in the three portions 500a, 500b, 500c of the second encapsulation layer 500. e500 is typically greater than 5 nm, and preferably less than 30 nm.

[0146] Again, a deposition technique guaranteeing good conformity of the first encapsulation layer 400 (CVD, ALD) will be preferred.

[0147] As illustrated in Figures 16A and 16B, it is possible at this stage of the method to carry out a step of implanting a doping species in the second encapsulation layer 500. The implantation preferably also extends into the first encapsulation layer 400, preferably also into the metal layer 300 and preferably also into the dielectric layer 200. This implantation step will be described in more detail later. Figures 17A and 17B illustrate the doping that can be obtained in the metal layer after the implantation carried out during the step illustrated in Figure 16. The doping species implanted during this step can be the first doping species, the second doping species, the third doping species or a separate doping species.

[0148] Figures 18A and 18B illustrate the partial removal of the second encapsulation layer 500.

[0149] Advantageously, during this step, the first portion 500a and the third portion 500c of the second encapsulation layer 500 are removed. This removal step is optional. In particular, the first portion 500a may be removed later in the method, as will be described further below. The third portion 500c may be kept in the stack, without consequence.

[0150] As illustrated in Figures 19A and 19B, it is possible at this stage of the method to carry out a step of implanting a doping species in the second encapsulation layer 500. The implantation preferably also extends into the first encapsulation layer 400, preferably also into the metal layer 300 and preferably also into the dielectric layer 200. This implantation step will be described in more detail later. Figures 19A and 19B illustrate the doping that can be obtained in the metal layer after the implantation carried out during the step illustrated in Figure 18.

[0151] Figures 21A and 21B illustrate an optional step of forming a filling layer 600 above, in the stacking direction Z, the support layer 200, the metal layer 300, the first encapsulation layer 400, the second encapsulation layer 500 and the portion of the support layer 100 not being covered by any of these layers 200, 300, 400, 500. The filling layer 600 may for example be based on SiO2.

[0152] The filling layer 600 has an upper face 601 extending mainly in a plane parallel to the longitudinal plane XY. The deposition of this filling layer 600 thus makes it possible to create a continuous and substantially flat face from which to carry out a polishing step represented by the transition from FIGS. 21A and 21B to FIGS. 22A and 22B.

[0153] This polishing step is preferably carried out by chemical mechanical polishing (commonly referred to as CMP). The polishing is preferably configured to selectively stop on the upper face 211 of the first dielectric layer 210, after having completely removed the second dielectric layer 220, a portion of the wall 3000, a portion of the main portion 410b of the first encapsulation layer 400 and a portion of the main portion 510b of the second encapsulation layer 500, all of these portions extending above, in the stacking direction Z, the plane in which the upper face 211 of the first dielectric layer 210 mainly extends. If it has not been removed previously, the first portion 500a of the second encapsulation layer 500 can be removed by this polishing step.

[0154] Figures 23A and 23B illustrate the formation on the wall 3000 - and, advantageously, also on the encapsulation layers 400, 500 - of a memory layer 700 and an upper electrode 800. A secondary filling layer 600' can also be formed around these elements, on the filling layer 600 and on the first support layer 210. The secondary filling layer 600' can for example be based on SiO2.

[0155] The assembly comprising the metal layer 300, the memory layer 700 and the upper electrode 800 forms a memory point 1000.

[0156] The structural characteristics of this memory point 1000 will be described in more detail later.

[0157] Implementation stage

[0158] The method according to the invention provides at least one implantation step aimed at implanting with a doping species at least the first encapsulation layer 400, and preferably also the portion of the metal layer 300 which will become the heating element of the memory device 1 manufactured by the method. The following paragraphs aim to describe this implantation step more precisely.

[0159] The dopant species implanted during this step may be one of the following species: argon, carbon, nitrogen, silicon, xenon, titanium, tantalum, tungsten, germanium, oxygen, cobalt and neon. Several of these species may be implanted.

[0160] The implantation is typically carried out at an energy between 1 and 500 KeV, for example at 12 keV.

[0161] The implantation is preferably configured so that the first encapsulation layer 400 is doped on a portion 450 having a thickness e450 with e450 > 0.05*e400, and preferably e450 > 0.10*e400.

[0162] The implantation is furthermore preferably configured so that the heating element 3000 is implanted over its entire thickness eec, typically equal to e300o described above.

[0163] In all the embodiments of the implantation envisaged below, the implantation is carried out according to an implantation angle aimpi measured relative to the plane in which the first main flank 303 of the metal layer 300 mainly extends. aimpi is therefore typically measured relative to the transverse plane YZ. aimpi is in particular adjusted according to the spacing between the memory points 1000 formed simultaneously by the method according to the invention. Thus, the closer the memory points 1000 are, the lower aimpi must be. Typically, aimpi is between 15° and 75°, preferably between 25° and 45°.

[0164] Before the implantation step, the metal layer 300 has an electrical resistivity greater than 102 pQ.cm, or even greater than 103 pQ.cm, and typically less than 104 pQ.cm. After the implantation step, when the latter also targets the metal layer 300, the latter preferably has an electrical resistivity less than 103 pQ.cm.

[0165] The stack provided at the start of the method according to the invention corresponds to any one of the stacks illustrated in figures 9, 12, 15 and 18.

[0166] It is perfectly conceivable that the implantation step is made up of several implantation sub-steps, each implantation sub-step corresponding to one of the implantation steps described below. For example, an implantation sub-step can be provided between the formation of the metal layer 300 and the formation of the first encapsulation layer 400, in order to implant the metal layer and possibly the first dielectric layer 210, then an implantation sub-step between the formation of the first encapsulation layer 400 and the formation of the second encapsulation layer 500, in order to implant the first encapsulation layer 400 and possibly the layers that it covers (metal layer 300, first dielectric layer 210).

[0167] It is also possible that several implantations are carried out successively, for example to implant several doping species at the level of the same layer(s).

[0168] According to one embodiment, the implantation of the first encapsulation layer 400 is carried out before (FIGS. 10B and 13B) the step of forming the second encapsulation layer 500. According to another embodiment, it is carried out after (FIGS. 16B and 19B). It can take place at the same time as the implantation of other layers, and in particular at the same time as the implantation of the metal layer 300 and possibly the implantation of the second encapsulation layer 500 (see the embodiments described above).

[0169] As mentioned previously, the metal layer 300 is preferably also implanted.

[0170] According to an embodiment illustrated in [Fig.7B], the implantation of the metal layer 300 takes place when its first main flank 303 is not covered. In other words, in this embodiment, the first main flank 303 of the metal layer 300 is left free. The step of implantation of the metal layer 300 is therefore carried out before the step of forming the first encapsulation layer 400 (and, if it is carried out, before the step of forming the second encapsulation layer 500).

[0171] According to another embodiment, the step of implanting the metal layer 300 is carried out after the step of forming the first encapsulation layer 400 and, if it is carried out, before the step of forming the second encapsulation layer 500. In this case, the implantation of the heating element 3000 of the device 1 is therefore carried out through the first encapsulation layer 400. According to an example of this embodiment, the implantation is carried out before the partial removal of the metal layer 300 and the first encapsulation layer 400 described above (FIGS. 10B, 11B). According to another example, the implantation is carried out after this partial removal (FIGS. 13B, 14B).

[0172] In this embodiment, the first encapsulation layer 400, and in particular its main portion 410b, is also implanted. It is expected that this implantation is effective in at least one portion called the doped portion 450 of the main portion 410b of the first encapsulation layer 400, and that this doped portion 450 preferably has a doping species concentration greater than or equal to 5.10 20 atoms / cm3. This doped portion 450 extends from the first main flank 303 of the metal layer 300 (see FIGS. 11B and 14B).

[0173] [Fig.24] represents the result of a software simulation of the carbon implantation of a SiN / TiN / SiN tri-layer. In this simulation, the first SiN layer can be assimilated to the first dielectric layer 210, the TiN layer to the heating element 3000 and the second SiN layer to the first layer encapsulation 400. The parameters were set to simulate an implantation at 12 keV with a dose of 1016 at.cm2 centered in the heating element and also effective in the neighboring portions of the dielectric layer and the first encapsulation layer, at aimpi=45°. It is observed that such an implantation generates a carbon peak in the heating element 3000 at a concentration of more than 25.1020 atoms / cm3. The creation of a gradient in each of the SiN layers from the interface with the heating element is also observed. This gradient extends over approximately twenty nanometers.

[0174] According to another embodiment, the step of implanting the metal layer 300 is carried out after the step of forming the first encapsulation layer 400 and after the step of forming the second encapsulation layer 500. In this case, the implantation of the heating element 3000 of the device 1 is therefore carried out through the second encapsulation layer 500 and through the first encapsulation layer 400. According to an example of this embodiment, the implantation is carried out before the partial removal of the second encapsulation layer 500 described above (FIGS. 16B, 17B). According to another example, the implantation is carried out after this partial removal (FIGS. 19B, 20B) on a thickness e450 taken perpendicular to this same flank 303.

[0175] In this embodiment, the first encapsulation layer 400 is also implanted, preferably over its entire thickness e400. The second encapsulation layer 500, and in particular its second portion 500b, is also implanted. It is provided that at least one portion called the doped portion 550 of the second portion 500b of the second encapsulation layer 500 has a doping species concentration greater than or equal to 1.1020 atoms / cm3. This doped portion 550 extends from the first main flank 403 of the first encapsulation layer 500 (see FIGS. 17B and 14B) over a thickness e550 taken perpendicular to this same flank 403.

[0176] For the sake of clarity and in particular to distinguish the different moments of the process at which the implantation can be carried out, the doping resulting from the implantations illustrated in Figures 7, 10, 13, and 16 are only illustrated in Figures 8, 11, 14 and 17, respectively. The doping resulting from the implantation illustrated in Figures 19 is illustrated up to Figure 23.

[0177] It is understood that all the steps described above making it possible to arrive at the memory point 1000 can be carried out, preferably simultaneously, above different zones of the support 100 in order to manufacture a plurality of memory points 1000.

[0178] As explained previously, it turned out that by carrying out an implantation step in the first encapsulation layer, its stoichiometry and its atomic structure are modified, which has the effect of reducing its heat transfer coefficient. This causes a thermal confinement effect of the heating element, and the heat emanating from the latter is thus dissipated more towards the memory layer 700 than in the other surrounding regions. The implantation thus has the effect of improving the ratio between the energy supplied to the heating element and the energy actually used for programming the state of the memory layer 700.

[0179] As described in detail previously, it has also been found that by also implanting the metal layer 300, its stoichiometry and its atomic structure are modified and new chemical elements are added in this same layer. Unexpectedly, this has the effect of improving the temperature resistance of the heating element 3000. This is particularly true when the implantation is carried out through the or even both encapsulation layers 400, 500, because then species are transferred from these layers to the heating element 3000.

[0180] Furthermore, the implantation makes it possible to improve the resistivity of the heating element 3000. This induces a stronger Joule effect within the heating element 3000 and therefore better control of the programming of the state of the memory layer 700. This increase in the metal layer 300 is notably due to the amorphization of the latter during the implantation.

[0181] Phase change memory device

[0182] Another object of the invention relates to the device 1 which can be obtained by any of the embodiments of the method described previously.

[0183] WALL structure

[0184] A particular embodiment of the device 1 will now be described with reference to FIG. 23. This embodiment relates to a WALL type memory point. It is understood, however, that other types of structures can be envisaged. These other structures will be described further.

[0185] Figure 23 illustrates a single memory point 1000 of the device 1 according to the invention, but it is understood that the device 1 can comprise several.

[0186] The memory point 1000 comprises a metal layer 300 based on a metallic material. The metal layer 300 typically comprises a wall 3000 and a return 320b. The wall 3000 extends between a first main flank 303 and a second main flank 304 of the metal layer 300. The wall 3000 and the return 320b together form an elbow, which may also be designated “L”. The return 320b is however optional. The metal layer 300 may comprise only the wall 3000.

[0187] The first main flank 303 and the second main flank 304 of the metal layer 300 preferably extend parallel to the second direction Y and to the stacking direction Z.

[0188] The metal layer 300 has an upper face 301 and a lower face 302. opposite each other and each extending substantially in a plane parallel to the longitudinal plane XY. The metal layer 300 extends entirely between its upper face 301 and its lower face 302.

[0189] The wall 3000 has an upper face 3001 and a lower face 3002 opposite each other and each extending substantially in a plane parallel to the longitudinal plane XY. The upper face 301 of the metal layer 300 and the upper face 3001 of the wall 3000 on the one hand and the lower face 302 of the metal layer 300 and the lower face 3002 of the wall 3000 on the other hand are preferably merged. In other words, preferably, the wall 3000 extends over the entire height of the metal layer 300.

[0190] The memory point 1000 further comprises, on the upper face 301 of the metal layer 300, a memory layer 700 based on a phase change material.

[0191] For example, the memory layer 700 may be based on or made of any material belonging to the ternary diagram of germanium Ge, antimony Sb and tellurium Te. For example, this material is chosen from GelSb2Te4, GeTe, Sb2Te3, Ge7SblTe2. The memory layer 700 may also be based on or made of an alloy of a material from the ternary diagram of Ge, Sb and Te and one or more element(s) from the following: Si, As, Se, N, S, In, Ga, Bi.

[0192] The memory layer 700 has an upper face 701 and a lower face 702 opposite each other and each extending in a plane perpendicular to the stacking direction Z. The upper face 701 and the lower face 702 of the memory layer 700 are also designated main faces 701, 702 of the memory layer.

[0193] The memory point 1000 further comprises, on the upper face 701 of the memory layer 700, a so-called upper electrode 800.

[0194] The wall 3000 constitutes the heating element 3000 of the memory point 1000.

[0195] The heating element 3000 is thermally coupled to the memory layer 700 so that at least a portion of the heat produced by the heating element 3000 by Joule effect is transferred, by conduction, to the memory layer 700. Preferably, the heating element 3000 is in contact with the memory layer 700.

[0196] The following paragraphs provide details of the typical dimensions of the heating element and the memory layer 700 in the case of a WALL structure as shown in [Fig.23B].

[0197] The heating element 3000 has a thickness eec, taken perpendicular to its main flanks 303, 304. This thickness is thus measured along the first direction X in the figures. Typically, eec is greater than 1 nm, preferably less than 50 nm, preferably less than 10 nm. For example, eec is substantially equal to 5 nm.

[0198] The heating element 3000 also has a height hec taken along the second main flank 304, in the stacking direction Z.

[0199] The heating element 3000 is configured so that hec > a * eec, with a > 2, preferably a > 5. Thus, the heating element 3000 has a height hec, in the Z direction, which is significant relative to its thickness eec in the X direction.

[0200] The heating element 3000 further has a width lec, measured perpendicular to hec and eec.

[0201] According to one embodiment, U > ô * eec, with ô > 2, preferably ô > 5. Thus, the heating element 3000 has a width lec, in the Y direction, which is significant relative to its thickness eec in the X direction.

[0202] With these relative dimensions hec, lec, and eec, the heating element 3000 has a wall shape which can be described as a wall or mur in English.

[0203] The memory layer 700 has a thickness ecm, measured perpendicular to the main faces 701, 702 of the memory layer 700 and from one main face to the other. Thus, ecm is measured in the same direction as hec. Typically, ecm is greater than 5 nm, preferably less than 200 nm, for example equal to 50 nm.

[0204] The memory layer 700 further has a length Lcm and a width lcm measured perpendicular to ecm and perpendicular to each other. Lcm is measured in the same direction as eec and lcm is measured in the same direction as lec*

[0205] The device 1 is advantageously configured so that hec > [3 * ecm, with [3 > 2, preferably [3 > 5, preferably [3 > 10.

[0206] The device 1 is advantageously configured so that Lcm > y * eec, with y > 2, preferably y > 5, preferably y > 10. This makes it possible to concentrate the transmission of the heat emitted by the Joule effect to a reduced area of ​​the memory layer 700. Indeed, for the memory point 1000 to be functional, it is sufficient for an electrical conduction to be created between the main faces 701, 702 of the memory layer 700. This can be obtained by a change of state of the phase change material in a reduced portion of the memory layer 700 only. By concentrating the impact of the Joule effect on a reduced portion of the memory layer 700, the efficiency of the memory point 1000 is maximized.

[0207] The wall 3000 can extend over the entire width lcm of the memory layer 700 (lec=lcm), or be less wide than the memory layer 700 (lec <lcm)-

[0208] As mentioned previously, the memory point 1000 may also have other types of structures. Different examples of possible structures are presented below.

[0209] So-called “ring” structure

[0210] A second example structure is illustrated in [Fig.25A]. In this example, the metal layer 300 differs from the example described with reference to [Fig.23B] in that it forms a closed contour in projection in the longitudinal plane XY. In particular, the first main flank 303 and the second main flank 304 of the metal layer 300 preferably each form a closed contour, preferably circular, in projection in the longitudinal plane XY. The metal layer 300 may in particular surround the dielectric layer 210, which may have a cylindrical shape, preferably circular. The metal layer 300 preferably has a base 310 whose main faces extend parallel to the longitudinal plane XY. The base 310 of the metal layer 300 is intended to be placed in contact with a metal via. The metal layer 300 is preferably flush with the upper face 401 of the first encapsulation layer 400 and with the upper face 211 of the first dielectric layer 210.

[0211] In this example, the memory layer 700 is located above the metal layer 300, the first support layer 210 and the first encapsulation layer 400.

[0212] Due to the shape of the metal layer 300, this structure can be referred to as a “ring” structure.

[0213] In the case of a ring structure, the implantation can for example be carried out after the formation of the first encapsulation layer 400, the metal layer 300 and a portion of the first stop layer 210 deposited against the second main flank 304. The implantation is then preferably configured to be effective in a portion 450 of the first encapsulation layer 400, in the metal layer 300 and in the portion of the first stop layer 210 already deposited. The cavity defined by the metal layer 300 can then be finished being filled by the first stop layer 210. The memory layer 700 can then be formed above the metal layer 300, the first encapsulation layer 400 and the first dielectric layer 210.

[0214] Structure called “confined ring”

[0215] A third example of structure is illustrated in [Fig.25B]. This structure is very close to the structure previously described. However, it differs in that the memory layer 700 forms a closed contour in projection in the longitudinal plane XY. It is located in the stacking direction Z in the extension of the metal layer 300. It separates in the longitudinal plane XY the first encapsulation layer 400 from the first dielectric layer 210. This time it is the memory layer 700 which is preferably flush with the upper face 401 of the first encapsulation layer 400 and with the upper face 211 of the first dielectric layer 210.

[0216] This structure therefore differs from the previous one in that the memory layer 700 is housed between the first encapsulation layer 400 and the first dielectric layer 210. For this reason, this structure can be referred to as a “confined ring” structure.

[0217] The implantation of a confined ring structure can be carried out in the same way as in the case of a ring structure. A step of removing an upper portion of the metal layer 300 will however be provided in addition in order to arrange between the first encapsulation layer 400 and the first support layer 210 an opening in which the memory layer 700 will then be formed.

[0218] Structure called “ring with micro-trench”

[0219] A fourth example of structure is illustrated in [Fig.25C]. This example differs from the second example in that a dielectric layer 900 partially separates the metal layer 300 and the memory layer 700. The contact between these two layers is made on only a portion of the contour defined by the metal layer 300. The memory layer 700 extends above the dielectric layer 900 as well as in a through opening made in the dielectric layer 900, which can be called a trench. This trench opens onto the metal layer 300 and thus allows contact between the memory layer 700 and the metal layer 300.

[0220] This structure can be referred to as a “micro-trench ring” structure.

[0221] The implantation of a ring structure with micro-trench can be carried out in the same way as in the case of a ring structure. A step of deposition of the dielectric layer 900 will however be provided in addition before the formation of the memory layer 700.

[0222] Structure called “bridge”

[0223] A fifth example of structure is illustrated in [Fig.25D]. The main flanks 303, 304 of the metal layer 300 extend in this example in planes substantially parallel to the longitudinal plane XY. The metal layer 300 also preferably comprises two portions, separated from each other by the memory layer 700. Preferably, the memory layer 700 also extends above the first encapsulation layer 400. This structure can be referred to as a “bridge” structure.

[0224] It is possible, to form the device 1 according to this exemplary embodiment of the invention, to provide a stack comprising the first dielectric layer 210, the metal layer 300 and the first encapsulation layer 400, to carry out an implantation of the first encapsulation layer 400 (as well as preferably of the metal layer 300 and of the first dielectric layer 210), then to form an opening in the first encapsulation layer 400 and in the metal layer 300 and finally to form the memory layer 700 at least partially in this opening.

[0225] Through the various embodiments described above, it clearly appears that the invention proposes an effective solution for improving the temperature resistance of the heating element of a PCM type memory device. The invention also makes it possible to improve the resistivity of this element, and, in the embodiments providing the presence of one or more encapsulation layers against the heating element, to improve its thermal confinement.

[0226] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Claims

1. A phase change memory device (1) comprising a memory point (1000), the memory point (1000) comprising: • a metal layer (300) based on a metal material and forming a heating element (3000), • a memory layer (700) based on a phase change material, the phase change material being configured so that the memory layer (700) selectively switches from a first resistive state (LRS) having a first resistivity to a second resistive state (HRS) having a second resistivity greater than the first resistivity (LRS), • an upper electrode (800), the heating element (3000) being intended to receive an electric current making it possible to produce heat by the Joule effect and to transfer a portion of this heat to the memory layer (700) so as to selectively switch the memory layer (700) from one of the first resistive state (LRS) and the second resistive state (HRS),towards the other among the first resistive state (LRS) and the second resistive state (HRS), the heating element (3000) has a first main flank (303) and a second main flank (304), opposite to each other, the memory device further comprising a first encapsulation layer (400) extending from the first main flank (303) of the metal layer (300), characterized in that the first encapsulation layer (400) has a portion (450), called doped, having a doping based on at least one species, called first doping species, the doped portion (450) extending from the first main flank (303) of the metal layer (300).,

2. Device (1) according to the preceding claim in which the concentration of doping species in the doped portion (450) is greater than or equal to 5.1020 atoms / cm3, preferably greater than or equal to 1.1021 atoms / cm3.

3. Device (1) according to any one of the preceding claims in which the first encapsulation layer (400) has a thickness e400 taken in a direction perpendicular to the first sidewall main (303) of the metal layer (300), the doped portion (450) extending over a thickness e450 in this same direction within the first encapsulation layer (400), with e450 > 0.05*e400, preferably e450 > 0.10*e400.

4. Device (1) according to any one of the preceding claims in which the metal layer (300) has a thickness e300 between its first main flank (303) and its second main flank (304), with e300 <10 nm.

5. Device (1) according to any one of the preceding claims in which the metal layer (300) has doping based on a second doping species, preferably identical to the first doping species.

6. Device (1) according to any one of the preceding claims further comprising a first dielectric layer (210) extending against the second main flank (304) of the metal layer (300), the first dielectric layer (210) having a portion (215), called doped, having a doping based on at least one species, called third doping species, preferably identical to the first doping species, the doped portion (215) of the first dielectric layer (210) extending from the second main flank (304) of the metal layer (300).

7. Device (1) according to any one of the preceding claims in which the first doping species is chosen from the following species: silicon, carbon, argon, nitrogen, xenon, titanium, tantalum, tungsten, germanium, oxygen, cobalt, neon and their alloys.

8. Device (1) according to any one of the preceding claims in which the metallic material is based on at least one of the following materials: TiN, TiC, TiSiN, TiSiCN, TiWN, TaN, TaCN.

9. A method of manufacturing a phase change memory device (1) comprising a memory point (1000), the method comprising the following steps: • providing an assembly comprising at least: i. a metal layer (300) based on a metallic material and intended to form a heating element (3000) for the memory point (1000), the metal layer (300) having a first main flank (303), ii. a first encapsulation layer (400) extending from the first main flank (303) of the metal layer (300), • implanting a species called the first doping species in a portion (450), called doped, of the first encapsulation layer (400), the doped portion (450) extending from the main flank (303) of the metal layer (300), • forming against a face (301) of the metal layer (300) a stack comprising: i. a layer called the memory layer (700) based on a phase change material, thermally coupled with the metal layer (300) so that heat produced by the Joule effect by the metal layer (300) is transferred to the memory layer (700), ii. an upper electrode.

10. Method according to the preceding claim in which the first doping species is chosen from the following species: silicon, carbon, argon, nitrogen, oxygen, xenon, titanium, tantalum, tungsten, germanium, cobalt, neon and their alloys.

11. Method according to any one of the two preceding claims further comprising a step of implanting a species called second doping species, preferably identical to the first doping species, in the metal layer (300), the step of implanting the metal layer (300) being carried out through the first encapsulation layer (400).

12. Method according to any one of the three preceding claims in which the first encapsulation layer (400) is based on at least one of the following materials: SiN, SiCN, SiC.

13. A method according to claim 11 alone or in combination with claim 12 wherein the first encapsulation layer (400) has a first main flank (403) and a second main flank (404) opposite each other, the second main flank (404) being opposite the first main flank (303) of the metal layer (300), the method further comprising forming a second layer encapsulation layer (500) against the first main flank (403) of the first encapsulation layer (400), and in which the implantation of the second doping species in the metal layer (300) is carried out through the second encapsulation layer (500).

14. A method according to any one of the five preceding claims wherein providing the assembly comprises the following steps: • providing a support layer (100) having an upper face (101) extending mainly in a plane parallel to the longitudinal plane (XY), • forming on a portion of the upper face (101) of the support layer (100) a dielectric layer (200), the dielectric layer (200) having a flank (203) preferably extending mainly in a plane parallel to the transverse plane (YZ), • forming at least against the flank (203) of the support layer (200), and preferably on the upper face (101) of the support layer (100), the metal layer (300).

15. A method according to the preceding claim wherein the dielectric layer (200) comprises a first dielectric layer (210) and a second dielectric layer (220), the second dielectric layer (220) and the support layer (100) being separated by the first dielectric layer (210), the method further comprising a step of polishing a portion of the metal layer (300) and the second dielectric layer (220), with a selective stop on the first dielectric layer (210).

Images