Non-linear analog control of multi-phase electrical circuits

Abstract

The invention relates to a multi-phase electrical circuit for supplying a target load, comprising: a power cell with N supply branches converging at the output node; a control circuit comprising: a voltage regulation circuit configured to generate an alternating binary regulation signal from a combination of the output voltage and a noise voltage; a distribution circuit configured to generate, for each supply branch, at least one dedicated activation signal from the regulation signal; the plurality of activation signals being phase-shifted relative to each other by a phase shift that varies over time. Figure for the abstract: Fig. 1

Description

Title of the invention: Non-linear analog control of multi-phase electrical circuits

[0001] Scope

[0002] The present invention relates to multi-phase electrical circuits for space applications. More particularly, the invention relates to the implementation of non-linear and analog control of multi-phase circuits.

[0003] Problem raised

[0004] Multiphase converters are integrated into power supply systems to improve energy efficiency, optimize voltage regulation, and manage the load more evenly. They operate with electrical signals distributed across multiple phases, allowing for balanced load distribution. These converters are versatile, capable of converting between direct and alternating voltage, and regulating voltage or current to meet the specific needs of electrical devices.

[0005] In the context of a multiphase converter, a "phase" is understood to be an individual power supply branch of the electrical circuit that performs the conversion of electrical energy. Multiphase converters use several of these phases, typically two, three, or more, which operate independently to perform the energy conversion. Each phase operates with a time lag relative to the others, thus creating a time sequence in which each phase contributes successively to the total output of the converter. This approach distributes the electrical load and reduces current variations, which can lead to greater efficiency and reduced current ripple. For example, in a two-phase converter, two phases operate alternately to reduce the voltage. Similarly, a three-phase converter would involve three phases operating successively.

[0006] A multi-phase converter generally comprises a power cell formed by the plurality of phases and a control circuit configured to control the activation and deactivation of the different phases to obtain the time offset of operation of the phases relative to each other.

[0007] With the increasing power requirements of computing units, voltage regulator modules (VRMs) must supply more current while improving their responsiveness to the load transistors. To achieve this, the use of multi-phase or multi-phase series-capacitor topologies is preferred. Combining these topologies with nonlinear control optimizes the performance of these converters. weavers. However, it is complex to apply effective nonlinear control to multiphase or multiphase series capacitance converters, especially in applications that do not include a digital controller such as a microprocessor, FPGA or CPU.

[0008] More specifically, implementing the control circuit with digital controllers results in a circuit with degraded technological robustness in the context of space applications. Indeed, conventional digital control circuits often exhibit limitations in terms of reliability in the extreme environments of space. Currently available solutions are often based on conventional digital control circuits that are not optimized for the specific constraints of space, particularly radiation resistance, reliability, and stability.

[0009] Furthermore, the invention attempts to solve the problem related to changes in the operating frequencies of the control signals for the different phase-shifted phases. Indeed, when the control circuit is not governed by a fixed clock frequency, it becomes difficult to generate phase-shifted control signals with an indeterminate frequency. In this case, the control circuit must phase-shift the control signals, starting from a single input signal, without knowing beforehand the triggering time of the next phase. This is referred to as the design of a "non-linear" control circuit.

[0010] For the description of the invention, we will use the terminology "power branch" to refer to the electrical phases of a multi-phase circuit.

[0011] Response to the problem and provision of a solution

[0012] To overcome the limitations of existing solutions, the invention proposes a multi-phase electrical circuit with a non-linear, analog phase control circuit. The non-linearity of the control circuit allows for phase shifting of a main control signal across several phases without knowing its period. Furthermore, the architecture proposed according to the invention improves the operational stability of the multi-phase circuit independently of the output load, which is adjustable according to the intended application.

[0013] The analog implementation of the control circuit according to the invention ensures the compatibility of the multi-phase circuit with a harsh environment, and more particularly with a space environment. This offers superior reliability compared to digital microcontrollers sensitive to environmental constraints for space applications.

[0014] Summary / Claims

[0015] The invention relates to a multi-phase electrical circuit configured to generate an output current or output voltage to power a target load. Said circuit multi-phase electrical system including: - a power cell comprising: • an input node to provide an input voltage; • an electrical mass; • an output node to provide said output voltage, • N feed branches that converge at the output node, N being a natural number greater than 1, each power supply branch, comprising: • a central node separated from the input node by at least one first switch and from the electrical ground by at least one second switch; - a control circuit comprising: • a voltage regulation circuit configured to generate an alternating binary regulation signal from the combination of the output voltage with an alternating noise voltage; said noise voltage being generated by the voltage regulation circuit from • the electrical potential of the center node of a selected power supply branch; • or from the input voltage; • a distribution circuit configured to generate, for each power supply branch, at least one dedicated activation signal from the regulation signal; the plurality of activation signals being phase-shifted relative to each other by a phase shift that varies over time.

[0016] According to a particular aspect of the invention, the voltage regulation circuit includes a comparator for comparing an intermediate signal to a predetermined reference voltage. Said intermediate signal having a DC component corresponding to the output voltage and an AC component corresponding to the noise voltage.

[0017] According to a particular aspect of the invention, the voltage regulation circuit comprises a divider bridge comprising a pair of resistors separated by a third switch and configured to generate a fraction of the input voltage when the third switch is conducting; the third switch being controlled by the regulation signal.

[0018] According to a particular aspect of the invention, the voltage regulation circuit comprises N diodes such that each diode has an anode connected to the central node of a supply branch associated with said diode and such that the cathodes of the diodes are connected to a common node separated from the electrical ground by a fourth switch controlled by the regulation signal.

[0019] According to a particular aspect of the invention, the distribution circuit comprises a chain of N D-type flip-flops all synchronized according to the regulation signal and mounted such that: the output of a flip-flop of rank i=l at Nl is connected to the input of the next flip-flop of rank i+1.

[0020] According to a particular aspect of the invention, the distribution circuit further comprises an OR type logic cell having a first input connected to the output of the N-rank flip-flop, a second input receiving an initialization signal and an output connected to the input of the i=l-rank flip-flop.

[0021] According to a particular aspect of the invention, the distribution circuit further comprises N AND type logic cells; each AND type cell having a first input receiving the output of an associated D flip-flop and a second input receiving the regulation signal and an output to provide the activation signal to an associated power supply branch.

[0022] According to a particular aspect of the invention, the control circuit further comprises a protection circuit inserted between the voltage regulation circuit and the distribution circuit and configured to limit the duration of the up or down of the regulation signal to a predetermined threshold.

[0023] According to a particular aspect of the invention, the control circuit further comprises a dead time circuit inserted between the distribution circuit and the power cell and configured to generate for each power branch, a first and a second complementary activation signal, each transition edge of the second activation signal being time-shifted with respect to the first activation signal.

[0024] According to a particular aspect of the invention, each power supply branch includes an associated elementary inductance mounted between the central node and the output node; each power supply branch being configured to generate an elementary current through the associated elementary inductance.

[0025] Detailed Description of Figures

[0026] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0027] [Fig.1] Fig.1 illustrates a multi-phase electrical circuit according to a first embodiment of the invention.

[0028] [Fig.2a] [Fig.2a] illustrates a first example of a power cell of the circuit multi-phase electrical according to the invention.

[0029] [Fig.2b] [Fig.2b] illustrates a second example of a power cell of the circuit multi-phase electrical according to the invention.

[0030] [Fig. 3a] [Fig. 3a] illustrates a first example of a voltage regulation circuit of the multi-phase electrical circuit according to the invention.

[0031] [Fig. 3b] [Fig. 3b] illustrates a second example of a voltage regulation circuit of the multi-phase electrical circuit according to the invention.

[0032] [Fig.4] [Fig.4] illustrates the control signal distribution circuit of the circuit multi-phase electrical according to the invention.

[0033] [Fig. 5] [Fig. 5] illustrates a timing diagram of the internal and external signals of the circuit control of the multi-phase electrical circuit according to the invention.

[0034] [Fig.6] [Fig.6] illustrates a multi-phase electrical circuit according to a second mode of realization of the invention.

[0035] [Fig.7a] [Fig.7a] illustrates an example of the implementation of the protection circuit in the multi-phase electrical circuit according to a second embodiment of the invention.

[0036] [Fig.7b] [Fig.7b] illustrates one in the multi-phase electrical circuit according to a second method of embodiment of the invention.

[0037] [Fig.7c] [Fig.7c] illustrates a multi-phase electrical circuit according to a second mode of the realization of the invention.

[0038] Figure 1 illustrates a multiphase electrical circuit DI according to a first embodiment of the invention. The multiphase electrical circuit DI comprises a power cell 1 and a control circuit 2. The power circuit 1 is formed by N supply branches with indices i = 1 to N configured to generate an output current L to a load 3 to be powered. The control circuit 2 is configured to generate activation signals CMD, with i = 1 to N, phase-shifted relative to each other by a phase shift that varies over time. Each activation signal CMD is dedicated to the supply branch with the same index i to trigger said supply branch to power the load 3 for a duration. The activated supply branch is then in a conducting state.

[0039] The power cell 1 comprises an input node 12 to provide an input voltage Vin; an electrical ground GND; an output node 11 to provide said output voltage Vout; and the N supply branches that converge to the output node 11. The load to be supplied 3 is connected between the output node 11 and ground GND. The power cell 1 generates: - the output current Iout through the load to be powered 3; - the output voltage across the terminals of load 3 and propagated via a first feedback loop to control circuit 2 - at least one noise voltage Vml to VmN reinjected via a second feedback loop to the control circuit 2.

[0040] The control circuit 2 comprises a voltage regulation circuit 21 and a distribution circuit 22. The voltage regulation circuit 21 is configured to generate a regulation signal Vreg from the combination of the DC component of the backpropagated output voltage Vout with the AC component of the The noise voltage is selected from at least one noise voltage Vmi to VmN and reinjected via the second feedback loop. The regulation signal Vreg is a binary and periodic digital signal destined for the distribution circuit 22.

[0041] The distribution circuit 22 is configured to generate, for each power supply branch, a dedicated activation signal CMDi, CMD2, CMD3 from the regulation signal Vreg. The activation signals are phase-shifted relative to each other by a phase shift that varies over time. The regulation signal Vreg represents a source signal from which the multiple activation signals CMD will be generated; with a variable phase shift allowing the power supply branches of the power cell 1 to be activated sequentially without the need for a synchronizing clock signal.

[0042] The reinjection of the output voltage Voutet of the noise voltage Vmidans the control circuit 2 makes it possible to obtain a stable multi-phase electrical circuit DI independent of the activation frequency of the required supply branches.

[0043] The noise voltage Vmi is in phase with the conduction of each of the power supply branches so as to obtain load-independent operation that can be adjusted according to the intended application. Furthermore, this noise generation allows the generation of a regulation signal Vreg that reproduces the variation over time of the current flowing through the associated power supply branch.

[0044] Figure 2a illustrates a first example of a power cell 2 of the multiphase electrical circuit DI according to the invention. In this illustrative and non-limiting example, the power cell 2 is a multiphase buck converter for converting the DC input voltage Vin to an output voltage Vout lower than the input voltage. The output voltage Vout is measured at the output node 11. The power cell 2 comprises a plurality of supply branches PHI to PHN that converge at the output node 11. The target load 3 consists, for example, of a load capacitor Cout and a load resistor Rload connected in parallel between the output node 11 and ground GND.

[0045] Each power supply branch PH; comprises a first switch Qu, a second switch Qi2, a central node 13, and an associated elementary inductor L; connected between the central node 13 and the output node 11. For each power supply branch PH;, the central node 13 is separated from the input node 12 by at least the first associated switch Q1h. For each power supply branch PH;, the central node 13 is separated from ground GND by at least the second associated switch Qi2. The first switch Q1 is controlled by the activation signal CMD; associated with the power supply branch PH;. The second switch Qi2 is controlled by the complement of the activation signal CMD; associated with the power supply branch PH;. For example, when the activation signal CMD; is high, the first switch Qu is low. When the CMD enable signal is low, the first switch Qu is in a blocking state and the second switch Qi2 is in a conducting state. This induces current flow through the PH; supply branch from the input node 12 to the output node 11 via the associated central node 13 and the associated elementary inductor L;. Conversely, when the CMD; enable signal is low, the first switch Qu is in a blocking state and the second switch Qi2 is conducting. This induces the central node 13 to ground (GND) and the absence of current in the PH; supply branch. The various CMD; enable signals are phase-shifted such that each supply branch operates with a time lag relative to the others, which helps to distribute the load and reduce current fluctuations. This allows for a reduction in current ripple and a decrease in energy losses.By distributing the load across multiple PH; power supply branches, the converter can better handle current variations.

[0046] Figure 2b illustrates a second example of a power cell 2 of the multiphase electrical circuit DI according to the invention. In this illustrative and non-limiting example, the power cell 2 is a multiphase buck converter with a series capacitor, enabling the conversion of the DC input voltage Vin to an output voltage Vout lower than the input voltage. The power cell 2 according to the second example incorporates all the characteristics and advantages detailed for the first example. The power cell 2 according to the second example differs from the first example in the following way: Each power supply branch PH, with i = 1 to Nl, further includes an intermediate capacitor Cfly connected in series between the first switch Qu and the central node 13.Furthermore, for each power supply branch PH1, with i=1 to N1, the common node between intermediate capacitor Cfly and the first switch Qu is connected to the first switch Q(i+i) of the next power supply branch PH1+i. The last power supply branch of rank i=N lacks the intermediate capacitor Cfly. Only the initial power supply branch PH1 is connected to the input node 12 through its first switch Qu. The power cell 2 according to the second example exhibits better technical robustness compared to the first example, because the first and second switches Q1 and Q12 have voltages across their terminals lower than the input voltage Vin.

[0047] Figure 3a illustrates a first example of the voltage regulation circuit 21 of the control circuit 2 according to the invention. The voltage regulation circuit 21 is configured to generate an alternating binary regulation signal Vreg from the combination of the output voltage Vout with a noise voltage Vnoise.

[0048] In the first example, the voltage regulation circuit 21 includes a resistive voltage divider bridge formed by a pair of resistors R4, R6 separated by a switch Qi. The resistive voltage divider bridge R4, R6 is configured to generate a fraction of the input voltage Vin when the switch Qi is closed. The third switch Qi is controlled by the regulation signal Vreg via a feedback loop internal to the voltage regulation circuit 21. The voltage divider R4,R6, controlled by the regulation signal Vreg, generates a noise voltage Vnoise synchronized with the regulation signal Vreg. The resistive voltage divider is sized to obtain a noise voltage Vnoise when the switch Qi is conducting equal to the voltage measurable at the central node 13 of the activated power supply branch PH. Injecting the synchronized noise voltage Vnoise ensures that the currents flowing through the different power supply branches are equal. Thus, the stability of the DI converter is guaranteed without the need for current measurement. On the other hand, the voltage regulation circuit 21 receives the output voltage Vout from the output node 11 propagated via the first feedback loop of the multiphase DI electrical circuit described in [Fig. 1].The combination of the internally generated noise voltage Vnoise with the backpropagated output voltage Voutforms an intermediate voltage Vint. The voltage regulation circuit 21 further includes a comparator COMP configured to compare an intermediate signal Vint to a predetermined reference voltage Vref. The output signal of the comparator COMP is the regulation signal Vreg, which is a periodic binary signal.

[0049] The voltage regulation circuit 21 further includes a resistor R2 mounted between the output node providing the output voltage Vout and the non-inverting input of the comparator COMP corresponding to the intermediate signal Vint. The resistor R2 allows the DC component of the output voltage Vout to be superimposed on the non-inverting input of the comparator COMP.

[0050] The voltage regulation circuit 21 further includes a capacitor C2 mounted between, on the one hand, the node providing the output voltage Vout and, on the other hand, the node providing the noise voltage Vnoise. Capacitor C2 allows the noise voltage Vnoise to be integrated through at least the resistor R4 so as to obtain a triangular signal between the output voltage Vout and the noise voltage Vnoise.

[0051] The voltage regulation circuit 21 further includes a capacitor Cl mounted between, on the one hand, the output node providing the output voltage Vout and, on the other hand, the non-inverting input of the comparator COMP corresponding to the intermediate signal Vint. The capacitor Cl acts as a high-pass filter. The capacitor Cl allows the AC component of the noise voltage Vnoise to be superimposed on the non-inverting input of the comparator COMP. This results in an intermediate signal Vint having a DC component corresponding to the output voltage Vout and an AC component corresponding to the noise voltage Vnoise. The impedance of the capacitor Cl is lower than the impedance of the resistor R2 at the operating frequency. This prevents a voltage drop between the noise voltage Vnoise and the intermediate signal Vint.

[0052] The voltage regulation circuit 21 internally generates an intermediate signal Vint A triangular waveform synchronized with the branch current is applied to an input of the comparator COMP, which has two activation thresholds. The intermediate signal Vint reproduces the waveform of the current flowing through the inductance of the conducting power supply branch. This yields the periodic binary regulation signal Vreg, with a frequency freg determined by the time constant R4.C2 and the values ​​of the two hysteresis thresholds of the comparator COMP.

[0053] Optionally, the voltage regulation circuit 21 further includes a resistor R5 connected between, on the one hand, the node providing the noise voltage Vnoise and, on the other hand, the output of the voltage divider R4,R6. In this case, the frequency freg is determined by the time constant (R4+R5).C2 by the values ​​of the two hysteresis thresholds of the comparator COMP. The addition of the resistor R5 provides an additional degree of freedom for sizing the frequency freg

[0054] Figure 3b illustrates a second example of the voltage regulation circuit 21 of the control circuit 2 according to the invention. The voltage regulation circuit 21 is configured to generate an alternating binary regulation signal Vreg from the combination of the output voltage Vout with a noise voltage Vnoise.

[0055] In the second example, the voltage regulation circuit 21 comprises N diodes D; of rank i=1 to N, where N is the number of supply branches PH;. In this example, N=3 is assumed. Each diode D; of rank i has an anode connected to the central node 13 of the supply branch PH; associated with said diode D;. The cathodes of the diodes D; are connected to a common node 211. The common node 211 is separated from ground (GND) by a switch Q2. The switch Q2 is controlled by the regulation signal Vreg via a feedback loop internal to the voltage regulation circuit 21. For any one of the supply branches PH;, when the first switch Q is conducting, the central node 13 has a center voltage Vminon of zero. The corresponding diode D; is subjected to a positive voltage and thus becomes conducting. The other diodes Dj (with j^i) are in the blocking state.The center voltage Vmi is thus propagated to the common node 211 to form the noise voltage Vnoise. This noise signal allows the image of the current flowing through the elementary inductance L; of the activated supply branch PH; to be added to the regulation loop. This ensures the distribution of currents in the inductances L; if they are identical. Activating switch Q2 ensures the common node 211 is grounded when all supply branches are deactivated.

[0056] On the other hand, the voltage regulation circuit 21 receives the output voltage Vout from the output node 11 propagated via the first feedback loop of the multiphase electrical circuit DI described in [Fig. 1]. The combination of the internally generated noise voltage Vnoise with the backpropagated output voltage Vout forms an intermediate voltage Vint. The noise voltage Vnoise is propagated to a common node with the output voltage Vout. The intermediate signal Vint thus has a DC component corresponding to the output voltage Vout and an AC component corresponding to the noise voltage Vnoise.

[0057] The voltage regulation circuit 21 further includes a comparator COMP configured to compare an intermediate signal Vint to a predetermined reference voltage Vref. The output signal of the comparator COMP is the regulation signal Vreg, which is a periodic binary signal.

[0058] In general, the voltage regulation circuit 21 generates a periodic binary regulation signal Vreg from an intermediate voltage Vint having a DC component corresponding to the output voltage Vout and an AC component corresponding to the noise voltage Vnoise. This combination ensures that the currents flowing through the different supply branches are equal and thus improves the stability of the DI converter.

[0059] Alternatively, according to a particular embodiment, the N diodes D, of rank i=1 to N, are replaced by N switches controlled by external signals. For example, the switches are implemented by transistors. In this case, it is possible to eliminate the switch Q2.

[0060] Figure 4 illustrates the distribution circuit 22 of the control circuit 2 according to the invention. The distribution circuit 22 receives the regulation signal Vreg generated by the voltage regulation circuit 21. The distribution circuit 22 is configured to generate, for each power supply branch PH;, a dedicated activation signal CMD; from the regulation signal Vreg. The activation signals CMD; are phase-shifted from each other without requiring an external clock signal with a fixed frequency. The distribution circuit 22 comprises a chain of N D-type flip-flops, where N is the number of power supply branches PH;. By way of non-limiting example, an example with three power supply branches and therefore three D-type flip-flops, labeled 221, 222, and 223, is described. The flip-flops 221, 222, and 223 are all synchronized by the regulation signal Vreg.Flip-flops 221, 222, 223 are connected such that the output s; of a flip-flop of rank i=l to Nl is connected to the input of the next flip-flop of rank i+1. The chain of N flip-flops forms a shift register.

[0061] The distribution circuit 22 includes an OR logic gate 230 having a first input connected to the output s3 of the last flip-flop 223; a second input receiving an initialization signal Initl; and an output connected to the input of the flip-flop of rank i=1. The logic gate 230 initializes the flip-flop chain by injecting a high logic state onto the input of the initial flip-flop of rank i=1 when the initialization signal Initl is high. During an initialization step preceding the converter's operation, the initialization signal Initl is high, state "1", so as to obtain a logic value "1" on the input of the Flip-flop 221 of position i=1. The inputs and outputs of the other flip-flops in the chain are at a low logic state "0". Initially, the output of flip-flop 221 of position i=1 is at a low logic state "0". The distribution circuit 22 further includes N AND logic gates. In the illustrated example, these are the three AND gates labeled 231, 232, and 233. Each AND gate has a first input receiving the output of an associated D flip-flop. Each AND gate has a second input receiving the control signal Vreg. Each AND gate is intended to provide the CMD enable signal to an associated power supply branch PHi. The first AND gate 231 receives the output signal Si from flip-flop 221 and generates the CMDi enable signal to control the PHi power supply branch of position i=1.The second ET 232 cell receives the output signal s2 from the flip-flop 222 and generates the activation signal CMD2 to control the PH2 supply branch of rank i=2. The third ET 233 cell receives the output signal s3 from the flip-flop 223 and generates the activation signal CMD3 to control the PH3 supply branch of rank i=3.

[0062] Generally, a power supply branch PHi supplies current to the load circuit when the associated enable signal CMD; is in a logic high state "1". The associated enable signal CMD; is in a logic high state "1" when the output signal s; of the associated flip-flop and the regulation signal Vregs are simultaneously in a logic high state "1".

[0063] We will now describe the time evolution of the output signals sb, s2, and s3 during a control cycle Cyc comprising three successive steps E1, E2, and E3, as illustrated by the timing diagrams in [Fig. 5]. [Fig. 5] describes a timing diagram of the internal and external signals of the control circuit 3 in order to illustrate the operation of the distribution circuit 22.

[0064] The first step El is triggered by the initial rising edge FMI on the control signal Vreg. This rising edge causes the high logic state "1" to be transmitted from the input of the first flip-flop 221 to its output sb. A high logic state "1" is thus obtained only on the first output sb. The high logic state "1" on the first output Si is also transmitted to the input of the second flip-flop 222. The high logic state "1" is maintained on the output s^ant as long as there has been no rising edge following the initial rising edge FMI. The output signals s2 and s3 of the other flip-flops D in the chain are maintained in a low logic state "0".Thus, at the beginning of step El, we obtain the following configuration: the output signal Side of the flip-flop 221 and the regulation signal Vreg are simultaneously in the logic high state "1", which generates a high pulse on the activation signal CMDi while keeping the other activation signals CMD2 and CMD3 in a logic low state. Only the supply branch PHi of rank i=1 is conducting and injects a supply current towards the target load 3.

[0065] The second step E2 is triggered by the rising edge FM2 on the regulation signal Vreg. This rising edge FM2 causes the high logic state "1" to be transmitted from the input of the second flip-flop 222 to its output s2. This results in a high logic state "1" only on the second output s2. The high logic state "1" on the second output s2 is also transmitted to the input of the third flip-flop 223. The OR gate 230 receives two low logic states "0" on its two inputs. The output Si of the flip-flop 221 goes to the low logic state "0". The high logic state "1" is maintained on the output s2 as long as there has been no rising edge following the rising edge FM2. The output signals Si and s3 of the other D flip-flops in the chain are maintained in a low logic state "0".Thus, at the beginning of step E2, we obtain the following configuration: the output signal s2 of the 222 flip-flop and the regulation signal Vreg are simultaneously in a high logic state "1", which generates a high pulse on the activation signal CMD2 while keeping the other activation signals CMDi and CMD3 in a low logic state. Only the PH2 supply branch of rank i=2 is conducting and injects a supply current towards the target load 3.

[0066] The third step E3 is triggered by the rising edge FM3 on the regulation signal Vreg. This rising edge FM3 causes the high logic state "1" from the input of the third flip-flop 223 to its output s23. This results in a high logic state "1" only on the third output s3. The high logic state "1" on the third output s3 is also transmitted to the input of the first flip-flop 221 via the OR gate 230. The high logic state "1" is maintained on the output s3 as long as there is no rising edge following the rising edge FM3. Similarly, the rising edge FM3 causes the low logic state "0" from the input of the second flip-flop 222 to its output s2. Similarly, for the output si of the 221 flip-flop. The output signals Si and s2 of the other D flip-flops in the chain are thus maintained in a low logic state “0”.Thus, at the beginning of step E3, we obtain the following configuration: the output signal s3 of the 223 flip-flop and the regulation signal Vreg are simultaneously in a logic high state "1", which generates a high pulse on the activation signal CMD3 while keeping the other activation signals CMDi and CMD2 in a logic low state. Only the supply branch PH3 of rank i=3 is conducting and injects a supply current towards the target load 3.

[0067] The distribution circuit 22 then allows the generation of phase-shifted CMD activation signals without prior knowledge of a predetermined value of the target phase shift or the frequency of the control signal Vreg. The number of flip-flops and AND logic gates is equal to the number of PH supply branches. The frequency of the control signal Vreg that synchronizes the flip-flop chain is divided by the number of N supply branches. The switching frequency of each of the PH supply branches of the DI converter is governed by the following relationship: fcMD =freg / N; with / adjust frequency of the regulation signal Vreg and N the number of PH supply branches;

[0068] The control circuit 2 further includes means for generating signals complementary to the CMD activation signals; for controlling the second switches Qi2. Said means cover, for example, reversing circuits.

[0069] Figure 6 illustrates a multi-phase DI electrical circuit according to a second embodiment of the invention. In the second embodiment, the control circuit 2 further comprises a protection circuit 23 inserted between the voltage regulation circuit 21 and the distribution circuit 22. The protection circuit 23 receives the regulation signal Vreg from the voltage regulation circuit 21 and generates a master signal VCmd to the distribution circuit 22. The master signal VcMo acts as a clock signal for the chained D flip-flops instead of the regulation signal Vreg, as in the first embodiment. The protection circuit 23 is configured to limit the duration of the high or low state of the regulation signal Vreg to a predetermined threshold T0N,max*. The protection circuit 23 allows the conduction time of a supply branch PH; to be limited.Controlling the maximum conduction time T0N,max allows for a controlled and temporary imbalance in the current flowing through the converter's supply branches during a transient current edge. This imbalance is generally undesirable, but it has been shown to improve the converter's response time if allowed for a controlled duration.

[0070] By way of example, to implement the protection circuit 23, a D flip-flop can be used in SET / RESET mode as illustrated in [Fig. 7a]. The SET signal sets the master signal VCmd to a high state, and the RESET signal sets it to a low state. In case of conflict, the RESET signal prevails. [Fig. 7b] illustrates the RESET signal generation circuit in the protection circuit 23. The master signal VCMD is injected into the input of a Ton_gen circuit, which sets the maximum activation time to T0Njmax. The Ton_gen circuit includes an RC filter formed by a resistor R23 and a capacitor C23, across which the voltage of the master signal VcMD is applied. The Ton_gen circuit also includes a diode D23 with its anode connected to the common node between the resistor R23 and the capacitor C23. The cathode of diode D23 is connected to the other terminal of resistor R23.The output signal of the Ton_gen circuit is retrieved at the common node between resistor R23 and capacitor C23 and propagated to the first input of an AND logic gate. The second input of the AND logic gate receives the complement of the regulation signal Vreg (supplied by the negative output of comparator COMP, for example). The RESET signal is generated by the memory cell and sent to the D flip-flop of the protection circuit 23.

[0071] Figure 7c illustrates the RESET signal generation circuit in the protection circuit 23. It is an AND gate receiving the signal on a first input. RESET already generated and on the other input the regulation signal Vreg.

[0072] Preferably, according to the second embodiment described in [Fig. 6], the control circuit 2 further comprises a dead time circuit 24 inserted between the distribution circuit 22 and the power cell 1. The dead time circuit 24 is configured to generate, for each power supply branch, a first CMD and a complementary second activation signal CMDban-e,i. Each transition edge of the second activation signal CMDban-e,i is time-shifted relative to the first activation signal. This avoids cross-conduction problems between the first switch Qu and the second switch Qi2 in a power supply branch PH.

[0073] The implementation of the dead time circuit 24 is independent of the implementation of the protection circuit 23 in the control circuit 2 according to the invention. According to a third embodiment, the control circuit 2 comprises the voltage regulation circuit 21, a protection circuit 23, and the distribution circuit 22 as described above. According to a fourth embodiment, the control circuit 2 comprises the voltage regulation circuit 21, the distribution circuit 22, and the dead time circuit 24 as described above.

[0074] The invention is compatible with several types of multiphase circuits, including power converters such as DC / DC, AC / AC, AC / DC, and DC / AC, as well as switch-mode power supplies (SMPS). This solution would be beneficial for any multiphase, multilevel, or hybrid converter using nonlinear control. Furthermore, inverters for direct current to alternating current (DC-AC) conversion in solar, wind, and energy storage systems could also benefit from the control generation according to the invention.

Claims

Demands

1. A multi-phase electrical circuit (Dl) configured to generate an output current (Iout) or an output voltage (Vout) to supply a target load (3); said multi-phase electrical circuit (Dl) comprising: a power cell (1) comprising: • an input node (12) to provide an input voltage (Vin); • an electrical ground (GND); • an output node (11) to provide said output voltage (Vout), • N feed branches (PHi, PHN) converging at the output node (11), where N is a natural number greater than 1, each feed branch (PHi, PHn) comprising: • a central node (13) separated from the input node (12) by at least one first switch (Qn, QNi) and from the electrical ground (GND) by at least one second switch (Q12> Qn2); a control circuit (2) comprising: • a voltage regulation circuit (21) configured to generate an alternating binary regulation signal (Vreg) from the combination of the output voltage (Vout) with an alternating noise voltage (Vnoise); said noise voltage (Vnoise) being generated by the voltage regulation circuit (21) from • the electrical potential of the central node (13) of a selected supply branch (PHb PHN); • or from the input voltage (Vin); • a distribution circuit (22) configured to generate for each power supply branch, at least one dedicated activation signal (CMDi, CMD2, CMD3) from the regulation signal (Vreg); the plurality of activation signals being phase-shifted from each other according to a phase shift that varies over time.

2. Multi-phase electrical circuit (Dl) according to claim 1 wherein the voltage regulation circuit (21) includes a comparator (COMP) for comparing an intermediate signal (Vint) to a predetermined reference voltage; said intermediate signal (Vint) having a DC component corresponding to the output voltage (Vout) and an AC component corresponding to the noise voltage (Vnoise).

3. Multi-phase electrical circuit (Dl) according to any one of claims 1 or 2 wherein the voltage regulation circuit (21) comprises a divider bridge including a pair of resistors (R4,R6) separated by a third switch (Qi) and configured to generate a fraction of the input voltage (Vin) when the third switch is conducting; the third switch (Qi) being controlled by the regulation signal (Vreg).

4. Multi-phase electrical circuit (D1) according to any one of claims 1 or 2 wherein the voltage regulation circuit (21) comprises N diodes (Db D2, D3) such that each diode (Db D2, D3) has an anode connected to the center node (13) of a supply branch associated with said diode and such that the cathodes of the diodes are connected to a common node (211) separated from electrical ground (GND) by a fourth switch (Q2) controlled by the regulation signal (Vreg).

5. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 4 in which the distribution circuit (22) comprises a chain of N D-type flip-flops (221, 222, 223) all synchronized according to the regulation signal (Vreg) and mounted such that: the output of a flip-flop of rank i=l to Nl is connected to the input of the next flip-flop of rank i+1.

6. Multi-phase electrical circuit (Dl) according to claim 5 wherein the distribution circuit (22) further comprises an OR type logic cell having a first input connected to the output of the N-rank flip-flop, a second input receiving an initialization signal (Initl) and an output connected to the input of the i=l-rank flip-flop.

7. A multi-phase electrical circuit (D1) according to any one of claims 5 or 6, wherein the distribution circuit (22) further comprises N AND logic cells; each AND cell having a first input receiving the output of an associated D flip-flop and a second input receiving the regulation signal (Vreg) and an output for providing the activation signal (CMDi, CMD2, CMD3) to a branch associated power supply.

8. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 7 wherein the control circuit (2) further comprises a protection circuit (23) inserted between the voltage regulation circuit (21) and the distribution circuit (22) and configured to limit the duration of the up or down of the regulation signal (Vreg) to a predetermined threshold.

9. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 8 wherein the control circuit (2) further comprises a dead time circuit (24) inserted between the distribution circuit (22) and the power cell (1) and configured to generate for each power branch, a first (CMDb CMD2, CMD3) and a second activation signal (CMDNi, CMDN2, CMDN3) complementary, each transition edge of the second activation signal being time-shifted with respect to the first activation signal.

10. Multi-phase electrical circuit (Dl) according to any one of claims 1 to 9 wherein each supply branch (PHi, PHN) comprises an associated elementary inductance (Lb LN) mounted between the central node (13) and the output node (11); each supply branch (PHi, PHN) being configured to generate an elementary current (h, IN) through the associated elementary inductance.

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