COMPUTER-IMPLEMENTED METHOD FOR TESTING LOGIC CIRCUITS IMPLEMENTING CACHE FUNCTIONALITY
Patent Information
- Application Number
- FR2024001695
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-02-21
- Publication Date
- 2025-08-22
Smart Images
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Abstract
Description
Title of the invention: COMPUTER-IMPLEMENTED METHOD FOR TESTING LOGIC CIRCUITS IMPLEMENTING CACHE FUNCTIONALITY
[0001] Embodiments and implementations relate to the cache memory means, in particular the logic circuits implementing the integrated circuit cache functionality, and more particularly the tests of these logic circuits.
[0002] Cache memory is a storage space of an integrated circuit used for storing instructions, in this case we speak of an instruction cache memory, or data cache memory, in the case of a data cache memory. A cache memory can be formed of memory cells such as "SRAM" or "DRAM" type memory cells. Logic circuits (also known as "Cache logic" in English) can also implement the cache functionality, that is to say reproduce the operation of a cache memory.
[0003] Throughout the lifetime of the integrated circuit, such logic circuits implementing the cache functionality (which may subsequently be referred to more simply as "cache logic circuit" or "cache logic") may exhibit hardware failures linked to their wear.
[0004] When these logic circuits are used in applications that comply with functional safety standards or use secure functionalities, tests of the logic circuits are carried out periodically to detect these hardware failures, in particular permanent failures. Indeed, these failures typically lead to corruption of the data stored by the logic circuits and therefore generate a malfunction of the integrated circuit.
[0005] Unlike memory cells whose failures can be detected and possibly corrected by the use of parity bits or error correction codes for example, cache logic circuits may require other solutions allowing the detection of their failures.
[0006] These other solutions may include in particular the use of “BISTs” (English acronym for “Built-in self-test”) systems known to enable the detection of failures of cache memories and logic circuits, or the implementation of cache redundancy in these logic circuits (“cache redundant implementation” in English), or even tests based on the use of software.
[0007] BIST systems and the implementation of cache redundancy nevertheless represent relatively expensive solutions and, consequently, software testing of Cache logic circuits remain the preferred solution.
[0008] A conventional test of cache logic circuits by software is typically preceded by an initialization of these logic circuits which consists in particular of emptying the contents in memory to allow the test to be executed in a “deterministic” manner.
[0009] In other words, the test performed on the cache logic circuits following the initialization of these logic circuits leads to a result making it possible to determine whether the logic circuits have faults, unlike a result which would have been obtained by tests performed on logic circuits whose contents have not been emptied.
[0010] This type of test therefore prevents the user from benefiting from storage by such cache logic circuits after each execution of the test since the contents of these circuits are emptied before each test and therefore it is necessary to store the instructions or data again at the end of each test.
[0011] Thus, there is a need to propose solutions which make it possible to detect failures of cache logic circuits and which do not have the aforementioned drawbacks.
[0012] A cache logic circuit may be intended to store instructions. This logic circuit is then referred to as an instruction cache logic circuit or more simply as “instruction cache logic”.
[0013] A cache logic circuit may be intended to store data. This logic circuit is then referred to as a data cache logic circuit or more simply as “data cache logic”.
[0014] According to one embodiment of an aspect, relating to the testing of an instruction cache logic, there is provided a computer-implemented method of testing an instruction cache logic circuit of an integrated circuit, comprising: - storage in the cache logic circuit of a sequence of instructions comprising M instructions, - reading an initial count value of a cache access counter, (“hit counter” in English) - an execution of the sequence of instructions and, for each instruction executed from the cache logic circuit, an incrementation of the current count value of the cache access counter, - a reading of the final count value of the cache access counter,
[0015] - a blocking of the execution of instructions not provided for by the test for a period extending from the reading of the initial count value to the reading of the final count value, - a subtraction of the initial count value from the final count value, and - a comparison of the result of said subtraction with the value M.
[0016] The above-mentioned blocking is advantageously achieved by disabling interrupts that may lead to unintended execution of these instructions by the test. Unintended execution of these instructions may trigger an additional count by the cache access counter and may thus modify the result of the test. By disabling these interrupts, the test result is thus prevented from being modified by unintended execution of instructions, thereby increasing the reliability of the test.
[0017] Such a method makes it possible to determine when the logic circuit is faulty from the values of the cache access counter (“hit counter”).
[0018] Indeed, we can consider that this logic circuit is not faulty if the result of the subtraction is equal to the number M of instructions. On the contrary, the comparison makes it possible to indicate the presence of a fault in the logic circuit if this result is different from M.
[0019] Such a method makes it possible to perform a test of the logic circuit implementing the cache functionality by software without requiring an emptying of the contents of the logic circuit.
[0020] The method according to this aspect therefore makes it possible to detect a failure of the logic circuit while making it possible to continue to use the instructions already stored in this logic circuit without having to store them again.
[0021] Furthermore, the method according to this aspect makes it possible to avoid resorting to hardware solutions which may be expensive and of complex design.
[0022] While the mode of implementation of this aspect which has just been mentioned provides for a single execution of the sequence of M instructions, it would be possible, in another mode of implementation, to provide for a loop processing, that is to say N (N greater than one in this case whereas N was equal to 1 in the previous mode of implementation) executions of the sequence of instructions with at the end, a comparison of the result of the subtraction mentioned above with the value of the product NxM, to determine the presence or absence of failures of the instruction cache logic circuit.
[0023] According to an embodiment of another aspect, relating to the testing of a data cache logic, there is provided a computer-implemented method of testing a data cache logic circuit of an integrated circuit, the integrated circuit comprising a first memory and a second memory, the method comprising: - storage of at least one data item in at least one memory location of the second memory, - storing a sequence of instructions in the first memory, the sequence of instructions comprising at least one storage instruction in the logic circuit of data cache, of the address of said at least one memory location and of the corresponding data stored at this memory location and at least one instruction for reading the addresses and the data of the data cache logic circuit, - a reading of a first initial count value of a cache access counter ("hit counter"), and / or of a second initial count value of a cache miss counter ("miss counter"), (the first initial count value and the second initial count value may be identical or different), - an execution of the sequence of instructions and, for each storage instruction and each read instruction: O an incrementation of the current value of the cache access counter (“hit counter”) when one of the addresses read in the data cache logic circuit corresponds to the address of said at least one memory location of the second memory, O and / or an incrementation of the current value of the cache miss counter when none of the addresses read in the data cache logic circuit corresponds to the address of said at least one memory location of the second memory, - a reading of a first final count value of the cache access counter and / or a second final count value of the cache miss counter,
[0024] - a blocking of the reading of data not provided for by the test for a period extending from reading the first initial count value and / or the second initial count value to reading the first final count value and / or the second final count value, - a subtraction of the first initial count value from the first final count value to obtain a first result and / or a subtraction of the second initial count value from the second final count value to obtain a second result, and - a comparison of said first result with a value equal to the number of read instructions contained in the sequence of instructions and / or of said second result with a value equal to 0.
[0025] By analogy with what was mentioned for the instruction cache logic circuit, the blocking mentioned here is achieved by disabling interrupts that may lead to an unintended reading by the test of the data stored in the data cache logic circuit. The unintended reading of this data may trigger an additional count by the cache access counter ("hit counter") or by the cache miss counter ("miss counter") and may thus modify the result of the test. By disabling these interrupts, the modification of the result of the test by the unintended reading of data is thus prevented, which thus increases the reliability of the test.
[0026] By analogy to what was mentioned above, the method according to this aspect makes it possible to determine when the data cache logic circuit is faulty from the values of the cache access counter and / or the cache miss counter.
[0027] Indeed, it can be considered that the data cache logic circuit is operating correctly if the first result is equal to the number of read instructions present in the instruction sequence and if the second result is equal to 0. The comparison makes it possible to indicate the presence of a failure of the data cache logic circuit in the opposite case.
[0028] The other advantages mentioned above relating to the testing method and the reliability of testing an instruction cache logic circuit are also valid in the case of the testing method of a data cache logic circuit.
[0029] Furthermore, while the mode of implementation of this other aspect which has just been mentioned provides for a single execution of the sequence of instructions, it would be possible, in another mode of implementation, to provide for a loop processing, that is to say N (N greater than one in this case whereas N was equal to 1 in the previous mode of implementation) executions of the sequence of instructions with at the end, a comparison of the result of the subtraction mentioned above with the value equal to N times the number of read instructions contained in the sequence of instructions, to determine the presence or absence of failures of the data cache logic circuit.
[0030] The method according to this other aspect may advantageously comprise an interruption of the sequence of instructions if the data read in the data cache logic circuit at said address is different from the data stored in the memory location of the second memory located at this address.
[0031] Verifying the data stored by the data cache logic circuit during the execution of the instructions makes it possible to detect a failure of this cache logic circuit before determining the result of the test from the initial and final count values.
[0032] Thus, it is possible to shorten the duration of the test of the data cache logic circuit when a failure is detected by comparing the data stored by this logic circuit and that stored in the second memory for the same address.
[0033] According to yet another aspect, there is provided a computer program product configured to test a cache logic circuit (of instructions or data) of an integrated circuit, the computer program product comprising instructions which, when the program is executed by a computer, cause the latter to implement the method for testing an instruction cache logic circuit defined previously or the method for testing a data cache logic circuit defined previously. cededly.
[0034] According to yet another aspect, there is provided a computer system comprising: - a memory comprising a computer program product as defined previously, - a processing unit configured to execute said computer program product.
[0035] Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and implementation, which is in no way limiting, and the appended drawings in which:
[0036] [Fig.l] ;
[0037] [Fig.2] ;
[0038] [Fig.3] ; and
[0039] [Fig.4] schematically illustrate methods of implementation and realization of the invention.
[0040] In the following, figures 1 and 3 relate to the testing of an instruction cache logic and figures 2 and 4 relate to the testing of a data cache logic, and this in the context of a loop-free processing (N=1).
[0041] [Fig.l] schematically illustrates a computer system SYS comprising an integrated circuit IC according to an embodiment of the invention.
[0042] The integrated circuit IC comprises an instruction cache logic circuit LcacheA. This logic circuit LcacheA implements the cache functionality.
[0043] Such a logic circuit is known to those skilled in the art under the designation “Cache logic” in English and makes it possible to store instructions. The structure and operation of such a cache logic circuit LcacheA are conventional and will therefore not be detailed in the present application. Subsequently, the term “logic circuit LcacheA” will sometimes simply be used to designate the instruction cache logic circuit LcacheA implementing the cache functionality, for the purposes of simplification.
[0044] The integrated circuit IC also comprises a first memory MEM1, such as a RAM memory (for “Random access memory” in English and known as “memory live” in French) for example and a processing unit UT, such as a processor.
[0045] The first memory MEM1 comprises a space dedicated to the storage of a computer program product, for example embedded system software, and a space dedicated to the storage of a sequence of instructions SW. The sequence of instructions SW comprises for example several instructions denoted InstA to InstB stored at the memory locations of addresses AddA to AddB. The embedded system software is configured to test the logic circuit LcacheA, in particular by executing the SW instruction sequence.
[0046] The processing unit is configured to execute the embedded software so as to implement the method described below in relation to [Fig. 3]. To do this, the processing unit UT is connected to the first memory MEM1.
[0047] The integrated circuit IC also comprises a second memory MEM2, which may be a RAM memory for example, configured to store a sequence of instructions, different from the sequence of instructions SW recorded in the first memory MEM1. The sequence of instructions stored in the second memory MEM2 comprises for example M=3 instructions InstOO, InstOl and Inst02.
[0048] In particular, each instruction of the sequence of instructions is stored at an address of a memory location of the second memory MEM2. For example, the address AddOO of the memory location includes the instruction InstOO.
[0049] The logic circuit LcacheA is configured to store an address of a memory location of the second memory MEM2 and the instruction stored in the second memory MEM2 at this memory location.
[0050] The processing unit UT is configured to execute the instructions stored in the logic circuit LcacheA, for example the instruction InstOO associated with the address AddOO.
[0051] Further, the integrated circuit IC includes an HCNT counter.
[0052] This HCNT counter is known to those skilled in the art under the English term “Hit counter” which can be translated as “cache access counter” in French.
[0053] This counter HCNT is configured to increment a ValCurrl count value each time the processing unit UT executes an instruction stored in the logic circuit LcacheA.
[0054] The processing unit UT is also configured to read the count value ValCurrl of the counter HCNT.
[0055] [Fig. 3] schematically illustrates an example of a method, based on the use of the HCNT counter, implemented by computer, in particular by embedded software, for testing the logic circuit LcacheA of the integrated circuit IC described previously in relation to [Fig. 1]. It is assumed that the initial counting value of the first HCNT counter is 0 before implementing the method, although this initial counting value may be different from 0.
[0056] The method comprises a step S21 of blocking the execution of instructions not provided for by the test.
[0057] More particularly, INTR interrupts ([Fig.l]), generated for example by peripherals PERIPH or internal resources of the processing unit UT, can lead to an unplanned execution of these instructions by the processing unit UT. The unplanned execution of these instructions can trigger an additional count by the counter HCNT and can thus modify the result of the test.
[0058] In this regard, the above-mentioned blocking can be carried out by deactivation by the processing unit UT of the INTR interrupts.
[0059] Such deactivation is a conventional and known operation.
[0060] This blocking, which makes it possible to increase the reliability of the test, is carried out up to a step S26 of reactivation of the interruptions.
[0061] The method comprises a step S22 in which the processing unit UT executes the instruction sequence stored in the second memory MEM2.
[0062] In this example the instruction sequence comprises M=3 instructions InstOO, InstOl and Inst02.
[0063] Step S22 also comprises storing in the logic circuit LcacheA the sequence of instructions InstOO, InstOl and Inst02.
[0064] The method also comprises a step S23 of reading an initial count value Vallnitl of the first counter HCNT.
[0065] The initial count value Vallnitl is read by the processing unit UT.
[0066] The method comprises a step S24 of executing the instruction sequence InstOO, InstOl and Inst02.
[0067] During this step S24, the instructions InstOO, InstOl and Inst02 are read from the logic circuit LcacheA and executed by the processing unit UT.
[0068] Step S24 comprises, for each executed instruction, an incrementation of the current counting value ValCurrl of the counter HCNT when the executed instruction is an instruction stored in the logic circuit LcacheA.
[0069] However, it may happen that in the event of a failure of the logic circuit LcacheA, the processing unit UT does not execute the instruction stored in the logic circuit LcacheA. In this case, the current counting value ValCurrl is not incremented.
[0070] The method then comprises a step S25 of reading a final counting value ValFnll of the first counter HCNT. In the absence of failure of the logic circuits LcacheA, the final counting value ValFnll is equal to 3 in this example.
[0071] The final count value ValFnll is read by the processing unit UT.
[0072] The method then comprises step S26 (mentioned above) of activating the INTR interrupts, in particular when these INTR interrupts have been deactivated in step S21.
[0073] The method comprises a step S27 of subtracting the initial count value Vallnitl from the final count value ValFnll. The result DI of this subtraction, which is therefore equal to 3 in this example in the absence of failure of the logic circuit LcacheA, is stored in a third variable.
[0074] Step S27 also comprises a comparison of the result DI with the number M of instructions of the sequence of instructions.
[0075] The result of this comparison allows us to conclude that there is no failure of the logic circuit LcacheA if DI is equal to M or that there is a failure if DI is different from M.
[0076] Such a method makes it possible to perform a test of the LcacheA logic circuit by software without requiring a dump of the contents of the logic circuit. It is therefore possible to detect a failure of the logic circuit while still allowing the instructions already stored in this logic circuit to continue to be used without having to store them again.
[0077] This avoids the need for hardware solutions that can be expensive and complex in design.
[0078] [Fig.2] schematically illustrates a system SYS comprising an integrated circuit IC according to another embodiment of the invention.
[0079] The integrated circuit IC comprises a data cache logic circuit LcacheB. This logic circuit implements the cache functionality. Such a logic circuit is again known to those skilled in the art under the designation “Cache logic” in English and makes it possible to store data. The structure and operation of such a logic circuit LcacheB, although possibly different from those of a cache logic circuit LcacheA described previously in relation to [Fig.l], are conventional and will therefore not be detailed in the present application.
[0080] Subsequently, the term “LcacheB logic circuit” will sometimes simply be used to designate the LcacheB data cache logic circuit implementing the cache functionality, for the purposes of simplification.
[0081] The integrated circuit IC also comprises a first memory MEM1, and a processing unit UT such as a processor.
[0082] The processing unit UT and the first memory MEM1 may be the same as those described previously in relation to [Fig.l]. The embedded system software (instruction sequence SW) stored in the first memory MEM1 is this time configured to test the logic circuit LcacheB.
[0083] The processing unit UT is configured to execute the embedded software so as to implement the method described below in relation to [Fig.4].
[0084] Furthermore, the integrated circuit IC comprises a second memory MEM2. The second memory MEM2 is configured to store data at an address of a memory location of the second memory MEM2. For example, the data DatOO is stored at the memory location located at the address Add03.
[0085] The logic circuit LcacheB is configured to store an address of a memory location of the second memory MEM2 and the data stored in the second memory MEM2 at this memory location. Here, for example, it is assumed that the logic circuit LcacheB is faulty and that the data DatO1 stored in this logic circuit LcacheB is different from the data DatOO stored in the second memory MEM2 to the corresponding address Add03.
[0086] The processing unit UT is configured to read the data stored in the logic circuit LcacheB, for example the data DatOl associated with the address Add03.
[0087] The integrated circuit IC also includes an HCNT counter and an MCNT counter.
[0088] The counter HCNT, again referred to as the “cache access counter” (“Hit counter”), is configured to increment a count value ValCurrl each time the processing unit UT reads data stored in the logic circuit LcacheB.
[0089] The counter MCNT, known to those skilled in the art by the English term “Miss counter” which can be translated as “cache failure counter” in French, is configured to increment a counting value ValCurr2 each time the processing unit UT reads data stored in the second memory MEM2 and this data is not stored in the logic circuit LcacheB. The processing unit UT is also configured to read the counting value ValCurrl of the counter HCNT and the counting value ValCurr2 of the counter MCNT.
[0090] [Fig.4] schematically illustrates an example of a method, based on the use of the HCNT counter, implemented by computer, in particular embedded software, for testing the LcacheB logic circuit of the integrated circuit IC described previously in relation to [Fig.2].
[0091] It is assumed here that the initial count value ValCurrl of the HCNT counter is 0, although this initial count value may be different from 0.
[0092] The method comprises a step S31 of blocking the reading of data not provided for by the test.
[0093] More particularly, by analogy with what was described for step S21 of [Fig. 3], INTR interrupts ([Fig. 2]), generated for example by peripherals PERIPH or internal resources of the processing unit UT, can lead to an unplanned reading of these data by the processing unit UT. The unplanned reading of these data can trigger an additional count by the counter HCNT and can thus modify the result of the test.
[0094] In this regard, the above-mentioned blocking can be carried out by deactivation by the processing unit UT of the INTR interrupts.
[0095] Such deactivation is a conventional and known operation.
[0096] This blocking, which makes it possible to increase the reliability of the test, is carried out up to a step S38 of reactivation of the interruptions.
[0097] The method comprises a step S32 of storing in at least one memory location of the second memory MEM2 at least one piece of data, for example the data DatOO at the memory location with address Add03 of the second memory MEM2.
[0098] The method then comprises a step S33 comprising a reading of the data DatOO by the processing unit UT from the memory location of the second memory MEM2 at the address Add03, and a storage of the address Add03 of the memory location and the data DatOO stored in this memory location of the second memory MEM2, in the logic circuit LcacheB.
[0099] The method comprises a step S34 of reading the initial count value Vallnit2 of the counter HCNT of the integrated circuit IC.
[0100] The initial count value Vallnit2, which is for example 1 at this stage, is read by the processing unit UT.
[0101] The method comprises a step S35 comprising a reading of the addresses and data of the logic circuit LcacheB.
[0102] Step S35 comprises an incrementation of the current counting value ValCurrl of the counter HCNT when the processing unit UT reads data stored in the logic circuit LcacheB.
[0103] However, a cache miss may occur if the logic circuit LcacheB fails and the processing unit UT reads the data stored in the memory location of the memory MEM2 while it is not stored in the logic circuit LcacheB. In this case, the current counting value ValCurrl is not incremented.
[0104] The method comprises a step S36 of interrupting the instruction sequence SW if the data read in the logic circuit LcacheB at the address of the memory location of the second memory MEM2 is different from the data stored in the memory location of the second memory MEM2 located at this address. Indeed, it is possible that data stored in the logic circuit LcacheB is corrupted in the event of a failure and that this data therefore does not correspond to that stored in the second memory MEM2 at the corresponding address.
[0105] More precisely, in the example illustrated in Figures 2 and 4, the data read at the address Add03 from the logic circuit LcacheB during the execution of the instruction sequence is the data DatO1 which is different from the data DatOO stored in the memory location of the second memory MEM2 located at this address Add03. Consequently, the execution of the instruction sequence SW by the processing unit UT is interrupted (step S36) and makes it possible to indicate that a failure of the logic circuit LcacheB has been detected.
[0106] Subsequently, it is considered that no execution of the instruction sequence has been interrupted.
[0107] The method then comprises a step S37 of reading a final counting value ValFnl2 of the HCNT counter.
[0108] The final count value ValFnl2 is read by the processing unit UT. In this example, in the absence of a cache miss, the final count value ValFnl2 is 2 since the initial value was assumed to be 1.
[0109] The method comprises a step S38 of activating the INTR interrupts analogous to step S26 described previously in relation to [Fig.3].
[0110] The method comprises a step S39 analogous to step S27 described previously in relation to [Fig.3]. Step S39 comprises a subtraction of the initial count value Vallnit2 from the final count value ValFnl2 to obtain a first result DI which here is 2-1=1. Step S39 comprises a comparison of the first result DI with the number of read instructions contained in the sequence of instructions SW.
[0111] The result of this comparison then allows us to conclude, on the assumption that no execution of the instruction sequence has been interrupted, that there has been no failure of the logic circuit LcacheB since the first result DI is equal to the expected value which is 1.
[0112] The advantages of the method for testing the LcacheB logic circuit are similar to those mentioned for testing the LcacheA logic circuit.
[0113] While the HCNT counter was used to test the LcacheB logic circuit, it would be possible to also use the MCNT counter (“Miss counter”). The value of the MCNT counter is incremented each time the processing unit UT reads the data DatOO in the second memory MEM2 and this data is not stored in the LcacheB logic circuit.
[0114] And the absence or presence of failure of this logic circuit would be determined by comparing to 0 the result of the difference between the final counting value and the initial counting value of this MCNT counter.
Claims
Claims
1. A computer-implemented method for testing an instruction cache logic circuit (LcacheA) of an integrated circuit (IC), comprising: - storing in the cache logic circuit (LcacheA) an instruction sequence comprising M instructions (InstOO, InstOl, Inst02), - a reading of an initial count value (Vallnitl) of a cache access counter (HCNT), - N executions of the sequence of instructions, with N greater than or equal to 1, and, for each instruction executed from the cache logic circuit (LcacheA), an incrementation of the current counting value (ValCurr) of the counter (HCNT), - a reading of a final value (ValFnl) of the counter (HCNT), - blocking the execution of instructions not provided for by the test for a period extending from the reading of the initial counting value (Vallnitl) until the reading of the final counting value (ValFnl), - a subtraction of the initial count value (Vallnitl) from the final count value (ValFnl), and - a comparison of the result of said subtraction (Dl) with a value equal to the product NxM.
2. A computer-implemented method of testing a data cache logic circuit (LcacheB) of an integrated circuit (IC), the integrated circuit comprising a first memory (MEM1) and a second memory (MEM2), the method comprising: - storage in at least one memory location of the second memory of at least one data item (DatOO), - storage of a sequence of instructions (SW) in the first memory (MEM1), the sequence of instructions comprising at least one instruction for storing in the cache logic circuit (LcacheB), the address (Add03) of said at least one memory location and the corresponding data (DatOO) stored at this memory location and at least one instruction for reading the addresses and data from the data cache logic circuit (LcacheB), - a reading of a first initial count value of a cache access counter (HCNT) and / or a second count value initial of a cache miss counter (MCNT), - N executions of the instruction sequence (SW), with N greater than or equal to 1, and, for each store instruction and each read instruction: O an incrementation of the current counting value (ValCurrl) of the cache access counter (HCNT) when one of the addresses read in the cache logic circuit (LcacheB) corresponds to the address of said at least one memory location of the second memory (MEM2), O and / or an incrementation of the current counting value (ValCurr2) of the cache miss counter (MCNT) when none of the addresses read in the cache logic circuit (LcacheB) corresponds to the address of said at least one memory location of the second memory (MEM2), - a reading of a first final value (ValFnl2) of the cache access counter (HCNT) and / or of a second final value of the cache miss counter (MCNT), - a blocking of the reading of data not provided for by the test for a period extending from the reading of the first initial counting value and / or the second initial counting value until the reading of the first final counting value and / or the second final counting value, - a subtraction of the first initial count value (Vallnit2) from the first final count value (ValFnl2) of the cache hit counter (HCNT) to obtain a first result (Dl) and / or a subtraction of the second initial count value from the second final count value of the cache miss counter (MCNT) to obtain a second result (D2), and - a comparison of said first result (D1) with a value equal to N times the number of read instructions contained in the sequence of instructions (SW) and / or of said second result (D2) with a value equal to 0.
3. Method according to claim 2, comprising an interruption of the sequence of instructions (SW) if the data read in the cache memory means (DatOl) at said address is different from the data (DatOO) stored in the memory location of the second memory (MEM2) located at this address (Add03).
4. Computer program product configured to test a cache logic circuit (LcacheA, LcacheB) of an integrated circuit, the product computer program comprising instructions which, when the program is executed by a computer, cause the latter to implement the method according to claim 1 or the method according to one of claims 2 to 3.
5. Computer system comprising: - a memory (MEM1) comprising a computer program product according to claim 4, - a processing unit (UT) configured to execute said computer program product.
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