Method of smoothing the free and rough surfaces of a plurality of silicon-on-insulator substrates

Abstract

The invention relates to a method for smoothing the free and rough surfaces of a plurality of silicon-on-insulator substrates. The method is implemented on a plurality of substrates arranged, in a boat, in the chamber of an annealing furnace. The boat is placed between an injection zone of an extending gas flow and a discharge zone of the gas flow. The temperature of the gas flow circulating in the furnace is raised to a plateau temperature (Tf) between 1050°C and a ceiling temperature chosen so that the dissolution of the dielectric layer does not exceed a ratio of 25 nm / h, and applied for at least 30 minutes. The invention also relates to a finishing sequence of an SOI substrate comprising a smoothing step implementing this method. Figure 6

Description

Title of the invention: Method for smoothing the free and rough surfaces of a plurality of silicon-on-insulator substrates FIELD OF THE INVENTION

[0001] The present invention relates to the field of silicon-on-insulator (SOI) substrates. These substrates find applications in particular in the fields of microelectronics, optoelectronics, and electromechanical microsystems. Their manufacture can lead to the formation of free surfaces whose state, if not properly prepared, is incompatible with the formation of components, in particular components in the aforementioned fields. For example, these free surfaces can be excessively rough. The present invention therefore relates more particularly to a method for smoothing the free surface of an SOI substrate. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Document US6372609 discloses a method for preparing a silicon-on-insulator (SOI) substrate using Smart Cut™ technology. This technology, well known to those skilled in the art, proposes transferring a thin layer, taken from a silicon donor substrate, onto a support by assembling this donor substrate and this support. An insulating layer, typically a silicon oxide, is previously formed on the donor substrate and / or on the support and is interposed between the transferred thin layer and the support. The thin layer is defined in the donor substrate by introducing light species, usually by implantation of hydrogen and / or helium ions, these species tending to form a fragile layer delimiting the thin layer.The detachment of the thin layer from the rest of the donor substrate, and its transfer to the support, is obtained by mechanically or thermally stressing the assembly formed by the donor substrate and the support, which causes the fracture of the donor substrate at the level of the fragile layer.

[0003] As already mentioned, the transferred thin layer must generally undergo additional treatments so that the SOI substrate can be used as a substrate for the formation of components. It is generally sought to treat this thin layer, during a finishing sequence, to give it a determined and very uniform thickness by thinning, and to improve its crystalline qualities.

[0004] In addition to its thickness and crystalline qualities, it is essential in many applications that the exposed surface of the thin film be very smooth, and have a roughness well below 0.5 nm in root mean square measurement over an atomic force measurement field of 30 micrometers by 30 micrometers. To obtain a thin film having such roughness, it is known to apply to the substrate, after the transfer of the thin layer onto the support substrate, one or a plurality of smoothing annealing operations in neutral or reducing atmospheres. To reduce the roughness and bring it below the desired threshold value, it is usually necessary to expose the free surface of the thin layer to an environment or a gas flow brought to a temperature between 1100°C and 1200°C. At this temperature, the native oxide layer covering it is removed from the free surface of the thin layer and passivated, this oxide being transported into the environment or the gas flow. The silicon of the thin layer thus exposed and devoid of this passivation layer is then able to be smoothed effectively, by annealing, under the effect of temperature by rearrangement of the silicon atoms on the surface of the layer.

[0005] This may involve so-called "rapid" annealing ("rapid thermal anneal" according to the accepted Anglo-Saxon expression) consisting of exposing the exposed surface of the upper layer to the annealing atmosphere at temperature for a very short time, less than 2 minutes. The neutral or reducing atmosphere of the annealing chamber is suddenly heated to the treatment temperature which can reach 1200°C, then cooled during heating / cooling ramps which can exceed 50° / s. During this treatment, the substrate is held by its rear face in the furnace chamber, on a plurality of points of a support. The applicant has however observed that this type of annealing generates slip lines or planes ("slip Unes" according to the Anglo-Saxon terminology used in the field) at the points of contact of the substrate with the support.These slip lines or planes come from thermal stresses and gravitational stresses that this substrate undergoes during the very rapid thermal excursion that it undergoes. They sometimes make the substrate unsuitable for use in the following stages of manufacturing microelectronic components or, at the very least, can lead to the formation of non-functional components when these are arranged in line with these defects.

[0006] By way of illustration, [Fig. 1] shows a map of defects present in an SOI substrate for which the finishing sequence included rapid annealing at 1200°C. This map was prepared by inspection equipment implementing a deflectometry technique, as is for example presented in document US7812942. This map clearly shows the sliding lines or planes arranged at the level of the tips having supported the substrate during its annealing treatment.

[0007] Alternatively to rapid annealing, a long annealing, often referred to in the field as “batch annealing,” can be applied during the finishing step of substrate preparation, because the substrates are generally placed in batches in the furnace chamber, held longitudinally in a nacelle in a horizontal or vertical arrangement. A gas flow circulates in the chamber between a gas flow injection zone to a gas flow evacuation zone, these zones being respectively arranged at the two ends of the chamber and therefore of the nacelle.

[0008] The temperature of the gas flow circulating in the chamber is gradually raised, in gentle ramps of a few degrees per minute to reach a treatment temperature typically of the order of 1100°C to 1200°C. The treatment is continued for an extended period at this temperature, of the order of a few minutes to several hours. The gentleness of the ramps makes it possible to limit the thermal stresses undergone by the substrate and limits the appearance of the lines or sliding planes observed at the end of a rapid heat treatment.

[0009] However, it has been observed that this collective treatment of SOI substrates leads to a large variability in the smoothing effect, from one substrate to another, unless the temperature of the gas flow is raised to a temperature above 1150°C and this relatively high temperature is maintained for a relatively long time of more than 120 min. If these conditions are not met, the substrates positioned relatively closer to the injection zone are treated more efficiently than those positioned relatively further from this zone. To maintain a uniform quality of the SOI substrates treated during this smoothing annealing, it is therefore necessary to expose them to a relatively high temperature, above 1150°C and to provide a large thermal budget.

[0010] By way of illustration, [Fig. 2] shows a measurement of diffuse background noise (“haze” according to the commonly used English terminology) of the free surface of the SOI substrates according to their positions in the nacelle after a smoothing annealing exposing these substrates to a temperature of 1125° for 1 h. On the abscissa axis, the numbering of the rank of the substrate in the nacelle increases as it approaches the gas flow injection zone. On the ordinate axis, the measurement of diffuse background noise is representative of the state of the free surface of the SOI substrate, in particular its roughness, a high measurement indicating degraded quality, i.e. high roughness. Such a measurement can be carried out using the Surfscan™ inspection tool from KLA-Tencor. Reference may be made to the article “Seeing through the haze” by F.Holsteyns, Yield Management Solution, Spring 2004, pp 50-54 for more complete information on this inspection technique. The degradation of the quality of the free surface of SOI substrates which are far from the gas flow injection zone of the furnace chamber compared to those which are close to it is clearly observed, when the temperature and the thermal budget are limited, here a plateau temperature of 1125° applied for 1 h. It therefore appears that such a smoothing heat treatment with a relatively low plateau temperature and a low thermal budget is not suitable for collectively and satisfactorily treating a plurality of SOI substrates to smooth their free surfaces.

[0011] However, it is generally desirable to reduce the thermal budgets applied during substrate manufacturing, primarily for economic and ecological reasons of reducing energy consumption.

[0012] It is also desirable to reduce the maximum temperature to which these SOI substrates are exposed during their manufacture. Some SOI substrates are in fact particularly sensitive to thermal stresses and are likely to develop, at high temperature, slip lines or planes, even when the finishing sequence implements a long annealing with gentle slopes. This is particularly the case when the support is chosen to have a high resistivity, for example greater than 1000 Ohms.cm. To obtain such resistivity, the support has a low interstitial oxygen content, which makes it mechanically fragile.

[0013] When the support of the SOI substrate comprises an electric charge trapping layer, for example a polycrystalline silicon layer, the exposure of this support to a high temperature can lead to at least partial recrystallization of this layer. Its electric charge trapping properties are of course affected.

[0014] Furthermore, it is known that when the thin layer of the SOI substrate has a relatively small thickness, less than 400nm, a phenomenon of dissolution of the silicon oxide dielectric layer occurs, during which the oxygen of this layer tends to diffuse through the thin layer towards the free surface to be transported in the form of volatile compounds SiO by the gas flow. This phenomenon tends to reduce the thickness of the dielectric layer. It is all the more important when the gas flow temperature is high: for a thin layer of 200nm, the dielectric layer thins by a few nanometers per hour when the SOI substrate is exposed to a gas flow having a temperature of 1050°C to more than 100m / h when this temperature is 1200°C.

[0015] [Fig.3] thus represents, for an SOI having a thin layer of 200nm, the dissolved thickness of the silicon oxide dielectric layer (ordinate axis, in Angstroms) as a function of time (abscissa axis, in min) for different maximum annealing temperatures. This dissolution phenomenon leads to altering the thickness uniformity of the dielectric layer and the thin layer, which is not desirable.

[0016] Document US9875914 proposes in this regard to exploit this dissolution phenomenon to produce an SOI substrate having a silicon oxide dielectric layer of very reduced and very uniform thickness. To this end, this document proposes, in certain embodiments, to treat a plurality of SOI substrates in the chamber of an annealing furnace between a zone for injecting a gas flow extending longitudinally on a first side of the nacelle on which the substrates are retained and a gas flow evacuation zone extending longitudinally on a second side of the nacelle. The gas flow brought to a high temperature, of the order of 1200°C, is established transversely in the chamber, between the injection zone and the evacuation zone, the gas flow circulating against the free surfaces of the substrates to promote the evacuation of the volatile species resulting from the dissolution of the dielectric layer. The method proposed by this document is completely foreign to the problem of smoothing at reduced temperature and thermal budget, since it seeks to promote the dissolution phenomenon by bringing the structure of the SOI substrate to a high temperature, of more than 1150°C and preferably 1200°C. SUBJECT OF THE INVENTION

[0017] It would therefore be desirable to have a method for collectively smoothing a plurality of SOI substrates, capable of reducing the roughness of their free surfaces uniformly from one substrate to another, this method exposing the plurality of SOI substrates to a reduced plateau temperature and applying a reduced thermal budget compared to the methods of the state of the art.

[0018] One aim of the invention is to provide a solution to this need. BRIEF DESCRIPTION OF THE INVENTION

[0019] In order to achieve this aim, the subject of the invention provides a method for smoothing the free and rough surfaces of a plurality of silicon-on-insulator substrates. This method comprises the following steps: a. providing a plurality of substrates identical to each other, each substrate comprising a support, a dielectric layer of silicon dioxide disposed on the support and a thin layer of silicon having a thickness of less than 400 nm disposed on the dielectric layer, the thin layers of the substrates having exposed faces defining the free and rough surfaces of the plurality of silicon-on-insulator substrates; b. arranging the plurality of substrates in receiving slots of a nacelle, the slots being arranged longitudinally on the nacelle to place the free surfaces of the substrates parallel to each other; c. engaging the nacelle in the chamber of an annealing furnace between a zone for injecting a gas flow extending longitudinally on a first side of the nacelle and a zone for discharging the gas flow extending longitudinally on a second side of the nacelle, opposite the first side; d. establishing the gas flow between the injection zone and the discharge zone, the gas flow circulating transversely along the free surfaces of the substrates when the boat is engaged in the furnace chamber; e. raising a temperature of the gas flow to a plateau temperature between 1050°C and a ceiling temperature chosen so that the dissolution of the dielectric layer does not exceed a ratio of 25 nm / h; f. maintain the plateau temperature of the gas flow for a period greater than or equal to 30 min so as to uniformly reduce the roughness of the free surfaces of the substrates.

[0020] According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination: • the gas flow is formed from a non-oxidizing gas; • the gas flow consists of pure argon; • the substrates have a thin layer of 200nm and the ceiling temperature is 1150°C; • the plateau temperature is maintained for a period of less than 720 min, preferably less than 360 min and very preferably less than 120 min; • the temperature of the gas flow is raised using a relatively rapid rising ramp, greater than 1.5°C / min, to a pivot temperature, then raised using a relatively slow rising ramp, less than 1.5°C / min, from the pivot temperature to the plateau temperature; • the increase in the temperature of the gas flow includes an intermediate stage of thermalization of the substrates at a temperature below 1000°C; • the smoothing process includes, after maintaining the plateau temperature, cooling the gas flow to a nacelle extraction temperature.

[0021] According to another aspect, the invention proposes a finishing sequence for a silicon-on-insulator substrate comprising at least one smoothing step implementing the application of such a smoothing method.

[0022] According to other advantageous and non-limiting characteristics of this other aspect of the invention, taken alone or in any technically feasible combination: • the finishing sequence includes a stabilization step; • the stabilization step is carried out before at least one smoothing step; • the finishing sequence includes, after at least one smoothing step, a thinning step; • the finishing sequence comprises two smoothing steps, at least one of which involves the application of a smoothing process as described previously; • the stabilization step is applied between the two smoothing steps. Brief description of the drawings

[0023] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0024] [Fig.l]

[0025] [Fig.l] represents a map of the defects present in an SOI substrate after rapid annealing at 1200°C;

[0026] [Fig.2]

[0027] [Fig.2] represents a measurement graph of the diffuse background noise of the free surfaces of SOI substrates according to their positions in a nacelle, after a long smoothing annealing;

[0028] [Fig.3]

[0029] [Fig. 3] represents, for an SOI having a thin layer of 200nm, the dissolved thickness of the silicon oxide dielectric layer as a function of time for different maximum annealing temperatures;

[0030] [Fig.4]

[0031] [Fig.4] represents an annealing furnace capable of implementing a smoothing process in accordance with the invention;

[0032] [Fig.5a]

[0033] [Fig.5a] represents a measurement graph of the diffuse background noise of the free surface of SOI substrates according to their positions in a nacelle, after a smoothing annealing exposing the SOI substrates to 1075°C for 15 min;

[0034] [Fig.5b]

[0035] [Fig.5b] illustrates the effectiveness of a smoothing method according to the invention for reducing the roughness of the free face of a SOL substrate.

[0036] [Fig.6]

[0037] [Fig.6] shows the evolution of the temperature of the gas flow during a smoothing process in accordance with the present invention;

[0038] [Fig.7]

[0039] [Fig.8]

[0040] Figures 7 and 8 illustrate two possible finishing sequences of an SOI substrate comprising a smoothing step implementing a smoothing method according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0041] For the sake of clarity, it is specified that in the context of the present description, an SOI substrate comprises a support, a dielectric layer of silicon dioxide arranged on the support and a thin layer of silicon having a thickness of less than 400 nm arranged on the dielectric layer. The thin layer of the substrate has an exposed face defining a free surface whose roughness is sought to be reduced.

[0042] To enable collective processing leading to obtaining SOI substrates all having the same properties, the SOI substrates which are the subject, in batches, of the smoothing method of the present description, are all identical to each other.

[0043] As a preamble, it is recalled that a batch smoothing oven comprises a chamber extending longitudinally. This direction of longitudinal extension of the chamber can be either vertical or horizontal. The SOI substrates are placed in receiving slots of a nacelle configured to be placed in the chamber of the oven, the slots being arranged longitudinally on the nacelle to place the free surfaces of the substrates parallel to each other. In a nacelle adapted to occupy a chamber whose longitudinal extension is vertical, the substrates are held horizontally, one above the other, in the slots of the nacelle. Conversely, in a nacelle adapted to occupy a horizontal chamber, the substrates are held vertically in the slots of the nacelle.In all cases, and whatever the configuration of the oven, horizontal or vertical, a nacelle can comprise several tens or even several hundreds of slots and therefore receive several tens or hundreds of SOI substrates. In the context of the present description, a nacelle comprises at least 150 slots to receive 150 SOI substrates. In addition to the SOI substrates, the nacelle can comprise so-called “dummy” wafers, making it possible in particular to carry out characterization steps after treatment without using one of the SOI substrates.

[0044] It is also recalled that the smoothing effect of the gas flow requires having “exposed” the thin layers of the SOI substrates by eliminating the native oxide layer necessarily present on the free surfaces of these substrates, by simple exposure of these free surfaces to the surrounding air.

[0045] The gas flow allowing the smoothing is of course formed of a non-oxidizing gas, typically a reducing gas comprising hydrogen or a neutral gas, such as argon. It may be a mixture of hydrogen and neutral gas. The gas flow may in particular consist of argon alone.

[0046] The experiments conducted by the applicant, some of which were presented in the introduction to this application, made it possible to understand why a conventional oven used for the collective treatment of SOI substrates with a view to smoothing them could not be suitable, in particular when these SOI substrates have a thin layer less than 400 nm thick and therefore likely to develop the phenomenon of dissolution of the dielectric layer buried under the thin layer.

[0047] In such a conventional smoothing furnace, the gas flow flows longitudinally in the furnace chamber, along the nacelle and therefore successively from one substrate to the other. It flows from those arranged in the nacelle on the side of the gas flow injection zone to those arranged in the nacelle on the side of the flow discharge zone. During this flow, the gas flow gradually becomes loaded with volatile species, of the SiO type. These volatile species transported by the gas flow result from the decomposition of the native oxide initially present on the free surfaces of the SOI substrates. They also result from the oxygen in the silicon oxide dielectric layer which, by dissolution, diffuses towards the free surfaces of the SOI substrates to be transported there.

[0048] The gas flow is therefore continuously supplied with volatile species, and its concentration in such species tends to increase during its flow between the injection zone and the evacuation zone. However, for a given temperature, the capacity of the gas flow to incorporate and transport the volatile species which accumulate on the free surfaces of the SOI substrates is limited, and dependent on the concentration with which these species are present in the flow. Also, by progressing longitudinally from one plate to the other in the oven and by progressively loading itself with volatile species, the gas flow progressively loses its capacity to transport them and therefore to eliminate the native oxide layer which covers and passivates the free surfaces of the SOI substrates. The SOI substrates arranged on the side of the evacuation zone cannot therefore be treated as effectively as those arranged on the side of the injection zone.

[0049] In the methods of the prior art, the temperature of the gas flow is raised to a plateau temperature of more than 1150°C, for a duration of at least 120 min, in order to increase the transport capacity of the gas flow. By using a high temperature, the dissolution phenomenon is encouraged, which continuously supplies the gas flow with volatile species, and which persists the difficulty in treating the free surfaces of the SOI substrates arranged on the side of the evacuation zone. It is therefore necessary, even by raising the plateau temperature to more than 1150°C, to continue the treatment duration for at least 120 min to obtain an identical or similar smoothing effect for all the SOI substrates arranged in the nacelle. However, as noted in the introduction to this application, it would be preferable to limit the plateau temperature and this thermal budget.

[0050] This problem could be circumvented by loading the nacelle with only an incomplete number of SOI substrates relative to the number of slots available in the nacelle, for example by placing an SOI substrate in only half of these slots. However, it is clear that this solution is not satisfactory, because it tends to greatly reduce the production rate.

[0051] To effectively overcome this problem, and to collectively and efficiently process a plurality of SOI substrates, it is therefore proposed to use a smoothing oven whose configuration is skillfully modified.

[0052] The chamber 1 of such an annealing furnace, shown in [Fig. 4], comprises at least one injection zone Zi of a gas flow (three in the example shown in [Fig. 4]) and at least one evacuation zone Ze (three in the example shown) of the gas flow which extend longitudinally along the chamber 1 of the furnace. In the example shown, the injection zones Zi are all fluidically connected to a distributor, arranged at a distal end 1a of the chamber 1 and the evacuation zones Ze are all fluidically connected to a collector also arranged at the distal end 1a of the chamber 1. The distributor and the collector are respectively fluidically connected to gas inlets and an outlet.

[0053] When a nacelle filled with SOI substrates is arranged in the oven chamber, by engaging it by its proximal end 1b, the injection zone extends longitudinally along a first side of the nacelle and the evacuation zone also extends longitudinally along a second side of the nacelle, opposite the first side.

[0054] In such a configuration, the gas flow circulates transversely in the furnace chamber, between the injection zone Zi and the evacuation zone Ze, along the free surfaces of the SOI substrates when the boat is engaged in the furnace chamber, without passing from one SOI substrate to another. The gas flow is evacuated without being excessively charged with volatile species, and each SOI substrate of the boat is treated with the same efficiency. In particular, it is possible to remove the native oxide layer present on the free surfaces of the SOI substrates, even at a relatively low temperature, for example 1050°C. With the native oxide layer removed, the gas flow can produce a smoothing effect on the exposed free surface.

[0055] Furthermore, care is taken to maintain the temperature of the gas flow in the furnace chamber below a ceiling temperature chosen so that the dissolution of the dielectric layer does not exceed a ratio of 25 nm / h. Thus, the quantity of volatile species to be transported is limited and it is ensured that the free surface of each plate is treated uniformly. With reference to [Fig. 3], for an SOI substrate having a thin layer of 200 nm, the ceiling temperature is 1150°C. For other thin layer thicknesses, the person skilled in the art will be able to establish charts similar to that presented in [Fig. 3], by calculation or by experimentation.

[0056] The temperature of the gas flow is maintained at a plateau temperature, between 1050°C and the predefined ceiling temperature, for the time necessary to obtain the desired smoothing effect, i.e. to reduce the roughness of all the free surfaces of the SOI substrates below a desired threshold roughness. This duration is greater than or equal to 30 min, preferably between 30 min and 720 min, or between 30 min and 260 min and very preferably between 30 min and 120 min. It obviously depends on the roughness of the free surfaces of the SOI substrates initially provided and which must be reduced. The threshold roughness can correspond to a roughness of 0.5 nm in mean square measurement on an atomic force measurement field of 30 micrometers by 30 micrometers.

[0057] In any event, it has been observed that using the oven which has just been presented, a relatively low thermal budget of 1050°C for 30 min is sufficient to cause the smoothing effect of the free and rough surfaces of the SOI substrates arranged in the fully loaded nacelle.

[0058] By way of illustration, [Fig.5a] shows the measurement of diffuse background noise of the free surface of SOI substrates according to their positions in the nacelle after a smoothing annealing exposing the SOI substrates to 1075°C for 15 min, on the one hand using a smoothing annealing furnace of the state of the art (points A) and on the other hand with a smoothing annealing furnace according to the invention (point B).

[0059] On the abscissa axis, the numbering of the nacelle slots increases as one approaches the gas flow injection zone of a furnace of the prior art. It is noted that during the processing of the SOI substrates in the furnace of the prior art, the nacelle was not entirely provided with SOI substrate, because there is no measurement point for the positions having the highest numbers (substantially from rank 110). On the contrary, the nacelle used during the processing of the SOI substrates in the furnace according to the invention, the slots of the nacelle are entirely occupied by the SOI substrates.

[0060] On the ordinate axis, the diffuse background noise measurement is representative of the state of the free surface of the SOI substrate, in particular its roughness.

[0061] We clearly observe in this [Fig.5a] the advantage provided by a smoothing annealing in accordance with the invention: the roughness of the free surfaces of the substrates is very uniform and very low for all the SOI substrates carried by the nacelle.

[0062] [Fig.5b] illustrates the effectiveness of the smoothing process for reducing the roughness of the free face of an SOI substrate. On the left part of this figure, the roughness, measured by its diffuse background noise level, of a plurality of SOI substrates is shown before the smoothing process is applied. These are SOI substrates obtained directly after a fracture step of a process implementing Smart Cut™ technology. These SOI substrates have a very rough free face, with an average diffuse background noise level of 131. On the right part of the figure, the diffuse background noise level measured after application of a smoothing process according to the invention is shown. A very low level is observed, 0.14 on average, and without significant dispersion.

[0063] It is noted that this very low level is lower than that obtained from the same starting SOI substrates by applying rapid smoothing annealing (average diffuse background noise level of the order of 31) presented in the introduction to this application.

[0064] [Fig.6] shows the evolution of the temperature of the gas flow during a smoothing process in accordance with the present invention.

[0065] The gas flow is generally established before the introduction of the nacelle into the furnace chamber. The initial temperature of the flow is relatively low, between 400°C and 600°C, and typically of the order of 500°C during this introduction to avoid any thermal shock. Once the nacelle is suitably positioned in the furnace chamber, the temperature of the gas flow is gradually raised to a pivot temperature Tp (here 1000C0) using a relatively rapid rising ramp, greater than 1.5°C / min, typically of the order of 2°C / min.

[0066] During this temperature rise, an intermediate level Pi below 1000°C can be provided, for example at 900°C as shown in the figure. This level, for example of 30 min, makes it possible to uniformly thermalize the SOI substrates placed in the oven.

[0067] When the temperature reaches the pivot temperature Tp, the temperature of the gas flow continues to be raised, but less rapidly, using a relatively slow rising ramp, less than 1.5°C per min, typically of the order of 1°C per min. This limits the thermal stresses that apply at very high temperature on the SOI substrate, due to a possible gradient between different portions of the substrate, which makes it possible to avoid or limit the appearance of slip planes or lines.

[0068] The temperature of the gas flow is raised using this relatively slow ramp to the plateau temperature which, as already stated, is between 1050°C and a ceiling temperature chosen so that the dissolution of the dielectric layer does not exceed a ratio of 25 nm / h.

[0069] This plateau temperature Tf is maintained between 30 min and 2 hours in order to deploy the smoothing effect for the time necessary to reduce the roughness of the free surfaces of the SOI substrates below the desired threshold roughness.

[0070] At the end of this plateau P, the temperature of the gas flow is gradually reduced using a relatively slow descending ramp, less than 1.5°C / min and typically of the order of 1°C / min to reach the pivot temperature Tp, here 1000°C.

[0071] The cooling of the gas flow is then continued using a relatively rapid descending ramp, greater than 1.5°C / min, typically of the order of 2°C / min, to reach the extraction temperature of the nacelle, relatively low, between 400°C and 600°C, and typically of the order of 500°C.

[0072] By thus controlling the temperature profile of the gas flow, the total duration of the treatment is limited while limiting or avoiding the appearance of planes or slip lines in the SOI substrates. SOI substrate manufacturing process

[0073] A method for manufacturing SOI substrates is now presented, taking advantage of the smoothing method which has just been presented.

[0074] The provision of the starting SOI substrates can be obtained via Smart Cut™ technology, as explained in the introduction to this application.

[0075] According to this technology, during a weakening step, a buried fragile layer is formed in a monocrystalline silicon donor substrate by introduction through a main surface of the substrate, generally by implantation, of so-called "light" species such as hydrogen and / or helium. The implantation energy defines the average depth of introduction of these species and the position of the fragile layer in the thickness of the donor substrate.

[0076] This embrittlement step is often preceded by a step of oxidation of the donor substrate, in order to form a surface layer of silicon oxide intended to form, at least in part, the buried dielectric layer of the SOL substrate.

[0077] The fragile layer defines, with the main surface of the donor substrate, a layer that one seeks to transfer onto a support to form the SOI substrate. In the context of the present description, the fragile layer is positioned under the surface of the donor substrate to define a thin silicon layer with a thickness of less than 400nm.

[0078] To transfer this thin layer and the possible surface dielectric layer of the donor substrate, the latter is assembled to a support, during an assembly step, generally by molecular adhesion of its main face on a main face of the support. This support may comprise or consist of a monocrystalline silicon substrate, but this does not constitute a limitation in itself, and other types of support may be used. When it comprises silicon, the support may also have been previously oxidized so that the surface silicon oxide, combined with that possibly formed on the donor substrate, constitutes the buried dielectric layer of the SOI substrate.

[0079] Alternatively or in addition to oxidation, the support may have received layers of any kind by deposition on its main face, or by any other type of treatment. This may in particular be a layer for trapping electrical charges, typically formed from a thickness of polycrystalline silicon.

[0080] During a subsequent fracture step, the assembly thus formed is fractured at and along the fragile layer of the donor substrate, so as to transfer the thin layer onto the support. At the end of this fracture, there is, on the one hand, a residue of the donor substrate, which can be reused in a new cycle of sampling, and on the other hand an SOI substrate composed of the thin layer, the dielectric layer buried under the thin layer and the support.

[0081] The fracture can be caused in multiple ways, thermally and / or mechanically. Usually, a plurality of assemblies is arranged in a so-called "fracture" furnace and the temperature of this furnace raised to a moderate temperature, typically between 300°C and 600°C. This heat treatment, possibly mechanically assisted or using fracture initiators respectively integrated in the assemblies, causes the detachment of the thin layers from the donor substrates.

[0082] As mentioned in the introduction, the SOI substrates resulting from this layer transfer sequence are generally not suitable for directly receiving components. Due to the fracture step, a transferred thin layer has a deteriorated crystalline quality and a very rough free surface.

[0083] It is therefore usual to apply a sequence of treatment steps, called a finishing sequence, to the SOI substrate obtained at the end of the fracture step to restore the crystalline quality of the layer, reduce the roughness of its free surface below a threshold roughness, and give it a determined and very uniform thickness by thinning.

[0084] According to a first approach shown in [Fig.7], such a finishing sequence comprises the application of two smoothing steps L1, L2, each step implementing the smoothing method presented in the previous section of this description.

[0085] The first smoothing step is carried out directly after the fracture step, without counting any steps applied to the SOI substrates which do not structurally modify these substrates, such as cleaning or metrology steps.

[0086] Between the first smoothing step and the second smoothing step, an intermediate STAB step called “stabilization” is applied. Such a step consists of placing the plurality of SOI substrates obtained at the end of the first smoothing step in an oxidation furnace. A surface thickness of the thin layer is therefore oxidized and the structures are brought to a temperature between 850°C and 950°C. At the end of this heat treatment, the surface oxide layer is removed, typically by selective etching using a solution comprising hydrofluoric acid. This stabilization treatment contributes to improving the crystalline quality of the thin layer and to reducing its thickness to approach its target thickness.

[0087] The stabilization step is followed by the second smoothing step.

[0088] After this second smoothing step, a fine thinning of the layer is carried out. thin, to reduce its thickness to the target thickness. This AMI fine thinning step may include sacrificial oxidation of the thin film or the application of a silicon etching solution, for example a tetramethylammonium hydroxide (TMAH) based solution.

[0089] [Fig.8] illustrates a finishing sequence for a plurality of SOI substrates comprising a single smoothing step L1 implementing the smoothing method described above.

[0090] This finishing sequence is based on the same steps as those of the previous approach, but organized in a different way. According to this other approach, the fracture step is directly followed by a stabilization step STAB. The stabilization step is directly followed by a single smoothing step L1, then the fine thinning step AMI is applied.

[0091] Of course, the two approaches of Figures 7 and 8 are not the only finishing sequences that can be deployed to exploit the smoothing method that is the subject of the present description. More generally, such a finishing sequence can comprise any number of smoothing steps. These smoothing steps can be combined, in any suitable manner, with other steps aimed at improving the crystalline quality, the surface condition and / or the thickness of the thin layer, such as the stabilization and fine thinning steps that have been presented.

[0092] In particular, in a finishing sequence, it is possible to mix a smoothing method according to the invention with a smoothing step implementing a smoothing method according to those of the prior art, for example by exposing the plurality of SOI substrates to a temperature well above that inducing a dissolution greater than 25 nm / h or by exposing the SOI substrates to rapid annealing. Although in this case it is not possible to take advantage of all the benefits of the invention, such a finishing sequence can remain advantageous in that it makes it possible to further reduce the roughness of the free face of the SOI substrates below what is possible to obtain with the smoothing method according to the invention alone.

[0093] The smoothing method just described, exposing a plurality of SOI substrates to a reduced temperature and thermal budget compared to the smoothing methods of the state of the art, has numerous advantages.

[0094] It makes it possible to collectively process a batch of SOI substrates comprising a large number of such substrates, more than 150 of these substrates, while preserving a uniform quality of processing from one substrate to another in the batch.

[0095] The temperature rise of the gas flow can be controlled in order, in combination with the relatively low plateau temperature, to avoid or limit the occurrence of slip lines or planes. This makes it possible to consider using mechanically fragile supports, such as those having a low concentration of interstitial oxygen making it possible to give these supports a high resistivity, greater than 1000 ohms.cm or greater than 2000 ohms.cm.

[0096] It is noted that it is possible to integrate a proportion of nitrogen into such supports having a low concentration of interstitial oxygen, in a concentration between 1 10A14 at / cmA3 to 5 10A15 at / cm3, in order to make it more mechanically resistant. The temperature and the thermal budget applied during the smoothing annealing only cause a limited diffusion of nitrogen into the rest of the structure.

[0097] When the SOI substrate is intended for applications in the field of radiofrequency components, an electric charge trapping layer can be placed in the support without the risk of it recrystallizing.

[0098] It makes it possible to reduce the roughness of the free surfaces of SOI substrates to reach a generally acceptable level, better than the level reached by simple rapid annealing.

[0099] Since the dissolution of the buried dielectric in silicon dioxide is limited, the variability in the thickness of this dielectric and of the thin layer that this phenomenon can cause is also limited.

[0100] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

1.

2.

3. Claims A method of smoothing the free and rough surfaces of a plurality of silicon-on-insulator substrates, the method comprising the following steps: a. providing a plurality of substrates identical to each other, each substrate comprising a support, a dielectric layer of silicon dioxide disposed on the support and a thin layer of silicon having a thickness of less than 400 nm disposed on the dielectric layer, the thin layers of the substrates having exposed faces defining the free and rough surfaces of the plurality of silicon-on-insulator substrates; b. arranging the plurality of substrates in receiving slots of a nacelle, the slots being arranged longitudinally on the nacelle to place the free surfaces of the substrates parallel to each other; c. engaging the nacelle in the chamber of an annealing furnace between a zone for injecting a gas flow extending longitudinally on a first side of the nacelle and a zone for discharging the gas flow extending longitudinally on a second side of the nacelle, opposite the first side; d. establishing the gas flow between the injection zone and the evacuation zone, the gas flow circulating transversely along the free surfaces of the substrates when the boat is engaged in the furnace chamber; e. raising a temperature of the gas flow to a plateau temperature (Tf) between 1050°C and a ceiling temperature chosen so that the dissolution of the dielectric layer does not exceed a ratio of 25 nm / h; f. maintain the plateau temperature (Tf) of the gas flow for a period greater than or equal to 30 min so as to uniformly reduce the roughness of the free surfaces of the substrates. Smoothing method according to the preceding claim in which the gas flow is formed from a non-oxidizing gas. Smoothing method according to the preceding claim in which the gas flow consists of argon.

4. Smoothing method according to one of the preceding claims in which the substrates have a thin layer of 200 nm and for which the ceiling temperature is 1150°C.

5. Smoothing method according to one of the preceding claims in which the plateau temperature is maintained for a duration of less than 720 min, preferably less than 360 min and very preferably less than 120 min.

6. Smoothing method according to one of the preceding claims in which the temperature of the gas flow is raised using a relatively rapid rising ramp, greater than 1.5°C / min, up to a pivot temperature (Tp), then raised using a relatively slow rising ramp, less than 1.5°C / min, from the pivot temperature (Tp) to the plateau temperature (Tf).

7. Smoothing method according to one of the preceding claims in which the increase in the temperature of the gas flow comprises an intermediate stage (Pi) of thermalization of the substrates at a temperature below 1000°C.

8. Smoothing method according to one of the preceding claims comprising, after maintaining the plateau temperature (Tf), cooling the gas flow to an extraction temperature from the nacelle.

9. Finishing sequence of a silicon-on-insulator substrate comprising at least one smoothing step (L1; L1, L2) implementing the application of a smoothing method according to one of the preceding claims.

10. Finishing sequence according to the preceding claim comprising a stabilization step (STAB).

11. Finishing sequence according to the preceding claim in which the stabilization step (STAB) is carried out before the at least one smoothing step (L1).

12. Finishing sequence according to one of claims 9 to 11 comprising, after the at least one smoothing step, a thinning step (AMI).

13. Finishing sequence according to one of claims 9 to 11 comprising two smoothing steps (L1, L2), at least one implementing the application of a smoothing method according to one of claims 1 to 8.

14. Finishing sequence according to claim 13 when combined with claim 10 in which the stabilization step (STAB) is applied between the two smoothing steps (L1,L2).

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