Heterojunction structure for a high electron mobility transistor

Abstract

Heterojunction structure for a high electron mobility transistor, comprising successively: - a substrate (1); - a nucleation layer (2), made of a material chosen from monocrystalline silicon Si having a crystal orientation of the "111" type and monocrystalline aluminum nitride AlN having a hexagonal crystal structure of the "2H" type; - a buffer layer (3) devoid of carbon atoms, made of a material chosen from aluminum nitride AlN and aluminum-gallium nitride AlxGa1-xN with x>0.5; - first and second semiconductor layers (4, 5), made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers (4, 5) have a heterojunction (H) adapted to form a two-dimensional electron gas. Figure 5

Description

Title of the invention: Heterojunction structure for a high electron mobility transistor Technical field

[0001] The invention relates to the technical field of power electronics, more particularly to high electron mobility transistors (HEMTs).

[0002] The invention finds its application in particular in: - components for high voltage power conversion, for example in the range [600 V - 1770 V], and high frequency; - components for electrical protection, for example in the voltage range [600 V - 1770 V]. State of the art

[0003] A heterojunction structure for a high electron mobility transistor HEMT successively comprises: - a substrate; - a nucleation layer; - a buffer layer; - first and second semiconductor layers, made respectively from first and second IILN type alloys chosen so that the first and second semiconductor layers have a heterojunction suitable for forming a two-dimensional electron gas (2DEG for “2-Dimensional Electron Gas” in English).

[0004] The first semiconductor layer is called the channel layer. The second semiconductor layer is called the barrier layer.

[0005] The buffer layer is a thick layer (typically with a thickness greater than 1 μm) allowing in particular: (i) electrically insulating the channel layer from the substrate; (ii) to ensure compatibility in terms of physical properties between the substrate material and the channel layer material.

[0006] Point (i) makes it possible to obtain good vertical voltage resistance. This electrical insulation is essential, particularly when the substrate is semiconducting, for example for a silicon Si substrate.

[0007] Point (ii) mainly allows compatibility in terms of difference in crystal lattice mismatch in order to avoid the formation of crystal defects which are detrimental in terms of reliability and performance.

[0008] It is known from the state of the art to use a silicon Si substrate and a buffer layer based on gallium nitride GaN. In order to satisfy points (i) and (ii), it is known: - to introduce carbon doping into the buffer layer in order to obtain good electrical insulation; - to form a superlattice of the AIN / GaN type for the buffer layer, in order to compensate for a strong crystal lattice mismatch between the silicon substrate and the channel layer (generally in GaN).

[0009] Such a state-of-the-art heterojunction structure is not entirely satisfactory insofar as: - carbon doping degrades the crystalline quality, and introduces charge trapping likely to cause harmful dynamic effects, such as control delays (“gate-lag”, “drain-lag” in English) or a collapse of the current; - the formation of a super-network is complex to implement and consumes operating time. Statement of the invention

[0010] The invention aims to remedy all or part of the aforementioned drawbacks. To this end, the invention relates to a heterojunction structure for a high electron mobility transistor, successively comprising: - a substrate; - a nucleation layer, made of a material different from the substrate and chosen from monocrystalline silicon Si having a crystalline orientation of the “111” type and monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type; - a buffer layer, made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGai_xN with x>0.5; the buffer layer being devoid of carbon atoms; - first and second semiconductor layers, made respectively from first and second IILN type alloys chosen so that the first and second semiconductor layers have a heterojunction suitable for forming a two-dimensional electron gas.

[0011] Thus, such a heterojunction structure according to the invention makes it possible to dispense with carbon doping of the state of the art thanks to the buffer layer made of aluminum nitride AIN or made of an aluminum-gallium nitride AlGaN enriched in aluminum, that is to say of empirical formula AlxGabxN with x>0.5. Aluminum nitride AIN and aluminum-gallium nitride AlGaN enriched in aluminum each have a band gap greater than that of gallium nitride GaN, so that the channel layer (i.e. the first semiconductor layer) is better electrically isolated from the substrate compared to the state of the art, which allows better confinement of the two-dimensional electron gas.

[0012] The nucleation layer is made of a material different from that of the substrate, so that the substrate and the nucleation layer can form a so-called composite substrate. Monocrystalline silicon Si, having a crystal orientation of the “111” type, and monocrystalline aluminum nitride AIN, having a hexagonal crystal structure of the “2H” type, are materials of the nucleation layer having a low lattice mismatch with the buffer layer made of AIN or aluminum-enriched AlGaN.

[0013] A composite substrate makes it possible not to restrict the choice of the substrate material according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the substrate material according to other criteria, for example its coefficient of thermal expansion CTE (Coefficient of Thermal Expansion in English), its transparency to electromagnetic radiation (e.g. in the presence of a bonding layer to detach it) etc.

[0014] The heterojunction structure according to the invention may comprise one or more of the following characteristics.

[0015] According to a characteristic of the invention: - the material from which the buffer layer is made has a first coefficient of thermal expansion, noted CTE1; - the substrate is made of a material having a second coefficient of thermal expansion, noted CTE2; the material in which the substrate is made being chosen so that \CTE2-CTE\\ . . cte\ - w / o

[0016] Thus, an advantage provided is to be able to form a thick buffer layer (thickness greater than 1 μm) of good crystalline quality (typically of the order of or less than 109 dislocations per cm2) by organometallic vapor phase epitaxy MOCVD (MetalOrganic Chemical Vapor Deposition) or by molecular beam epitaxy MBE (Molecular-Beam Epitaxy), while avoiding the formation of a superlattice for the buffer layer.

[0017] According to a characteristic of the invention, the substrate is made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN.

[0018] Thus, an advantage provided by such materials is their low difference in CTE with the buffer layer.

[0019] According to a characteristic of the invention, the heterojunction structure comprises a bonding layer extending between the substrate and the nucleation layer, the bonding layer being designed to detach the substrate from the heterojunction structure when the bonding layer is subjected to electromagnetic radiation; the substrate being made of a material transparent to electromagnetic radiation.

[0020] Thus, an advantage provided is to be able to recycle the substrate.

[0021] According to a characteristic of the invention, the bonding layer comprises: - a first adhesive underlayer, preferably made of a material chosen from amorphous silicon and polycrystalline silicon; - a second release sub-layer, designed to detach the substrate from the heterojunction structure when the second release sub-layer is subjected to electromagnetic radiation; the second release sub-layer preferably being made of a metallic material such as aluminum Al, tin Sn or zinc Zn, or preferably made of a carbon material such as carbon nanotubes or graphene.

[0022] Thus, an advantage provided by such materials for the second release sub-layer is that they can detach from the substrate when subjected to infrared electromagnetic radiation, thanks to their strong absorption in the infrared.

[0023] According to a characteristic of the invention, the buffer layer has a thickness greater than or equal to 1 μm.

[0024] Thus, an advantage provided is to improve the vertical electrical insulation of the channel layer (i.e. the first semiconductor layer). The absence of carbon atoms in the buffer layer also makes it possible to perfectly electrically isolate two adjacent transistors without having to manage their electrical potential on the rear face (i.e. under the buffer layer). Such a thick buffer layer greatly limits, or even eliminates, the back barrier problem encountered when placing high voltage transistors on the same substrate (same chip). This problem is known with a state-of-the-art GaN gallium nitride buffer layer and is exacerbated with the increase in voltage (in particular from 100 V).Finally, this electrical insulation obtained by the buffer layer is not achieved at the expense of significant thermal losses, particularly when the buffer layer is made of aluminum nitride AIN, to a lesser extent when the buffer layer is made of aluminum-gallium nitride AlGaN enriched with aluminum. For example, electrical insulation obtained by a silicon-on-insulator (SOI) type substrate has significant thermal resistance due to the presence of the insulator, typically a layer of silicon dioxide SiO2.

[0025] According to a characteristic of the invention, the material in which the buffer layer is monocrystalline.

[0026] Thus, an advantage provided is to obtain a buffer layer of good crystalline quality as well as good thermal conductivity (i.e. does not form a thermal barrier), particularly when the buffer layer is made of aluminum nitride AIN.

[0027] According to a characteristic of the invention: - the first type III-N alloy is an alloy with the empirical formula AlxGabxN, with x>0; - the second type III-N alloy is an alloy with the empirical formula AlyGai yN, with y>x.

[0028] Thus, an advantage provided is to obtain a heterojunction making it possible to form a two-dimensional electron gas.

[0029] The invention also relates to a high electron mobility transistor, comprising: - a heterojunction structure in accordance with the invention; - first and second metal zones, each extending through the second semiconductor layer so as to form an ohmic contact with the heterojunction; - a source electrode and a drain electrode, respectively electrically connected to the first and second metal zones; - a third metal zone, the first and second metal zones extending on either side of the third metal zone; - a grid electrode, electrically connected to the third metal zone.

[0030] According to a characteristic of the invention, the third metal zone is arranged to: - extend over the second semiconductor layer so as to form a Schottky contact with the second semiconductor layer; or - extend over a dielectric layer covering the second semiconductor layer; or - extend over a p-type doped gallium nitride GaN layer or a p-type doped aluminum-gallium nitride AlGaN layer, covering the second semiconductor layer; or - extend inside the second semiconductor layer so as to form a recessed gate electrode.

[0031] When the third metal zone extends over the second semiconductor layer (i.e. the barrier layer) so as to form a Schottky contact with the second semiconductor layer, the HEMT transistor is generally of the normally on type.

[0032] When the third metal zone extends over a dielectric layer (the dielectric layer covering the second semiconductor layer), the HEMT transistor is also of the normally on type.

[0033] When the third metal zone extends over a p-type doped gallium nitride GaN layer (the p-type doped GaN layer covering the second semiconductor layer), the HEMT transistor is of the normally off type.

[0034] When the third metal zone extends inside the second semiconductor layer so as to form a recessed gate electrode, the HEMT transistor is of the normally off type.

[0035] According to a characteristic of the invention, the transistor comprises at least one field plate arranged to form a lateral extension of the third metal zone, the lateral extension being oriented towards the second metal zone.

[0036] Thus, an advantage provided is to improve the lateral voltage resistance between the gate electrode and the drain electrode.

[0037] The invention also relates to a method for manufacturing a heterojunction structure for a high electron mobility transistor, comprising the successive steps: a) use a donor substrate, made of monocrystalline silicon Si having a crystal orientation of the “111” type; b) assembling the donor substrate to a recipient substrate; c) thinning the donor substrate so as to obtain a nucleation layer; d) forming a buffer layer on the nucleation layer, the buffer layer being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer being devoid of carbon atoms; e) successively forming first and second semiconductor layers on the buffer layer, the first and second semiconductor layers being made respectively from first and second IILN type alloys chosen so that the first and second semiconductor layers have a heterojunction suitable for forming a two-dimensional electron gas.

[0038] Thus, such a method according to the invention makes it possible to obtain a composite substrate (receiving substrate / nucleation layer) at the end of step c), allowing the formation of a buffer layer made of aluminum nitride AIN or aluminum-gallium nitride AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the substrate receiver according to other criteria, for example its CTE, its transparency to electromagnetic radiation (eg in the presence of a layer of adhesive to detach it) etc.

[0039] According to a characteristic of the invention, step b) comprises the steps: bi) forming a bonding layer on the recipient substrate or on the donor substrate; b2) joining the donor substrate to the recipient substrate via the bonding layer; the bonding layer formed during step bi) preferably being designed to detach the receiving substrate from the heterojunction structure obtained at the end of step e) when the bonding layer is subjected to electromagnetic radiation; the receiving substrate being made of a material transparent to electromagnetic radiation.

[0040] Thus, an advantage provided is to obtain a composite substrate (receiving substrate / bonding layer / nucleation layer) at the end of step c), allowing the formation of a buffer layer of aluminum nitride AIN or aluminum-gallium nitride AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the receiving substrate according to other criteria, for example its CTE, its transparency to electromagnetic radiation (eg in the presence of a bonding layer to detach it) etc. Such a bonding layer makes it possible to recycle the receiving substrate after step e).

[0041] The invention finally relates to a method for manufacturing a heterojunction structure for a high electron mobility transistor, comprising the successive steps: a') forming a nucleation layer on a growth substrate, the nucleation layer being made of monocrystalline aluminum nitride AIN having a hexagonal crystal structure of the “2H” type, the nucleation layer having: - a first, free face, having an aluminum Al type polarity; - a second face, opposite the first face, having a nitrogen N type polarity; b') joining the growth substrate to a temporary substrate on the side of the first face of the nucleation layer; then removing the growth substrate so as to expose the second face of the nucleation layer; (c) assembling the temporary substrate to a receiving substrate on the side of the second face of the nucleation layer; then removing the temporary substrate so as to expose the first face of the nucleation layer; (d) forming a buffer layer over the nucleation layer, the buffer layer being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer being devoid of carbon atoms; e) successively forming first and second semiconductor layers on the buffer layer, the first and second semiconductor layers being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers have a heterojunction suitable for forming a two-dimensional electron gas.

[0042] Thus, such a method according to the invention makes it possible to obtain a composite substrate (receiving substrate / nucleation layer) at the end of step c'), allowing the formation of a buffer layer made of aluminum nitride AIN or aluminum-gallium nitride AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the receiving substrate according to other criteria, for example its CTE, its transparency to electromagnetic radiation (eg in the presence of a bonding layer to detach it) etc.

[0043] Since a bulk substrate of monocrystalline AIN is not commercially available in a sufficient diameter and quality, it is not currently possible to use a donor substrate of monocrystalline AIN and then thin it in order to form a nucleation layer, in which case a single transfer to a receiving substrate would be necessary. The nucleation layer of monocrystalline AIN is obtained by epitaxial growth on a growth substrate. Carrying out steps b') and c') leads to a double transfer making it possible to recover the aluminum-type polarity on the free surface of the nucleation layer before step d), in order to obtain a satisfactory crystalline quality for the buffer layer formed during step d).

[0044] According to a characteristic of the invention, step c') comprises the steps: c'i) forming a bonding layer on the receiving substrate or on the second face of the nucleation layer; c'2) assembling the temporary substrate to the receiving substrate via the bonding layer; the bonding layer formed during step c'i) preferably being designed to detach the receiving substrate from the heterojunction structure obtained at the end of step e) when the bonding layer is subjected to electromagnetic radiation; the receiving substrate being made of a material transparent to electromagnetic radiation.

[0045] Thus, an advantage provided is to obtain a composite substrate (receiving substrate / bonding layer / nucleation layer) at the end of step c'), allowing the formation of a buffer layer of aluminum nitride AIN or aluminum-gallium nitride AlGaN enriched in aluminum. The composite substrate makes it possible not to restrict the choice of the material of the receiving substrate according to its possible crystal lattice mismatch with the buffer layer. It is thus possible to choose the material of the receiving substrate according to other criteria, for example its CTE, its transparency to electromagnetic radiation (eg in the presence of a bonding layer to detach it) etc. Such a bonding layer makes it possible to recycle the receiving substrate after step e).

[0046] Definitions

[0047] - By "comprising successively an element A, an element B etc.", we mean that elements A and B are arranged consecutively in a defined order following the normal to a surface receiving elements A and B, i.e. the vertical direction (from bottom to top) under normal conditions of use.

[0048] - By "substrate" is meant a self-supporting physical support, made of a material crystalline. A substrate can be a "slice", also called a "wafer" which is generally in the form of a disc cut from an ingot of a crystalline material.

[0049] - By "nucleation layer" is meant a layer forming a crystalline germ at allowing epitaxial growth.

[0050] - By "different material" is meant that a material A is different from a material B when: (i) material A has a qualitative chemical composition different from that of material B; or (ii) material A has a qualitative chemical composition identical to that of material B but a quantitative chemical composition different from that of material B; or (iii) material A has a qualitative chemical composition identical to that of material B but in a different crystalline form. As non-limiting examples, (i) polycrystalline silicon carbide SiC is different from monocrystalline aluminum nitride AIN and monocrystalline silicon Si; (ii) the alloy AlxGabxN is different from the alloy AlyGai yN when y^x; (iii) monocrystalline aluminum nitride AIN is different from polycrystalline aluminum nitride AIN.

[0051] - By "111-type crystal orientation" is meant a crystal orientation defined by the Miller indices (111).

[0052] - By "hexagonal crystal structure of the 2H type" is meant that the structure hexagonal crystalline has a 2H polytype.

[0053] - By “buffer layer” is meant a layer designed to: (i) electrically insulating the channel layer (i.e. the first semiconductor layer) from the substrate, and (ii) improve the crystalline quality of the layers formed above the buffer layer through the thickness of the buffer layer and the smoothing of the mesh parameters.

[0054] - By "semiconductor layer" is meant a layer made of a material having an electrical conductivity at 300 K between 106 S / cm and 103 S / cm.

[0055] - By "type III-N alloy" is meant an alloy between at least one element of the column III of the periodic table of elements (TPE) and nitrogen N. The alloy can be binary in the presence of a single element from column III of the TPE and nitrogen N. The alloy can be ternary in the presence of two elements from column III of the TPE and nitrogen N. The alloy can be quaternary in the presence of three elements from column III of the TPE and nitrogen N etc.

[0056] - By "heterojunction" we mean a junction between two semi-materials conductors with different band gaps.

[0057] - By "transparent" we mean that the substrate has a transmission coefficient in intensity greater than 80%, preferably greater than 85%, more preferably greater than 90% averaged over the spectrum of the electromagnetic radiation to which the bonding layer is subjected, for example an infrared domain.

[0058] - By "thickness" is meant the dimension along the normal to the surface of the substrate on which the nucleation layer extends, or where appropriate the bonding layer, i.e. the vertical direction under normal conditions of use.

[0059] - By "dielectric" we mean that the layer is made of a material having an electrical conductivity at 300 K less than or equal to 106 S / cm.

[0060] - By "p-type doped" is meant that the layer of gallium nitride GaN contains p-type dopants, i.e. species (e.g. impurities) which, introduced into the matrix of gallium nitride GaN, generate a hole in the valence band.

[0061] - By "field plate" is meant a metal plate arranged to reduce the electric field strength near the gate electrode.

[0062] - By "aluminum-type polarity" is meant that the Al-N bond begins with a aluminum atom Al along the vertical direction. The first face of the nucleation layer has an aluminum-type polarity, i.e. with aluminum atoms Al on the surface.

[0063] - By "nitrogen-type polarity" is meant that the Al-N bond begins with a nitrogen atom N along the vertical direction. The second face of the nucleation layer has a nitrogen-type polarity, i.e. with nitrogen atoms N on the surface.

[0064] - By "exposing" is meant an action of exposing one side of the bare layer cleation so that said face becomes a free face.

[0065] - By "crystal mesh mismatch" is meant the quantitative difference between the mesh parameters of the materials concerned. Brief description of the drawings

[0066] Other characteristics and advantages will appear in the detailed description of different embodiments of the invention, the description being accompanied by examples and references to the attached drawings.

[0067] [Fig-1] is a schematic sectional view, illustrating a first embodiment of a heterojunction structure according to the invention.

[0068] [Fig.2] is a schematic sectional view, illustrating a second embodiment of a heterojunction structure according to the invention, with the presence of a bonding layer.

[0069] [Fig.3] is a schematic sectional view, illustrating a first embodiment of a high electron mobility transistor according to the invention, with the presence of a gate surmounting a dielectric layer (gate insulator).

[0070] [Fig.4] is a schematic sectional view, illustrating a second embodiment of a high electron mobility transistor according to the invention, with the presence of a gate surmounting a p-type doped gallium nitride GaN layer.

[0071] [Fig.5] is a schematic view similar to [Fig.3], with the presence of a layer of collage.

[0072] [Fig.6] is a schematic view similar to [Fig.4], with the presence of a layer of collage.

[0073] [Fig.7] includes schematic sectional views, illustrating a first mode of implementation of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer produced in a monocrystalline silicon Si having a crystalline orientation of the “111” type.

[0074] [Fig.8] includes schematic sectional views, illustrating a second mode of implementation of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer produced in a monocrystalline silicon Si having a crystalline orientation of the “111” type, and with the presence of a bonding layer.

[0075] [Fig.9] is a schematic sectional view, illustrating a step a') of a method of fa construction of a heterojunction structure according to the invention, with a nucleation layer made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0076] [Fig. 10] is a schematic sectional view illustrating an assembly of a substrate of growth to a temporary substrate during a step b') of a method for manufacturing a heterojunction structure according to the invention.

[0077] [Fig. 11] is a schematic sectional view, illustrating a removal of the growth substrate during a step b') of a method for manufacturing a heterojunction structure according to the invention.

[0078] [Fig. 12] is a schematic sectional view, illustrating an assembly of a temporary substrate to a receiving substrate during a step c') of a method for manufacturing a heterojunction structure according to the invention.

[0079] [Fig.l2bis] is a schematic view similar to [Fig. 12], with the presence of a bonding layer.

[0080] [Fig. 13] is a schematic sectional view, illustrating a removal of the temporary substrate during a step c') of a method for manufacturing a heterojunction structure according to the invention.

[0081] [Fig.l3bis] is a schematic view similar to [Fig. 13], with the presence of a bonding layer.

[0082] [Fig. 14] is a schematic sectional view, illustrating a step d) of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0083] [Fig.l4bis] is a schematic view similar to [Fig. 14], with the presence of a bonding layer.

[0084] [Fig. 15] is a schematic sectional view, illustrating a step e) of a method for manufacturing a heterojunction structure according to the invention, with a nucleation layer made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0085] [Fig.l5bis] is a schematic view similar to [Fig. 15], with the presence of a bonding layer.

[0086] It should be noted that the drawings described above are schematic, and are not necessarily to scale for the sake of readability and to simplify their understanding. The sections are made along the normal to the surface of the substrate(s) shown in the corresponding figure, that is to say along a vertical axis in normal conditions of use. Detailed description of the implementation methods

[0087] Elements that are identical or provide the same function will have the same references for the different embodiments, for the sake of simplification. Heterojunction structure

[0088] An object of the invention is a heterojunction structure for a high-voltage transistor. electronic mobility, comprising successively: - a substrate 1; - a nucleation layer 2, made of a material different from the substrate 1 and chosen from monocrystalline silicon Si having a crystalline orientation of the “111” type and monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type; - a buffer layer 3, made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer 3 being devoid of carbon atoms; - first and second semiconductor layers 4, 5, made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers 4, 5 have an H heterojunction suitable for forming a two-dimensional electron gas.

[0089] Substrate

[0090] The substrate 1 is made of a material having a coefficient of thermal expansion, denoted CTE2. The material from which the substrate 1 is made is advantageously chosen so that < i, where CTE1 is the coefficient of thermal expansion of the material from which the buffer layer 3 is made.

[0091] The substrate 1 is advantageously made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN. The substrate 1 is advantageously a bulk substrate. By “bulk substrate” is meant a substrate whose volume is homogeneous from the point of view of its crystalline structure (monocrystalline or polycrystalline). Thus, contrary to a usual meaning, the term “bulk” is not reserved in the present description for the monocrystalline form of a substrate, and can therefore refer to the polycrystalline form of a substrate.

[0092] The substrate 1 is advantageously made of a material transparent to electromagnetic radiation to which a CC bonding layer interposed between the substrate 1 and the nucleation layer 2 can be subjected (see paragraph “Bonding layer”). As a non-limiting example, the material from which the substrate 1 is made is advantageously transparent in the infrared.

[0093] The substrate 1 may have a diameter of 200 mm or 300 mm. The substrate 1 may have a thickness of the order of 500 μm.

[0094] Nucleation layer

[0095] The nucleation layer 2 is made of a material different from the substrate 1 so that the substrate 1 and the nucleation layer 2 form a composite substrate.

[0096] According to a first embodiment, the nucleation layer 2 is made of a monocrystalline silicon Si having a crystalline orientation of the “111” type.

[0097] According to a second embodiment, the nucleation layer 2 is made of a monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0098] The nucleation layer 2 may have a thickness of between a few hundred nanometers and around ten microns. By way of non-limiting example, the nucleation layer 2 may have a thickness of between 100 nm and 5 μm.

[0099] Buffer layer

[0100] The buffer layer 3 extends over the nucleation layer 2. The buffer layer 3 is devoid of carbon-type dopants. The buffer layer 3 is a monolithic layer. In other words, the buffer layer 3 does not comprise distinct sub-layers made of different materials. In other words, the buffer layer 3 does not form a multi-layer structure, as in a superlattice.

[0101] According to a first embodiment, the buffer layer 3 is made of aluminum nitride AIN.According to a second embodiment, the buffer layer 3 is made of aluminum-gallium nitride AlxGai_xN with x>0.5. The material in which the buffer layer 3 is made is advantageously monocrystalline. In other words, according to the first embodiment, the aluminum nitride AIN is advantageously monocrystalline. According to the second embodiment, the aluminum-gallium nitride AlxGa[ xN, with x>0.5, is advantageously monocrystalline.

[0102] The buffer layer 3 advantageously has a thickness greater than or equal to 1 μm. The buffer layer 3 may have a thickness of the order of a few microns, and is generally less than 10 μm. By way of non-limiting example, the buffer layer 3 may have a thickness of the order of 4 μm.

[0103] First and second semiconductor layers

[0104] The first semiconductor layer 4 extends over the buffer layer 3. The first semiconductor layer 4 is made of a first IILN type alloy. The first semiconductor layer 4 may have a thickness of the order of 500 nm.

[0105] The second semiconductor layer 5 extends over the first semiconductor layer 4. The second semiconductor layer 5 is made of a second IILN type alloy. The second semiconductor layer may have a thickness of the order of 20 nm.

[0106] The first and second IILN type alloys are designed such that the first and second semiconductor layers 4, 5 have a heterojunction H adapted to form a two-dimensional electron gas. By way of non-limiting example, the first IILN type alloy may be an alloy of empirical formula AlxGa[ xN, with x>0, while the second IILN type alloy may be an alloy of empirical formula Aly Gai yN, with y>x. When x=0, the first IILN type alloy is a binary alloy of gallium nitride GaN. When x^0, the first IILN type alloy is an alloy aluminum-gallium nitride ternary AlGaN.

[0107] Bonding layer

[0108] The heterojunction structure advantageously comprises a CC bonding layer extending between the substrate 1 and the nucleation layer 2, the CC bonding layer being designed to detach the substrate 1 from the heterojunction structure when the CC bonding layer is subjected to electromagnetic radiation. The electromagnetic radiation may come from laser irradiation.

[0109] For this purpose, the bonding layer CC may comprise a first adhesive sub-layer which is advantageously made of a material chosen from amorphous silicon and polycrystalline silicon. The bonding layer CC may comprise a second release sub-layer which is designed to detach the substrate 1 from the heterojunction structure when the second release sub-layer is subjected to electromagnetic radiation. The second release sub-layer is advantageously made: - in a metallic material such as aluminum Al, tin Sn, zinc Zn; or - in a carbon material such as carbon nanotubes or graphene.

[0110] Such materials for the second release sub-layer absorb in the infrared so as to separate the substrate 1 from the heterojunction structure when these materials are subjected to infrared radiation.

[0111] Of course, it is conceivable to use a CC bonding layer extending between the substrate 1 and the nucleation layer 2 which is not designed to detach the substrate 1 from the heterojunction structure. As non-limiting examples, the CC bonding layer can be made of a material chosen from amorphous silicon, polycrystalline silicon and polycrystalline aluminum nitride AIN.

[0112] On-board diode(s)

[0113] The heterojunction structure advantageously comprises at least a first diode, intended to be reverse biased. The first diode comprises a p / n junction which can extend: (i) within substrate 1; Or (ii) within the CC bonding layer where applicable; or (iii) within nucleation layer 2; or (iv) at the interface between substrate 1 and nucleation layer 2, in the absence of a CC bonding layer; or (v) at the interface between the substrate 1 and the CC bonding layer if any; or (vi) at the interface between the CC bonding layer and the nucleation layer 2.

[0114] Such a first diode, intended to be reverse biased, makes it possible to provide additional electrical insulation to that provided by the buffer layer 3. The electrical insulation obtained can be both vertical and lateral. Electrical insulation lateral is advantageous in the presence of adjacent future high electron mobility transistors.

[0115] The p / n junction of the first diode is located according to the p-type and n-type dopants chosen and according to the properties of the substrate 1, the nucleation layer 2 and the CC bonding layer if applicable. For example, a nucleation layer 2 made in a monocrystalline silicon Si having a crystal orientation of the “111” type can easily be p-doped or n-doped, which is not the case for a nucleation layer 2 made in a monocrystalline aluminum nitride AIN having a hexagonal crystal structure of the “2H” type. Of course, the CC bonding layer must not be designed to detach the substrate 1 from the heterojunction structure when the CC bonding layer comprises dopants in order to form all or part of the first diode.

[0116] According to a first exemplary embodiment, the substrate 1 is made of p-type doped polycrystalline silicon carbide SiC and the bonding layer CC is made of n-type doped polycrystalline silicon. According to a second exemplary embodiment, the bonding layer CC is made of p-type doped polycrystalline silicon and the nucleation layer 2 is made of n-type doped monocrystalline silicon Si, having a crystal orientation of the “111” type.

[0117] The heterojunction structure advantageously comprises at least one second diode, intended to be forward biased, mounted in series and head-to-tail (i.e. in anti-series) with the first diode. Such an anti-series assembly of the first and second diodes makes it possible to limit the reverse voltage of the second diode in the blocked state, so as not to damage it. Indeed, significant electrical potential differences may exist between the substrate 1 and the nucleation layer 2 (or with the CC bonding layer where appropriate). Furthermore, such an anti-series assembly makes it possible to guarantee that one of the two diodes is in the blocked state. High electron mobility transistor

[0118] An object of the invention is a high electron mobility transistor (HEMT), comprising: - a heterojunction structure in accordance with the invention; - first and second metal zones ZM1, ZM2, each extending through the second semiconductor layer 5 so as to form an ohmic contact with the heterojunction H; - a source electrode S and a drain electrode D, respectively electrically connected to the first and second metal zones ZM1, ZM2; - a third metal zone ZM3, the first and second metal zones ZM1, ZM2 extending on either side of the third metal zone ZM3; - a grid electrode G, electrically connected to the third metal zone ZM3.

[0119] First and second metal zones

[0120] The first metal zone ZM1 extends through the second semiconductor layer 5 so as to form an ohmic contact with a first lateral edge of the heterojunction H. The second metal zone ZM2 extends through the second semiconductor layer 5 so as to form an ohmic contact with a second lateral edge of the heterojunction H. The first and second lateral edges of the heterojunction H, facing each other, delimit an active zone of the heterojunction H extending between the first and second metal zones ZM1, ZM2. The first and second metal zones ZM1, ZM2 extend on either side of the third metal zone ZM3.

[0121] The source electrode S is electrically connected to the first metal zone ZML The drain electrode D is electrically connected to the second metal zone ZM2.

[0122] Third metal zone

[0123] The third metal zone ZM3 is advantageously arranged to: - extend over the second semiconductor layer 5 so as to form a Schottky contact with the second semiconductor layer 5; or - extend over a dielectric layer 6 covering the second semiconductor layer 5; or - extend over a layer 7 of p-type doped gallium nitride GaN or over a layer 7 of p-type doped aluminum-gallium nitride AlGaN, covering the second semiconductor layer 5; or - extend inside the second semiconductor layer 5 so as to form a recessed gate electrode G.

[0124] According to a first embodiment, the third metal zone ZM3 extends over the second semiconductor layer 5 so as to form a Schottky contact with the second semiconductor layer 5. The HEMT transistor is then generally of the normally on type.

[0125] According to a second embodiment, the third metal zone ZM3 extends over a dielectric layer 6 covering the second semiconductor layer 5. The HEMT transistor in question is then of the normally on type. As non-limiting examples, the dielectric layer 6 may be made of silicon dioxide SiO2, silicon nitride Si3N4, aluminum nitride AIN or alumina A12O3. The dielectric layer 6 also makes it possible to passivate the surface of the second semiconductor layer 5.

[0126] According to a third embodiment, the third metal zone ZM3 extends over a layer 7 of p-type doped gallium nitride GaN (or over a layer 7 of p-type doped aluminum-gallium nitride AlGaN), covering the second semiconductor layer 5. The HEMT transistor is of the normally off type (“Normally -Off” in English).

[0127] According to a fourth embodiment, the third metal zone ZM3 extends (partially) inside the second semiconductor layer 5 so as to obtain a recessed gate electrode G. The HEMT transistor is of the normally off type.

[0128] The gate electrode G is electrically connected to the third metal zone ZM3.

[0129] The first, second and third metal zones ZM1, ZM2, ZM3 are advantageously made from aluminum Al and / or copper Cu.

[0130] Field plate(s)

[0131] The transistor advantageously comprises at least one field plate FP arranged to form a lateral extension of the third metal zone ZM3. The lateral extension is advantageously oriented towards the second metal zone ZM2.

[0132] The field plate(s) FP are made of a metallic material, preferably aluminum Al or copper Cu. The field plate(s) FP make it possible to have a better distribution of the electric field, i.e. to reduce the intensity of the electric field near the gate electrode G, in order to obtain good lateral voltage resistance, and thereby a high breakdown voltage.

[0133] Manufacturing process with a Si “111” nucleation layer

[0134] An object of the invention is a method of manufacturing a heterojunction structure for a high electron mobility transistor, comprising the successive stages: a) use an SD donor substrate, made of monocrystalline silicon Si with a crystal orientation of the “111” type; b) assembling the donor substrate SD to a recipient substrate 1; c) thinning the donor substrate SD so as to obtain a nucleation layer 2; d) forming a buffer layer 3 on the nucleation layer 2, the buffer layer 3 being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer 3 being devoid of carbon atoms; e) successively forming first and second semiconductor layers 4, 5 on the buffer layer 3, the first and second semiconductor layers 4, 5 being made respectively from first and second IILN type alloys chosen so that the first and second semiconductor layers 4, 5 have an H heterojunction suitable for forming a two-dimensional electron gas.

[0135] Step a)

[0136] Step a) consists of using a donor substrate SD, made of mono silicon Si crystalline having a crystal orientation of the “111” type. The SD donor substrate can have a thickness of the order of a few hundred microns.

[0137] Step b)

[0138] Step b) consists of assembling the donor substrate SD to a recipient substrate 1. Step b) can be carried out by direct bonding. By "direct bonding" is meant a spontaneous bond resulting from the direct contact of two surfaces, i.e. in the absence of an additional element such as glue, wax or solder. Adhesion mainly comes from van der Waals forces resulting from the electronic interaction between atoms or molecules of two surfaces, hydrogen bonds due to surface preparations or covalent bonds established between the two surfaces. Direct bonding can be activated (i.e. surface activation) with a plasma. Direct bonding can be performed under vacuum or under ultrahigh vacuum. Bonding can be direct between the donor substrate SD and the receiving substrate 1. When the donor substrate SD and / or the receiving substrate 1 are coated with a dielectric layer (e.g. an oxide layer, preferably amorphous) before bonding, bonding can be direct between a dielectric layer and a substrate, or between two dielectric layers. The thickness of the dielectric layer(s) (e.g. of the order of 100 nm) is adapted so as not to induce a significant thermal barrier.

[0139] The receiving substrate 1 is advantageously made of a material having a coefficient of thermal expansion, noted CTE2. The material in which the receiving substrate 1 is made is advantageously chosen so that \CTE2-CTE\\ . , where CTEl ~1U / C CTE1 is the coefficient of thermal expansion of the material in which the buffer layer 3 is made during step d).

[0140] The receiving substrate 1 is advantageously made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN. The receiving substrate 1 is advantageously a bulk substrate.

[0141] The receiving substrate 1 is advantageously made of a material transparent to electromagnetic radiation to which a CC bonding layer interposed between the substrate 1 and the nucleation layer 2 can be subjected. By way of non-limiting example, the material from which the receiving substrate 1 is made is advantageously transparent in the infrared.

[0142] Indeed, step b) may include the steps: bi) forming a CC bonding layer on the receiving substrate 1 or on the donor substrate SD; b2) assembling the donor substrate SD to the recipient substrate 1 via the bonding layer CC.

[0143] The bonding layer CC formed during step bj is advantageously designed to detach the receiving substrate 1 from the heterojunction structure obtained at the end of step e) when the bonding layer CC is subjected to electromagnetic radiation. The electromagnetic radiation may come from laser irradiation.

[0144] The CC bonding layer formed during step bj may comprise: - a first adhesive underlayer, advantageously made from a material chosen from amorphous silicon and polycrystalline silicon; - a second release sub-layer, designed to detach the receiving substrate 1 from the heterojunction structure obtained at the end of step e) when the second release sub-layer is subjected to electromagnetic radiation.

[0145] The second release sub-layer is advantageously produced: - in a metallic material such as aluminum Al, tin Sn, zinc Zn; or - in a carbon material such as carbon nanotubes or graphene.

[0146] Such materials for the second release sub-layer absorb in the infrared so as to separate the receiving substrate 1 from the heterojunction structure obtained at the end of step e) when these materials are subjected to infrared radiation.

[0147] When the CC bonding layer is not designed to detach the receiving substrate 1, step b) may comprise a step consisting of doping the CC bonding layer (by implantation or by diffusion of dopants) so as to obtain a p / n junction within it, or with the receiving substrate 1 (in which case the receiving substrate 1 is doped).

[0148] Step b) is advantageously followed by thermal annealing adapted to reinforce the bonding interface between the donor substrate SD and the recipient substrate 1. By “thermal annealing” is meant a heat treatment comprising: (i) a phase of gradual temperature increase (rise ramp) until a temperature called the annealing temperature is reached; (ii) a holding phase (plateau) at the annealing temperature, for a period called the annealing time; (iii) a cooling phase.

[0149] The thermal annealing is carried out according to a thermal budget adapted to reinforce the bonding interface between the donor substrate SD and the receiving substrate 1. By “thermal budget”, we mean an input of energy of a thermal nature, determined by the choice of a value of the annealing temperature and the choice of a value of the annealing duration. The annealing temperature can be between 300°C and 500°C. The annealing duration is of the order of a few minutes to a few hours.

[0150] Step c)

[0151] Step c) consists of thinning the donor substrate SD so as to obtain a nucleation layer 2. The term “thinning” is understood as making it less thick the SD donor substrate, without limitation to a technique of a particular nature as means of obtaining a reduced thickness for the SD donor substrate.

[0152] By way of non-limiting example, step c) may comprise a step of grinding the SD donor substrate, followed by a step of chemical mechanical polishing (CMP) of the SD donor substrate. Other techniques are conceivable, involving for example a Smart-cut™ of the SD donor substrate.

[0153] The final thickness of the nucleation layer 2 can be adjusted by applying thermal annealing, under an oxidizing or neutral atmosphere. The annealing temperature can be between 1100°C and 1200°C. The annealing time can be of the order of a few hours.

[0154] Step c) may include a step consisting of doping the nucleation layer 2 (by implantation or by diffusion of dopants) so as to obtain a p / n junction: - within it, or - with the receiving substrate 1 (in which case the receiving substrate 1 is doped), or - with the CC bonding layer (in which case the CC bonding layer is doped and is not designed to detach the receiving substrate 1).

[0155] Step d)

[0156] Step d) consists of forming a buffer layer 3 on the nucleation layer 2. Step d) advantageously comprises a prior step consisting of cleaning the surface of the nucleation layer 2.

[0157] Step d) is advantageously carried out by organometallic vapor phase epitaxy MOCVD, by molecular beam epitaxy MBE, or by hybrid vapor phase epitaxy HVPE.

[0158] The buffer layer 3 is made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5.

[0159] The buffer layer 3 formed during step d) is advantageously made of a monocrystalline material. To do this, as mentioned previously, step d) can be carried out by MOCVD epitaxy, by MBE epitaxy or by HVPE epitaxy. It is also possible, in order to limit the operating time, to form a polycrystalline material by physical vapor deposition (PVD) and then to crystallize this material (this is called recrystallization). Step d) can combine MOCVD epitaxy with recrystallized PVD deposition. Recrystallization can be carried out by thermal annealing.

[0160] The buffer layer 3 formed during step d) advantageously has a thickness greater than 1 μm.

[0161] Step e)

[0162] Step e) consists of successively forming the first and second semi- conductive layers 4, 5 on the buffer layer 3. Step e) can be carried out by MOCVD epitaxy or by MBE epitaxy.

[0163] The first semiconductor layer 4 extends over the buffer layer 3. The first semiconductor layer 4 is made of a first IILN type alloy.

[0164] The second semiconductor layer 5 extends over the first semiconductor layer 4. The second semiconductor layer 5 is made from a second IILN type alloy.

[0165] The first and second IILN type alloys are designed such that the first and second semiconductor layers 4, 5 have a heterojunction H adapted to form a two-dimensional electron gas. By way of non-limiting example, the first IILN type alloy may be an alloy of empirical formula AlxGabxN, with x>0, while the second IILN type alloy may be an alloy of empirical formula Aly GabyN, with y>x. When x=0, the first IILN type alloy is a binary alloy of gallium nitride GaN. When x^O, the first IILN type alloy is a ternary alloy of aluminum-gallium nitride AlGaN.

[0166] Manufacturing process with a “2H” AIN nucleation layer

[0167] An object of the invention is a method of manufacturing a heterojunction structure for a high electron mobility transistor, comprising the successive steps: a') forming a nucleation layer 2 on a growth substrate SC, the nucleation layer 2 being made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type, the nucleation layer 2 having: - a first face 20, free, having an aluminum Al type polarity; - a second face 21, opposite the first face 20, having a nitrogen N type polarity; b') assembling the growth substrate SC to a temporary substrate ST on the side of the first face 20 of the nucleation layer 2; then removing the growth substrate SC so as to expose the second face 21 of the nucleation layer 2; c') assembling the temporary substrate ST to a receiving substrate 1 on the side of the second face 21 of the nucleation layer 2; then removing the temporary substrate ST so as to expose the first face 20 of the nucleation layer 2; d) forming a buffer layer 3 on the nucleation layer 2, the buffer layer 3 being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer 3 being devoid of carbon atoms; e) successively forming first and second semiconductor layers 4, 5 on the buffer layer 3, the first and second semiconductor layers 4, 5 being made respectively from first and second IILN type alloys chosen so that the first and second semiconductor layers 4, 5 have a hetero- H junction suitable for forming a two-dimensional electron gas.

[0168] Step a')

[0169] Step a') consists of forming a nucleation layer 2 on a growth substrate SC. By way of non-limiting example, the growth substrate SC can be made of silicon Si. Step a') can be carried out by MOCVD epitaxy or by MBE epitaxy.

[0170] The nucleation layer 2 is made of monocrystalline aluminum nitride AIN having a hexagonal crystalline structure of the “2H” type.

[0171] Nucleation layer 2 has: - a first face 20, free, having an aluminum Al type polarity; - a second face 21, opposite the first face 20, having a nitrogen N type polarity.

[0172] Step b')

[0173] Step b') comprises the successive steps: b'i) assembling the growth substrate SC to a temporary substrate ST on the side of the first face 20 of the nucleation layer 2; b'2) removing the growth substrate SC so as to expose the second face 21 of the nucleation layer 2.

[0174] Step b'i) can be carried out by direct bonding. The bonding can be direct between the growth substrate SC and the temporary substrate ST. When the growth substrate SC and / or the temporary substrate ST are coated with a dielectric layer (e.g. an oxide layer, preferably amorphous) before bonding, the bonding can be direct between a dielectric layer and a substrate, or between two dielectric layers. The thickness of the dielectric layer(s) (e.g. of the order of 100 nm) is adapted so as not to induce a significant thermal barrier.

[0175] As a non-limiting example, the temporary substrate ST can be made of silicon Si.

[0176] Step b'2) can be carried out by etching. The etching can be dry or wet, possibly in combination with grinding and chemical-mechanical polishing.

[0177] Step c')

[0178] Step c') comprises the successive steps: - assembling the temporary substrate ST to a receiving substrate 1 on the side of the second face 21 of the nucleation layer 2, preferably by direct bonding; - removing the temporary substrate ST so as to expose the first face 20 of the nucleation layer 2, preferably by etching (dry or wet, possibly in combination with grinding and chemical-mechanical polishing).

[0179] The bonding can be direct between the temporary substrate ST and the receiving substrate 1. When the temporary substrate ST and / or the receiving substrate 1 are coated with a dielectric layer (e.g. an oxide layer, preferably amorphous) before bonding, the bonding can be direct between a dielectric layer and a substrate, or between two dielectric layers. The thickness of the dielectric layer(s) (e.g. of the order of 100 nm) is adapted so as not to induce a significant thermal barrier.

[0180] The bonding may not be direct between the temporary substrate ST and the receiving substrate 1. For this purpose, it is possible to use a polymer layer to assemble the temporary substrate ST to the receiving substrate 1 on the side of the second face 21 of the nucleation layer 2. If necessary, it is possible to remove the temporary substrate ST with a laser source.

[0181] The receiving substrate 1 is advantageously made of a material having a coefficient of thermal expansion, noted CTE2. The material in which the receiving substrate 1 is made is advantageously chosen so that jcrg2-CTgl| . «, where cte\ -1' f CTE1 is the coefficient of thermal expansion of the material in which the buffer layer 3 is made during step d).

[0182] The receiving substrate 1 is advantageously made of a material chosen from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN. The receiving substrate 1 is advantageously a bulk substrate.

[0183] The receiving substrate 1 is advantageously made of a material transparent to electromagnetic radiation to which a CC bonding layer interposed between the substrate 1 and the nucleation layer 2 can be subjected. By way of non-limiting example, the material from which the receiving substrate 1 is made is advantageously transparent in the infrared.

[0184] Indeed, step c') may include the steps: ci) forming a CC bonding layer on the receiving substrate 1 or on the second face 21 of the nucleation layer 2; c'2) assembling the temporary substrate ST to the receiving substrate 1 via the bonding layer CC.

[0185] The CC bonding layer formed during step c'i) is advantageously designed to detach the receiving substrate 1 from the heterojunction structure obtained at the end of step e) when the CC bonding layer is subjected to electromagnetic radiation. The electromagnetic radiation may come from laser irradiation.

[0186] The CC bonding layer formed during step c'i) may comprise: - a first adhesive underlayer, advantageously made from a material chosen from amorphous silicon and polycrystalline silicon; - a second release sub-layer, designed to detach the receiving substrate 1 from the heterojunction structure obtained at the end of step e) when the second release sub-layer is subjected to electromagnetic radiation.

[0187] The second release sub-layer is advantageously produced: - in a metallic material such as aluminum Al, tin Sn, zinc Zn; or - in a carbon material such as carbon nanotubes or graphene.

[0188] Such materials for the second release sub-layer absorb in the infrared so as to separate the receiving substrate 1 from the heterojunction structure obtained at the end of step e) when these materials are subjected to infrared radiation.

[0189] When the CC bonding layer is not designed to detach the receiving substrate 1, step c') may comprise a step consisting of doping the CC bonding layer (by implantation or by diffusion of dopants) so as to obtain a p / n junction within it, or with the receiving substrate 1 (in which case the receiving substrate 1 is doped).

[0190] Step c') advantageously comprises a thermal annealing step adapted to reinforce the bonding interface between the temporary substrate ST and the receiving substrate 1.

[0191] Step d)

[0192] Step d) consists of forming a buffer layer 3 on the nucleation layer 2. More precisely, step d) consists of forming a buffer layer 3 on the first face 20 of the nucleation layer 2 exposed at the end of step c'). Step d) advantageously comprises a prior step consisting of cleaning the surface of the nucleation layer 2.

[0193] Step d) is advantageously carried out by organometallic vapor phase epitaxy MOCVD, by molecular beam epitaxy MBE or by hybrid vapor phase epitaxy HVPE.

[0194] The buffer layer 3 is made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5.

[0195] The buffer layer 3 formed during step d) is advantageously made of a monocrystalline material. To do this, as mentioned previously, step d) can be carried out by MOCVD epitaxy, by MBE epitaxy or by HVPE epitaxy. It is also possible, in order to limit the operating time, to form a polycrystalline material by physical vapor deposition (PVD) and then to crystallize this material (this is called recrystallization). Step d) can combine MOCVD epitaxy with recrystallized PVD deposition. Recrystallization can be carried out by thermal annealing.

[0196] The buffer layer 3 formed during step d) advantageously has a thickness greater than 1 μm.

[0197] Step e)

[0198] Step e) consists of successively forming the first and second semiconductor layers 4, 5 on the buffer layer 3. Step e) can be carried out by a MOCVD epitaxy or by MBE epitaxy.

[0199] The first semiconductor layer 4 extends over the buffer layer 3. The first semiconductor layer 4 is made of a first IILN type alloy.

[0200] The second semiconductor layer 5 extends over the first semiconductor layer 4. The second semiconductor layer 5 is made from a second IILN type alloy.

[0201] The first and second IILN type alloys are designed such that the first and second semiconductor layers 4, 5 have a heterojunction H adapted to form a two-dimensional electron gas. By way of non-limiting example, the first IILN type alloy may be an alloy of empirical formula AlxGabxN, with x>0, while the second IILN type alloy may be an alloy of empirical formula Aly GabyN, with y>x. When x=0, the first IILN type alloy is a binary alloy of gallium nitride GaN. When x^0, the first IILN type alloy is a ternary alloy of aluminum-gallium nitride AlGaN.

[0202] The invention is not limited to the embodiments disclosed. Those skilled in the art are able to consider their technically operative combinations and to substitute equivalents for them.

Claims

Claims

1. Heterojunction structure for a high electron mobility transistor, comprising successively: - a substrate (1); - a nucleation layer (2), made of a material different from the substrate (1) and chosen from monocrystalline silicon Si having a crystal orientation of the "111" type and monocrystalline aluminum nitride AIN having a hexagonal crystal structure of the "2H" type; - a buffer layer (3), made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer (3) being devoid of carbon atoms; - first and second semiconductor layers (4, 5), made respectively of first and second III-N type alloys chosen so that the first and second semiconductor layers (4, 5) have a heterojunction (H) adapted to form a two-dimensional electron gas.

2. Heterojunction structure according to claim 1, in which: - the material from which the buffer layer (3) is made has a first coefficient of thermal expansion, noted CTE1; - the substrate (1) is made from a material having a second coefficient of thermal expansion, noted CTE2; the material from which the substrate (1) is made being chosen so that < 1 tw • CT El -W / o

3. A heterojunction structure according to claim 1 or 2, wherein the substrate (1) is made of a material selected from polycrystalline silicon carbide SiC and polycrystalline aluminum nitride AIN.

4. A heterojunction structure according to one of claims 1 to 3, comprising a bonding layer (CC) extending between the substrate (1) and the nucleation layer (2), the bonding layer (CC) being designed to detach the substrate (1) from the heterojunction structure when the bonding layer (CC) is subjected to electromagnetic radiation; the substrate (1) being made of a material transparent to electromagnetic radiation.

5. Heterojunction structure according to claim 4, in which the bonding layer (CC) comprises: - a first adhesive sub-layer, preferably made in a material selected from amorphous silicon and polycrystalline silicon; - a second release sub-layer, designed to detach the substrate (1) from the heterojunction structure when the second release sub-layer is subjected to electromagnetic radiation; the second release sub-layer preferably being made of a metallic material such as aluminum Al, tin Sn or zinc Zn, or preferably made of a carbon material such as carbon nanotubes or graphene.

6. Heterojunction structure according to one of claims 1 to 5, in which the buffer layer (3) has a thickness greater than or equal to 1 pm.

7. Heterojunction structure according to one of claims 1 to 6, in which the material from which the buffer layer (3) is made is monocrystalline.

8. Heterojunction structure according to one of claims 1 to 7, in which: - the first III-N type alloy is an alloy of empirical formula AlxGa,x N, with x>0; - the second III-N type alloy is an alloy of empirical formula AlyGa i.yN, with y>x.

9. High electron mobility transistor, comprising: - a heterojunction structure according to one of claims 1 to 8; - first and second metal zones (ZM1, ZM2), each extending through the second semiconductor layer (5) so as to form an ohmic contact with the heterojunction (H); - a source electrode (S) and a drain electrode (D), respectively electrically connected to the first and second metal zones (ZM1, ZM2); - a third metal zone (ZM3), the first and second metal zones (ZM1, ZM2) extending on either side of the third metal zone (ZM3); - a gate electrode (G), electrically connected to the third metal zone (ZM3).

10. A transistor according to claim 9, wherein the third metal zone (ZM3) is arranged to: - extend over the second semiconductor layer (5) so as to form a Schottky contact with the second semiconductor layer (5); or - extend over a dielectric layer (6) covering the second semiconductor layer (5); or - extend over a layer (7) of p-type doped gallium nitride GaN or over a layer (7) of p-type doped aluminum-gallium nitride AlGaN, covering the second semiconductor layer (5); or - extend inside the second semiconductor layer (5) so as to form a recessed gate electrode (G).

11. Transistor according to claim 9 or 10, comprising at least one field plate (FP) arranged to form a lateral extension of the third metal zone (ZM3), the lateral extension being oriented towards the second metal zone (ZM2).

12. Method for manufacturing a heterojunction structure for a high electron mobility transistor, comprising the successive steps: a) using a donor substrate (SD), made of monocrystalline silicon Si having a crystal orientation of the “111” type; b) assembling the donor substrate (SD) to a receiving substrate (1); c) thinning the donor substrate (SD) so as to obtain a nucleation layer (2); d) forming a buffer layer (3) on the nucleation layer (2), the buffer layer (3) being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer (3) being devoid of carbon atoms;e) successively forming first and second semiconductor layers (4, 5) on the buffer layer (3), the first and second semiconductor layers (4, 5) being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers (4, 5) have a heterojunction (H) suitable for forming a two-dimensional electron gas.;

13. Method according to claim 12, wherein step b) comprises the steps: bi) forming a bonding layer (CC) on the receiving substrate (1) or on the donor substrate (1); b2) assembling the donor substrate (SD) to the receiving substrate (1) via the bonding layer (CC); the bonding layer (CC) formed during step bi) preferably being designed to detach the receiving substrate (1) from the heterojunction structure obtained at the end of step e) when the bonding layer (CC) is subjected to electromagnetic radiation; the receiving substrate (1) being made of a material transparent to electromagnetic radiation.

14. Method of manufacturing a heterojunction structure for a high electron mobility transistor, comprising the successive steps: a') forming a nucleation layer (2) on a growth substrate (SC), the nucleation layer (2) being made of monocrystalline aluminum nitride AIN having a hexagonal crystal structure of the “2H” type, the nucleation layer (2) having: - a first face (20), free, having an aluminum Al type polarity; - a second face (21), opposite the first face (20), having a nitrogen N type polarity; b') assembling the growth substrate (SC) to a temporary substrate (ST) on the side of the first face (20) of the nucleation layer (2); then removing the growth substrate (SC) so as to expose the second face (21) of the nucleation layer (2); c') assembling the temporary substrate (ST) to a receiving substrate (1) on the side of the second face (21) of the nucleation layer (2); then removing the temporary substrate (ST) so as to expose the first face (20) of the nucleation layer (2); d) forming a buffer layer (3) on the nucleation layer (2), the buffer layer (3) being made of a material chosen from aluminum nitride AIN and aluminum-gallium nitride AlxGabxN with x>0.5; the buffer layer (3) being devoid of carbon atoms; e) successively forming first and second semiconductor layers (4, 5) on the buffer layer (3), the first and second semiconductor layers (4, 5) being made respectively from first and second III-N type alloys chosen so that the first and second semiconductor layers (4, 5) have a heterojunction (H) suitable for forming a two-dimensional electron gas.

15. The method of claim 14, wherein step c') comprises the steps: c) forming a bonding layer (CC) on the receiving substrate (1) or on the second face (21) of the nucleation layer (2); c'2) assembling the temporary substrate (ST) to the receiving substrate (1) via the bonding layer (CC); the bonding layer (CC) formed during step c'i) being preferably designed to detach the receiving substrate (1) from the heterojunction structure obtained at the end of step e) when the bonding layer (CC) is subjected to electromagnetic radiation; the receiving substrate (1) being made of a material transparent to electromagnetic radiation.

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