Integrated circuit chip comprising a radio frequency component

Abstract

Integrated circuit chip comprising a radiofrequency component The present description relates to an integrated circuit chip (100) comprising at least one component (120), arranged in and / or on a structure (110) comprising a semiconductor substrate (111) on which rests an insulating layer (112) on which rests a semiconductor layer (113), in which at least two PN junctions are arranged at the interface between said substrate (111) and said insulating layer (112). Figure for abstract: Fig. 1

Description

Title of the invention: Integrated circuit chip comprising a radiofrequency component Technical field

[0001] The present description relates generally to the field of integrated circuit electronic chips and their manufacturing methods. It relates more particularly to the field of integrated circuit electronic chips comprising a radiofrequency component and their manufacturing methods. Prior art

[0002] Radio frequency components are generally referred to as components intended to use alternating electrical signals at frequencies in the range from 3 kHz to 30 GHz. Known radio frequency components include active components such as amplifiers, mixers and data converters, and passive components such as capacitors, inductors and antennas.

[0003] It would be desirable to be able to improve, at least in part, certain aspects of integrated circuit chips comprising a radiofrequency component. Summary of the invention

[0004] There is a need for electronic components formed on a better electrically insulated SOI type structure.

[0005] There is a need for integrated circuit chips for radio frequency applications comprising such electronic components.

[0006] There is a need for methods of manufacturing such electronic components.

[0007] One embodiment overcomes all or part of the drawbacks of known electronic components.

[0008] One embodiment overcomes all or part of the drawbacks of known integrated circuit chips intended for radiofrequency applications.

[0009] One embodiment overcomes all or part of the drawbacks of known manufacturing methods for such electronic chips.

[0010] One embodiment provides an electronic component formed in and on an SOI type structure in which PN junctions are formed at the interface between the supporting substrate and the buried oxide layer.

[0011] One embodiment provides an integrated circuit chip comprising such an electronic chip.

[0012] One embodiment provides a method of manufacturing such an electronic component.

[0013] One embodiment provides an integrated circuit chip comprising at least one component, disposed in and / or on a structure comprising a semiconductor substrate on which rests an insulating layer on which rests a semiconductor layer, wherein at least two PN junctions are disposed at the interface between said substrate and said insulating layer.

[0014] According to one embodiment, said at least two PN junctions are arranged against the interface between said substrate and said insulating layer.

[0015] According to one embodiment, the PN junctions comprise an alternation of N-type doped wells and P-type doped wells.

[0016] According to one embodiment, said N-type doped wells have a width greater than or equal to 78 nm.

[0017] According to one embodiment, said P-type doped wells have a width greater than or equal to 200 nm.

[0018] According to one embodiment, said semiconductor substrate comprises a resistivity greater than 125 Ohm.cm.

[0019] According to one embodiment, said component is a switch.

[0020] According to one embodiment, said component is a MOS type transistor.

[0021] According to one embodiment, the chip is suitable for radiofrequency applications, the component being intended to use alternating electrical signals at frequencies in the range from 3 kHz to 30 GHz.

[0022] According to one embodiment, the chip is an SPDT type switch, said component being a switch.

[0023] According to one embodiment, the chip is a radio frequency switch with frequency band selection, said component being a switch.

[0024] Another embodiment provides a method of manufacturing an integrated circuit chip comprising at least one component, and being formed in and / or on a structure comprising a semiconductor substrate on which rests an insulating layer on which rests a semiconductor layer, said method comprising a step of forming at least two PN junctions formed at the interface between said substrate and said insulating layer.

[0025] According to one embodiment, the step of forming said at least two PN junctions comprises the following steps: - a first masking step; - a first step of implanting P-type dopants at the interface between said substrate and said insulating layer to form P-type doped wells; - a second masking step; - a second step of implanting N-type dopants at the interface between said substrate and said insulating layer to form N-type doped wells; And - an annealing step.

[0026] According to one embodiment, the P-type dopants comprise Boron.

[0027] According to one embodiment, the N-type dopants comprise Arsenic.

[0028] According to one embodiment, the annealing step is a thermal ramp step. made by a laser.

[0029] According to one embodiment, the method comprises, after the step of forming said at least two PN junctions, a step of manufacturing said component.

[0030] According to one embodiment, said component is formed from said semiconducting layer. Brief description of the drawings

[0031] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0032] [Fig.l] represents a sectional view of an embodiment of an integrated circuit chip;

[0033] [Fig.2] illustrates a step of an embodiment of a manufacturing method of the embodiment of [Fig.l];

[0034] [Fig.3] illustrates another step of an embodiment of a manufacturing method of the embodiment of [Fig.1];

[0035] [Fig.4] illustrates another step of an embodiment of a manufacturing method of the embodiment of [Fig.1];

[0036] [Fig.5] illustrates another step of an embodiment of a manufacturing method of the embodiment of [Fig.l];

[0037] [Fig.6] illustrates another step of an embodiment of a manufacturing method of the embodiment of [Fig.1];

[0038] [Fig.7] illustrates another step of an embodiment of a manufacturing method of the embodiment of [Fig.1];

[0039] [Fig.8] illustrates another step of an embodiment of a manufacturing method of the embodiment of [Fig.1];

[0040] [Fig.9] shows an embodiment of a chip comprising the embodiment of [Fig.l];

[0041] [Fig. 10] represents an example of the chip of [Fig.9]; and

[0042] [Fig.l 1] represents another example of the chip of [Fig.9]. Description of the embodiments

[0043] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0044] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0045] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0046] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0047] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0048] The embodiments described below relate to the electrical insulation of electronic chips, and more particularly to the electrical insulation of integrated circuit chips adapted to receive radiofrequency signals, i.e. alternating electrical signals having a frequency in the range from 3 kHz to 30 GHz. The components in question here are chips formed in and / or on a substrate-on-insulator type structure, or SOI type structure. It may happen that leakage currents transverse the insulating layer entering the SOI type structure by capacitive effect, it is therefore important to properly insulate such chips. One way of overcoming this problem is to form PN junctions at the interface between the buried insulating layer and the support substrate of the SOI type structure. An electronic chip formed in and / or on such a structure is described in relation to [Fig.l], and a method of manufacturing such a chip is described in connection with Figures 2 to 8. .

[0049] In addition, the embodiments described below are particularly suitable for use in integrated circuit chips used for radio frequency applications, i.e. for applications using radio frequency signals. Examples of application of the embodiments are described in relation to FIGS. 9 to 11.

[0050] [Fig.l] is a sectional view of an integrated circuit chip 100 formed in and / or on an SOI type structure 110 and comprising at least one electronic component 120.

[0051] The SOI 110 (Substrate On Insulator) type structure comprises a stack comprising: - a semiconductor substrate 111 (P), also called support substrate 111; - a buried insulating layer 112 (BOX) resting on and in contact with an upper face of the support substrate 111; and - a semiconductor layer 113 resting on and in contact with an upper face of the buried insulating layer 112, opposite a lower face of the insulating layer 112 in contact with the upper face of the support substrate 111.

[0052] The support substrate 111 is a substrate made of a semiconductor material, i.e. a material comprising one or more elements from column 14 of the periodic table of elements, such as silicon or germanium. According to a preferred embodiment, the support substrate 111 is a high resistivity substrate, i.e. a substrate having a resistivity greater than or equal to 125 Ohm.cm.

[0053] The buried layer 112 is an electrically insulating layer having a thickness generally between 10 and 400 nm, preferably between 200 and 400 nm. According to one embodiment, the layer 112 is made of silicon oxide.

[0054] The semiconductor layer 113 is a layer made of a material comprising one or more elements from column 14 of the periodic table of elements, such as silicon or germanium. According to one example, the semiconductor layer 113 has a thickness generally between 40 nm and 500 pm, preferably between 40 nm and 3 pm.

[0055] According to one embodiment, the SOI structure further comprises an isolation means making it possible to prevent leakage of component charges, formed from the semiconductor layer 113, into the buried insulating layer 112 by capacitive effect. This isolation means consists of the formation of PN junctions at the interface between the support substrate 111 and the buried insulating layer 112. For this, an alternation of P-type 114 (P) and N-type 115 (N) doped wells are formed at this interface. According to one embodiment, the SOI structure 110 comprises at least two PN junctions formed at this interface, preferably more than 5 PN junctions, for example of the order of at least ten PN junctions. In [Fig.l], in order not to overload the figure, 6 PN junctions are shown. An embodiment of a method for manufacturing such an SOI structure is described in detail in relation to Figures 2 to 8.

[0056] More particularly, here we call alternation of N-type doped wells 114 and P-type doped wells 115 a succession of wells 114 and 115 in which each well 114 is surrounded by two wells 115, and each well 115 is surrounded by two wells 114. In this way, PN junctions, as illustrated in [Fig.l], are formed along the interface between the substrate 111 and the buried insulating layer 112.

[0057] According to one embodiment, the wells 114 are portions of the support substrate 111 extending from its upper face which are P-type doped. In other words, the wells 114 have been doped using one or more chemical elements forming part of column 13 of the periodic table of elements, such as boron. According to one example, the wells 114 have a minimum thickness of 3 μm, and a minimum width of 200 nm. According to one example, the well 114 comprises a concentration of doping elements of between 1018 cm3 and 1020 cm3, for example of the order of 1019 cm3.

[0058] According to one embodiment, the wells 115 are portions of the support substrate 111 extending from its upper face which are N-type doped. In other words, the wells 115 have been doped using one or more chemical elements forming part of column 15 of the periodic table of elements, such as arsenic. According to one example, the wells 115 have a minimum thickness of 3 μm, and a minimum width of 78 nm, for example between 78 nm and 5 μm. According to one example, the well 114 comprises a concentration of doping elements of between 1018 cm3 and 1020 cm3, for example of the order of 1019 cm3

[0059] In the example of [Fig.l], the electronic component 120 is a switch, such as a switch adapted to receive radiofrequency signals, i.e. signals with a frequency between 3 kHz and 30 GHz. More particularly, in the example of [Fig.l], the component 120 is a metal-oxide-semiconductor field-effect transistor, or MOSFET transistor, or MOS transistor. In addition, the component 120 is an N-channel MOS transistor, or N-type MOS transistor, or NMOS transistor.

[0060] The component 120, or transistor 120, is formed from the semiconductor layer 113. The transistor 120 comprises an N-type doped source region 121 (N), formed over the entire thickness of a portion of the semiconductor layer 113 (on the left in [Fig.l]), and an N-type doped drain region 122 (N), formed over the entire thickness of another portion of the semiconductor layer 113 (on the right in [Fig.l]). The regions 121 and 122 are separated by a P-type doped channel region 123 (P). The channel region 123 is formed over the entire thickness of a portion of the semiconductor layer 113 (in the center in [Fig.l]).

[0061] The component 120 further comprises a gate stack comprising a gate insulator layer 124 formed on an upper face of the channel region 123, and a gate layer 125 (N) resting on and in contact with the gate insulator layer 123. The layers 124 and 125 have a width of the order of the width of the channel region 123.

[0062] The component 120 further comprises spacers 126 for protecting the side faces of the stack of grids. Examples of spacers are illustrated in [Fig.l] and are within the reach of a person skilled in the art. In [Fig.l], the spacers 126 comprise three insulating layers resting on top of each other.

[0063] The component 120 further comprises siliciding layers 127 arranged on an upper face of the source 121 and drain 122 regions and on an upper face of the gate layer 125.

[0064] An advantage of the embodiment illustrated in [Fig.l] is that it makes it possible to avoid charge leaks in the buried insulating layer 112.

[0065] Figures 2 to 9 are sectional views illustrating steps of an embodiment of a method of manufacturing a device of the type of device 100 described in relation to [Fig.l].

[0066] In the step of [Fig. 2], an SOI 200 structure of the type of the SOI 110 structure described in relation to [Fig. 1] is considered. The structure 200 thus comprises: - a support semiconductor substrate 201 of the type of the support substrate 111 described in relation to [Fig.l]; - a buried insulating layer 202 of the type of buried insulating layer 112 described in relation to [Fig.l], the layer 202 resting on and in contact with the support substrate 202; and - a semiconductor layer 203 of the type of the semiconductor layer 113 described in relation to [Fig.l], the layer 203 resting on and in contact with the buried insulating layer 202 on a face opposite the support substrate 201.

[0067] In the step of [Fig. 3], a mask 204 is formed on an upper face of the semiconductor layer 203, opposite the face of the semiconductor layer 203 in contact with the buried insulating layer 202. The mask 204 makes it possible to define the width of P-type doped wells of the type of wells 114 described in relation to [Fig. 1]. According to one example, the mask 204 is produced by a photolithography step.

[0068] In the step of [Fig. 4], P-type doping elements are implanted deep into the structure 200 of [Fig. 3]. More particularly, these doping elements form P-type doped wells 205 at the interface between the buried insulating layer 202 and the support substrate 201. These wells 205 may extend over a portion of the insulating layer 202 and a portion of the support substrate 201. According to one embodiment, the doping elements are here chemical elements forming part of column 13 of the periodic table of elements. According to one example, the doping elements comprise boron.

[0069] In the step of [Fig.5], the mask 204 is removed from the upper face of the semiconductor layer 203.

[0070] Furthermore, in the step of [Fig.5], a mask 206 is formed on an upper face of the semiconductor layer 203, opposite the face of the semiconductor layer 203 in contact with the buried insulating layer 202. The mask 206 makes it possible to define the width of N-type doped boxes of the type of boxes 115 described in relation to [Fig.l]. According to one example, the mask 206 is produced by a photolithography step.

[0071] In the step of [Fig. 6], N-type doping elements are implanted deep into the structure 200 of [Fig. 5]. More particularly, these doping elements form N-type doped wells 207 at the interface between the buried insulating layer 202 and the support substrate 201, designated in [Fig. 6] by a dotted line 208. These wells 207 may extend over a portion of the insulating layer 202 and a portion of the support substrate 201. According to one embodiment, the doping elements are here chemical elements forming part of column 15 of the periodic table of elements. According to one example, the doping elements comprise arsenic.

[0072] According to one embodiment, and as indicated in relation to [Fig.l], the P-type doped 205 and N-type doped 207 wells are arranged alternately. More particularly, each well 204 is surrounded by two wells 205, and each well 205 is surrounded by two wells 204. In this way, PN junctions, as illustrated in [Fig.6], are formed along the interface between the substrate 201 and the buried insulating layer 202. To obtain such a result, the masks 204 and 206 have periodic openings in opposition to each other.

[0073] In the step of [Fig.7], an annihilation operation is implemented. This step makes it possible to make the layer 202 insulating again. According to one example, the annihilation operation is a heat treatment step, for example an annealing step or a thermal ramp step. According to a particular example, the annihilation operation is a thermal ramp step carried out by a laser, with a temperature varying between 500 and 600°C.

[0074] The step of [Fig.7] makes it possible to migrate the doping elements present in the buried insulating layer 202 and, more generally, to reduce the thickness of the boxes 205 and 207.

[0075] In the step of [Fig.8], a component 209, of the type of component 120 is formed from the semiconductor layer 203. The steps for manufacturing such a component are within the scope of the person skilled in the art.

[0076] According to one embodiment, the dimensions of the boxes 205 and 207 are established according to the different manufacturing steps of the component 209. Indeed, the manufacturing steps of the component 209 may include heat treatment operations which may cause the doping elements of the boxes 205 and 507 to diffuse, and this phenomenon must be avoided. This is why the boxes 207 have a minimum thickness of 3 pm, and a minimum width of 200 nm, and the boxes 207 have a minimum thickness of 3 pm, and a minimum width of 78 nm. In practice the 207 boxes have a width much greater than 78 nm, for example of the order of several hundred nm.

[0077] [Fig. 9] shows an example of an integrated circuit chip 901 (RF) of the type of the integrated circuit chip 100 described in relation to [Fig. 1].

[0078] As stated previously, an application of the chip 100 described in relation to [Fig.l] may be an integrated circuit chip formed on an SOI structure of the type of the structure 110 described in relation to [Fig.l], a previous version of which has problems of current leakage in the buried insulating layer of said structure.

[0079] More particularly, the integrated circuit chip 901 represents a preferred application of the chip 100 of [Fig. 1], since the chip 901 is adapted to use radio frequency signals. More precisely, the chip 901 comprises at least one electronic component 902 (HW) of the type of the component 120 described in relation to [Fig. 1], adapted to use one or more radio frequency signals. As previously described, the component 902 can be any electronic component adapted to process one or more radio frequency signals, such as a switch, a transmission line or an integrated inductor.

[0080] [Fig. 10] shows another example of an integrated circuit chip 1000 of the type of integrated circuit chip 100 described in connection with [Fig.l].

[0081] The integrated circuit chip 1000 is an SPDT (Single Pole Double Throw) type switch or relay intended to be controlled by radio frequency signals, for example signals using home WiFi communication protocols.

[0082] According to one example, the integrated circuit chip 1000 comprises an input node RX1000 and an output node TX1000 adapted, respectively, to receive and transmit radio frequency signals.

[0083] The integrated circuit chip 1000 further comprises a connection to an antenna ANT1000, and a connection PDET100 for collecting an image of the output power of the antenna. This image is obtained using a signal taken from a directional coupler INV1001 described below.

[0084] The integrated circuit chip 1000 comprises, on a first branch for receiving a signal by the antenna, a capacitor Cl001, an amplifier LNA1000, a filtering circuit F1001, and a switch SW1001. A first conduction terminal of the capacitor Cl001 is connected, preferably connected, to the input node RX1000, and a second conduction terminal of the capacitor Cl001 is connected, preferably connected, to an output of the amplifier LNA1000. An input of the amplifier LNA1000 is connected, preferably connected, to an output of the filtering circuit F1001. According to one example, the amplifier LNA1000 is a low-noise amplifier. The switch SW1001 is arranged in parallel with the amplifier LNA1000 and the filtering circuit F1001. More particularly, a terminal of conduction of the switch SW1001 is connected, preferably connected, to the output of the amplifier LNA1000, and a second conduction terminal of the switch SW1001 is connected, preferably connected, to an input of the filter circuit F1001.

[0085] The integrated circuit chip 1000 further comprises a switch SW1002, one input of which is connected, preferably connected, to the antenna ANT1000 and comprising two outputs. A first output is connected to the first branch, and, more precisely, is connected, preferably connected, to the input of the filtering circuit F1001. A second output is connected to a second transmission branch of the chip 1000 described below.

[0086] The integrated circuit chip 1000 further comprises a coil B1001 connecting the antenna ANT1000 to a terminal receiving a reference potential, for example ground. Thus, a first terminal of the coil B1001 is connected, preferably connected, to the antenna ANT1001, and a second terminal of the coil B1001 is connected, preferably connected, to the node receiving the reference potential.

[0087] The integrated circuit chip 1000 further comprises a second branch for transmitting signals to the antenna ANT1000, comprising a capacitor C1002, an amplifier PA 1001, a filter circuit F1002, the directional coupler INV1001 and a diode DI001. A first conduction terminal of the capacitor C1002 is connected, preferably connected, to the input node TX1000, and a second conduction terminal of the capacitor C1002 is connected, preferably connected, to an input of the amplifier PA1001. An output of the amplifier PA1001 is connected, preferably connected, to an output of the filter circuit F1002. According to one example, the amplifier PA1001 is a controllable gain amplifier. An input of the inverter IV1001 is connected, preferably connected, to the output of the filter circuit F1002.A first output of the coupler INV1001 is connected, preferably connected, to the second output of the switch SW1002, and a second output of the coupler INV1001 is connected, preferably connected, to an anode of the diode D1001. The directional coupler INV1001 makes it possible to sample a fraction of the signal arriving at the antenna in order to be able to determine an image of the power level emitted by this antenna. The cathode of the diode DI001 is connected, preferably connected, to the connection PDET100.

[0088] According to one example, the switch SW1002 may be the component 120 described in relation to [Fig.l].

[0089] [Fig. 11] shows another example of an integrated circuit chip 1100 of the type of integrated circuit chip 100 described in connection with [Fig.l].

[0090] The integrated circuit chip 1100 is a frequency band selectable radio frequency switch.

[0091] The integrated circuit chip 1100 includes a control interface INT1100 (MIPI Interface) and a set of SW 1100 switches.

[0092] The interface INT1100 is adapted to control the set of switches SW 1100 and receives for this purpose a communication signal VIO 1100, a clock signal CLK1100, and a data signal SDATA1100. The interface INT1100 is, in addition, connected to a reference potential, for example the ground GND1100.

[0093] The set of switches SW 1100 comprises N switches, N being an integer greater than one, all having a common input connected to an antenna ANT1100, and separate outputs. More particularly, each switch of the set SW1100 has a first conduction terminal connected, preferably connected, to the antenna ANT1100, and a second conduction terminal connected, preferably connected, to an output of the set SW1100. In the example illustrated in [Fig. 11], the set comprises eight (8) switches.

[0094] According to one example, the set of switches SW 1100 may be the component 120 described in relation to [Fig.l].

[0095] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0096] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Integrated circuit chip (100; 901; 1000; 1100) comprising at least one component (120; 902; SW1002; SW1100), arranged in and / or on a structure (110) comprising a semiconductor substrate (111) on which rests an insulating layer (112) on which rests a semiconductor layer (113), in which at least two PN junctions are arranged at the interface between said substrate (111) and said insulating layer (112).

2. A chip according to claim 1, wherein said at least two PN junctions are disposed against the interface between said substrate (111) and said insulating layer (112).

3. A chip according to claim 1 or 2, wherein the PN junctions comprise alternating N-type doped wells (115) and P-type doped wells (114).

4. The chip of claim 3, wherein said N-type doped wells (115) have a width greater than or equal to 78 nm.

5. A chip according to claim 3 or 4, wherein said P-type doped wells (114) have a width greater than or equal to 200 nm.

6. A chip according to any one of claims 1 to 5, wherein said semiconductor substrate (111) comprises a resistivity greater than 125 Ohm.cm.

7. A chip according to any one of claims 1 to 6, wherein said component is a switch (120; 902; SW1002; SW1100).

8. A chip according to claim 7, wherein said component is a MOS type transistor (120).

9. A chip according to any one of claims 1 to 8, being suitable for radio frequency applications, the component being intended to use alternating electrical signals at frequencies in the range from 3 kHz to 30 GHz.

10. A chip according to claim 9, being an SPDT type switch, said component being a switch (SW 1002).

11. A chip according to claim 9, being a radio frequency switch with frequency band selection, said component being a switch (SW1002).

12. A method of manufacturing an integrated circuit chip (100; 901; 1000; 1100) comprising at least one component (120; 902; SW1002; SW 1100), and being formed in and / or on a structure comprising a semiconductor substrate (201) on which rests an insulating layer (202) on which rests a semiconductor layer (203), said method comprising a step of forming at least two PN junctions (115; 114) formed at the interface between said substrate (201) and said insulating layer (202).

13. The method of claim 12, wherein the step of forming said at least two PN junctions (115; 114) comprises the following steps: - a first masking step (204); - a first step of implanting P-type dopants at the interface between said substrate (201) and said insulating layer (202) to form P-type doped wells (205); - a second masking step (206); - a second step of implanting N-type dopants at the interface between said substrate (201) and said insulating layer (202) to form N-type doped wells (207); and - an annealing step.

14. The method of claim 13, wherein the P-type dopants comprise Boron.

15. A method according to claim 13 or 14, wherein the N-type dopants comprise Arsenic.

16. A method according to any one of claims 13 to 15, wherein the annealing step is a thermal ramp step performed by a laser.

17. Method according to any one of claims 12 to 16, comprising, after the step of forming said at least two PN junctions, a step of manufacturing said component (120; 902; SW1002; SW1100).

18. The method of claim 17, wherein said component (120; 902; SW1002; SW 1100) is formed from said semiconductor layer (203).

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