SEMICONDUCTOR SUBSTRATE FOR LASER SEPARATION AND METHOD FOR MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES

Abstract

A semiconductor substrate (Sub) designed to enable laser separation of an active material layer (ActMat), comprising: a support substrate (Sprt); an inorganic layer (Inorg) on ​​the support substrate, the inorganic layer being formed from a material selected from Al2O3, TiO2, WO3, La2O3, LaAlO3 and TiN; an electrically insulating layer (Ins) on the inorganic layer; and the active material layer (ActMat) on the electrically insulating layer, the active material layer being monocrystalline. Figure to be published with the abstract: Fig. 3

Description

Title of the invention: SEMICONDUCTOR SUBSTRATE FOR LASER SEPARATION AND METHOD FOR THE MANUFACTURE OF THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES FIELD OF THE INVENTION

[0001] The present invention relates to the field of the semiconductor industry and provides a semiconductor substrate designed to enable laser separation of a monocrystalline layer. The present invention also relates to a method for manufacturing a three-dimensional semiconductor structure using said substrate. CONTEXT OF THE INVENTION

[0002] Semiconductor devices are becoming increasingly complex, vertically integrating a plurality of semiconductor chips performing various functions. The main motivations for vertical integration are the reduction of inter-chip distances and the reduction of the overall lateral dimensions of the devices.

[0003] For decades, semiconductor devices were fabricated solely from bulk semiconductor materials, primarily silicon wafers several hundred micrometers thick. For cost and performance reasons, many semiconductor devices today are fabricated on relatively thin layers of semiconductor materials, less than 10 micrometers thick. In addition, the vertical integration mentioned above also requires the fabrication of semiconductor chips on thin layers to facilitate their integration into three-dimensionally designed devices.

[0004] In the industry, these integrations are known as 2.5D IC (2.5-Dimensional Integrated Circuit) or 3D IC (3-Dimensional Integrated Circuit), which represent advanced packaging techniques that combine multiple integrated circuits, or microchips, onto a single carrier. Stacked microchips may use vertical connections such as TSVs (Through Silicon Vias) and microbump assembly technology (flip-chip) to provide electrical connection between the microchips.

[0005] In the manufacturing chain of a single 2.5 ID or 3D IC technology package, the industrial players who supply the semiconductor substrates are generally not the same as those who process these substrates, used as a base material to manufacture the microchips themselves, and the latter may also be different from the players who integrate a diversity of microchips on a single support.

[0006] Furthermore, manufacturing tools that have been developed for a specific range of manufacturing processes sometimes prove inadequate for newly developed manufacturing processes or applications. Since these manufacturing tools are extremely expensive to replace, in order to amortize their development and purchase costs, they must be used to manufacture devices according to suboptimal but as efficient processes as possible.

[0007] We recognize a need to provide semiconductor substrates and processes suitable for use by a variety of players in the semiconductor industry for various applications, including those requiring advanced encapsulation techniques. In addition, these substrates must enable alternative manufacturing processes that make the best use of existing manufacturing tools. SUBJECT OF THE INVENTION

[0008] A first aspect of the invention is a semiconductor substrate comprising a layer of active material which can be easily separated by laser irradiation, an operation known as "laser lift-off" in English terminology. The layer of active material is intended to form an active layer of a semiconductor device.

[0009] A second aspect of the invention is a method of manufacturing said semiconductor substrate.

[0010] A third aspect of the invention is a method of manufacturing an active layer, formed from the layer of active material of the first subject of the invention.

[0011] A fourth aspect of the invention is a method of manufacturing a 3D integrated semiconductor device. Summary of the invention

[0012] A first subject of the invention is a semiconductor substrate designed to enable laser separation of a layer of active material, comprising: a support substrate; an inorganic layer on the support substrate, the inorganic layer being formed of a material selected from A12O3, TiO2, WO3, La2O3, LaA103 and TiN; an electrically insulating layer on the inorganic layer; and the layer of active material on the electrically insulating layer, the layer of active material being monocrystalline.

[0013] According to additional features, in the semiconductor substrate, the support substrate may be formed of monocrystalline silicon; the inorganic layer may have a thickness of between 10 nm and 2 pm; the insulating layer may comprise silicon oxide and have a thickness of between 10 nm and 1 pm; and the active material layer may be selected from Si, SiGe, GaAs, SiC, GaN and PZT and may have a thickness of between 5 nm and 2 pm.

[0014] The substrate according to the invention benefits from the high quality of a single-crystal material and can be economically included in a manufacturing process of highly integrated semiconductor devices. Indeed, the substrate is suitable for a rapid and inexpensive method of separating a processed active layer from a layer of active material of the substrate.

[0015] A second object of the invention is a method for manufacturing the semiconductor substrate of the invention comprising the following steps: implanting a light ion species through an upper surface of an active material donor substrate so as to form a weakening plane in the active material donor substrate; forming, in this order, the inorganic layer and the electrically insulating layer on a surface of a support substrate; bonding the upper surface of the active material donor substrate to a free surface of the insulating layer; and splitting the active material donor substrate at the weakening plane so as to leave the active material layer attached to the support substrate via the insulating layer and the inorganic layer.

[0016] A third subject of the invention is a method of manufacturing an active layer comprising implementing the method of manufacturing the semiconductor substrate according to the second subject of the invention in a first manufacturing unit, further comprising the following steps: sending the semiconductor substrate to a second manufacturing unit; and sending to said second manufacturing unit information representative of the fact that the active material layer of the semiconductor substrate must be separated from the support substrate in a separation step involving the irradiation of the inorganic layer with infrared radiation.

[0017] According to other non-limiting characteristics of the invention, considered individually or in any technically feasible combination:

[0018] - the method of manufacturing an active layer for a semiconductor device, comprising implementing the method for manufacturing the semiconductor substrate according to the first subject of the invention, may further comprise the steps of treating the layer of active material so as to form the active layer; and separating the active layer from the support substrate at the inorganic layer by irradiating the inorganic layer using infrared radiation;

[0019] - the method of manufacturing an active layer for a semiconductor device, comprising the implementation of the method for manufacturing the semiconductor substrate according to the first subject of the invention, may further comprise the following steps: treating the layer of active material so as to form the active layer; positioning and bonding connection pads of the active layer on connection pads of a receiving substrate; separating the support substrate from the active layer at the level of the inorganic layer by irradiating the inorganic layer with radiation infrared; cleaning a surface of the active material layer opposite the receiving substrate after separation from the supporting substrate; after the cleaning step, processing the active material layer so as to form a completed active layer; and

[0020] - the active layer may comprise a layer of semiconductor material of a thickness less than 1 micrometer.

[0021] A fourth object of the invention is a method of manufacturing a three-dimensional integrated semiconductor device comprising repeating the method of manufacturing an active layer for a semiconductor device on the same portion of the same receiving substrate so as to form a first stack consisting of a plurality of stacked active layers, one of the layers of active material to be stacked on a previously obtained active layer being positioned thereon by means of a first handling apparatus.

[0022] According to other non-limiting characteristics of the invention, considered individually or in any technically possible combination:

[0023] - the method of forming a three-dimensional integrated semiconductor device may further comprise the following steps: cutting the first stack so as to form a plurality of semiconductor elements each comprising an elementary part of the first stack; on a control substrate, forming a second stack of a plurality of elementary parts, two adjacent stacked elementary elements of the second stack being connected to each other by first electrically conductive balls, the second stack being connected to the control substrate by second electrically conductive balls, wherein, when forming the second stack, the elementary parts are positioned one on top of the other by means of a second handling apparatus distinct from the first handling apparatus;

[0024] - the first manipulation device and the second manipulation device may have a first height limit and a second height limit for the objects they can position, respectively, the first height limit being smaller than the second height limit;

[0025] - the first handling apparatus may be hybrid gluing equipment and the second handling device may be flip-chip bonding equipment; and

[0026] - the three-dimensional integrated semiconductor device may be a device of memory, each elementary part of the first stack being a digital memory element.

[0027] A manufacturing method according to the invention is a low-cost and rapid alternative to conventional transfer technologies. This method makes it possible to simply transfer high-quality semiconductor layers which may be thin and / or monocrystalline layers. This method further makes it possible to overcome equipment limitations regarding the maximum height of manipulated elements to be integrated into a semiconductor device.

[0028] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows, with reference to the appended figures, in which:

[0029] [Fig-1] [Fig.l] illustrates the formation of a weakening layer in a donor substrate for a method of manufacturing a semiconductor substrate according to the invention;

[0030] [Fig.2] [Fig.2] illustrates the manufacturing steps of the manufacturing process of a semiconductor substrate;

[0031] [Fig.3] [Fig.3] illustrates a manufacturing step of the method for manufacturing a semiconductor substrate;

[0032] [Fig.4] [Fig.4] illustrates the manufacturing steps of the method for manufacturing a semiconductor substrate;

[0033] [Fig.5] [Fig.5] illustrates the method of manufacturing a semiconductor substrate;

[0034] [Fig.6] [Fig.6] illustrates a method of manufacturing an active layer;

[0035] [Fig.7] [Fig.7] illustrates a method of forming a semiconductor device three-dimensional integrated;

[0036] [Fig.8] [Fig.8] illustrates the method of manufacturing an active layer;

[0037] [Fig.9] [Fig.9] illustrates the method of forming a semiconductor device three-dimensional integrated;

[0038] [Fig. 10] [Fig. 10] illustrates the method of forming a three-dimensional integrated semiconductor device;

[0039] [Fig. 11]] [Fig. 11] illustrates the method of forming a three-dimensional integrated semiconductor device;

[0040] [Fig. 12] [Fig. 12] illustrates the method of manufacturing an active layer; and

[0041] [Fig. 13] [Fig. 13] illustrates conventional integration methods for the three-dimensional semiconductor devices.

[0042] DETAILED DESCRIPTION OF A SPECIFIC EMBODIMENT OF THE INVENTION

[0043] Embodiment of the invention

[0044] Semiconductor substrate structure and manufacturing method

[0045] A first embodiment of the invention is explained with the aid of Figures 1 to 3 and [Fig.5], which show the steps of manufacturing a semiconductor substrate designed to allow laser separation of a layer of active material.

[0046] [Fig.3] illustrates the semiconductor substrate Sub, which comprises: a support substrate Sprt; an inorganic layer Inorg on the silicon substrate, the inorganic layer being formed from a material selected from TiN, Al2O3, TiO2, WO3, La2O3 and LaA103; an electrically insulating layer Ins on the inorganic layer; and the ActMat active material layer on the electrically insulating layer, the active material layer preferably being monocrystalline. The organic layer is designed to be sufficiently absorbent with respect to infrared irradiation, such as laser irradiation, to efficiently achieve laser separation of the active material layer, as such or processed as an active layer, from the supporting substrate.

[0047] Figures 1 to 3 and 5 illustrate a method 100 for manufacturing the semiconductor substrate Sub, which comprises the manufacturing steps 110 to 190.

[0048] First, in step 110, an active material donor is provided. The active material donor is selected from substrates, such as wafers, of Si, SiGe, GaAs, SiC, GaN and PZT (lead zirconate titanate), which may have a single-crystal structure.

[0049] During an ion implantation step 130, a light ion species, hydrogen H+ or helium He+, is introduced into the active material donor substrate Don through an upper surface T.Surf of this donor substrate Don so as to form a weakening plane Frgl inside the donor substrate Don. The weakening plane is substantially parallel to the upper surface T.Surf, as illustrated in [Fig.l]. The volume of the donor substrate Don comprised between the upper surface T.Surf and the weakening plane Frgl defines the layer of active material ActMat. In a subsequent step, this layer will be detached from the rest of the donor substrate Don by Smart Cut™ technology to be transferred onto a support structure.

[0050] The introduction of ions can correspond to the implantation of hydrogen, i.e. the ion bombardment of the T.Surf face of the donor substrate Don with hydrogen ions, as illustrated by [Fig.l]. Generally, the type, dose and energy of the implanted species are chosen according to the thickness of the layer to be transferred and the physicochemical properties of the donor substrate Don. These parameters can be adjusted to define a layer of active material having a thickness between 5 nm and 2 pm.

[0051] In parallel with steps 110 and 130, a support substrate Sprt is provided in a step 120.

[0052] During a step 140 of forming a stack, the inorganic layer Inorg and the electrically insulating layer Ins are formed, in this order, on a surface of the support substrate Sprt, forming a first stack Stck comprising, in this order, the support substrate Sprt, the inorganic layer Inorg and the insulating layer Ins.

[0053] The inorganic layer Inorg is preferably formed from a material chosen from A12O3, TiO2, WO3, La2O3, LaA103 and TiN and so as to have a thickness of between 20 nm and 2 pm. These materials have excellent compatibility with most semiconductor processes used in industry, allowing thus providing a quasi-universal substrate for a very wide range of already developed applications as well as for potential applications. TiN is preferably chosen for its even higher overall compatibility with these processes and with the laser separation operation which consists of detaching the active material layer from the supporting substrate. The inorganic Inorg layer can be formed by ALD (Atomic Layer Deposition), more particularly by PE-ALD (Plasma Enhanced Atomic Layer Deposition), PE-CVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or by PCD (Photochemical Deposition), for example.

[0054] The semiconductor manufacturing processes mentioned in the above paragraph should be understood as conventional processes used in the semiconductor industry to manufacture microchips from raw materials, in particular semiconductor materials, such as FEOL (Front End Of Line), BEOL (Back End Of Line), SoL (Sea of ​​Leads), RDL (Redistribution Layer) or TSV (Through Silicon Vias) manufacturing, for example. Indeed, some or more of these processes could be applied to the active material layer before the layer is detached from the supporting substrate, hence the need for the inorganic layer to be compatible with these processes.

[0055] The insulating layer Ins preferably comprises silicon oxide or silicon nitride and has a thickness of between 10 nm and 1 μm. The insulating layer Ins may be formed by LPCVD (Low Pressure Chemical Vapor Deposition) or (Plasma Enhanced Chemical Vapor Deposition), for example. Silicon oxide is a material that will promote the bonding between the donor substrate Don and the first stack Stck.

[0056] Then, during a bonding step 150, the upper surface T.Surf of the donor substrate Don is brought into intimate contact with the free surface F.Surf of the insulating layer Ins, thus forming a molecular adhesion and / or an electrostatic bond between the donor substrate and the insulating layer, as mentioned for example in the French patent application published under number 2,914,492. The surfaces brought into intimate contact can be prepared by cleaning, brushing, drying, polishing or plasma activation, as is known in the art.

[0057] As is known, during a molecular adhesion process, the exposed surfaces of the insulating layer and the donor substrate, which are perfectly clean, flat and smooth, are brought into intimate contact to promote electrostatic bonding or the development of molecular bonds, for example van der Waals or covalent bonds. The assembly of the two bodies is then obtained without the use of an adhesive. The bonding may comprise the application of a low-temperature heat treatment (for example between 50 and 300°C, typically 100°C) to cure the crystal defects in the donor substrate and strengthen the bonding energy sufficiently to allow for a possible subsequent thinning step or other processing.

[0058] Then, during a fractionation step 170, the active material donor substrate Don is fractionated, or split, at the weakening plane Frgl so as to leave the active material layer ActMat attached to the support substrate Sprt via the insulating layer Ins and the inorganic layer Inorg. The stack obtained after fractionation is the semiconductor substrate Sub illustrated in [Fig.3].

[0059] More precisely, after the bonding step, the layer of active material is detached from the rest of the donor substrate by fracture at the weakening plane Frgl and therefore transferred to the support Sprt, as illustrated by [Fig. 3] which shows the substrate Sub formed by the assembly of the first stack Stck with the layer of active material ActMat. This detachment step may also consist of applying a heat treatment at a temperature between 350°C and 1000°C to detach the layer of active material from the donor substrate and complete its transfer to the first stack. As an alternative or in addition to the heat treatment, this step may consist of applying a blade or a jet of gaseous or liquid fluid, or any other mechanical force on the weakening plane Frgl.

[0060] After step 170, which produces the Sub structure illustrated by [Fig. 3], a stabilizing heat treatment may optionally be applied to the Strc structure during a post-fragmentation step S190. The stabilizing heat treatment makes it possible to heal the crystalline defects of the active material layer and to consolidate the bond between this active material layer and the insulator, for example by bringing the Sub substrate to a temperature between 300°C and 600°C for a period of between 30 minutes and 10 hours. This heat treatment is preferably carried out by exposing the free face of the active material layer to a neutral gas atmosphere.

[0061] The post-fission step 190 also preferably comprises a step of smoothing the free layer of the active material layer, for example by CMP (Chemical Mechanical Polishing) and / or by wet etching. At this stage, the semiconductor substrate Sub can be ready for any treatment envisaged by the user of the substrate.

[0062] The semiconductor substrate may also be sent to the user without the smoothing step having been carried out, in order to allow this user to carry out a smoothing step of his choice. Indeed, the semiconductor substrate Sub is intended to be used by various actors, and the manufacturing unit where it was manufactured will generally be different from the manufacturing unit where the layer of active material will be processed to form a functional semiconductor device or a part of such a device.

[0063] Transmission for active layer processing

[0064] [Fig. 12] illustrates foreseeable situations in which semiconductor substrates Sub obtained as described above are manufactured in a first manufacturing unit Ul, are packaged in a packaging box CBox and sent to a second manufacturing unit U2 where the layers of active material ActMat of these semiconductor substrates Sub are processed to form the active layer ActLay, and are possibly integrated into semiconductor packages Pack.

[0065] During the operation of sending from U1 to U2, in addition to the substrates themselves, information Inf relating to the intended use of the substrates is transmitted to the manufacturing unit U2. More precisely, the information Inf may be representative of the fact that the substrates must be subjected to a light irradiation treatment, such as an infrared irradiation treatment by an infrared laser IR, in order to detach the active material layer from the rest of the substrate Sub. It should be understood here that the detachment process applies to the active material layer ActMat as such or to the active material layer after it has been transformed into an active layer ActLay, as will be seen later.

[0066] As illustrated in (A) of [Fig. 10], in a sending process SendO, the information Inf can take the form of a physical information notice directly attached to the box Cbox. The physical information notice can be sent separately by the manufacturing unit U1 to the manufacturing unit U2.

[0067] Alternatively, as illustrated in (B) of [Fig. 10], the information Inf may take a dematerialized form such as an electronic message or a file sent to the second manufacturing unit U2 in a sending process Send2 separately from the semiconductor substrates Sub which may be sent to the second manufacturing unit U2 in a first process Sendl.

[0068] The starting and destination points of the semiconductor substrates must be respectively the first and second manufacturing unit, where the facilities for processing the semiconductor substrates are located. However, the starting and destination points of the information may, in practice, be office buildings that manage these manufacturing units or are linked to them. In this document, for the sake of concise explanations, it is understood that these office buildings are considered part of the manufacturing units, even though they may be physically located at other locations than the manufacturing facilities that process the semiconductor substrate.

[0069] Active Layer Processing - Generic

[0070] Figures 4 and 6 illustrate a generic processing method 200 for obtaining an active ActLay layer from the semiconductor substrate Sub described above and illustrated by [Fig.3].

[0071] In a processing step 210, the active material layer ActMat is processed to form the active layer ActLay while the active material layer is still attached to the supporting substrate Sprt via the insulating layer Ins and the inorganic layer Inorg. The processes applied to the active material layer ActMat may be any one or a combination of conventional processes used in the semiconductor industry, such as FEOL, BEOL, SoL, RDL or TSV manufacturing, which may involve manufacturing techniques by adding or subtracting material, doping, surface treatment, etc. The active layer is intended to be integrated into a semiconductor device such as a memory, a MEMS (Micro Electro Mechanical System) or a sensor.

[0072] Then, during a separation step 230, the inorganic layer (Inorg) is irradiated with infrared radiation IR which can be emitted by a laser, so that the active layer ActLay detaches from the support at the level of the inorganic layer, as illustrated by [Fig.4]. The irradiation preferably occurs through the Sprt substrate, which is chosen to be sufficiently transparent to the wavelength of the irradiation so that the latter reaches and degrades the inorganic layer.

[0073] After the separation step 230, some or all of the insulating layer Ins and the inorganic layer Inorg may still remain attached to the active layer ActLay. During a cleaning step 250, these remains of the insulating layer Ins and the inorganic layer Inorg are removed by selective dry and / or wet etching so as to leave the active layer ActLay bare, as illustrated in [Fig.4].

[0074] In the example illustrated by [Fig.4], the active layer is simply detached from the support substrate Sprt. However, the active layer may be transferred to a permanent support substrate, to a temporary substrate such as a cutting tape for further handling and / or processing, or may be directly integrated into a semiconductor device as described below.

[0075] Active Layer Processing - Integration

[0076] Figures 7 and 8 illustrate a processing method 300 for obtaining a completed ActLay' active layer from the semiconductor substrate Sub described above and illustrated by [Fig.3], and then integrating one or more of these ActLay' active layers into a semiconductor device SC.

[0077] In a processing step 310 similar to the process 210 described previously, the ActMat active material layer is processed so as to form the ActLay active layer while the active material layer is still part of the semiconductor substrate Sub. The processes applied to the ActMat active material layer can be any one or a combination of conventional processes used in the semiconductor industry, such as FEOL, BEOL, SoL, RDL or TSV manufacturing, which may involve manufacturing techniques by addition or subtraction of material, doping, surface treatment, etc. The active layer is intended to be integrated into a semiconductor device, such as a memory, a MEMS (Micro Electro Mechanical System) or a sensor. The ActLay active layer has been structured so as to be able to receive, process and / or transmit electrical signals. For this purpose, it has electrical connection pads on its surface.

[0078] During a bonding step 330, in order to integrate the active layer on a semiconductor device, the connection pads are positioned and fixed to corresponding connection pads located on this semiconductor device. The result of this step is illustrated in (A) of [Fig.8].

[0079] The connection is preferably made by hybrid bonding, which allows dielectric layers to be bonded to dielectric layers and electrically conductive layers to dielectric conductive layers to be bonded simultaneously. Such hybrid bonding makes it possible to obtain highly integrated devices, with shortened electrical connections: the active layers bonded together are in direct contact with each other. Reference may be made to [Fig. 11] and the corresponding passage of this description.

[0080] In a separation step 350, illustrated in (B) of [Fig.8], the support substrate Sprt is separated from the active layer ActLay at the inorganic layer Inorg by light irradiation. Reference may be made to step 230 for further details, as steps 230 and 350 are identical in principle and implementation, with the actual parameters depending on the specific device being manufactured.

[0081] In a cleaning step 370, similar to cleaning step 250, the portions of the insulating layer Ins and the inorganic layer Inorg remaining attached to the active material layer ActMat are removed, as illustrated in (C) of [Fig.8], so that the active material layer can be further processed to form a functional layer of a semiconductor device.

[0082] In a processing step 390, the ActLay active layer is processed to form a completed ActLay' active layer, as illustrated in (D) of [Fig.8]. The processes applied to the ActLay active layer may be any one or a combination of conventional processes used in the semiconductor industry. In this example, the process is intended to provide the electrical connection between the two opposite faces of the active layer. In a specific example, this is to enable a functional connection between the Cnt control layer of the Cnt substrate and one or other of the ActLay active layers that may be stacked on the completed ActLay' active layer.

[0083] As indicated by the number 395 in [Fig.7], the sequence of manufacturing steps 310-330-350-370-390 can be repeated on the same part of the substrate Tmp so as to stack a plurality of completed active layers ActLay' on top of each other, each being connected to the others and to the control layer Cnt of the substrate Tmp.

[0084] Three-dimensional integrated semiconductor device

[0085] Figures 9-11 illustrate a method of forming a three-dimensional integrated semiconductor device based on the method 300 discussed above and illustrated by Figures 7 and 8.

[0086] As illustrated in [Fig. 8], an active layer ActLay' can be formed by bonding and processing an active layer on a substrate equipped with a control layer Cnt. The same process can be repeated to successively bond several completed active layers ActLay' on top of each other so as to obtain a first stack StckLay of interconnected active layers ActLay (or ActLay') on a carrier substrate Sub, as illustrated in [Fig. 9]. In practice, the sequence of manufacturing steps 310-330-350-370-390 can be repeated on the same portion of the same receiving substrate so as to form a first stack StckLay consisting of a plurality of stacked active layers ActLay. The active layers ActLay to be stacked on a previously obtained active layer ActLay' are positioned and bonded thereon by means of a first handling apparatus.

[0087] In principle, an arbitrary number of active layers can be stacked in this manner. However, the first handling apparatus must be capable of performing both (i) precise positioning (also referred to as "alignment" of a wafer or an integrated circuit (referred to as a "die" in the semiconductor industry) and (ii) hybrid bonding to ensure a functional and efficient electrical connection between the last-added ActLay active layer and the previously obtained completed ActLay active layer.

[0088] As illustrated in [Fig.l 1], in this situation, a hybrid bonding process involves the precise alignment of the respective conductive pads Pad of an ActLay active layer and a completed ActLay' active layer. These pads are embedded in the respective dielectric layers Diel. At an initial stage of the bonding process, the respective dielectric layers are brought into direct contact and bonded to each other at room temperature. Then, a heat treatment is applied and metallic diffusion occurs between the pads, forming electrical connections between the ActLay active layer and the completed ActLay' active layer.

[0089] The problem is that the available devices capable of performing such a process, called hybrid gluing equipment, have only limited handling capacity, more precisely limited vertical capacity. As long as the specifications of the integrated device do not require too many active layers to be stacked, the available devices can efficiently position and bond the elements concerned. However, recent applications require the stacking of such a number of active layers that the available devices are not sufficient.

[0090] It is therefore necessary to circumvent this height limitation of currently available devices. This is an application of the process described using Figures 7 to 10.

[0091] The process 300 implemented n times makes it possible to integrate and connect n active layers ActLay' on a substrate Tmp, as illustrated by the upper part of [Fig.9], n being a positive integer. The lower parts of Figures 9 and 10 illustrate a process developed to overcome the limited vertical capacity.

[0092] During a cutting step 410 following the n implementations of the method 300, the first stack StckLay comprising a plurality of n terminated active layers ActLay' is cut so as to form a plurality of semiconductor elements D.Elmnt each comprising an elementary portion Elmnt of the first stack StckLay, as illustrated by [Fig.9]. In [Fig.9], the elementary portions Elmnt are shown still attached to their respective portions of the substrate Tmp, but it is understood that they can also be detached from the substrate portions by any conventional method deemed adequate by the practitioner.

[0093] During an integration step 430, a second stack StckEll of a first plurality of elementary portions Elmnt and a third stack StckE12 of a second plurality of elementary portions Elmnt are integrated on a control substrate ContSub, which can be equipped with a connection pad (not shown in [Fig.10]).

[0094] Two adjacent stacked elementary elements Elmnt of a second stack StckEll and a third stack StckE12 given are connected to each other via first electrically conductive balls uBimpl, the second stack StckEll and the third stack StckE12 being each connected to the control substrate ContSub via respective second electrically conductive balls uBimp2. In English terminology, these electrically conductive balls are referred to as "solder balls".

[0095] When forming the second stack StckEll and the third stack StckE12, the elementary portions Elmnt are positioned on top of each other by means of a second handling apparatus distinct from the first positioning apparatus. This handling apparatus is designed to establish electrical connections between the adjacent stacked elements using the electrically conductive balls in a well-known manner such as the so-called "flip-chip" bonding process. The corresponding handling apparatus is referred to as equipment flip-chip bonding. Devices of this type can have a vertical capacity greater than that of the first available handling device. Thus, the height limitation mentioned above can be overcome.

[0096] Other advantages of this method include faster and more economical implementation than other transfer methods for an active material layer or an equivalent active layer.

[0097] [Fig. 13] illustrates generic conventional approaches for integrating three-dimensional functional semiconductor layers on top of each other. These approaches include forming (i) a first stack comprising a first substrate Subi, a first functional layer Func.Layl and a first oxide layer Oxl; (ii) a second stack comprising a second substrate Sub2, a buried oxide layer BOX, a second functional layer Func.Lay2 and a second oxide layer 0x2; (iii) joining the two stacks through their respective oxide layers Oxl and 0x2; and (iv) removing the second substrate Sub2 and the layer BOX.

[0098] Step (iv) is particularly long (generally several hours) and requires a long and expensive treatment such as chemical-mechanical polishing and wet and / or dry etching to thin and remove the second substrate Sub2 and the BOX layer.

[0099] The conventional approach of [Fig. 13] also generally implements a hybrid oxide-copper bond, and not just an oxide-oxide bond as described above.

[0100] In contrast, in the present invention, step (iv) is replaced by a simple and rapid light irradiation. Furthermore, the cleaning of the materials remaining attached to the functional layer (ActLay), which concerns thinner layers of materials than in the conventional methods collectively illustrated by [Fig. 13], is also easier.

[0101] Furthermore, the method according to the invention makes it possible to transfer and integrate very thin layers of functional material (ActMat) to form the active layer. For example, it is possible to form and transfer a layer of active material of less than 1 micrometer.

[0102] A typical application that could benefit from these advantages is the manufacture of digital memories. For such applications, it can be considered that the active layers must have a thickness of 0.8 micrometers, with each completed active layer having a thickness of, typically, 5 micrometers. Stacks of 8 active layers, representing a thickness of 40 micrometers, are already in production. However, it is expected that several dozen layers, 64 for example, will have to be stacked in the coming years, which will be limited by the vertical constraints of the equipment. hybrid bonding. The process described in this document overcomes the limitations imposed by hybrid bonding equipment.

[0103] The figures in this document are not necessarily to scale. Some features and components may be shown exaggerated relative to other components or in a somewhat schematic form, and some details of conventional elements may not be shown, for the sake of clarity and conciseness.

[0104] Of course, the invention is not limited to the embodiment described, and other embodiments may be used without departing from the scope of the invention as defined by the claims.

Claims

Claims

1. Semiconductor substrate (Sub) designed to allow laser separation of an active material layer (ActMat), comprising: - a support substrate (Sprt); - an inorganic layer (Inorg) on ​​the support substrate, the inorganic layer being formed from a material selected from A12O3, TiO2, WO3, La2O3, LaA103 and TiN; - an electrically insulating layer (Ins) on the inorganic layer; and - the active material layer (ActMat) on the electrically insulating layer, the active material layer being monocrystalline.

2. Semiconductor substrate (Sub) according to claim 1, wherein: - the support substrate (Sprt) is formed of monocrystalline silicon; - the inorganic layer (Inorg) has a thickness of between 10 nm and 2 pm; - the insulating layer (Ins) comprises silicon oxide and has a thickness of between 10 nm and 1 pm; and - the active material layer (ActMat) is selected from Si, SiGe, GaAs, SiC, GaN and PZT and has a thickness of between 5 nm and 2 pm.

3. Method (100) for manufacturing the semiconductor substrate (Sub) according to claim 1 or 2, comprising the following steps: - implanting (130) a light species (H+) of ion through an upper surface (T.Surf) of an active material donor substrate (Don) so as to form a weakening plane (Frgl) inside the active material donor substrate (Don); - forming (140), in this order, the inorganic layer (Inorg) and the electrically insulating layer (Ins) on a surface of a support substrate (Sprt); - bonding (150) the upper surface (T.Surf) of the active material donor substrate (Don) to a free surface (F.Surf) of the insulating layer (Ins); and - splitting (170) the donor substrate (Don) of active material at the level of the weakening plane (Frgl) so as to leave the layer of active material (ActMat) fixed to the support substrate (Sprt) by through the insulating layer (Ins) and the inorganic layer (Inorg).

4. A method (200) of manufacturing an active layer (ActLay) for a semiconductor device, comprising implementing the method (100) of manufacturing the semiconductor substrate (Sub) according to claim 3, further comprising the steps of: - treating (210) the active material layer (ActMat) so as to form the active layer (ActLay); and - separating (230) the active layer (ActLay) from the support substrate (Sprt) at the inorganic layer (Inorg) by irradiating the inorganic layer with infrared radiation (IR).

5. A method (300) of manufacturing an active layer (ActLay) comprising implementing the method (100) of manufacturing the semiconductor substrate (Sub) according to claim 3, further comprising the steps of: - treating (310) the active material layer (ActMat) so as to form the active layer (ActLay); - positioning and fixing (330) the connection pads (Pad) of the active layer (ActLay) to the connection pads (Pad) of a receiving substrate (Tmp); - separating (350) the support substrate (Sprt) from the active layer (ActLay) at the inorganic layer (Inorg) by irradiating the inorganic layer with infrared radiation (IR); - cleaning (370) a surface of the active material layer (ActMat) opposite the receiving substrate (Tmp) after separation of the support substrate (Sprt); and - after the cleaning step, treating (390) the layer of active material so as to form a completed active layer (ActLay1).

6. Method (200, 300) for manufacturing an active layer (ActLay) comprising implementing the method (100) for manufacturing the semiconductor substrate (Sub) according to claim 3 in a first manufacturing unit (U1), further comprising the steps of: - sending (SndO, Sndl) the semiconductor substrate (Sub) to a second manufacturing unit (U2); and - sending (SndO, Snd2) to said second manufacturing unit (U2) information representative of the fact that the active material layer (ActMat) of the semiconductor substrate (Sub) must be separated of the support substrate (Sprt) in a separation step involving irradiation of the inorganic layer (Inorg) with infrared radiation (IR).

7. A method (200) of manufacturing an active layer (ActLay) for a semiconductor device, comprising implementing the method (200, 300) of manufacturing the active layer (ActLay) according to claim 6, further comprising the steps of: - processing (210) the active material layer (ActMat) so as to form the active layer (ActLay); and - separating (230) the active layer (ActLay) from the support substrate (Sprt) at the inorganic layer (Inorg) by irradiating the inorganic layer with infrared radiation (IR).

8. A method (300) of manufacturing an active layer (ActLay) comprising implementing the method (200, 300) of manufacturing the active layer (ActLay) according to claim 6, further comprising the steps of: - treating (310) the active material layer (ActMat) so as to form the active layer (ActLay); - positioning and fixing (330) the connection pads (Pad) of the active layer (ActLay) to the connection pads (Pad) of a receiving substrate (Tmp); - separating (350) the support substrate (Sprt) from the active layer (ActLay) at the inorganic layer (Inorg) by irradiating the inorganic layer with infrared radiation (IR); - cleaning (370) a surface of the active material layer (ActMat) opposite the receiving substrate (Tmp) after separation from the support substrate (Sprt); and - after the cleaning step, treating (390) the layer of active material so as to form a completed active layer (ActLay1).

9. A method according to any one of claims 4 to 8 for manufacturing an active layer (ActLay), wherein the active layer comprises a layer of a semiconductor material with a thickness of less than 1 micrometer.

10. A method of forming a three-dimensional integrated semiconductor device (3D SC) comprising repeating (380) the method (300) according to claim 8 or 9 on the same portion of the same receiving substrate so as to form a first stack (StckLay) consisting of a plurality of stacked active layers (ActLay), one of the layers of active material (ActMAt) intended to be stacked on a previously obtained active layer (AcLay) being positioned thereon by means of a first handling device.

11. The method according to claim 10, further comprising the steps of: - cutting (410) the first stack so as to form a plurality of semiconductor elements (D.Elmnt) each comprising an elementary part (Elmnt) of the first stack (StckLay); - on a control substrate (ContSub), forming (430) a second stack (StckEll) of a plurality of elementary parts (Elmnt), two adjacent stacked elementary elements (Elmnt) of the second stack (StckEll) being connected to each other by first electrically conductive balls (uBimpl), the second stack (StckEll) being connected to the control substrate (ContSub) by second electrically conductive balls (uBimp2), wherein, when forming the second stack (StckEll), the elementary portions (Elmnt) are positioned one on top of the other by means of a second handling device distinct from the first handling device.

12. The method of claim 11, wherein the first handling apparatus and the second handling apparatus have a first height limit and a second height limit for the objects they can position, respectively, the first height limit being smaller than the second height limit.

13. The method of claim 11 or 12, wherein the first handling apparatus is hybrid bonding equipment and the second handling apparatus is flip-chip bonding equipment.

14. The method according to one of claims 10 to 13, in which the three-dimensional integrated semiconductor device is a memory device, each elementary part (Elmnt) of the first stack (StckLay) being a digital memory element.

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