Monolithic device including a transistor and a capacitor cointegrated on a diamond-based substrate, and method of manufacturing such a device

Abstract

The invention relates to a monolithic device (200) including a field effect transistor (100) and at least one capacitor (150), and comprising: - a support substrate (50), - a stack comprising a first (10) and a second (20) conductive layer made of monocrystalline diamond, and an intermediate layer (30) made of monocrystalline diamond, electrically insulating, interposed between the first and second conductive layers, which respectively form a first (11) and a second (21) contact of the capacitor (150), - an active layer (40) made of monocrystalline diamond, in which the conduction channel (41) of the transistor (100) is formed, the active layer (40) extending parallel to a main plane (x,y) and being arranged on the first conductive layer (10). The second conductive layer (20) has an epitaxial interface (62) with the active layer (40), and forms a drain electrode (23) or source electrode of the transistor (100). Figure 1a

Description

Title of the invention: Monolithic device including a transistor and a capacitor cointegrated on a diamond-based substrate, and method of manufacturing such a device FIELD OF THE INVENTION

[0001] The present invention relates to the field of microelectronics and semiconductors. In particular, the invention relates to a device comprising a transistor and at least one capacitor, monolithically integrated on a diamond-based substrate, said device being suitable for power applications. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Monocrystalline diamond is a semiconductor with a very wide band gap. It has properties and characteristics that theoretically allow the production of power components, such as diodes, transistors and capacitors, with performances not previously achieved with other semiconductors. A transistor made on diamond makes it possible to drastically reduce switching losses, which allows a power converter to operate at very high frequencies (typically beyond one MHz). At these frequencies, the voltage switching edges are very steep and each switching at the terminals of the transistor generates an overvoltage of several hundred, or even several thousand volts; this requires an oversizing of the transistor voltage compared to the initial specification of the converter. SUBJECT OF THE INVENTION

[0003] The present invention makes it possible to limit this overvoltage at the terminals of the transistor during switching by adding one or more high-voltage capacitors. The invention relates to a monolithic device including at least one transistor and at least one capacitor, cointegrated on diamond. The invention also relates to a method for monolithic integration of a transistor and at least one capacitor on a diamond-based substrate. BRIEF DESCRIPTION OF THE INVENTION

[0004] The present invention relates to a monolithic device including a field effect transistor and at least one capacitor (150). The monolithic device comprises:

[0005] - a support substrate,

[0006] - a stack comprising a first conductive layer and a second conductive layer of monocrystalline diamond comprising p-type dopants, and an intermediate layer of monocrystalline diamond, electrically insulating, intercalated between the first conductive layer and the second conductive layer, the first conductive layer being arranged on the support substrate, the first conductive layer and the second conductive layer respectively forming a first and a second contact of the capacitor,

[0007] - an active layer of monocrystalline diamond comprising p-type dopants, in which the conduction channel of the transistor is formed, the active layer extending parallel to a main plane and being arranged on the first conductive layer.

[0008] The second conductive layer has an epitaxial interface with the active layer, and forms a drain or source electrode of the transistor.

[0009] According to advantageous characteristics of the invention, taken alone or in any feasible combination: • the active layer has a boron concentration between 1015 / cm3 and 1019 / cm3; • the first conductive layer and the second conductive layer have a boron concentration greater than 1019 / cm3; • the intermediate layer has a nitrogen or phosphorus concentration between 1014 / cm3 and 1021 / cm3; • the first conductive layer and the second conductive layer have a thickness, along an axis normal to the main plane, of between 5 nm and 50 qm, preferably between 50 nm and 1 qm; • the intermediate layer has a thickness, along an axis normal to the main plane, of between 10 nm and 2 mm, preferably between 500 nm and 50 pm; • the active layer has a thickness, along an axis normal to the main plane, of between 100 nm and 20 pm; • the support substrate has a resistivity greater than 10 kohm.cm; • a remote contact from the source or drain electrode is formed opposite back of the support substrate, and the support substrate has a resistivity of less than 50 mohm.cm; • the capacitor is connected in parallel with the transistor; • the support substrate is made of monocrystalline diamond or comprises a surface film of monocrystalline diamond, and an epitaxial interface is defined between said support substrate and the first conductive layer; • a bonding interface is defined between the support substrate and the first conductive layer; • the support substrate comprises monocrystalline or polycrystalline diamond, and / or monocrystalline or polycrystalline silicon carbide, and / or a film adjacent to the bonding interface.

[0010] The invention also relates to a method of manufacturing a monolithic device as above, comprising the following steps:

[0011] a) providing the support substrate,

[0012] b) the formation of the first conductive layer on the support substrate,

[0013] c) forming the intermediate layer on a portion of the first layer driver,

[0014] d) forming the active layer on another part of the first conductive layer,

[0015] e) the formation of the second conductive layer on the active layer and on the intermediate layer, by epitaxial growth,

[0016] f) structuring the second conductive layer in the main plane, to form the capacitor, adjacent to the transistor, and defining the drain or source electrode of the transistor and the second contact of the capacitor in said second conductive layer.

[0017] According to advantageous characteristics of the invention, taken alone or in any feasible combination: • the source and the first contact, or the drain and the first contact are electrically connected by continuity of the first conductive layer; • the support substrate is made of monocrystalline diamond or comprises a surface film of monocrystalline diamond, and step b) is carried out by epitaxial growth, in particular by implementing a microwave plasma-assisted chemical vapor deposition technique; • step c) is carried out by epitaxial growth, in particular by implementing a microwave plasma-assisted chemical vapor deposition technique; • step b) is carried out by transferring the first conductive layer onto the support substrate; • step b) includes the following sub-steps: - the implantation of light species of the hydrogen, helium type or a combination of these two species in a donor substrate, to define a buried fragile plane, - assembly of the donor substrate on the support substrate via a direct bonding interface, - separation along the buried fragile plane leading to the transfer of a useful layer, originating from the donor substrate and intended to form the first conductive layer, onto the support substrate; • the useful layer has a thickness of less than 2 pm at the end of the separation and a subsequent sub-step of growth by epitaxy is carried out to increase this thickness. Brief description of the drawings

[0018] Other characteristics and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which:

[0019] [Fig. la]

[0020] [Fig.lb]

[0021] [Fig. the]

[0022] [Fig.ld] Figures 1a, 1b, 1c and 1d show embodiments of a monolithic device according to the invention,

[0023] [Fig.2a]

[0024] [Fig.2b]

[0025] [Fig.2c]

[0026] [Fig.2d]

[0027] [Fig.2e]

[0028] [Fig.2f]

[0029] [Fig.2f'] Figures 2a, 2b, 2c, 2d, 2e, 2f and 2f show a first mode of implementation implementing the manufacturing method, in accordance with the present invention;

[0030] [Fig.3a]

[0031] [Fig.3b]

[0032] [Fig.3b']

[0033] [Fig.3b”]

[0034] [Fig.3b'”]

[0035] [Fig.3c]

[0036] [Fig.3d]

[0037] [Fig.3e]

[0038] [Fig.3f]

[0039] [Fig.3f'] Figures 3a, 3b, 3b', 3b", 3b'", 3c, 3d, 3e, 3f and 3f' present a second mode of implementation of the manufacturing method, in accordance with the invention.

[0040] The figures are schematic representations which, for the sake of readability, are not to scale. In particular, the thicknesses of the layers along the z axis are not to scale relative to the lateral dimensions along the x and y axes.

[0041] The same references in the figures or in the description may be used for elements of the same nature. DETAILED DESCRIPTION OF THE INVENTION

[0042] The invention relates to a monolithic device 200 including at least one field effect transistor 100 (JFET, MESFET, MOSFET, etc.) and at least one capacitor 150, said components being monolithically cointegrated on a diamond-based substrate ([Fig.la], [Fig.lb], [Fig.le], [Fig.ld]).

[0043] The device 200 comprises an active layer 40 made of monocrystalline diamond comprising p-type dopants, and in which the conduction channel 41 of the transistor 100 is formed. The active layer 40 (as well as the other layers and stack described later) extends parallel to a main plane (x,y) and has a thickness along a z axis normal to said plane.

[0044] Preferably, the active layer 40 has a boron concentration of between 1015 / cm3 and 1019 / cm3; its thickness is typically between 100 nm and 20 pm, preferably between 100 nm and 5 pm.

[0045] The device 200 also includes a monocrystalline diamond stack comprising a first conductive layer 10, a second conductive layer 20 and an electrically insulating intermediate layer 30, interposed between the first conductive layer 10 and the second conductive layer 20. The first conductive layer 10 and the second conductive layer 20 comprise p-type dopants and have a resistivity typically between 1 mohm.cm and 10 kohm.cm, advantageously less than or equal to 1 ohm.cm, less than or equal to 100 mohm.cm, or even less than or equal to 10 mohm.cm. Preferably, the first conductive layer 10 and the second conductive layer 20 therefore have a boron concentration typically greater than 1019 / cm3. They respectively form a first 11 and a second 21 contact of the capacitor 150.

[0046] The intermediate layer 30 advantageously comprises deep n-type dopants producing energy levels located more than 0.4 eV from the conduction band of the diamond. The intermediate layer 30 may have a nitrogen or phosphorus concentration of between 1014 / cm3 and 1021 / cm3. These species constitute deep donors for the diamond and will give the intermediate layer 30 a resistivity greater than 10 kohm.cm.

[0047] The first 10 and second 20 conductive layers typically have a thickness of between 5 nm and 50 μm, preferably between 50 nm and 1 μm. The thickness of the intermediate layer 30 may be between 10 nm and 2 mm, preferably between 500 nm and 50 μm.

[0048] In the monolithic device 200, the active layer 40 and the intermediate layer 30 are adjacent in the main plane (x,y), each arranged on a distinct part of the first conductive layer 10.

[0049] The second conductive layer 20 comprises an epitaxial interface 62 with the active layer 40 and with the intermediate layer 30. The second conductive layer 10 is structured in a plane parallel to the main plane (x,y), so as to form on the one hand a drain electrode 23 of the transistor and on the other hand the second contact 21 of capacitor 150.

[0050] In the same plane parallel to the main plane (x,y), the source electrode 12 and the first contact 11 of the capacitor 150 are defined in the first conductive layer 10.

[0051] The drain 23 and source 12 electrodes of the transistor 100 could of course be interchanged with respect to the illustrations of figures 1a to 1d. The transistor 100 comprises electrodes (12, 23) on its upper face and on its lower face (or on the lower face of the active layer 40), which corresponds to a vertical architecture.

[0052] The capacitor 150 is preferably connected in parallel with the transistor 100. The RC circuit (capacitor 150), mounted in parallel with the switch (transistor 100) protects the terminals of the latter from switching overvoltages.

[0053] For such a parallel assembly of the two components, the source 12 of the transistor 100 and the first contact 11 of the capacitor 150 are electrically connected (FIGS. 1a to 1d). This connection, made possible by the production of a single continuous layer (the first conductive layer 10), is particularly advantageous because it avoids the addition of unfavorable connections in terms of parasitic inductances. Alternatively, if an interruption of the first conductive layer 10 were required given design or integration constraints, a wire connection or a metal interconnection (by producing an additional lithography level involving a passivation layer and metallization) can be envisaged between the source 12 and the first contact 11.

[0054] The drain 23 of the transistor 100 is connected to the second contact 21 of the capacitor 150 (not shown in the figures), either by wire connection or by metal interconnection.

[0055] Alternatively, as previously discussed, the drain electrode could be defined at the lower face of the active layer 40, and be connected to the first contact 11 of the capacitor 150; and the source electrode could be defined at the upper face of the active layer 40, and be connected to the second contact 21.

[0056] As illustrated in Figures 1a, 1b, 1c, 1d, the monolithic device 200 comprises a support substrate 50. The first conductive layer 10 is arranged on the support substrate 50, the intermediate layer 30 is arranged on a portion of the first conductive layer 10, the active layer 40 is arranged on another portion of the first conductive layer 10, and finally the second conductive layer 20 is arranged both on the active layer 40 and on the intermediate layer 30. At least one epitaxial interface 62 is defined between the second conductive layer 20 and the active layer 40. Advantageously, an epitaxial interface 61 is also defined between the active layer 40 and the first conductive layer 10. These very high quality allow excellent electrical contact between the active layer 40 and its electrodes 12,23.

[0057] The second conductive layer 20 is structured in a plane parallel to the main plane (x,y) to form the drain electrode 23 of the transistor 100 and the second contact 21 of the capacitor 150.

[0058] The gate electrode G of the transistor is arranged on an upper face of the active layer 40. According to a possible architecture, the gate G is located around the upper drain electrode 23 (or alternatively the source electrode) and arranged in trenches, in order to be able to control the conduction of the channel 41 over its entire extent between source 12 and drain 23. Other known architectures for vertical transistors could alternatively be implemented.

[0059] The support substrate 50 may comprise one or more materials chosen from monocrystalline or polycrystalline diamond, monocrystalline or polycrystalline silicon carbide, or a dielectric or electrically conductive material. It may have a resistivity chosen from a wide range, typically from a few ohm.cm to 105 kohm.cm. In the variants presented in FIGS. 1a, 1b and 1c, it is recommended that the support substrate 50 be more resistive than the first conductive layer 10, at least by a decade, because it contributes to the voltage resistance of the transistor 100.

[0060] According to a particular variant, illustrated in [Fig.1d], the source electrode 12 of the transistor 100 and / or the first contact 11 of the capacitor 150 may be located on the rear face of the support substrate 50 thanks to the presence of a remote contact 52, for example formed from a metallic material. In this case, the support substrate 50 advantageously has a resistivity less than or equal to 50 mohm.cm.

[0061] This configuration of the device 200 greatly simplifies its manufacturing process and allows efficient monolithic cointegration of one (or more) transistor(s) and one (or more) capacitor(s). The synergy of developing the transistor(s) and the capacitor(s), with a low number of stacked layers due to the multifunctionality of said layers, is also an advantage for obtaining high-quality layers.

[0062] This monolithic integration is also advantageous in that the two components 100,150 benefit from excellent heat transfer linked to the thermal conductivity properties of diamond. In addition, the geographical proximity of the components 100,150 makes it possible to considerably reduce parasitic inductances.

[0063] According to a first embodiment ([Fig.la], [Fig.ld]), an epitaxial interface 65 is defined between the support substrate 50 and the first conductive layer 10. In this case, the support substrate 50 is formed from monocrystalline diamond or comprises a surface film (on the side of its face intended to receive the first conductive layer 10) in monocrystalline diamond, to allow epitaxial growth of said first conductive layer 10, during the development of the monolithic device 200.

[0064] According to a second embodiment ([Fig. 1b], [Fig.1c], [Fig.1d]), a bonding interface 72 is defined between the support substrate 50 and the first conductive layer 10. In this case, the support substrate 50 can be formed from a very wide variety of materials. Advantageously, it comprises a film 51 (dielectric or electrically conductive), adjacent to the bonding interface 72, which makes it possible to guarantee or improve the insulation or vertical conduction between the first conductive layer 10 and the support substrate 50.

[0065] The method for manufacturing the monolithic device 200 will now be described. It comprises a step a) consisting of providing the support substrate 50 ([Fig.2a], [Fig.3a]). As mentioned previously, the support substrate 50 may comprise one or more materials chosen from monocrystalline or polycrystalline diamond, monocrystalline or polycrystalline silicon carbide, or a dielectric or electrically conductive material. The nature of the support substrate 50 may nevertheless be constrained according to the different modes of implementation of the subsequent step b) of the method.

[0066] The support substrate 50 may be in the form of a circular wafer, as is usually the case in the field of microelectronics, with a diameter of 25mm, 50mm, 100mm, 150mm or 200mm. Its thickness is typically between 50 qm and 900 qm, preferably between 200 qm and 700 qm. Of course, the support substrate 50 is not limited to the aforementioned shape and dimensions, and may also be in a square or rectangular form with smaller or larger dimensions.

[0067] It is manufactured by a known technique such as for example HPHT (“High Pressure High Temperature”) or CVD (“Chemical Vapor Deposition”) deposition.

[0068] The method then comprises a step b) corresponding to the formation of the first conductive layer 10 on the support substrate 50, by epitaxial growth, according to a first embodiment ([Fig.2b]), or by thin layer transfer, according to a second embodiment ([Fig.3b], [Fig.3b]', [Fig.3b]”, [Fig.3b]”').

[0069] The first conductive layer 10 made of monocrystalline diamond, intended to form the first contact 11 of the capacitor 150 and the source electrode 12 of the transistor 100, is preferably expected with a boron concentration greater than 1019 / cm3 and a thickness between 5 nm and 50 qm, preferably between 50 nm and 1 qm (as mentioned above in the description of the monolithic device 200).

[0070] In the first embodiment, a support substrate 50 made of monocrystalline diamond is required to allow epitaxial growth of the first layer. conductive 10, itself made of monocrystalline diamond. The support substrate 50 can then be entirely monocrystalline, or consist of a composite structure 50' including a base substrate 501 and a surface film 502 of monocrystalline diamond which will serve as a seed for epitaxial growth ([Fig.2a]). The composite structure 50' offers more flexibility as to the nature of the base substrate 501, which can be polycrystalline or monocrystalline of lower quality or even made of a material different from that of the surface film 502.This type of composite structure 50' can in particular be produced by a thin film transfer process such as the Smart Cut™ process, which involves implantation of light ions into a donor substrate, direct assembly between said donor substrate and the base substrate, and finally, separation along the buried fragile plane formed by the implantation; this leads to the transfer of a surface film 502 from the donor substrate onto the base substrate 501.

[0071] In the remainder of this description, only the case of a solid support substrate 50 will be described and illustrated, for simplification; this obviously does not exclude the option mentioned of a composite structure 50'.

[0072] The epitaxial growth according to the first embodiment of step b) can be carried out by any known technique, preferably by a microwave plasma-enhanced chemical vapor deposition (MW-PECVD) technique. The parameters such as the pressure in the deposition chamber, the temperature, the gases and the microwave power can be defined in the following ranges:

[0073] - Pressure: between 1 mbar and 1 bar;

[0074] - Temperature: between 500 and 1200°C;

[0075] - Power: between 50 Watts and 10 kWatts;

[0076] - Gas: methane, hydrogen, tri-methyl borane, diborane, dioxygen, dinitrogen, argon, phosphine and tri-methyl phosphine.

[0077] An epitaxial interface 65 is created between the first conductive layer 10 and the support substrate 50 ([Fig.2b]). The front face of the support substrate 50, which serves as a seed for the growth of the first conductive layer 10, is chosen so as to provide excellent crystalline quality to said first conductive layer 10.

[0078] In the second embodiment, the choice of the nature of the support substrate 50 is more flexible, because the first conductive layer 10 is transferred via a direct bonding interface 72 onto said substrate 50 and therefore does not require a growth seed. The support substrate 50 is preferably chosen so as to minimize the difference in thermal expansion compared to a monocrystalline diamond substrate.

[0079] To carry out the transfer, the following sub-steps can be implemented. First, an implantation of light species of hydrogen, helium type or a combination of these two species is carried out in a 10D donor substrate in monocrystalline diamond whose characteristics and properties correspond to those expected for the first conductive layer 10. These implanted species will define a buried fragile plane 1, along the principal plane (x,y), in the donor substrate 10D ( [Fig.3b]'). An implantation energy between 10 keV and 250 keV, and an implantation dose between 1.1016 / cm2 and 1.1018 / cm2 can be used to form a buried fragile plane 1 at a depth between 10 nm and 1500 nm, more particularly between a few tens of nm and 1000 nm. Note that a protective layer can be deposited on the donor substrate 10D before ion implantation. Similarly, cleaning sequences can be applied before and / or after the implantation sub-step, so as to eliminate potential particulate, hydrocarbon or metallic contamination.The protective layer can be kept or removed prior to the next sub-step.

[0080] The implanted 10D donor substrate is then assembled, by molecular adhesion, on the support substrate 50 via a direct bonding interface 72 ([Fig.3b]”). A film 51, dielectric or conductive, can be raw or deposited on the support substrate 50 prior to assembly ([Fig.3b]”'). The role of this film 51 can be to facilitate bonding or to improve the adhesion forces of the interface 72; it can also have an electrical function (insulation or vertical conduction) in the targeted device 200.

[0081] In the remainder of the description of the method, the film 51 will not be illustrated for reasons of simplification of the figures.

[0082] The faces to be assembled of the donor substrates 10D and support 50 advantageously undergo cleaning (for example, RCA) and / or surface activations (in particular by N2 or O2 plasma) so as to improve the quality and mechanical strength of the bonding interface 72. Direct bonding by molecular adhesion does not require an adhesive material, since bonds are established at the atomic scale between the assembled surfaces. Several types of bonding by molecular adhesion exist, which differ in particular by their conditions of temperature, pressure, atmosphere or treatments prior to bringing the surfaces into contact. We can cite bonding at room temperature with or without prior activation by plasma of the surfaces to be assembled, bonding by atomic diffusion ("Atomic diffusion bonding" or ADB according to the English terminology), bonding with surface activation ("Surface-activated bonding" or SAB), etc.

[0083] Finally, the sub-step of separation along the buried fragile plane 1 is usually carried out by applying a heat treatment, at a temperature between 400°C and 1200°C. Such a heat treatment induces the development of cavities and microcracks in the buried fragile plane 1, and their pressurization by the light species present in gaseous form, until the propagation of a fracture along said fragile plane 1. Alternatively or jointly, a mechanical stress can be applied to the bonded assembly and in particular at the buried fragile plane 1, so as to propagate or help to mechanically propagate the fracture leading to separation. When the separation is complete, a useful layer 10' is obtained, originating from the donor substrate 10D and intended to form the first conductive layer 10, transferred to the support substrate 50 ([Fig.3b]). The free face of the useful layer 10' is usually rough after separation. Heat treatments or surface treatments can be applied to it to improve the crystalline quality of the layer and its surface roughness, and thus obtain the first conductive layer 10.

[0084] When standard implantation energies are used, the useful layer 10' has a thickness of less than 2 μm at the end of the separation. If the first conductive layer 10 is expected to have a greater thickness, a sub-step of growth by epitaxy (for example by MW-PECVD) can be carried out to increase this thickness.

[0085] Returning to the general description of the method, once the first conductive layer 10 has been formed on the surface of the support substrate 50, a step c) corresponding to the formation of the intermediate layer 30 on a part of the first conductive layer 10 is carried out ([Fig.2c], [Fig.3c]).

[0086] Preferably, the intermediate layer 30 has a nitrogen or phosphorus concentration of between 1014 / cm3 and 1021 / cm3. The thickness of the intermediate layer 30 may be between 10 nm and 2 mm, preferably between 500 nm and 50 qm.

[0087] This step can be carried out by any known technique allowing epitaxial growth, preferably by a MW-PECVD deposition technique. Parameters in the same ranges of values ​​as previously mentioned can be used. Epitaxial growth ensures excellent interface quality between the first conductive layer 10 and the intermediate layer 30.

[0088] The intermediate layer 30 may be formed over the entire surface of the first conductive layer 10, then patterned by applying a lithography level, performing masking and dry etching of the intermediate layer 30 in the region where it is not desired, and finally removing the mask. Alternatively, the intermediate layer 30 may be formed by selective epitaxial growth on the first conductive layer 10, only in the region of interest, masking the region where growth is not required.

[0089] According to an alternative embodiment, the intermediate layer 30 can be transferred onto the first conductive layer 10 by a thin layer transfer technique (in a similar manner to the second embodiment of step b, detailed previously). In this alternative embodiment, the first conductive layer 10 is advantageously formed by epitaxial growth on the support substrate 50, in accordance with the first method of implementing step b) described.

[0090] The following step d) corresponds to the formation of the active layer 40 on another part of the first conductive layer 10 ([Fig.2d], [Fig.3d]).

[0091] The active layer 40 made of monocrystalline diamond, intended to form the conduction channel 41 of the transistor 100, is preferably expected with a boron concentration (p-type dopants) of between 1015 / cm3 and 1019 / cm3, and with a thickness typically of between 100 nm and 20 qm, preferably between 100 nm and 5 qm.

[0092] Like the previous step c), step d) can be carried out by any technique allowing epitaxial growth, advantageously by a MW-PECVD deposition technique. It can consist of selective growth, only on the desired part of the first conductive layer 10 or in growth on a full plate, followed by local etching (as stated with reference to step c).

[0093] Advantageously, the active layer 40 and the intermediate layer 30 together occupy the entire surface, in the main plane (x,y), so as to facilitate the following step e). Note that the thicknesses of the active layer 40 and intermediate layer 30 have been illustrated as identical in the figures for simplification, but they can of course be different.

[0094] At the end of step d), an epitaxial interface 61, of very good quality, is created between the active layer 40 and the first conductive layer 10.

[0095] The following step e) corresponds to the formation of the second conductive layer 20 on the active layer 40 and on the intermediate layer 30 ([Fig.2e], [Fig.3e]).

[0096] Preferably, the second conductive layer 20 has a boron concentration greater than 1019 / cm3 and a thickness of between 5 nm and 50 qm, preferably between 50 nm and 1 qm.

[0097] Like the two previous steps, step e) can be carried out by any technique allowing epitaxial growth, preferably by an MW-PECVD deposition technique.

[0098] An epitaxial interface 62 is then defined between the second conductive layer 20 and the active layer 40, and between the second conductive layer 20 and the intermediate layer 30.

[0099] In the advantageous case where the active layer 40 and the intermediate layer 30 together occupy the entire surface, in the main plane (x,y) (illustrated in FIGS. 2e, 3e), the second conductive layer 20 is not deposited on the first conductive layer 10, which avoids having to manage problems of electrical contact between these layers.

[0100] Preferably, the successive stages of epitaxial growth of the method according to the invention are carried out in the deposition chamber of MW-PECVD equipment, without exit into the ambient atmosphere, so as to avoid any contamination. If one or If exits to the ambient atmosphere had to be made, cleaning is required with the return to the deposition chamber in order to rid the surface of particulate, metallic or hydrocarbon contamination.

[0101] Finally, the manufacturing method comprises a step f) of structuring the second conductive layer 20 and potentially the intermediate layer 30 and / or the active layer 40, in the main plane (x,y). Step f) is based on successive local etchings of these layers 20, 30, 40, making it possible to define the second contact 21 of the capacitor 150 and to define the drain electrode 23 of the transistor 100 ([Fig.2f], [Fig.3f]).

[0102] To locally etch the layers, a mask, for example made of silicon nitride, is deposited and structured on the surface of the second conductive layer 20 by photolithography and etching, so as to mask only the areas in which the second conductive layer 20 must be preserved. The etching of the second conductive layer 20 can be carried out by dry etching, for example by oxygen plasma.

[0103] A second mask must then be deposited and structured, to define the areas to be etched of the intermediate layer 30 and / or the active layer 40, which areas will in particular make it possible to isolate the transistor 100 from the capacitor 150, and provide access to the first contact 11 of the capacitor 150 and to the source electrode 12 of the transistor 100, both formed in the first conductive layer 10. The first mask can be removed prior to the formation of the second mask, or at the end of step f) at the same time as the second mask. The same etching solutions as for the second conductive layer 20 can be used to structure the intermediate layer 30 (and / or the active layer 40).

[0104] In the figures, the source 12 of the transistor 100 and the first contact 11 of the capacitor 150 are electrically connected by continuity of the first conductive layer 10, this with the objective of connecting the capacitor 150 in parallel with the transistor 100. A wire connection ("wire bonding" according to the English terminology) or a metal interconnection (by producing an additional lithography level involving a passivation layer and metallization) can be envisaged between the drain 23 of the transistor 100 and the second contact 21 of the capacitor 150. The proximity of the two cointegrated components reduces the length of the metal connection line and therefore limits the problems of parasitic inductances.

[0105] The device 200 then comprises the capacitor 150 in the vicinity of the transistor 100, as well as the source 22 and drain 23 electrodes of said transistor 100 ([Fig.2f], [Fig.3f]).

[0106] Step f) also comprises the formation of a gate electrode G on an upper face of the active layer 40. According to the possible architecture mentioned above Previously, one (or more) trench(es) is made by etching in the active layer 40, around the drain electrode 23. The gate electrode G is then formed in these trenches ([Fig.2f]', [Fig.3f]'). This gate electrode G comprises an insulating layer, for example made of aluminum oxide, in contact with the active layer 40 and a metal layer, for example made of aluminum, in contact with said insulating layer. Conventional steps of deposition, photolithography and etching can be implemented for the production of the gate electrode G.

[0107] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention.

Claims

Claims

1. Monolithic device (200) including a field effect transistor (100) and at least one capacitor (150), characterized in that it comprises: - a support substrate (50), - a stack comprising a first conductive layer (10) and a second conductive layer (20) made of monocrystalline diamond comprising p-type dopants, and an intermediate layer (30) made of monocrystalline diamond, electrically insulating, interposed between the first conductive layer (10) and the second conductive layer (20), the first conductive layer being arranged on the support substrate (50), the first conductive layer (10) and the second conductive layer (20) respectively forming a first (11) and a second (21) contact of the capacitor (150), - an active layer (40) made of monocrystalline diamond comprising p-type dopants, in which the conduction channel (41) of the transistor (100) is formed,the active layer (40) extending parallel to a main plane (x,y) and being arranged on the first conductive layer (10), and in that the second conductive layer (20) comprises an epitaxial interface (62) with the active layer (40), and forms a drain electrode (23) or source electrode of the transistor (100).,

2. Monolithic device (200) according to claim 1, wherein: - the active layer (40) has a boron concentration of between 1015 / cm3 and 1019 / cm3, and / or - the first conductive layer (10) and the second conductive layer (20) have a boron concentration greater than 1019 / cm3, and / or - the intermediate layer (30) has a nitrogen or phosphorus concentration of between 1014 / cm3 and 1021 / cm3.

3. Monolithic device (200) according to one of claims 1 and 2, wherein: - the first conductive layer (10) and the second conductive layer (20) have a thickness, along an axis (z) normal to the main plane (x,y), of between 5 nm and 50 pm, preferably between 50 nm and 1 pm, and / or - the intermediate layer (30) has a thickness, along an axis (z) normal to the main plane (x,y), of between 10 nm and 2 mm, preferably initially between 500 nm and 50 μm, and / or - the active layer (40) has a thickness, along an axis (z) normal to the main plane (x,y), of between 100 nm and 20 μm.

4. Monolithic device (200) according to one of claims 1 to 3, in which the support substrate (50) has a resistivity greater than 10 kohm.cm.

5. Monolithic device (200) according to one of claims 1 to 3, in which: - a remote contact (52) of the source (12) or drain electrode is formed on the rear face of the support substrate (50), and - the support substrate (50) has a resistivity of less than 50 mohm.cm.

6. Monolithic device (200) according to one of claims 1 to 5, wherein the capacitor (150) is connected in parallel with the transistor (100).

7. Monolithic device (200) according to one of claims 1 to 6, wherein: - the support substrate (50) is made of monocrystalline diamond or comprises a surface film of monocrystalline diamond, and - an epitaxial interface (65) is defined between said support substrate (50) and the first conductive layer (10).

8. Monolithic device (200) according to one of claims 1 to 6, wherein a bonding interface (72) is defined between the support substrate (50) and the first conductive layer (10).

9. A monolithic device (200) according to claim 8, wherein the support substrate (50) comprises monocrystalline or polycrystalline diamond, and / or monocrystalline or polycrystalline silicon carbide, and / or a film (51) adjacent to the bonding interface (72).

10. A method of manufacturing a monolithic device (200) according to one of claims 1 to 9, comprising the following steps: a) providing the support substrate (50), b) forming the first conductive layer (10) on the support substrate (50), c) forming the intermediate layer (30) on a portion of the first conductive layer (10), d) forming the active layer (40) on another portion of the first conductive layer (10), e) forming the second conductive layer (20) on the layer active layer (40) and on the intermediate layer (30), by epitaxial growth, f) structuring the second conductive layer (20) in the main plane (x,y), to form the capacitor (150), adjacent to the transistor (100), and defining the drain electrode (23) or source of the transistor (100) and the second contact (21) of the capacitor (150) in said second conductive layer (20).

11. A manufacturing method according to claim 10, wherein the source (12) and the first contact (11), or the drain and the first contact (11) are electrically connected by continuity of the first conductive layer (10).

12. Manufacturing method according to one of claims 10 and 11, in which: - the support substrate (50) is made of monocrystalline diamond or comprises a surface film of monocrystalline diamond, and - step b) is carried out by epitaxial growth, in particular by implementing a microwave plasma-assisted chemical vapor deposition technique.

13. Manufacturing method according to one of claims 10 to 12, in which step c) is carried out by epitaxial growth, in particular by implementing a microwave plasma-assisted chemical vapor deposition technique.

14. Manufacturing method according to one of claims 10 and 11, in which step b) is carried out by transferring the first conductive layer (10) onto the support substrate (50).

15. Manufacturing method according to claim 14, wherein step b) comprises the following sub-steps: - the implantation of light species of hydrogen, helium type or a combination of these two species in a donor substrate (10D), to define a buried fragile plane (1), - the assembly of the donor substrate (10D) on the support substrate (50) via a direct bonding interface (72), - the separation along the buried fragile plane (1) leading to the transfer of a useful layer (10'), originating from the donor substrate (10D) and intended to form the first conductive layer (10), on the support substrate (50).

16. Manufacturing method according to claim 15, in which the useful layer (10') has a thickness of less than 2 μm at the end of the separation and a subsequent sub-step of epitaxial growth is carried out to increase this thickness.

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