Device and method for analog-to-digital conversion

Abstract

Device and method for analog-to-digital conversion The present description relates to an analog-to-digital converter (300), comprising: - one or more comparators (304), each configured to compare an analog signal (VIN) with a variable reference level (REF) specific to the comparator; - a controller (306) connected to an output of the one or more comparators (304) and configured to generate a control signal (CTRL) indicating the reference level (REF) of each comparator (304) as a function of an output signal of each of the one or more comparators and configured to generate a digital output signal (NUM) on the basis of the output signal of each of the one or more comparators. Figure for abstract: Fig. 3A

Description

Title of the invention: Device and method for analog-digital conversion Technical field

[0001] The present description relates generally to analog-to-digital conversion devices and methods. Prior art

[0002] An analog signal can be converted into a digital signal by analog-to-digital converters comprising, for example, a set of comparators. Each comparator then compares the analog signal to a fixed reference level specific to each comparator and the level of the analog signal is estimated from all the output signals of the comparators. The number of comparators in such a converter increases linearly with the number of reference levels.

[0003] The greater the number of comparators included in the converter, the greater its energy consumption and its size. There is therefore a need for an analog-digital converter with a relatively low level of consumption and / or size. Summary of the invention

[0004] One embodiment provides an analog-to-digital converter, comprising: - one or more comparators, each configured to compare an analog signal with a variable reference level specific to the comparator; and - a controller connected to an output of the one or more comparators and configured to generate a control signal indicating the reference level of each comparator based on an output signal of each of the one or more comparators and configured to generate a digital output signal based on the output signal of each of the one or more comparators.

[0005] According to one embodiment, the analog signal is oversampled.

[0006] According to one embodiment, the reference level of each comparator is se selected from a plurality of discrete voltage levels.

[0007] According to one embodiment, the number of comparators is greater than or equal to two, and the reference levels of the comparators are selected so as to be successive levels among the plurality of discrete voltage levels.

[0008] According to one embodiment, the analog-digital converter further comprises a generator of reference levels of the comparators, comprising a voltage divider formed of a plurality of resistors or diodes connected in series.

[0009] According to one embodiment, the reference level generator comprises a multiplexer configured to select reference levels based on the control signal.

[0010] According to one embodiment, the analog-to-digital converter further comprises at least one digital-to-analog converter connected to an output of the controller and configured to convert the control signal into one or more reference voltage levels supplied to one or more comparators or supplied to one or more voltage supply terminals of the reference level generator.

[0011] According to one embodiment, the difference between two successive reference levels and the sampling frequency are chosen so that the variation in amplitude of the analog signal between two successive samples does not exceed twice said difference.

[0012] Another embodiment provides a Delta-Sigma analog-to-digital converter, comprising the analog-to-digital converter described above.

[0013] Another embodiment provides an analog-to-digital conversion method, comprising: - the comparison, by one or more comparators of an analog-to-digital converter, of an analog signal with a variable reference level specific to the comparator; - the generation of a control signal, by a controller connected to an output of one or more comparators, indicating the reference level of each comparator as a function of an output signal from each of the one or more comparators; and - the generation of a digital output signal, by the controller, on the basis of the output signal of each of the one or more comparators.

[0014] According to one embodiment, the analog signal is oversampled.

[0015] According to one embodiment, the method further comprises selecting the level of reference of each comparator among a plurality of discrete voltage levels.

[0016] According to one embodiment, the number of comparators is greater than or equal to two, and the reference levels of the comparators are selected so as to be successive levels among the plurality of discrete voltage levels.

[0017] According to one embodiment, the method further comprises converting the control signal, by at least one digital-to-analog converter connected to an output of the controller, into a voltage level supplied to a voltage divider, formed of a plurality of resistors or diodes connected in series, included in a reference level generator.

[0018] According to one embodiment, the method further comprises selecting the reference levels based on the control signal, by a multiplexer connected to an output of a reference level generator comprising a voltage divider formed of a plurality of resistors or diodes connected in series. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] represents an example of a flash analog-to-digital converter;

[0021] [Fig.2] is a graph of a voltage of an analog signal and a voltage of a corresponding digital signal after conversion by an analog-to-digital converter;

[0022] [Fig.3A] schematically represents an analog-digital converter according to an embodiment of the present description;

[0023] [Fig.3B] schematically represents a reference level generator according to an embodiment of the present description;

[0024] [Fig.3C] is a flowchart of an example algorithm for choosing the reference levels to be selected from the analog-to-digital converter of [Fig.3A];

[0025] [Fig.4] graphically represents an example of the evolution of the voltage of signals present in the device of [Fig.3A] over time;

[0026] [Fig.5] represents, in the form of a flowchart, a method of converting an analog signal according to an embodiment of the present description;

[0027] [Fig.6] graphically represents an example of the evolution of the voltage over time of signals present in the device of [Fig.3A], in the case where the device of [Fig.3A] comprises only one comparator; and

[0028] [Fig.7] schematically represents a sigma-delta type analog-digital converter. Description of the embodiments

[0029] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0031] Unless otherwise specified, when referring to two elements connected between them, it means directly connected without intermediate elements other than conductors, and when we refer to two elements connected (in English "coupled") between them, it means that these two elements can be connected or be linked by means of one or more other elements.

[0032] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0034] In the following description, an oversampled signal is defined as a signal whose sampling frequency is higher than the Nyquist frequency.

[0035] [Fig.l] shows an example of a flash analog-to-digital converter 100, sometimes also called a parallel analog-to-digital converter.

[0036] The device 100 takes as input an analog signal 102 (“VIN”) and is configured to convert it into a digital signal 101 composed of N bits ranging from a least significant bit 104 (LSB) to a most significant bit 106 (MSB). The converter 100 comprises N comparators Xi, X2,..., XN.i, XN collectively referenced 110 each taking the analog signal 102 at their positive input and a reference voltage at their negative input. According to another embodiment, not illustrated in [Fig.l], the comparators each take the analog signal 102 at their negative input and a reference voltage at their positive input. The reference voltages are set by a voltage divider 116 comprising a first 112 and a second 114 voltage supply voltage terminals and a set of resistors connected in series between the two terminals.The first voltage terminal 112 is at a first voltage REF-, for example connected to a ground rail, and the second voltage terminal 114 is at a second voltage REF+, for example connected to a supply voltage rail. The first voltage REF- is lower than the second voltage REF+. The resistors of the voltage divider 116 have for example the same resistance value “R”. A set of N increasing and regularly spaced voltage values ​​Vxb Vx2,..., Vx(Ni), VxN is thus obtained at the nodes connecting the resistors together. The voltages Vxb Vx2,..., Vx(Ni), VxN are the reference voltages, also called reference levels and are connected to the comparators Xb X2,..., XN b XN respectively.Each of the comparators of the set 110 transmits as output a digital signal having for example a high voltage (“1”) if the input signal 102 is higher than the reference signal of the comparator and a low voltage (“0”) if the input signal 102 is lower than the reference signal of the comparator. The outputs of the comparators 110 are connected to a decoder 118 (“DECODER”) which transmits as output the digital signal 101 in the form of bits ranging from the least significant bit 104 to the most significant bit 106.

[0037] An analog-to-digital converter such as the device 100 comprising N comparators categorizes the values ​​taken by the analog signal 102 among N+1 voltage levels. Increasing the number of levels and therefore the precision and / or the The converter voltage range is accompanied by a linear increase in the number of comparators and therefore the space and power consumption required.

[0038] Although the voltage divider 116 of [Fig. 1] is implemented by series resistors, in another embodiment, diodes are used.

[0039] [Fig.2] is a graph of a voltage ("V") of an analog signal 202 and a voltage of a corresponding digital signal 204 after conversion by an analog-to-digital converter.

[0040] The analog signal 202 varies continuously over time ("t"). The digital signal 204 can only take a finite number of discrete values ​​Vb V2,..., VN.i, VN corresponding to the number of levels of the converter.

[0041] The value of the analog signal 202 is for example sampled, and the samples converted into digital values ​​at regular time intervals, for example governed by a clock signal.

[0042] [Fig.3A] schematically represents an analog-digital converter 300 according to one embodiment.

[0043] The analog-digital converter 300 is for example part of a Sigma-Delta type converter.

[0044] The analog-to-digital converter 300 comprises a first input 308 configured to receive an analog signal VIN, a second input 310 configured to receive a clock signal CLK and an output 320 configured to provide a digital output signal NUM.

[0045] The analog-to-digital converter 300 comprises three modules: a reference level generator 302 (“REFERENCE GENERATOR”), a set of comparators 303 (“COMP”) and a controller 306 (“CONTROLLER”).

[0046] The reference level generator 302 is for example capable of generating any voltage from a set of N reference voltage levels, N being equal to at least two and being chosen for example as a function of the sampling frequency of the analog signal, the amplitude of the variations of the analog signal, the number of comparators 304, etc. In some cases, the reference level generator 302 is implemented by a voltage divider comprising for example a set of N+1 resistors connected in series between two voltage terminals. In some cases, the generator 302 is implemented by the voltage divider 116 of the device 100 of [Fig. 1]. The reference level generator 302 comprises for example N voltage nodes, each intermediate to two neighboring resistors, corresponding to N distinct and increasing voltage values, for example the voltages Vxb Vx2,..., Vx(Ni), VxN of [Fig. 1].The reference level generator 302 is for example configured to generate at M outputs 307 a number M, between 2 and N, reference levels REF. The number M corresponds to the number of com. comparators 304 in the comparator set 303. In addition, the M reference levels REF generated correspond to M successive voltage values ​​among the N values ​​Vxb Vx2,Vx(N_i), VxN. The reference level generator 302 has for example an input 311 connected to an output 313 of the controller 306 and takes for example as input a control signal CTRL generated by the controller 306. The control signal CTRL indicates the M reference levels REF to be transmitted.

[0047] According to one embodiment, the reference level generator 302 comprises M multiplexers, not shown in [Fig.3A], each multiplexer taking for example as input all or part of the N voltages Vxl, Vx2,..., Vx(Nl), VxN and being controlled by the control signal CTRL to each transmit one of the M reference levels REF to the M outputs 307.

[0048] According to another embodiment, represented in [Fig.3B], the reference level generator 302 comprises a number of resistors less than N+1, for example equal to M+1.

[0049] [Fig.3B] schematically represents the reference level generator 302 according to this embodiment of the present description.

[0050] The resistors are connected in series between the supply voltage levels REF- and REF+ (see [Fig.l]), and the voltage level REF+ is variable and controlled by the control signal CTRL. At least one digital to analog converter 340 is then present in the reference level generator 302. The digital to analog converter 340 (“DAC”) is configured to convert the control signal CTRL, received at an input 342 connected to the input 311, into an analog signal, for example the analog signal REF+, at an output 344 connected to the voltage terminal 114 of [Fig.l]. The voltage level REF- is for example fixed and corresponds for example to the voltage of the ground rail, not shown in [Fig.3B]. According to another embodiment, the REF- and REF+ signals are both variable and provided by two digital-to-analog converters, each controlled by the CTRL control signal.

[0051] Referring again to [Fig.3A], and according to another embodiment, no illustrated in [Fig.3A], the reference level generator 302 comprises one or more digital-to-analog converters connected to an output of the controller 306 and configured to convert the digital CTRL control signal into M analog REF reference voltage levels transmitted to the M outputs 307.

[0052] The set of comparators 303 of the analog-to-digital converter 300 comprises M comparators 304. Each of the comparators 304 has a first input connected to the analog signal VIN and a second input connected to one of the M outputs 307 of the reference voltage generator 302. Each of the M comparators 304 compares the analog signal VIN to one of the M corresponding levels of successive REF reference levels. For example, the analog signal VIN is sampled, and the samples compared with the M REF reference levels, at regular intervals at a frequency given by the clock signal CLK. The sampling frequency defined by the clock signal CLK is, for example, high enough so that the analog signal VIN is oversampled. For example, the sampling frequency is between 1 and 10 MHz, for example between 5 and 7 MHz, for a bandwidth of the VIN signal between 1 and 50 kHz, for example between 15 and 25 kHz.

[0053] According to embodiments, the sampling frequency is at the Nyquist frequency and the analog signal VIN has low dynamics, i.e. low amplitude variations.

[0054] According to other embodiments, the analog signal VIN comprises a signal with a low frequency and having a high dynamic range superimposed on a signal with a high frequency and a low dynamic range.

[0055] Each of the M comparators 304 transmits as output, on the basis of the comparison, a digital signal comp_l,..., comp_M having for example a high voltage (“1”) if the analog signal VIN is greater than the reference signal of the corresponding comparator and for example a low voltage (“0”) if the analog signal VIN is less than the reference signal of the corresponding comparator. All of the M digital signals COMP are transmitted by M outputs 309 of the set of comparators 303.

[0056] In certain cases, the difference between 2 successive reference levels REF and the sampling frequency are chosen so that the variation in amplitude of the analog signal VIN between two successive samples does not exceed twice said difference.

[0057] The generation of the clock signal CLK, for example by an external circuit not shown, is known to those skilled in the art and will not be detailed.

[0058] The controller 306 comprises M inputs connected to the M outputs 309 of the module 303, these M inputs being configured to receive all of the digital signals COMP. The controller 306 for example also comprises an input configured to receive the clock signal CLK. The controller 306 is configured to generate the digital output signal NUM at an output 314 of the controller 306, the output 314 being connected to the output 320 of the device 300. The digital output signal NUM corresponds to the conversion of the analog signal VIN by the device 300 and is for example used by other external digital circuits not shown. The controller 306 is also configured to generate the control signal CTRL at the output 313.

[0059] The controller 306 comprises for example a circuit 322 (“NUM GEN”) comprising an input configured to receive the signal CLK and M inputs connected to the M outputs 309 of the module 303 in order to receive the digital signals COMP. The circuit NUM GEN is configured to generate the digital output signal NUM. The circuit NUM GEN comprises for example a counter 324 (“COUNT”) configured to store a level representing the reference levels to be applied to the comparators. For example, the counter COUNT stores the rank of the lowest reference level REF used during the last comparison. According to one embodiment, the circuit NUM GEN is configured to analyze all the signals COMP and deduce therefrom, using the value recorded by the counter during the previous comparison, the level of the compared sample. The circuit NUM GEN is for example configured to update the value of the counter and to generate the signal NUM at the output 314.

[0060] The controller 306 for example also comprises a circuit 326 (“CTRL GEN”) comprising an input configured to receive the signal CLK and M inputs connected to the M outputs 309 in order to receive the digital signals COMP. The circuit CTRL GEN is configured to generate the control signal CTRL at an output connected to the output 313 of the controller 306. According to one embodiment, the circuit CTRL GEN is configured to read the values ​​of the signals COMP corresponding to the maximum and minimum reference values ​​REF to generate the control signal CTRL indicating a variation of the reference signals REF. According to another embodiment, the circuit CTRL GEN also comprises an input connected to an output of the counter COUNT of the circuit NUM GEN and is for example configured to generate the control signal CTRL indicating the reference values ​​REF to be applied for the next comparison.

[0061] The generation of the NUM and CTRL signals by the NUM GEN and CTRL GEN circuits as well as the incrementation of the counter are clocked by the CLK signal.

[0062] According to another embodiment, the controller 306 does not have an input connected to the clock signal CLK. The signals CTRL and NUM are for example asynchronous and generated by a variation or a reading of the signal COMP.

[0063] According to one embodiment, the device 300 is configured to activate a variable number of comparators 304 over time and to generate, by the reference level generator 302, the number of reference values ​​REF corresponding to the number of activated comparators. The other comparators are for example deactivated. The number of active comparators 304 varies for example to follow the speed of variation of amplitude of the analog signal VIN. The simultaneous use of a large number of comparators 304 makes it possible to follow large variations in amplitude of the analog signal VIN over time while the use of a small number of comparators 304 makes it possible to temporarily reduce the consumption of the device 300. The controller 306 is for example configured to select the number of comparators to be used for each comparison, for example as a function of the speed level variations recorded during the previous few comparisons, for example recorded in a memory of the controller 306. For example, the speed information is indicated by the variation of the digital value NUM at the output of the device 300 and / or by increment and / or decrement values ​​of the value of the counter COUNT.

[0064] According to another embodiment, the device 300 comprises a single comparator 304 and N possible reference voltages REF. The number of comparators no longer makes it possible to frame the value of the analog signal VIN over time. According to an algorithm detailed in [Fig.6], the device 300 is configured to compare the value of the successive samples of the analog signal VIN with a reference value which evolves according to the result of the previous comparison. The level of the signal VIN is considered reached when the single reference value oscillates around the value of the analog signal VIN. In this operating mode, the analog signal VIN has, for example, slow amplitude variations relative to the sampling frequency.

[0065] [Fig.3C] is a flowchart of an example algorithm for choosing the M reference levels REF to be selected from the analog-to-digital converter 300 of [Fig.3A],

[0066] In the example of [Fig.3C], the converter 300 comprises 17 resistors, and is capable of generating 16 reference voltage values ​​REF. The converter 300 also comprises 3 comparators.

[0067] [Fig.3C] represents states that the controller 306 can take, which correspond to the level values ​​(“Level”) stored by the counter COUNT.

[0068] During an initialization step 350 (“NRST==0”), for example when the device 300 is switched on, the counter COUNT is for example initialized to the 7th level (“Level=7”) and the 3 reference levels REF take the 7th, 8th and 9th reference value. The analog signal VIN is compared to the 3 reference levels REF by the three comparators, a first comparator comparing the signal VIN to the lowest reference level (for example the 7th value when the counter is at the 7th level), a second comparator comparing the signal VIN to the median reference level (the 8th value when the counter is at the 7th level) and a third comparator comparing the signal VIN to the highest reference level (the 9th value when the counter is at the 7th level). The three comparators 304 generate three digital signals comp_l, comp_2 and comp_3 characteristic of the comparison (“out[7]=comp_l”, “out[8]=comp_2” and “out[9]=comp_3”).

[0069] In the example of [Fig.3C], the controller 306 analyzes the digital signals COMP of the first comparator, having the lowest reference value, and of the third comparator, having the highest reference value.

[0070] If the third comparator has a high output voltage (“comp_3==1”), in a step 354, the controller 306 is configured to increment the counter COUNT and to generate the control signal CTRL indicating to the generator 302 to move to the higher reference levels. The controller 306 therefore moves to the state corresponding to level 8 (“Level=8”), and the 3 reference levels REF take the 8th, 9th and 10th reference values.

[0071] In the state corresponding to level 8, the analog signal VIN is compared to the 3 reference levels REF and the three comparators 304 generate three digital signals comp_l, comp_2 and comp_3 characteristic of the comparison (“out[8]=comp_l”, “out[9]=comp_2” and “out

[10] =comp_3”). If the third comparator still has a high output voltage (“comp_3==l”), the controller 306 repeats step 354 in order to move to the higher state (not shown in [Fig.3C]) and is configured to generate the control signal CTRL indicating to the generator 302 to move to the higher reference levels.

[0072] Step 354 is repeated as long as the third comparator has a high output voltage until reaching the maximum state, corresponding to level 14 (“Level=14”) in this example. The 3 reference levels REF then take the 14th, 15th and 16th reference value. The analog signal VIN is compared to the 3 reference levels REF. The three comparators 304 generate three digital signals comp_l, comp_2 and comp_3 characteristic of the comparison (“out

[14] =comp_l”, “out

[15] =comp_2” and “out

[16] =comp_3”). If the third comparator still has a high output voltage (“comp_3==l”), the controller 306, in a step 358, is configured to generate the control signal CTRL indicating to the generator 302 to remain at the maximum level.

[0073] If, when the controller is in the state corresponding to level 8, the first comparator has a low output voltage (“comp_l==0”), the controller 306, in a step 362, is configured to decrement the counter COUNT and to generate the control signal CTRL indicating to the generator 302 to move to the lower reference levels. The controller 306 therefore moves to the state corresponding to level 7 (“Level=7”).

[0074] In the state corresponding to level 7, if the first comparator comp_l still has a low output voltage (“comp_l==0”), the controller 306 repeats step 362 in order to go to the lower state (not shown in [Fig.3C]) and is configured to generate the control signal CTRL indicating to the generator 302 to go to the lower reference levels.

[0075] Step 362 is repeated as long as the first comparator has a low output voltage until reaching the minimum state, corresponding to level 1 (“Level=1”) in this example. The 3 reference levels REF then take the 1st, 2nd and 3rd value reference. The analog signal VIN is compared to the 3 reference levels REF. The three comparators 304 generate three digital signals comp_l, comp_2 and comp_3 characteristic of the comparison (“out[l]=comp_l”, “out[2]=comp_2” and “out[3]=comp_3”).

[0076] If the first comparator still has a low output voltage (“comp_l==0”), the controller 306, in a step 366, is configured to generate the control signal CTRL indicating to the generator 302 to remain at the minimum level.

[0077] In this algorithm, if the first comparator has a low output voltage, the controller 306 is configured to decrement the counter COUNT and to generate the control signal CTRL indicating the generator 302 to go to the lower level. If the third comparator has a high output voltage, the controller 306 is configured to increment the counter COUNT and to generate the control signal CTRL indicating the generator 302 to go to the higher level. If the first comparator has a high output voltage and the third comparator has a low output voltage, then the current level is considered suitable and the controller 306, in a step 370, is configured not to modify the value of the counter COUNT and to generate the control signal CTRL indicating the generator 302 to remain at the current level and to generate the same reference levels REF.

[0078] An example of the evolution of the reference levels following this algorithm is described in table 1 below for the device 300.

[0079] [Tables 1] Tl T2 T3 T4 T5 T6 Vx5 0 0 0 Vx4 0 1 1 0 0 0 Vx3 1 1 1 1 0 0 Vx2 1 1 1

[0080] The first column represents examples of reference voltage values ​​(Vx 2, Vx3, Vx4, Vx5) and the following six columns represent the state of the output signal REF of the three comparators for six periods (T1, T2, T3, T4, T5, T6) of the clock signal CLK.

[0081] In the example of table 1, at the beginning of the period T1, the generator 302 is at level 2 and the reference levels Vx2, Vx3 and Vx4 are transmitted by the module 302 to the three comparators of the module 303. The two comparators taking Vx2 and Vx3 as input transmit as output the digital signals COMP having a high voltage (“1”) meaning that the analog signal VIN has a voltage higher than the voltages Vx2 and Vx3 and the comparator taking Vx4 as input transmits as output the digital signal having a low voltage (“0”) meaning that the analog signal VIN has a voltage lower than the voltage Vx4. We are in the case where the first comparator has a high output voltage and the third comparator has a low output voltage. The controller 306 is therefore configured to generate the control signal CTRL indicating to the generator 302 to remain at the current level and to generate the same reference levels REF.

[0082] At the start of period T2, generator 302 is at level 2 and the reference levels Vx2, Vx3 and Vx4 are transmitted by module 302 to the three comparators of module 303. The three comparators transmit as output the digital signals COMP having a high voltage meaning that the analog signal VIN has a voltage higher than the voltages Vx2, Vx3 and Vx4. This is the case where the third comparator has a high output voltage. Controller 306 is therefore configured to generate the control signal CTRL indicating to generator 302 to move to the higher level, to level 3.

[0083] At the start of period T3, generator 302 is at level 3 and reference levels Vx3, Vx4 and Vx5 are transmitted by module 302 to the three comparators of module 303. The two comparators taking Vx3 and Vx4 as input transmit as output the digital signal having a high voltage meaning that analog signal VIN has a voltage higher than voltages Vx3 and Vx4 and the comparator taking Vx5 as input transmits as output the digital signal having a low voltage meaning that analog signal VIN has a voltage lower than voltage Vx5. This is the case where the first comparator has a high output voltage and the third comparator has a low output voltage. Controller 306 is therefore configured to generate control signal CTRL indicating to generator 302 to remain at the current level and to generate the same reference levels REF.

[0084] At the start of period T4, generator 302 is at level 3 and reference levels Vx3, Vx4 and Vx5 are transmitted by module 302 to the three comparators of module 303. The comparator taking Vx3 as input transmits as output the digital signal having a high voltage meaning that analog signal VIN has a voltage higher than voltage Vx3. The two comparators taking Vx4 and Vx5 as input transmit as output the digital signal having a low voltage meaning that analog signal VIN has a voltage lower than voltages Vx4 and Vx5. This is the case where the first comparator has a high output voltage and the third comparator has a low output voltage. Controller 306 is therefore configured to generate control signal CTRL indicating to generator 302 to remain at the current level and to generate the same reference levels REF.

[0085] At the beginning of period T5, generator 302 is at level 3 and the levels of reference Vx3, Vx4 and Vx5 are transmitted by the module 302 to the three comparators of the module 303. The three comparators transmit as output the digital signal having a low voltage meaning that the analog signal VIN has a voltage lower than the voltages Vx3, Vx4 and Vx5. This is the case where the first comparator has a low output voltage. The controller 306 is therefore configured to generate the control signal CTRL indicating to the generator 302 to go to the lower level, to level 2.

[0086] At the start of period T6, generator 302 is at level 2 and reference levels Vx2, Vx3 and Vx4 are transmitted by module 302 to the three comparators of module 303. The comparator taking Vx2 as input transmits as output the digital signal having a high voltage meaning that analog signal VIN has a voltage higher than voltage Vx2. The two comparators taking Vx3 and Vx4 as input transmit as output the digital signal having a low voltage meaning that analog signal VIN has a voltage lower than voltages Vx3 and Vx4. This is the case where the first comparator has a high output voltage and the third comparator has a low output voltage. Controller 306 is therefore configured to generate control signal CTRL indicating to generator 302 to remain at the current level and to generate the same reference levels REF.

[0087] In the example of Table 1, the device 300 seeks to frame the voltage value of the VIN signal and the reference levels REF are chosen to follow the variations of the VIN signal over time.

[0088] Table 1 shows an example of programming of the controller 306 and other programmings are possible for the same analog signal VIN and the same number of comparators. For example, the reference levels can be shifted by two levels during a period.

[0089] A different number of comparators may be used. The number is for example chosen according to the anticipated variations of the analog signal VIN. The slower the variations of the analog signal VIN are likely to be, for example at most one level per period of the clock signal CLK, the lower the number of comparators needs to be.

[0090] [Fig.4] graphically represents an example of the evolution of the voltage (“V”) of signals CLK, comp_m, NUM, CTRL, REF present in the device 300 of [Fig.3A] over time (“t [%]”), expressed as a percentage of a period of the clock signal CLK.

[0091] The voltage of the clock signal CLK, the voltage comp_m of one of the M digital output signals COMP of a comparator 304 of the module 303, the voltage of the digital output signal NUM, the voltage of the control signal CTRL transmitted by the controller 306 and the voltage of one of the M reference levels REF are represented in [Fig.4].

[0092] At the start of a period of the clock signal CLK, at time 0%, for example at a rising edge of the clock signal CLK, the comparators 304 of the module 303 are activated and compare the analog signal VIN with the reference levels REF established during the previous period. Each of the M signals COMP converges towards a value representative of the comparison, for example over the period from 0 to 10%. The circuit NUM GEN of the controller 306 takes the signals COMP as input and adjusts the voltage level of the digital output signal NUM, for example at time 10%. The circuit CTRL GEN of the controller 306 receives the digital signal NUM and is configured to generate the control signal CTRL, for example at time 20%, used by the module 302 for the generation of the reference levels REF for the following period. For example, over the period from 20 to 100%, the REF reference levels are generated by module 302 and converge.

[0093] In the example of [Fig.4], the voltage level of the signal comp_m represented decreases, over the period from 0 to 10%, indicating a decrease in the voltage of the analog signal VIN, not represented in [Fig.4]. In response, the voltage level of the digital output signal NUM decreases, at time 10%, and the voltage level of the signal CTRL for example decreases, at time 20%, the generator 302 is then configured to move to the lower level to continue to follow the evolution of the analog signal VIN. The voltage level of the signal REF represented decreases, over the period from 20 to 100%, corresponding to the decrease in the generated reference levels.

[0094] According to another embodiment, the period begins at a falling edge of the clock signal CLK.

[0095] [Fig.5] represents, in the form of a flowchart, a method of converting the analog signal VIN of [Fig.3A] according to one embodiment. The steps of the method are for example carried out by the reference level generator 302, the comparators 304 and the controller 306 of [Fig.3A].

[0096] In a step 502 (“REFERENCE GENERATION”), reference levels REF are generated by the reference level generator 302. During initialization of the device, the reference levels correspond for example to the M median levels among the N possible levels.

[0097] In a step 504 (“COMPARISON”) following step 502, the reference levels REF are compared to the analog signal VIN at an instant indicated by the clock signal CLK and the M digital signals COMP are generated by the module 303.

[0098] In a step 506 (“CONVERSION”) following step 504, the digital output signal NUM is generated, for example by the circuit NUM GEN of the controller 306, at an instant indicated by the clock signal CLK and transmitted to the output 320 of the device 300.

[0099] In a step 508 (“COMMAND GENERATION”) following step 506, the control signal CTRL is generated, for example by the circuit CTRL GEN of the controller 306, at a time indicated by the clock signal CLK. The control signal CTRL is transmitted to the module 302 for the generation of the new reference levels REF and the method resumes at step 502.

[0100] [Fig.6] graphically represents an example of the evolution of the voltage (“V”) over time (“t”) of signals CLK, comp_l, NUM, CTRL present in the device 300 of [Fig.3A], in the case where the device 300 comprises only one comparator.

[0101] If the module 303 of the device 300 of [Fig.3A] comprises at least two comparators, the voltage level of the analog signal VIN can be framed by two consecutive reference levels, as described in the example of Table 1.

[0102] On the contrary, if the module 303 comprises only a single comparator, during a given period of the clock signal CLK, it is possible to determine a minimum or maximum level for the voltage level of the analog signal VIN. It is appropriate to use several periods to frame and know the level of the analog signal VIN.

[0103] An example of the signals corresponding to the application of a specific algorithm is illustrated in [Fig.6]. The clock signal CLK oscillates periodically between two voltage values ​​and the instants T1,..., T6 correspond to the successive rising edges. During the first period, between T1 and T2, the analog signal VIN is compared to a first reference value REF and the digital signal comp_l transmitted by the single comparator 304 goes to the high voltage so the voltage of the analog signal VIN is higher than the first reference voltage. The voltage of the digital output signal NUM increases indicating a rise in the estimated VIN voltage level. The voltage of the control signal CTRL also increases so that a higher reference level, corresponding to a second reference voltage, is used during the following period.

[0104] Between T2 and T3, the analog signal VIN is compared to the second reference value REF and the voltage of the digital signal comp_l remains at the high voltage. The voltage of the analog signal VIN is therefore higher than the second reference voltage. The voltage of the digital output signal NUM increases indicating a rise in the estimated VIN voltage level. The voltage of the control signal CTRL also increases so that a higher reference level, corresponding to a third reference voltage, is used during the following period.

[0105] Between T3 and T4, the voltage of the digital signal comp_l goes to low voltage which means that the voltage of the analog signal VIN is lower than the third reference voltage. The voltage of the digital output signal NUM decreases indicating a decrease in the estimated VIN voltage level and the voltage of the control signal CTRL also decreases so that a lower reference level, for example corresponding to the second reference value, is used during the following period.

[0106] Between T4 and T5, the voltage of the digital signal comp_l goes high so the voltage level of the analog signal VIN is higher than the second reference voltage. The voltage of the digital output signal NUM increases to indicate a rise in the estimated VIN voltage level and the voltage of the control signal CTRL also increases so that a higher reference level, for example corresponding to the third reference value, is used during the following period.

[0107] Between T5 and T6, the voltage of the signal comp_l decreases, which means that the voltage of the digital analog signal VIN is lower than the third reference voltage. The voltage of the digital output signal NUM decreases, indicating a decrease in the estimated VIN voltage level, and the voltage of the control signal CTRL also decreases so that a lower reference level, for example corresponding to the second reference value, is used during the following period.

[0108] In the example of [Fig.6], a high voltage at the output of the single comparator leads to an increase in the reference voltage for the following period and a low voltage at the output of the single comparator leads to a decrease in the reference voltage for the following period. Since only one comparator is present, it is not possible to simultaneously frame the analog signal VIN by two reference values. However, an oscillation between two neighboring reference values ​​is for example observed if the analog signal VIN is between these two values, as illustrated between T2 and T6 of [Fig.6]. This is possible for a variation of the analog signal VIN slower than the frequency of the clock signal CLK.

[0109] [Fig.7] represents a block diagram of a sigma-delta 700 type analog-digital converter comprising for example the converter 300 of [Fig.3A].

[0110] The sigma-delta type analog-to-digital converter 700 takes an analog input signal IN at an input and is configured to generate a digital signal OUT. The converter 700 comprises, for example, a subtractor 705, an integrator 710 and an analog-to-digital converter (“ADC”), for example the converter 300 of [Fig. 3A]. The converter 700 also comprises, for example, in a feedback loop, a digital-to-analog converter 715 (“DAC”) taking the output signal of the ADC 300 as input and configured to generate a second analog signal. The subtractor 705 comprises a first input connected to the input of the converter 700 and configured to receive the signal IN and a second input configured to receive the second analog signal. The subtracter 705 is configured to generate a signal corresponding to the difference of the two input signals and transmit it to the integrator 710. The integrator 710 comprises one or more integration stages and is configured to integrate the output signal of the subtracter 705 and generate the analog signal VIN. The signal VIN is transmitted to the analog-to-digital converter 300 configured to convert the analog signal VIN into the digital signal NUM. The analog-to-digital converter 300 further receives the clock signal CLK and is configured to sample the signal VIN, for example at a frequency higher than the Nyquist frequency to perform oversampling. The signal NUM is transmitted to the digital-to-analog converter 715.The NUM signal is also passed to a digital filter and decimator 720 (“FILTER + DECIMATOR”) configured to filter the NUM signal and generate the digital signal OUT.

[0111] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, a device comprises, for example, several converters 300 configured to each receive a subset of the samples of the analog signal VIN.

[0112] Finally, the practical implementation of the described embodiments and variants is within the reach of the person skilled in the art from the functional indications given above. In particular, voltage comparators are known in the art and their practical implementation is therefore within the reach of the person skilled in the art.

Claims

Claims

1. An analog-to-digital converter (300), comprising: - one or more comparators (304), each configured to compare an analog signal (VIN) with a variable reference level (REF) specific to the comparator; and - a controller (306) connected to an output of the one or more comparators (304) and configured to generate a control signal (CTRL) indicating the reference level (REF) of each comparator (304) as a function of an output signal (comp_m) of each of the one or more comparators and configured to generate a digital output signal (NUM) based on the output signal (comp_m) of each of the one or more comparators.

2. An analog-to-digital converter according to claim 1, wherein the analog signal (VIN) is oversampled.

3. An analog-to-digital converter according to any one of claims 1 to 2, wherein the reference level (REF) of each comparator is selected from a plurality of discrete voltage levels.

4. The analog-to-digital converter of claim 3, wherein the number of comparators (304) is greater than or equal to two, and the reference levels (REF) of the comparators (304) are selected to be successive levels among the plurality of discrete voltage levels.

5. An analog-to-digital converter according to any one of claims 1 to 4, further comprising a reference level generator (302) of the comparators (304), comprising a voltage divider formed from a plurality of resistors or diodes connected in series.

6. The analog-to-digital converter of claim 5, wherein the reference level generator (302) comprises a multiplexer configured to select the reference levels (REF) based on the control signal (CTRL).

7. An analog-to-digital converter according to any one of claims 1 to 6, further comprising at least one digital-to-analog converter connected to an output of the controller (306) and configured to convert the control signal (CTRL) into one or more reference voltage levels (REF) supplied to the one or more com- comparators (304) or supplied to one or more voltage supply terminals (REF-, REF+) of the reference level generator.

8. Analog-to-digital converter according to any one of claims 1 to 7, in which the difference between two successive reference levels and the sampling frequency are chosen so that the variation in amplitude of the analog signal (VIN) between two successive samples does not exceed twice said difference.

9. A Delta-Sigma analog-to-digital converter, comprising the analog-to-digital converter according to any one of claims 1 to 8.

10. A method of analog-to-digital conversion, comprising: - comparing, by one or more comparators (304) of an analog-to-digital converter (300), an analog signal (VIN) with a variable reference level (REF) specific to the comparator; - generating a control signal (CTRL), by a controller (306) connected to an output of the one or more comparators (304), indicating the reference level (REF) of each comparator as a function of an output signal (comp_m) of each of the one or more comparators; and - generating a digital output signal (NUM), by the controller (306), on the basis of the output signal (comp_m) of each of the one or more comparators.

11. An analog-to-digital conversion method according to claim 10, wherein the analog signal (VIN) is oversampled.

12. A method of analog-to-digital conversion according to any one of claims 10 to 11, further comprising selecting the reference level (REF) of each comparator from a plurality of discrete voltage levels.

13. The analog-to-digital conversion method of claim 12, wherein the number of comparators (304) is greater than or equal to two, and the reference levels (REF) of the comparators (304) are selected to be successive levels among the plurality of discrete voltage levels.

14. A method of analog-to-digital conversion according to any one of claims 10 to 13, further comprising converting the control signal (CTRL), by at least one digital-to-analog converter connected to an output of the controller (306), into a level of voltage supplied to a voltage divider, formed of a plurality of resistors or diodes connected in series, included in a reference level generator (302).

15. A method of analog-to-digital conversion according to any one of claims 10 to 13, further comprising selecting the reference levels (REF) based on the control signal (CTRL), by a multiplexer connected to an output of a reference level generator (302) comprising a voltage divider formed of a plurality of resistors or diodes connected in series.

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