Insulating trench

Abstract

Insulating Trench This description relates to an insulating trench (150) formed from a first face (102) of a semiconductor substrate (101) comprising on all its lateral walls a P-type doped semiconductor layer (152) formed by epitaxial growth. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Insulating trench technical field

[0001] This description relates generally to electronic systems and circuits, and their manufacturing processes. More specifically, this description relates to the insulation of electronic components and the use of insulating trenches for this purpose. Previous technique

[0002] The proper functioning of electronic devices comprising one or more electronic components may generally require the electrical isolation of this or these components from other components and / or the external environment.

[0003] The use of insulating trenches is a known means of electrical insulation.

[0004] It would be desirable to be able to improve, at least in part, certain aspects of electronic devices and their manufacturing processes. Summary of the invention

[0005] There is a need for electronic devices comprising electrically isolated electronic components, and which exhibit current leakage.

[0006] There is a need for electronic devices comprising electrically isolated pixels, and which exhibit current leakage.

[0007] There is a need for electronic devices comprising laterally electrically insulated electronic components using insulating trenches to limit current leakage.

[0008] An embodiment overcomes all or part of the disadvantages of known electronic devices comprising electrically isolated electronic components allowing to limit current leakage.

[0009] One embodiment provides for electrically isolating an electronic component using at least one insulating trench.

[0010] One embodiment provides for electrically isolating an electronic component using at least one insulating trench whose walls are covered by a heavily doped P-type semiconductor layer.

[0011] One embodiment provides for forming this semiconductor layer by epitaxial growth.

[0012] One embodiment provides for an insulating trench formed from a first face of a semiconductor substrate comprising on all its lateral walls a P-type doped semiconductor layer formed by epitaxial growth.

[0013] According to one embodiment, the trench has a depth greater than 3 pm.

[0014] According to one embodiment, said semiconductor layer has a concentration in P-type dopant elements greater than 1x1017 atoms.cm-3.

[0015] According to one embodiment, said semiconductor layer has a thickness greater than 5 nm.

[0016] According to one embodiment, the trench comprises a core made of an electrically insulating material.

[0017] According to one embodiment, said core comprises silicon oxide.

[0018] Another embodiment provides for an electronic device comprising a electronic component being electrically and laterally isolated by at least one insulating trench as described previously.

[0019] According to one embodiment, said component is a pixel.

[0020] Another embodiment provides for a method of manufacturing an insulating trench comprising the following successive steps: a) etch a first cavity from a first face of a semiconductor substrate; b) grow by epitaxy a P-type doped semiconductor material on the walls of said first cavity; c) fill said first cavity with an electrically insulating material.

[0021] According to one embodiment, the process comprises, between steps b) and c), the following successive steps: d) grind said semiconductor substrate from a second face opposite the first face until reaching the bottom of said first cavity; e) form a second cavity from said second face of said semiconductor substrate, said second cavity having a width less than a width of said first cavity.

[0022] Another embodiment provides for a method of manufacturing a device described above comprising the method of manufacturing an insulating trench described above.

[0023] According to one embodiment, said component is formed from said first face of said semiconductor substrate. Brief description of the drawings

[0024] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0025] [Fig.1] represents a cross-sectional view of an electronic device according to one embodiment;

[0026] [Fig.2] represents two graphs illustrating the advantage of the embodiment of [Fig.1];

[0027] [Fig.3] represents a cross-sectional view of a step in a manufacturing process of the embodiment of [Fig.1];

[0028] [Fig.4] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig.1];

[0029] [Fig.5] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig.1];

[0030] [Fig.6] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig.1];

[0031] [Fig.7] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig.1];

[0032] [Fig.8] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig.1];

[0033] [Fig.9] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig.1];

[0034] [Fig. 10] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig. 1];

[0035] [Fig.1 1] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig.1];

[0036] [Fig. 12] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig. 1];

[0037] [Fig. 13] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig. 1]; and

[0038] [Fig. 14] represents a cross-sectional view of another step in a manufacturing process of the embodiment of [Fig. 1]. Description of the implementation methods

[0039] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0040] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0041] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two connected (in English "coupled") elements between them, this means that these two elements can be connected or linked via one or more other elements.

[0042] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0043] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0044] The embodiments described below relate to the insulation of electronic components formed in and on a semiconductor substrate. The use of insulating trenches is common for electrically and laterally isolating electronic components. It is known that an electronic component can exhibit leakage currents even when surrounded by insulating trenches. The inventors discovered that introducing a heavily doped P-type layer at the wall of the insulating trenches limits these leakage currents. Such an insulating trench is described with reference to Figures 1 and 2. Two methods for manufacturing such an insulating trench are described with reference to Figures 3 to 6 and 7 to 14.

[0045] Moreover, the embodiments described below are particularly suited to the isolation of electronic components of the imager component type, such as pixels.

[0046] Furthermore, the embodiments described above are particularly suitable for use in any type of industrial market where electrical insulation of electronic components is required. More specifically, such an insulating trench can be used to: - the automotive industry, for example in the field of automotive electrification or in the field of Advanced Driver Assistance Systems (ADAS); - the industrial sector, for example in the field of green energy, in the field of infrastructure electrification, the Internet of Things (IoT) and Smart Homes, where electricity and energy consumption and data exchange are key elements; - the personal electronics industry, for example in the field of mobile telephony and the Internet of Things (IoT), as well as in the field of broadband interfaces; and - the communications equipment, computer and peripherals industry, for example in the field of infrastructure and data centers (Data Centers), and in the field of low Earth Orbit (LEO) satellites.

[0047] Fig. 1 is a cross-sectional view of an embodiment of an electronic device 100 comprising an embodiment of an insulating trench 150.

[0048] The device 100 is formed from a semiconductor substrate 101 comprising an upper face 102 and a lower face 103, opposite the upper face 102. In one example, the substrate 101 is made of a semiconductor material, that is, a material comprising at least one chemical element from column IV of the periodic table of elements, such as silicon (Si) or germanium (Ge). In one embodiment, the substrate 101 is made of silicon. In one example, the substrate 101 may rest on a support 104, such as another substrate. In this case, the lower face 103 of the substrate is in contact with the support 104.

[0049] The device 100 includes an electronic component 110 which is laterally insulated by one or more insulating trenches 150.

[0050] According to one example, the electronic component 110 is formed in and / or on the substrate 101 from its upper face 102. The electronic component 110 may be a single electronic component or a circuit comprising several electronic components. According to a preferred embodiment illustrated in [Fig. 1], the component 110 is a pixel that can be used in an imaging circuit, such as a screen. According to the preferred embodiment, the component 110 comprises a photodiode 111 formed in the substrate 101 and a layer 112 extending between the upper face 102 of the substrate 101 and the photodiode 111. According to one example, the layer 112 is a heavily doped P-type surface layer, produced by implantation to fabricate a pinch-off diode.

[0051] According to one example, component 110 may include metallization levels 113 resting on the upper layer 102 of the substrate 101.

[0052] According to one embodiment, the insulating trench(s) 150 extend from the upper face 102 of the substrate 101. In [Fig. 1], two trenches 150 are shown. The insulating trench(s) 150 are formed of an insulating core 151 and a semiconducting layer 152, also called a liner 152. The insulating core represents the inner part of the insulating trench 150 and is made of an insulating material, such as silicon oxide. According to one embodiment, the semiconductor layer 152 is P-type doped, preferably heavily P-type doped, and covers the side walls and bottom of the insulating trench 150. According to one embodiment, the layer 152 is obtained by epitaxial growth, which allows for uniform doping of the layer 152, and a clean interface between the core 151 and the layer 152.Methods for implementing a manufacturing process for a device of the type of device 100 are described in relation to figures 3 to 14.

[0053] According to one example, the trench(s) 150 have a depth greater than 3 pm, preferably greater than 6 pm. The trench(s) 150 have a width between 100 and 500 nm, for example on the order of 200 nm.

[0054] According to one embodiment, the concentration of P-type dopant elements in layer 150 is greater than 11017 atoms.cm. In one example, the dopant elements used to dope layer 150 include one or more elements from column III of the periodic table of elements, such as boron. In another example, layer 150 has a thickness greater than 5 nm, for example, on the order of 10 nm.

[0055] An advantage of using a layer of the type of layer 151 is described in relation to [Fig.2],

[0056] The [Fig.2] includes two graphs (A) and (B).

[0057] Graph (A) illustrates, by shades of grey, the concentration of doping elements in a region between two insulating trenches of the type of trenches 150 described in relation to [Fig.1].

[0058] Graph (B) illustrates, by lines and shades of grey, the electrostatic potential and associated current lines in a region between two insulating trenches of the type of trenches 150 described in relation to [Fig.1].

[0059] Graphs (A) and (B) show that using a heavily doped P-type liner prevents parasitic electrical conduction along the insulating trenches, which leads to leakage currents. Indeed, graph (A) shows that the implantation of dopant elements in this region is prevented at the junction between this region and the insulating trenches. Graph (B) shows, for its part, that the current lines remain confined within this region.

[0060] Figures 3 to 6 illustrate steps of a first method of implementing a manufacturing process for a device of the type of device 100 described in relation to [Fig. 1],

[0061] The manufacturing process of Figures 3 to 6 relates to a manufacturing process for an insulating trench of the type of insulating trenches 150 described in relation to [Fig. 1]. More particularly, this process is a front-face manufacturing process for a semiconductor substrate.

[0062] In the initial step of [Fig. 3], a semiconductor substrate 301 resting on a support 302 of the type of substrate 101 and support 104 described in relation to [Fig. 1] is considered. A mask allowing preparation for a subsequent etching operation is installed on an upper face 301Sup of the substrate 301.

[0063] This mask is composed of a protective stack 303 and a mask layer 304 comprising openings 305. The stack 303 comprises: - an insulating layer 303A, for example made of silicon oxide, resting on the face 301Sup of the substrate 301; - a 303B layer, for example made of nitrate, resting on the 303A layer; and - an insulating layer 303C, for example made of silicon oxide, resting on the layer 303B.

[0064] The mask layer 304 is, for example, a layer of resin remaining after the photolithography process. The openings 305 indicate the future location of the insulating trenches.

[0065] In step [Fig. 4], a cavity etching operation 306 is performed. The cavities 306 have the dimensions of the desired insulating trenches. According to one example, the cavities 306 have a depth greater than 3 pm, preferably greater than 6 pm. The cavities 306 have a width between 100 and 500 nm, for example, on the order of 200 nm.

[0066] In the step of [Fig. 5], a heavily doped P-type semiconductor layer 307 of the type of liner 152 described in relation to [Fig. 1] is formed. According to one example, the layer 307 is formed by epitaxial growth and covers the side walls and the bottom of the cavities 306.

[0067] In the step shown in [Fig. 6], the cavity 306 is filled with an insulating material 310 to form an insulating trench 311. The insulating material 310 forms the core of the insulating trench. As an example, the material 310 is silicon dioxide. The insulating trench 311 is therefore of the same type as the slice 150 described in relation to [Fig. 1].

[0068] The step in [Fig.6] can then be followed by manufacturing steps for an electronic component between trenches 311. According to one variant, these steps can be carried out before the steps described in relation to Figures 3 to 6.

[0069] Figures 7 to 14 illustrate steps of a second method of implementing a manufacturing process for a device of the type of device 100 described in relation to [Fig. 1],

[0070] The manufacturing process of Figures 7 to 14 relates to a manufacturing process for an insulating trench of the type of insulating trenches 150 described in relation to [Fig. 1]. More particularly, this process is a back-face manufacturing process for a semiconductor substrate.

[0071] In the initial step of [Fig.7], similar to the step in [Fig.4], a semiconductor substrate 701 is considered to be resting on a support 702 of the type of the substrate 101 and support 104 described in relation to [Fig.1]. A protective stack 703 is formed on an upper face 701Sup of the substrate 701. The stack 703 comprises: - an insulating layer 703A, for example of silicon oxide, resting on the face 701Sup of the substrate 701; - a 703B layer, for example made of nitrate, resting on the 703A layer; and - an insulating layer 703C, for example made of silicon oxide, resting on the layer 703B.

[0072] Cavities 704 are etched into the substrate 701 in the same manner as those described in relation to Figures 3 and 4. The cavities 704 have the dimensions of the desired insulating trenches. By way of example, the cavities 704 have a depth greater than 3 pm, preferably greater than 6 pm. The cavities 704 have a width between 100 and 500 nm, for example, on the order of 200 nm.

[0073] In the step of [Fig. 8], a heavily doped P-type semiconductor material 705 is formed in the cavities. According to one example, the material is formed by epitaxial growth and completely fills the cavities 705.

[0074] In step [Fig.9], an etching operation is carried out to flatten the upper face of the structure obtained at the end of step [Fig.8]. During this step, excess material 705 protruding from the face 701Sup of the substrate 701, and layers 703A and 703B are removed.

[0075] In the step shown in [Fig. 10], manufacturing steps for an electronic component arranged between insulating trenches can be implemented. In the example illustrated in [Fig. 10], a pixel-type component, similar to component 110 described in relation to [Fig. 1], comprises a photodiode 706 and an optical insulation layer 707. In one example, the photodiode 706 is formed in the substrate 701. In another example, the optical insulation layer is placed between the photodiode 706 and the upper face 701Sup of the substrate 701.

[0076] In step [Fig. 11], optional metallization levels 708 are formed on the remaining layer 703C of the stack. According to one example, the metallization levels 708 are connected to the component formed in step 10.

[0077] In the step of [Fig. 12], the structure obtained in the step of [Fig. 11] is turned over to have access to the back face 701Inf, or lower face 701Inf, of the substrate 701. The lower face 701Inf is opposite to the upper face 701Sup.

[0078] In the step shown in [Fig. 13], the support 702 is removed and a grinding operation is carried out on the rear face 701Inf of the substrate 701. The grinding is stopped when the bottom of the cavities 704 appears, i.e., when the material 705 is exposed.

[0079] In the step shown in [Fig. 14], an etching operation is performed on the material 705 to form a cavity 710 in the material 705. This step is intended to form the core of the insulating trench. The etching step thins the material 705 until it forms only a layer covering the lateral walls of the initial cavity 704. In other words, the etching step forms a cavity 710 with a width less than the width of the cavity 704. Thus, the material 705 is transformed into a layer of the type of layer 152 described in relation to [Fig. 1].

[0080] Once the cavity 710 is formed, it is partially or completely filled with an electrically insulating material, for example silicon oxide. An insulating trench 711 of the type of trench 150 described in relation to [Fig. 1] is thus formed.

[0081] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0082] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing an insulating trench (150; 311; 711) comprising the following successive steps: a) etching a first cavity (306; 704) from a first face (301Sup; 701Sup) of a semiconductor substrate (301; 701); b) growing by epitaxy a P-type doped semiconductor material (307; 705) on the walls of said first cavity (306; 704); c) filling said first cavity (310; 709) with an electrically insulating material.

2. A method according to claim 1, comprising, between steps b) and c), the following successive steps: d) grinding said semiconductor substrate (701) from a second face (701Inf) opposite the first face (701Sup) until reaching the bottom of said first cavity (306; 704); e) forming a second cavity (710) from said second face (701Inf) of said semiconductor substrate (701), said second cavity (710) having a width less than a width of said first cavity (704).

3. Method according to claim 1 or 2, wherein said first cavity has a depth greater than 3 pm.

4. A method according to any one of claims 1 to 3, wherein said semiconductor layer (152; 307; 705) has a concentration of P-type dopant elements greater than 1xlO17 atoms.cm3.

5. A method according to any one of claims 1 to 4, wherein said semiconductor layer (152; 307; 705) has a thickness greater than 5 nm.

6. Insulating trench (150; 311; 711) obtained by the manufacturing process according to any one of claims 1 to 5.

7. Trench according to claim 6, comprising a core (151; 310; 709) of an electrically insulating material.

8. Trench according to claim 7, wherein said core (151; 310; 709) comprises silicon oxide.

9. Electronic device (100) comprising an electronic component (110) being electrically and laterally isolated by at least one insulating trench (150) according to any one of claims 6 to 8.

10. Device according to claim 9, wherein said component is a pixel (110).

11. A method for manufacturing a device (100) according to claim 9 or 10 comprising the method according to any one of claims 1 to 5.

12. Method according to claim 11, wherein said component (110) is formed from said first face (102) of said semiconductor substrate (101).

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