Method for manufacturing an electronic device comprising a memory circuit

Abstract

Method for manufacturing an electronic device comprising a memory circuit. This description relates to an electronic device comprising: - a semiconductor substrate (13); - an insulating layer (18), on and in contact with the semiconductor substrate;and - a memory circuit comprising a plurality of memory cells, each comprising a bipolar selector transistor disposed in and on the semiconductor substrate, each bipolar selector transistor comprising a base region (29, 15), an emitter region (27) and a collector region (17), in which each bipolar selector transistor comprises an insulation structure (16) of a first dielectric material, the insulation structure comprising an upper part extending vertically in the insulating layer and a lower part extending vertically in the semiconductor substrate between the base region and the emitter region, the lateral faces of the upper part of the insulation structure being covered by spacers (21) of a second dielectric material. Figure for the abstract: Fig. 16B;

Description

Title of the invention: Method for manufacturing an electronic device comprising a memory circuit. Technical field

[0001] This description relates generally to electronic devices and more particularly to electronic devices comprising a memory circuit. Prior art

[0002] Electronic devices include both memory circuits and logic circuits. We are particularly interested here in electronic devices comprising memory circuits with memory elements arranged in a matrix, each memory element being associated with a bipolar selector transistor. This transistor is used to program, erase, or read each memory element independently.

[0003] It would be desirable to improve at least in part certain aspects of known electronic devices. Summary of the invention

[0004] For this purpose, one embodiment provides for an electronic device comprising: - a semiconductor substrate; - an insulating layer covering the semiconductor substrate, on top of and in contact with the semiconductor substrate; and - a memory circuit comprising a plurality of memory cells, each comprising a bipolar selector transistor disposed in and on the semiconductor substrate, each bipolar selector transistor comprising a base region, an emitter region and a collector region, in which each bipolar selector transistor comprises an insulation structure in a first dielectric material, the insulation structure comprising an upper part extending vertically in the insulating layer and a lower part extending vertically in the semiconductor substrate between the base region and the emitter region, the lateral faces of the upper part of the insulation structure being covered by spacers in a second dielectric material.

[0005] According to one embodiment, the device further comprises a logic circuit comprising a plurality of finned field-effect transistors arranged in and on the semiconductor substrate, each finned field-effect transistor comprising a source region and a drain region, wherein two adjacent finned field-effect transistors are separated by another insulating structure in the first dielectric material, the insulating structure comprising an upper part extending vertically into the insulating layer and a lower part extending vertically into the semiconductor substrate between the drain region and the source region of the two adjacent transistors, the lateral faces of the upper part of the insulating structure being covered by spacers in the second dielectric material.

[0006] According to one embodiment, the isolation structures of the memory circuit and the isolation structures of the logic circuit have the same depth.

[0007] According to one embodiment, the isolation structures of the memory circuit and the isolation structures of the logic circuit have different depths.

[0008] According to one embodiment, each memory cell comprises a memory element having a layer made of a phase change material.

[0009] According to one embodiment, the memory circuit comprises an interconnect stack arranged on the semiconductor substrate, comprising a succession of levels in which interconnect elements are defined.

[0010] According to one embodiment, the memory elements are arranged above the interconnect stack.

[0011] Another embodiment provides a method for manufacturing, in and on a semiconductor substrate, an electronic device comprising a memory circuit including a plurality of memory cells, each comprising a bipolar selector transistor formed in and on the semiconductor substrate, each bipolar selector transistor comprising a base region, an emitter region, and a collector region, the method comprising the steps of: - formation of sacrificial grids in a sacrificial material on the semiconductor substrate; - formation of spacers in a dielectric material on the lateral faces of sacrificial grids; - removal of the sacrificial material from the sacrificial grids and etching of the substrate opposite the sacrificial grids to form openings surrounded at the top by spacers and extending at the bottom into the substrate, and filling of the openings with another dielectric material to form insulating structures in the other dielectric material; and - formation of an insulating layer on and in contact with the semiconductor substrate, the insulation structures thus comprising an upper part extending vertically into the insulating layer and a lower part extending vertically into the semiconductor substrate between the base region and the emitter region of the bipolar transistors, the lateral faces of the upper part of each insulation structure being covered by the spacers.

[0012] According to one embodiment, the device further comprises a logic circuit, the logic circuit comprising a plurality of finned field-effect transistors, each having a source region and a drain region, the method comprising the steps of: - formation of sacrificial grids in a sacrificial material on the semiconductor substrate; - formation of spacers in the dielectric material on the lateral faces of the sacrificial grids; - removal of the sacrificial material from the sacrificial grids and etching of the substrate opposite the sacrificial grids to form openings surrounded at the top by spacers and extending at the bottom into the substrate, and filling of the openings with the other dielectric material to form further insulating structures in the other dielectric material; and - formation of the insulating layer on and in contact with the semiconductor substrate, the other insulation structures thus comprising an upper part extending vertically into the insulating layer and a lower part extending vertically into the semiconductor substrate between the source region and the drain region of each finned field-effect transistor, the lateral faces of the upper part of the other insulation structure being covered by the spacers.

[0013] According to one embodiment, the steps for forming the isolation structures of the memory circuit and the other isolation structures of the logic circuit are common. Brief description of the drawings

[0014] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0015] [Fig.1A], [Fig.1B] and [Fig.1C] are partial and schematic views of an example of an electronic device according to a first embodiment;

[0016] [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7A], [Fig.7B], [Fig.7C], [Fig.7D], [Fig.8A], [Fig.8B], [Fig.9A], [Fig.9B], [Fig.1OA], [Fig.1OB], [Fig.11A], [Fig.11B], [Fig.12A], [Fig.12B], [Fig.13A], [Fig.13B], [Fig.14A], [Fig.14B], [Fig.15A], [Fig.15B], [Fig.10A] and [Fig.10B] are views illustrating steps of an example of a manufacturing process for the electronic chip illustrated in Figures IA, IB and IC;

[0017] [Fig. 17A] and [Fig. 17B] are partial and schematic views of an example of an electronic device according to a second embodiment; and

[0018] [Fig.18A] and [Fig.18B] are partial and schematic views of an example of an electronic device according to a third embodiment. Description of the implementation methods

[0019] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0020] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0021] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0022] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0023] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0024] Figures IA, IA, and IA are partial, schematic cross-sectional views of an example of an electronic device according to a first embodiment. More specifically, Figures IA and IA are vertical cross-sectional views of said device, and Figure IA is a horizontal cross-sectional view of said device. Figure IA corresponds to a view along section plane AA of Figure IA, Figure IAB to a view along section plane BB of Figure IA, and Figure IA to a top view along horizontal section plane CC of Figures IA and IAB. Note that in Figure IA, some of the elements are shown in transparency.

[0025] In particular, [Fig. 1A], [Fig. 1B], and [Fig. 1C] illustrate a memory circuit of the electronic device 11. By way of example, the electronic device 11 includes, in a portion not shown, a logic circuit. The logic and memory circuits are, for example, fabricated simultaneously in and on the same semiconductor substrate.

[0026] Device 11 is, for example, an electronic chip.

[0027] The device 11 includes a semiconductor substrate 13. By way of example, the substrate 13 is made of silicon or silicon-based.

[0028] The substrate 13 comprises, for example, a semiconductor layer 15 doped with a first type of conductivity, for example of type N, for example doped with arsenic or phosphorus atoms. The layer 15 rests, for example, on, and is, for example, in contact with, another semiconductor layer 17 of the substrate 13 doped with a second type of conductivity, opposite to the first type of conductivity, for example of type P, for example doped with boron atoms.

[0029] The substrate 13 comprises, for example, a semiconductor layer 25. The layer 25 rests, for example, on the layer 15 and is, for example, in contact with it. Thus, the layer 25 is separated from the layer 17 by the layer 15. The layer 25 is, for example, flush with an upper face of the substrate 13. The semiconductor layer 25 is, for example, a layer formed by epitaxy from the upper face of the layer 15. The layer 25 is, for example, made of silicon, for example, single-crystal silicon. The layer 25 comprises, for example, a plurality of regions 27 and regions 29. In the embodiment shown in Figures IA to IC, the regions 27 extend longitudinally as lines in a first direction, and the regions 29 extend longitudinally as lines in the same first direction. As an example, regions 27 and 29 extend in the direction of the plane of [Fig.1B].Substrate 13 thus comprises, in the example of figures IA to IC, lines comprising an alternation of regions 27 and 29 extending in the first direction.

[0030] Each region 27 or 29 preferably extends over the entire height of the layer 25. Each region 27 or 29 thus lies flush with the upper face of the layer 25. Each region 27 or 29 is, for example, in contact, by its lower face, with the layer 15.

[0031] Regions 27 are, for example, doped with the second type of conductivity, for example, type P. As an example, regions 27 contain germanium and boron atoms. Regions 27 are, for example, more heavily doped than layer 17.

[0032] Regions 29 are, for example, doped with the first type of conductivity, for example, type N. As an example, regions 29 contain phosphorus atoms. Regions 29 are, for example, more heavily doped than layer 15.

[0033] The device 11 comprises a plurality of transistors 12 formed in and on the substrate 13. Each transistor 12 comprises, for example, a single region 27 and a single region 29 of substrate 13.

[0034] The transistors 12 are, for example, separated from each other and are, for example, electrically isolated by insulating trenches 14. The insulating trenches 14 are, for example, shallow trench insulation (STI). The trenches 14 are, for example, divided into two categories: trenches 14a extending longitudinally in the first direction and trenches 14b extending longitudinally in the second direction. As an example, isolation trenches 14a and 14b form, in top view, a grid.

[0035] The insulating trenches 14 extend, for example, from a face located at an intermediate level between the upper and lower faces of the layer 25. The trenches 14 preferably extend into a portion of the layer 25, into the layer 15, and into a portion of the layer 17. The insulating trenches 14 are, for example, filled with a dielectric material, for example, silicon oxide. The trenches 14a and 14b have, for example, the same depth. The depth of the trenches 14 is, for example, between 250 nm and 400 nm.

[0036] The transistors 12 are thus arranged in a matrix inside the grid formed by the trenches 14. The substrate 13 thus comprises rows and columns of transistors 12.

[0037] Each transistor 12 is contained within an elementary memory cell. Each memory cell further comprises a memory element M, preferably formed at least partially opposite said transistor 12, for example opposite region 27 of said transistor 12. Regions 29, unlike regions 27, are not, for example, surmounted by memory elements M. By way of example, within each memory cell, transistor 12 is a selection transistor for the memory element M.

[0038] The memory elements M are, for example, organized, in top view, according to a matrix of rows and columns. These are referred to respectively as wordlines extending in the second direction, i.e., the direction of trenches 14b, and bitlines extending in the first direction, i.e., the direction of trenches 14a. By way of example, each memory element M is located at the intersection of a bitline and a wordline. For example, the memory elements M illustrated in [Fig. 1B] are memory elements M of the same wordline WL, while the memory elements illustrated in [Fig. 1A] are memory elements of the same bitline BL. In [Fig. 1B], only six bitlines are shown, and in [Fig. 1A] only three wordlines are shown.However, in practice, a memory circuit may comprise a different number of bit lines and word lines, for example greater than six and three respectively.

[0039] By way of example, each isolation trench 14b extends longitudinally in the direction of the word lines, along the entire length of the word lines. By way of example, each isolation trench 14a extends longitudinally in the direction of the bit lines, along the entire length of the bit lines. The transistor matrix 12 corresponds substantially to the memory element matrix M.

[0040] In the example of Figures IA to IC, each transistor 12 is defined by layer 17, regions 27, and regions 29 connected to layer 15. In this example, the Region 27 constitutes an emitter region of transistor 12, layer 15 constitutes a base region of transistor 12, region 29 constitutes a base access region of transistor 12, and layer 17 constitutes a collector region of transistor 12. For example, the collector is common to all transistors 12 in the matrix and is, for instance, connected to ground. In this example, the base region 15 is common to all transistors 12 in the same word row of the memory circuit.

[0041] The transistors 12 are, for example, bipolar junction transistors (BJTs), of the PNP type.

[0042] The device 11 includes an insulating layer 18 covering the upper face of the semiconductor substrate 13 and more specifically the upper face of the layer 25. The insulating layer 18 is, for example, in contact with the upper face of the layer 25. The insulating layer 18 covers, for example, the entire upper face of the layer 25. The insulating layer 18 has, for example, a thickness between 80 nm and 300 nm, for example between 120 nm and 200 nm.

[0043] The device 11 further includes isolation structures or trenches 16. The trenches 16 are, for example, single diffusion break (SDB) trenches. The trenches 16 extend, for example, in layer 25, separating region 27 and region 29 of each transistor 12. In other words, regions 27 and 29 of each transistor 12 are separated by a trench 16. By way of example, each trench 16 extends longitudinally in the direction of the word lines, for example, along the entire length of the word lines.

[0044] Each trench 16 is for example located between two trenches 14b. Thus, the substrate 13 comprises, in the direction of the bit lines, an alternation of trenches 14b and trenches 16.

[0045] Each insulation trench 16 has an upper part 16s extending vertically into the insulating layer 18 and a lower part 16i extending vertically into the semiconductor substrate 13.

[0046] The lateral faces of the upper portion 16s of each insulation trench 16 are covered by spacers 21 made of a second dielectric material. The spacers 21 are, for example, made of an electrically insulating material, such as silicon nitride. By way of example, the upper portion 16s of each trench 16 includes a lower portion in which the flanks of the surrounding spacer 21 are in contact with the layer 25, and more specifically with regions 27 and 29. By way of example, the lower face of each spacer 21 rests on the upper face of the layer 15, for example, between regions 27 and 29.

[0047] The lower part 16i of the trenches 16 extends into the layer 15 from the upper face of the layer 15. By way of example, the lower part 16i of the trenches 16 does not extend into the layer 17.

[0048] The lateral faces of the lower part 16i of each insulation trench 16 are not covered by spacers and the insulation trench 16 is, in this part, directly in contact with the layer 15 of the substrate 13.

[0049] By way of example, the trenches 16 extend less deeply than the trenches 14. The trenches 16 extend, for example, from a face located at an intermediate level between the upper and lower faces of the layer 18. The insulation trenches 16 are, for example, filled with a dielectric material, for example, silicon oxide. The trenches 16 have, for example, a height or depth (measured between the upper and lower faces of the trenches 16) of between 50 nm and 150 nm.

[0050] Layer 18 is, for example, traversed by vias 20 and 22. Vias 20 and 22 are, for example, in contact, by their lower faces, with the upper face of layer 25 so that each region 27 and 29 is surmounted by a via 20 or 22. By way of example, vias 20 are in contact with regions 27. By way of example, vias 22 are in contact with regions 29. Vias 20 and 22 extend, for example, over the entire height of layer 18. Vias 20 and 22 thus extend from the upper face of layer 18 to the lower face of layer 18.

[0051] The layer 18 is for example surmounted by an interconnect stack 35. In this example, the interconnect stack 35 is formed between the substrate 13 and the memory elements M. The interconnect stack 35 is for example formed on the upper face of the insulating layer 18 and covers for example the entire surface of the insulating layer 18.

[0052] The interconnection stack 35 is, for example, formed of a succession of levels 36, each level 36 comprising an insulating layer 37 and an insulating layer 39. The interconnection stack 35 includes, for example, a level 36a, comprising an insulating layer 39a formed on and in contact with the upper face of the insulating layer 18. The interconnection stack 35 further includes, in level 36a, an insulating layer 37a formed on the insulating layer 39a. The insulating layer 37a is, for example, formed over the entire surface of the insulating layer 39a. By way of example, the insulating layer 37a is in contact, by its lower face, with the upper face of the insulating layer 39a.

[0053] The interconnect stack 35 may further comprise additional levels formed on the level 36a, i.e., on and in contact with the insulating layer 37a. In Figures IA and IB, the interconnect stack 35 comprises two additional levels 36b and 36c, for example, formed respectively from layers 37b and 39b and layers 37c and 39c. In practice, the number of levels in the interconnect stack 35 may be different from three, for example, greater than three.

[0054] By way of example, the interconnect stack 35 has a thickness between 200 nm and 800 nm, for example between 250 nm and 600 nm, for example on the order of 350 nm.

[0055] By way of example, the insulating layers 18 and 37 are made of a material with a low dielectric constant, for example, a material having a dielectric constant (corresponding to the permittivity of said material relative to the permittivity of free space) of less than 5, for example, less than 4. The insulating layers 37 are, for example, made of SiCN. By way of example, the insulating layers 39 are made of a low-permittivity oxide, known as "low k" or "ultra low k".

[0056] Each level 36 comprises conductive vias 69 and conductive tracks 71, the tracks 71 extending into layer 39, for example, from the top face of layer 39, thus being flush with the top face of layer 39. Preferably, the tracks 71 of a level 36 extend exclusively within layer 39 of said level 36. The vias 69 of a level of the stack 35 extend through layer 39 and through layer 37 of that same level 36. More precisely, the vias 69 of a level of the stack 35 extend from the bottom face of a track 71 of the same level to the bottom face of layer 37 or to the top face of a via 20 or 22 traversing layer 18.

[0057] The vias and conductive tracks 71 and 69 are, for example, made of a metallic material, for example copper. By way of example, the conductive tracks 71 extend laterally over an area between 20 nm by 20 nm and 60 nm by 60 nm, for example on the order of 30 nm by 30 nm. By way of example, the conductive tracks 71 extend laterally over an area greater than or equal to the area of ​​the vias 69.

[0058] In the embodiment shown in Figures IA to IC, the memory elements M are formed on the upper face of the stack 35. By way of example, the memory elements M are separated from the stack 35 by an insulating layer 45. The insulating layer 45 is, for example, made of silicon nitride, SiCN, an oxide, or a combination of several of these materials, for example, a combination of SiCN and an oxide. The layer 45 is, for example, in contact, via its lower face, with the upper face of the layer 39c. The layer 45 is also in contact, via its upper face, with the lower face of the memory elements M.

[0059] By way of example, the memory elements M are phase-change memory elements. By way of example, each element comprises a layer 47 made of a phase-change material, for example, a chalcogenide material, for example, a germanium-antimony-tellurium (GeSbTe) alloy, known as GST. The layer 47 has, for example, a thickness between 30 nm and 100 nm, for example, on the order of 50 nm. The memory elements M of the same bit row comprise, for example, a common layer 47. Thus, the device 11 comprises, for example, as many of layer 47 than of bit lines. Each layer 47 thus extends in the direction of the bit lines.

[0060] In each memory element M, the phase-change material is, for example, controlled by a metallic heating resistive element 49 located beneath the phase-change material. The element 49 is, for example, in contact, via its upper face, with the lower face of the layer 47. The element 49 is, for example, laterally surrounded by a layer of thermal insulation 51. For example, each element 49 has an "L" shape in the cross-sectional plane of [Fig. 1A]. By way of example, the layer 51 is made of nitride. By way of example, the heating element 49 has, for example, a height between 30 nm and 100 nm, for example, on the order of 60 nm.

[0061] Layer 47 is, for example, surmounted by a layer 53, for example made of a conductive material, for example made of a metallic material. More precisely, the upper surface of each layer 47 is, for example, at least partially covered, for example completely covered, by a layer 53. Each layer 53 preferably extends, in the direction of the bit lines, over the entire length of layer 47.

[0062] By way of example, in each memory element M, the metallic element 49 and the layer 53 form, respectively, a lower and an upper electrode of the memory element M, and more precisely, electrodes of the resistive element with variable resistance formed by the layer 47 in the phase-change material. By way of example, the memory elements M of the same bit row are surmounted by the same layer 53. In other words, the upper electrodes 53 of the memory elements M of the same bit row are interconnected.

[0063] Each memory element M is, for example, covered by an insulating layer 55 protecting, for example, layer 47 of the phase-change material from oxidation. By way of example, layer 55 covers the upper face of layer 53 and the sides of layers 53, 47, and 51. Layer 55 is, for example, made of a dielectric material. The insulating layer 55 is, for example, made of a nitride, for example, silicon nitride.

[0064] The memory elements M of adjacent bit lines are, for example, isolated from each other by an insulating layer 59. The insulating layer 59 is, for example, made of a material having a low dielectric constant. Alternatively, the layer 59 is made of an oxide, for example silicon dioxide.

[0065] Thus, in the embodiment of figures IA to IC, each memory element M is electrically connected to the selection transistor 12 to which it is associated by means of a conductive via 63 passing through all levels of the interconnect stack 35. By way of example, the via 63 passes through all the insulating layers 37 and 39 of the interconnect stack 35 located between layer 45 and layer 18.

[0066] By way of example, the via 63 associated with each memory element M is in contact, by its upper face, with the lower face of the heating resistive element 49 of the memory element M. The via 63 is for example in contact, by its lower face, with a conductive via 22, itself in contact with the upper face of the region 27 of the transistor 12 associated with the memory element M. In other words, for each memory element M, the corresponding via 63 electrically connects the heating element 49 of the memory cell to the underlying region 27.

[0067] The via conductor 63 is, for example, made of a metallic material. The via conductor 63 is, for example, made of tungsten. Alternatively, the via conductor is made of cobalt or copper. The via conductor 63 has, for example, a width, measured in the plane of [Fig. 1A] and in the plane of [Fig. 1B], of between 20 nm and 100 nm, for example on the order of 40 nm.

[0068] By way of example, the vias 69 extend, under layer 47, outside the memory circuit to be connected to it and to be able to apply potentials to the word lines of the memory elements M.

[0069] By way of example, layer 53 is connected, by its upper face, to a conductive element in order to be able to apply potentials to the bit lines of the memory elements M.

[0070] Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 7D, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 1OA, Fig. 9B, Fig. 1OA, Fig. 1OB, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 10A and Fig. 10B are views illustrating steps in an example of a manufacturing process for the electronic device in Figures IA, IB and IC.

[0071] More specifically, Figures 2 to 16B are views illustrating a method for simultaneously manufacturing, or co-integrating in the same integrated circuit device, the memory circuit of chip 11 shown in Figures 1A to 16B, comprising bipolar selector transistors, and a logic circuit, for example adjacent to the memory circuit, comprising fin field-effect transistors (FinFETs). Figures 2 to 16B show two regions a) and b) of the device in which two bipolar selector transistors and two FinFETs are formed, respectively. It will be understood that in practice, region a) may contain more than two bipolar selector transistors and region b) may contain more than two FinFETs.

[0072] Figure 2 illustrates, by means of a partial schematic cross-sectional view, a starting structure comprising the semiconductor substrate 13. In Figure 2, the substrate 13 comprises the first region a) in and on which a FinFET transistor is formed during of the process described below and the second region b) in and on which a bipolar selection transistor is formed during the process described below.

[0073] [Fig.3] illustrates, by a partial and schematic cross-sectional view, a structure obtained at the end of a trenching step 60 in the first region a) of the substrate 13 of [Fig.2].

[0074] The formation of the trenches 60 allows the fins of the FinFET transistors to be defined between the trenches 60. As an example, the trenches 60 extend in the direction of the bit lines, that is to say in the direction orthogonal to the direction of the cutting plane of [Fig.3].

[0075] The trenches 60 extend for example into the substrate 13, from the upper face of the substrate 13.

[0076] By way of example, the trenches 60 do not have, in cross-section, a rectangular shape with their bottom orthogonal to the lateral faces. The trenches 60 have, for example, in cross-section, a trapezoidal shape in which the width of the trenches 60 at the top face of the trenches 60 is greater than the width of the trenches 60 at the bottom face of the trenches 60. By way of example, the trenches have a spacing of between 20 nm and 100 nm, for example, between 30 nm and 50 nm. By way of example, the trenches 60 have a width, measured at the top face of the substrate 13, of between 10 nm and 90 nm, for example, between 20 nm and 40 nm. As an example, trenches 60 extend over a depth of between 20 nm and 400 nm, for example between 100 nm and 200 nm, for example on the order of 150 nm.The 60 trenches define the fins of the transistors which have, for example, a width between 2 nm and 30 nm, for example between 5 nm and 15 nm, for example between 7 nm and 8 nm.

[0077] Fig. 4 illustrates, by a partial and schematic cross-sectional view, a structure obtained after a step of depositing a layer 62 on the upper face of the structure illustrated in Fig. 3.

[0078] More particularly, during this step, the layer 62 is deposited on the upper face of the substrate 13 and in the trenches 60. By way of example, during this step, the layer 62 completely covers the upper face of the substrate 13. The layer 62 is, for example, a layer of a dielectric material, for example, an oxide.

[0079] Fig. 5 illustrates, by a partial and schematic cross-sectional view, a structure obtained after a step of removing layer 62 from an upper part of the structure illustrated in Fig. 4.

[0080] More specifically, initially, layer 62 is removed from the upper surface of the substrate 13 so as to expose the upper surface of the substrate 13. This removal is carried out, for example, by chemical-mechanical removal or polishing (CMP, of (English "Chemical Mechanical Polishing"). The removal of layer 62 is stopped, for example, when the upper face of the substrate 13 is exposed.

[0081] In a second step, during this stage, the layer 62 is removed from an upper part in the trenches 60 so as to retain the layer 62 only in a lower part of the trenches 60. This removal is carried out for example over a depth of between 10 nm and 100 nm, for example on the order of 50 nm.

[0082] [Fig.6] illustrates, by a partial and schematic cross-sectional view, a structure obtained at the end of a trench formation step 14b in the substrate 13 of [Fig.5].

[0083] The trenches 14b are, for example, formed in the substrate 13 by extending, in the substrate 13, from the upper face of the substrate 13. By way of example, the trenches 14b extend to a greater depth than the depth of the trenches 60. The trenches 14b are, for example, formed in the substrate 13 in the first a) and the second b) region of the substrate 13. By way of example, the trenches 14b make it possible to isolate, for some located in the memory circuit, the neighboring bit lines and to isolate, for others located between the logic circuit and the memory circuit, the logic circuit from the memory circuit.

[0084] Figures 7A, 7B, 7C and 7D illustrate, by means of partial and schematic views, a structure obtained at the end of a trench formation step 14a in the substrate 13 of [Fig. 6]. More particularly, Figures 7B, 7C and 7D are cross-sectional views, and [Fig. 7A] is a top view of the structure obtained at the end of the trench formation step 14a in the substrate 13 of [Fig. 6], [Fig. 7B] being a cross-sectional view along the section plane BB of [Fig. 7A], [Fig. 7C] being a cross-sectional view along the section plane CC of [Fig. 7A] and [Fig. 7D] being a cross-sectional view along the section plane DD of [Fig. 7A]. Fig. 7C also corresponds to a cross-sectional view in the first region a) of substrate 13 and Fig. 7D corresponds to a cross-sectional view in the second region b) of substrate 13.

[0085] The trenches 14a are, for example, formed in the substrate 13 by extending, in the substrate 13, from the upper face of the substrate 13. By way of example, the trenches 14a extend to a greater depth than the depth of the trenches 60. The trenches 14a are, for example, formed in the substrate 13 in the first a) and the second b) region of the substrate 13. By way of example, the trenches 14a make it possible to isolate the neighboring word lines. For example, a single trench 14a may extend into both the first region a) of substrate 13 and the second region b) of substrate 13. Alternatively, a single trench 14a may extend only into the first region a) of substrate 13 or only into the second region b) of substrate 13. As a further alternative, a single trench 14a may extend over only a portion only from the first region a) of substrate 13 and / or on only a portion of the second region b) of substrate 13.

[0086] By way of example, the formation of the trenches 14 includes a preliminary step of depositing a protective layer, for example a nitride layer, allowing the structure to be protected in areas not containing trenches 14. By way of example, after the formation of the trenches 14a and 14b, they are, for example, filled with a semiconductor material. By way of example, the trenches 14a and 14b are filled with an oxide. The step of filling the trenches 14a and 14b is, for example, followed by a CMP step stopping at the upper surface of the aforementioned protective layer. By way of example, where appropriate, after the CMP step, the protective layer is removed so as to expose the upper surface of the substrate 13.

[0087] Although it has been described in the present embodiment that the trenches 14a and 14b are filled with the dielectric material in a single step, it can be envisaged that the filling of the trenches 14b will be carried out, at the end of the step illustrated in [Fig.6], before the formation of the trenches 14a.

[0088] Furthermore, although it has been described in the present embodiment that trenches 14b are made before trenches 14a, it can be envisaged that the order of making these trenches is reversed and that trenches 14a are made before trenches 14b.

[0089] By way of example, although not shown, following the formation of trenches 14a and 14b, the structure is covered by a layer of a dielectric material, for example an oxide. The oxide layer thus covers the upper face of the substrate 13 in the first a) and second regions, the upper face of trenches 14a and 14b, the upper face of layer 62 in trenches 60, and the sides of trenches 60 above layer 62.

[0090] Figures 8A and 8B illustrate by partial and schematic cross-sectional views a structure obtained at the end of a formation step of layers 15 and 17 in the second region b) of the substrate 13 of the structure illustrated in Figures 7A to 7D.

[0091] In particular, [Fig.8A] illustrates a cross-sectional view along a cutting plane identical to that of [Fig.7C], i.e. a cut in region a) of the substrate 13 where the FinFET transistors are formed and [Fig.8B] illustrates a cross-sectional view along a cutting plane identical to that of [Fig.7D], i.e. a cut in region b) of the substrate 13 where the bipolar selection transistors are formed.

[0092] By way of example, during this step, the substrate 13 is doped so as to create, in an upper part of the substrate 13, the layer 15 doped with type N and, in a lower part of the substrate 13, the layer 17 doped with type P. By way of example, the implantation is, during this step, carried out so that the junction between the layer 15 and the layer 17 is less deep than the trenches 14a and 14b.

[0093] By way of example, this step is carried out only in the second region b) of the substrate 13. The first region a) of the substrate 13 does not include, after this step, layers 15 and 17.

[0094] Figures 9A and 9B illustrate by partial and schematic cross-sectional views a structure obtained at the end of a step of formation of sacrificial grids 67 on the surface of the structure illustrated in figures 8A and 8B.

[0095] More specifically, during this step, sacrificial grids 67 are formed on the upper surface of the substrate 13 in the first region a) and in the second region b). The grids 67 comprise, for example, a so-called sacrificial material. By way of example, the grids 67 comprise a semiconductor layer, for example, of polycrystalline silicon. By way of example, the grids 67 further comprise, on the semiconductor layer, a dielectric layer, for example, of silicon nitride.

[0096] The grids 67 are for example formed by depositing the aforementioned layers on a full plate before being engraved.

[0097] Figures 10A and 10B illustrate by partial and schematic cross-sectional views a structure obtained at the end of a step of forming spacers 21 and 68 on the structure illustrated in figures 9A and 9B.

[0098] More particularly, during this step, spacers 68 are formed on the first region a) of the substrate 13 illustrated in [Fig.9A] and spacers 21 are formed on the second region b) of the substrate 13 illustrated in [Fig.9B], the formation of spacers 68 being illustrated in [Fig.1OA] and the formation of spacers 21 being illustrated in [Fig.1OB].

[0099] By way of example, the spacers 68 and 21 are formed in a single step by depositing a layer on the upper face of the structure illustrated in Figures 9A and 9B. During this step, said layer covers the upper face of the substrate 13 in the first a) and second b) regions and the sides and the upper face of the grids 67.

[0100] Alternatively, the spacers 68 and 21 are formed in two successive steps. For example, the spacers 68 can be formed by depositing a layer on the upper face of the substrate 13 while the second region b) is masked. The spacers 21 are similarly formed by depositing a layer on the upper face of the substrate 13 while the first region a) is masked.

[0101] By way of example, on the upper face of the substrate 13, the layer or layers forming the spacers 68 and 21 are, for example, at the end of this step, removed so as to be kept only in contact with the grids 67.

[0102] Figures 1 IA and 1 IB illustrate by partial and schematic cross-sectional views a structure obtained at the end of a step of formation of regions 70 and 29 on and in the substrate 13 of the structure illustrated in Figures 10A and 10B.

[0103] More particularly, during this step, regions 70 are formed in the first region a) of substrate 13 illustrated in [Fig.1OA] and regions 29 are formed in the second region b) of substrate 13 illustrated in [Fig.1OB], the formation of regions 70 being illustrated in [Fig.1IA] and the formation of regions 29 being illustrated in [Fig.1IB].

[0104] By way of example, regions 70 and 29 are formed by epitaxy and then by implantation of N-type dopant atoms. Regions 70 and 29 have, for example, their upper faces offset with respect to the upper face of the substrate 13. By way of example, the upper face of regions 70 and 29 is in front of the upper face of the substrate 13, opposite the grids 67.

[0105] The regions 70 extend, for example, longitudinally between grids 67 and between grids 67 and trenches 14a. The regions 29 extend, for example, between grids 67 and trenches 14a only on one of the two sides of each grid 67.

[0106] By way of example, regions 70 and 29 are formed in a single step. Alternatively, regions 70 and 29 are formed in two successive steps.

[0107] By way of example, regions 70 correspond to the future source and drain regions of FinFET NMOS transistors. In such a structure, the drain of one transistor corresponds to the source of the neighboring transistor.

[0108] Figures 12A and 12B illustrate by partial and schematic cross-sectional views a structure obtained at the end of a formation step of regions 72 and 27 on and in the structure illustrated in Figures 11A and 11B.

[0109] More particularly, during this step, regions 72 are formed in the first region a) of substrate 13 illustrated in [Fig. 11 A] and regions 27 are formed in the second region b) of substrate 13 illustrated in [Fig. 11 IB], the formation of regions 72 being illustrated in [Fig. 12A] and the formation of regions 27 being illustrated in [Fig. 12B].

[0110] By way of example, regions 72 and 27 are formed by epitaxy and then by implantation of P-type dopant atoms. Regions 72 and 27 have, for example, their upper faces offset with respect to the upper face of the substrate 13. By way of example, the upper face of regions 72 and 27 is forward with respect to the upper face of the substrate 13.

[0111] The regions 72 extend, for example, longitudinally between grids 67 and between grids 67 and trenches 14a. The regions 27 extend, for example, between grids 67 and trenches 14a only on one of the two sides of each grid 67.

[0112] By way of example, regions 72 and 27 are formed in a single step. Alternatively, regions 72 and 27 are formed in two successive steps.

[0113] By way of example, regions 72 correspond to the future source and drain regions of FinFET PMOS transistors. In such a structure, the drain of one transistor corresponds to the source of the neighboring transistor.

[0114] By way of example, following the steps in Figures 11 and 12, in and on the first region a) of the substrate 13, areas extending between two trenches 14a have their gates 67 surrounded only by regions 70 so as to form NMOS or N-channel metal-oxide-semiconductor transistors. Similarly, by way of example, following the steps in Figures 11 and 12, in and on the first region a) of the substrate 13, areas extending between two trenches 14a have their gates 67 surrounded only by regions 72 so as to form PMOS or P-channel metal-oxide-semiconductor transistors.

[0115] As an example, at the end of the steps in Figures 11 and 121, the grids 67 are, in and on the second region b), surrounded on the one hand by regions 29 and on the other hand by regions 27.

[0116] Figures 13A and 13B illustrate by partial and schematic cross-sectional views a structure obtained after a step of forming a layer 74 on the upper face of the structure illustrated in Figures 12A and 12B and a step of polishing the structure thus obtained.

[0117] More particularly, during this step, we first form layer 74 on the upper face of the structure illustrated in figures 12A and 12B by covering the upper face of the substrate 13, in its first a) and second b) region, the upper faces of regions 70, 72, 27 and 29 and the grids 67.

[0118] In a second step, the structure thus obtained undergoes CMP so as to remove an upper part of layer 74 and reveal the upper face of the grids 67. During this step, an upper part of the spacers 68 and 21 is also removed along with layer 74. At the end of this step, the spacers remain only on the sides of the grids 67. At the end of this step, the upper face of the grids 67 is flush with the upper face of layer 74.

[0119] Figures 14A and 14B illustrate by partial and schematic cross-sectional views a structure obtained after a step of removing the sacrificial grids 67 from the structure illustrated in Figures 13A and 13B and filling the openings thus formed with a layer 76.

[0120] More specifically, during this step, the material constituting the grids 67 is initially removed. Openings are then created in the layer 74, surrounded by the spacers 68 and 21 and leading to the upper face of the substrate 13. The grids 67 are thus said to be "emptied".

[0121] In a second step, a layer 76 is deposited on the upper surface of the structure thus formed. By way of example, the layer 76 is deposited on the upper surface of the structure so that the openings formed in place of the grids 67 are filled by the layer 76. The layer 76 is, for example, a layer of a metallic material, for example titanium nitride, tantalum nitride and / or Tungsten. For example, layer 76 comprises several sublayers of one or more of the aforementioned materials. For example, the deposition of layer 76 in the openings formed in place of grids 67 is preceded by a deposition step, in these same openings, of an oxide and a dielectric material with high dielectric permittivity.

[0122] By way of example, at the end of this step, the structure undergoes a CMP step so as to reveal the upper face of layer 74 so that layer 76 remains only in the openings.

[0123] At the end of this step, layer 76 corresponds, in the openings of layer 74, to metallic grids 77.

[0124] Figures 15A and 15B illustrate by partial and schematic cross-sectional views a structure obtained at the end of a trench formation step 16 and 78 in the structure illustrated in Figures 14A and 14B.

[0125] More particularly, during this step, trenches 78 are formed in and opposite the first region a) of the substrate 13 illustrated in [Fig.14A] and trenches 16 are formed in and opposite the second region b) of the substrate 13 illustrated in [Fig.14B], the formation of trenches 78 being illustrated in [Fig.15A] and the formation of trenches 16 being illustrated in [Fig.15B].

[0126] During this step, trenches 78 and 16 are, for example, formed in place of some of the metal grids 77. More specifically, trenches 78 are, for example, formed in place of only some of the metal grids 77 of the first region a) of the substrate 13 and trenches 16 are formed in place of all the metal grids 77 of the second region b) of the substrate 13.

[0127] The trenches 78 and 16 are for example formed by removing the metallic material contained in the grids 77. At the end of the removal step, the openings thus created are, for example, extended in depth into the substrate 13, without opening into the layer 17. At the end of this step, the extended openings are filled with a dielectric material, for example an oxide.

[0128] The step of filling the openings with the dielectric material is for example followed by a CMP step so as not to leave any of the aforementioned material remaining on the upper face of the layer 74.

[0129] As an example, at the end of this step, trenches 16 and 78 correspond to single diffusion break (SDB) structures.

[0130] Trenches 16 and 78, for example, have the same depth.

[0131] Alternatively, trenches 16 and 78 have different depths.

[0132] By way of example, in the first region a) of the substrate 13, the trenches 78 isolate, in the left part of [Fig.15A], two FinFET NMOS transistors and in the right part of [Fig.15A], two FinEFT PMOS transistors.

[0133] Figures 16A and 16B illustrate by partial and schematic cross-sectional views a structure obtained after a step of removing layer 74 of the structure illustrated in Figures 15A and 15B and depositing the insulating layer 18 on the structure thus formed.

[0134] During this step, layer 74 is, for example, removed and insulating layer 18 is, for example, deposited on the upper face of the structure. By way of example, layer 18 is deposited opposite the first a) and second b) regions of the substrate 13.

[0135] [Fig.17A] and [Fig.17B] are partial and schematic sectional views of an example of an electronic device 211 according to a second embodiment, [Fig.17A] being a sectional view along section plane AA of [Fig.17B] and [Fig.17B] being a sectional view along section plane BB of [Fig.17A].

[0136] In particular, Figures 17A and 17B are views illustrating an electronic device 211 different from the device 11 illustrated in relation to Figures IA to IC, with the difference that, in device 211, the trenches 14a are not STI trenches but are so-called FIN trenches formed similarly to the trenches 60 defining the fins of FinFET transistors.

[0137] By way of example, the trenches 14a of device 211 are thus shallower than the trenches 14a of device 11. Furthermore, the trenches 14a of device 211 are, for example, narrower than the trenches 14a of device 11. In addition, the trenches 14a of device 211 have, for example, a greater repetition pitch than the repetition pitch of the trenches 14a of device 11. In this embodiment, the trenches define fins that have a width between 15 nm and 50 nm, for example between 20 nm and 30 nm, for example on the order of 25 nm. In this embodiment, the memory elements M are thus closer together in device 211 than in device 11.

[0138] Device 211 has, for example, a manufacturing process compatible with the manufacturing process of device 11 described in relation to Figures 2 to 16B, except that the trenches 14b are formed similarly to the trenches 60, for example, before, after, or at the same time as the trenches 60. The manufacturing process of device 211 also differs from the process described above in that the step described in relation to [Fig. 6] is omitted. By way of example, in this embodiment, layer 15 can extend deeper than the trenches 14a. Thus, the trenches 14a do not open into layer 17.

[0139] Fig. 18A and Fig. 18B are partial and schematic views of an example of an electronic device according to a third embodiment, Fig. 18A being a sectional view along section plane AA of Fig. 18B and Fig. 18B being a sectional view along section plane BB of Fig. 18A.

[0140] In particular, Figures 18A and 18B are views illustrating an electronic device 311 that differs from the device 11 shown in relation to Figures 1A to 1C in that, in device 311, there is no re-establishment of contact through traces 71 and vias 69 for each memory cell. Furthermore, in this embodiment, layers 47 and 53 extend in the direction of the word lines and the metal elements 49 extend in the direction of the bit lines. In addition, electronic device 311 differs from the device 11 shown in relation to Figures 1A to 1C in that the memory elements M are formed between the interconnect network 35 and the substrate 13. In this embodiment, layer 25 does not include an alternation of regions 27 and 29, and therefore there are no trenches 14b.

[0141] By way of example, in this embodiment, trenches 16 are present to separate two neighbouring regions 27 and to separate regions 27 from neighbouring regions 29.

[0142] An advantage of the present embodiment is that it allows the integration of FinFET transistors and bipolar selector transistors within a single electronic device, while remaining compatible with conventional manufacturing processes for FinFET and bipolar selector transistors. Indeed, the present embodiment allows the formation of trenches 16 in a bipolar selector transistor using steps present in the conventional manufacturing process for FinFET transistors.

[0143] Many applications are likely to benefit from the advantages provided by the electronic device 11, the electronic device 11 being able to be integrated into various types of devices.

[0144] By way of example, the electronic device 11 can be integrated into a device intended for the automotive industry. The electrification of motor vehicles is causing a sharp increase in the number of electronic components present in vehicles. The device includes, for example, thyristors, rectifiers, transient voltage suppression diodes, modules, etc., intended to be incorporated into said vehicles. Furthermore, driver assistance and driving automation are leading to an increase in the number of electronic components in vehicles. The device includes, for example, transient voltage suppression diodes, electrostatic discharge protection, and common-mode filters to protect the device against electrical hazards.

[0145] By way of example, the electronic device 11 can be integrated into a device intended for industrial use. In particular, the device is used, for example, for the development of green energy or for the electrification of infrastructure, for example, for charging stations or for solar energy collection. The device can also be used in the field of the Internet of Things or in the field of smart homes. The device is, for example, intended to be implemented in electrical power supply circuits for equipment, including, for example, 800 V or 1200 V thyristors, ultrafast 1200 V and silicon carbide diodes, transient voltage suppression diodes, and electrostatic discharge protection. The device can also be used for implementing cloud computing systems, 5G radio frequency communication networks, data centers, and servers. The device includes, for example, wide bandgap materials.

[0146] By way of example, the electronic device 11 can be integrated into a device intended for use in personal electronics, for example, to increase the volume of information exchanged via radio frequency communication, in 5G communication systems, or more generally in any connected device. The device is, for example, a mobile phone, or smartphone, or is part of an Internet of Things network. The device is, for example, connected via 5G, Wi-Fi, or broadband communication. The device includes, for example, high-speed interfaces, for example, with advanced filtering and protection against electrostatic discharge.

[0147] By way of example, the electronic device 11 can be integrated into a device intended for use in communication equipment, or in computers and peripherals. The device is used, for example, in 5G infrastructures and dedicated data centers. The device includes, for example, silicon carbide diodes, Schottky power transistors, electrostatic discharge protection devices, and transient voltage suppression diodes. The device can also be used in satellites, including, for example, integrated passive devices for radio frequency applications.

[0148] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the second and third embodiments illustrated in Figures 17A and 17B and in Figures 18A and 18B, respectively, are compatible.

[0149] Furthermore, although embodiments have been described in which the memory elements M are formed above the interconnect stack 35, the embodiments are not limited to this particular case. As an alternative, the memory elements M may be formed between the interconnect stack 35 and the substrate 13.

[0150] Furthermore, although an embodiment has been described in which regions 70 and 29 are realized in substrate 13 before regions 72 and 27, the realization of these regions can be reversed. Similarly, although a mode has been described In the implementation in which the trenches 14b are made in the substrate 13 before the trenches 14a, it is possible to reverse the execution of these trenches.

[0151] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic device (11; 211; 311) comprising: - a semiconductor substrate (13); - an insulating layer (18) covering the semiconductor substrate, on and in contact with the semiconductor substrate;and - a memory circuit comprising a plurality of memory cells, each comprising a bipolar selection transistor (12) disposed in and on the semiconductor substrate, each bipolar selection transistor comprising a base region (29, 15), an emitter region (27) and a collector region (17), in which each bipolar selection transistor comprises an insulation structure (16) of a first dielectric material, the insulation structure comprising an upper part (16s) extending vertically into the insulating layer (18) and a lower part (16i) extending vertically into the semiconductor substrate (13) between the base region (29) and the emitter region (27), the lateral faces of the upper part (16s) of the insulation structure (16) being covered by spacers (21) of a second dielectric material.;

2. A device according to claim 1, further comprising a logic circuit comprising a plurality of finned field-effect transistors arranged in and on the semiconductor substrate, each finned field-effect transistor comprising a source region (70, 72) and a drain region (70, 72), in which two neighboring finned field-effect transistors are separated by another isolation structure (78) in the first dielectric material, the isolation structure comprising an upper portion (78s) extending vertically in the insulating layer and a lower portion (78i) extending vertically in the semiconductor substrate between the drain region and the source region of the two neighboring transistors, the lateral faces of the upper portion (78s) of the isolation structure being covered by spacers (68) in the second dielectric material.

3. Device according to claim 2, wherein the isolation structures (16) of the memory circuit and the isolation structures (78) of the logic circuit have the same depth.

4. Device according to claim 2, wherein the isolation structures (16) of the memory circuit and the isolation structures (78) of the logic circuit have different depths.

5. Device according to any one of claims 1 to 4, wherein each memory cell comprises a memory element (M) having a layer (47) of a phase-change material.

6. Device according to any one of claims 1 to 5, wherein the memory circuit comprises an interconnect stack (35) disposed on the semiconductor substrate (13), comprising a succession of levels (36) in which interconnect elements (63, 69, 71) are defined.

7. Device according to claim 6 in its connection to claim 5, wherein the memory elements (M) are arranged above the interconnect stack (35).

8. A method for manufacturing, in and on a semiconductor substrate (13), an electronic device comprising a memory circuit comprising a plurality of memory cells, each comprising a bipolar selection transistor (12) formed in and on the semiconductor substrate, each bipolar selection transistor comprising a base region (29, 15), an emitter region (27) and a collector region (17), the method comprising the steps of: - forming sacrificial gates (67) in a sacrificial material on the semiconductor substrate (13); - forming spacers (21) in a dielectric material on the lateral faces of the sacrificial gates;- removal of sacrificial material in the sacrificial grids and etching of the substrate opposite the sacrificial grids so as to form openings surrounded in an upper part by the spacers and extending in a lower part into the substrate and filling of the openings with another dielectric material so as to form insulation structures (16) in the other dielectric material; and - formation of an insulating layer (18) on and in contact with the semiconductor substrate (13), the insulation structures thus comprising an upper part (16s) extending vertically into the insulating layer (18) and a lower part (16i) extending vertically into the semiconductor substrate (13) between the base region (29) and the emitter region (27) of the bipolar transistors; the lateral faces of the upper part (16s) of each insulation structure (16) being covered by the spacers (21).

9. A method according to claim 8, wherein the device further comprises a logic circuit, the logic circuit comprising a plurality of finned field-effect transistors each having a source region (70, 72) and a drain region (70, 72), the method comprising the steps of: - forming sacrificial grids (67) in a sacrificial material on the semiconductor substrate (13); - forming spacers (68) in the dielectric material on the lateral faces of the sacrificial grids; - removing the sacrificial material from the sacrificial grids and etching the substrate opposite the sacrificial grids so as to form openings surrounded in an upper part by the spacers and extending in a lower part into the substrate and filling the openings with the other dielectric material so as to form other insulating structures (78) in the other dielectric material;and - formation of the insulating layer (18) on and in contact with the semiconductor substrate (13), the other insulation structures thus comprising an upper part (78s) extending vertically into the insulating layer (18) and a lower part (78i) extending vertically into the semiconductor substrate (13) between the source region (70, 72) and the drain region of each finned field-effect transistor, the lateral faces of the upper part (78s) of the other insulation structure (78) being covered by the spacers (68).;

10. A method according to claim 9, wherein the steps of forming the isolation structures (16) of the memory circuit and the other isolation structures (78) of the logic circuit are common.

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