Process for preparing materials with a chalcopyrite structure

Abstract

A process for preparing a multilayer semiconductor system comprising the following steps: (a) depositing onto a single-crystal substrate a thin layer comprising a material containing at least one element from column IIIB and elements from column VB, referred to as IIIB-VB material, which material is epitaxially grown; (b) depositing onto the thin layer comprising the IIIB-VB material a metallic source of a d-block transition metal, preferably under an atmosphere of a chalcogen gas, preferably the chalcogen not being oxygen and preferably being sulfur; said metallic source of the d-block transition metal preferably comprising more than 99.9% of said transition metal expressed as a mass percentage relative to the total mass of said metallic source. Figure 1.

Description

Title of the invention: Process for preparing materials with a chalcopyrite structure

[0001] The present invention relates to the field of chalcopyrite structure materials, in particular those of formula Cu(In,Ga)S2, used in the form of thin film for their integration into electronic devices, and in particular but not exclusively, for integrated use in optoelectronic devices, such as photovoltaic devices. State of the art

[0002] Optoelectronic devices based on c-Si / CIGS stacks, i.e., optoelectronic devices comprising CIGS thin films on single-crystal silicon substrates, must not have interface defects between the different layers, and the material's strength must be reflected in high pull-out resistance. However, the synthesis of thin films of Cu(In,Ga)S2 chalcopyrite-structured materials, hereinafter referred to as (CIGS), on single-crystal silicon substrates, according to the most previously known prior art methods, presents primarily the disadvantages related to the lack of adhesion of the CIGS layer and the contamination of the substrate's silicon crystal by CIGS constituents during the growth of the CIGS thin film.This contamination of the silicon crystal ultimately disrupts the characteristics of the resulting optoelectronic systems and devices.

[0003] To overcome all or part of these drawbacks, the use of an intermediate thin layer of Al2O3 or In2O3:Sn between the Cu(In,Ga)S2 chalcopyrite and the silicon substrate is known, in particular, to increase the adhesion between the two layers. Alternatively, the use of an intermediate thin layer of III-V material can be carried out as described in the publication “Unveiling the role of copper content in the crystal structure and phase stability of epitaxial Cu(In,Ga)S2 films on GaP / Si(001)”, Mater Sci in Semicon Proc 166 (2023) 107685), with the introduction of an intermediate thin layer of GaP. More specifically, CIGS is deposited by an evaporation deposition technique onto a GaP / cSi pseudo-substrate. In other words, according to these prior art processes, the intermediate layer at the interface between silicon and CIGS is already synthesized before proceeding with the deposition of the CIGS layer, and remains intact at the end of the process.The residual presence of such interface layers between chalcopyrite and silicon has the disadvantage of disrupting the characteristics of optoelectronic devices using them.

[0004] The present invention aims, in particular, to improve the adhesion of the different layers of a multilayer semiconductor system, without having to use sublayers which cannot be eliminated or transformed, and whose presence disrupts the operation of said systems. Description of the invention

[0005] To overcome the drawbacks of the aforementioned prior art, the present invention relates to a method for preparing a multilayer semiconductor system, comprising the following steps: (a) deposit on a single-crystal substrate a thin layer comprising a material having at least one element of column IIIB and elements of column VB, referred to as IIIB-VB materials, which material is epitaxially grown; (b) deposit on the thin layer comprising the IIIB-VB material a metallic source of a d-block transition metal, preferably under an atmosphere of a gas composed of chalcogen, preferably the chalcogen is not oxygen and preferably it is sulfur; said metallic source of the d-block transition metal preferably comprising more than 99.9% of said transition metal expressed as a mass percentage relative to the total mass of said metallic source.

[0006] Further treatment of the stack obtained at the end of step (b) by application of a sulfur flux is advantageously carried out, in particular if step (b) is carried out without the presence of sulfur gas.

[0007] The inventors have demonstrated, in a completely unexpected manner, that the presence of an epitaxially grown IIIB-VB material on the single-crystal substrate makes it possible to obtain a stack constituting a multilayer semiconductor system comprising a IIIB-VB layer serving as a sacrificial layer, which is transformed during the implementation of said process. The addition of a transition metal such as copper, taken alone under a sulfur atmosphere to treat the c-Si / III-V stack induces the consumption of the III-V-based compound in favor of the formation of an M-IILS2, such as CuGaS2, largely preserving the crystalline quality of the thin film based on IILV epitaxially grown on silicon.The inventors have shown that the deposition of a metallic layer composed of one or more d-block metals, advantageously selected from one of the metals in the copper column, also known as IB column metals: Cu, Ag and Au; without concomitant deposition of other metallic elements, and in particular without concomitant deposition of IIIB and / or VB column metals, makes it possible to obtain a sacrificial layer.

[0008] The term material “IIIB-VB” is classically used under the designation “IILV” and either of these qualifications are used interchangeably within the framework of the invention.

[0009] In the context of the invention, the term "epitaxy" defines a technique for oriented growth, relative to each other, of two crystals possessing a certain number of common symmetry elements in their crystal lattices.

[0010] With regard to the preparation process described above in the context of the invention, steps (a) and (b) are independently carried out by a thin film deposition method selected from the following techniques: (i) Physical Vapor Deposition (PVD), preferably selected from vacuum co-evaporation, vacuum sputtering, and molecular beam epitaxy (MBE); (ii) Chemical Vapor Deposition (CVD), preferably selected from metalorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

[0011] The "molecular beam epitaxy" technique is a technique consisting of sending one or more molecular beams towards a pre-selected substrate, and is a technique of choice for achieving epitaxial growth. It allows the growth of nanostructured samples of several cm² at a rate of approximately one atomic monolayer per second.

[0012] Metal-organic vapor epitaxy is a crystal growth technique in which the elements to be deposited, in the form of metal-organic compounds or hydrides, are delivered to the single-crystal substrate by a carrier gas. This growth technique is particularly valued in the IILV semiconductor industry due to its good reproducibility and the high growth rates achievable.

[0013] Atomic Layer Deposition (ALD) is a thin film deposition process atomic. The principle consists of successively exposing a surface to different chemical precursors in order to obtain ultra-thin layers. It is used in the semiconductor industry.

[0014] Preferably, the single-crystal substrate implemented in step (a) is a single-crystal silicon substrate.

[0015] Preferably, at least one of the following characteristics is verified: the element of column IIIB of the IIIB-VB material implemented in step (a) is selected from at least one of the elements Ga, In and Al, preferably Ga, and the element of the The VB column of the IIIB-VB material is selected from at least one of the elements P, As, and Sb, preferably P; advantageously, the IIIB-VB material is selected from GaP, InP, GaAs, and InAs, preferably GaP. Thus, when the metallic layer implemented in step (b) is Cu, the exclusive co-evaporation of Cu and S causes the reaction between Cu2S and the GaP material to form the chalcopyrite CuGaS2, also known as "CGS".

[0016] Preferably, the transition metal of block d in step (b) is selected from the elements of column IB, and preferably the transition metal is selected from at least one of the metals Cu and Ag.

[0017] Preferably, the element in column IIIB of the IIIB-VB material is Ga; the element in column VB is P; the transition metal Mt is Cu.

[0018] Preferably, the process includes a treatment step (c), preferably a heat treatment by heating the layer stack to a temperature below 600°C and above 400°C for a duration of between 1 second and 1 hour, to react the metallic layer and the sulfur from step (b) with the IIIB-VB layer from step (a), preferably to obtain complete consumption of the IIIB-VB layer. When the IIIB-VB layer is GaP onto which a Cu deposit is applied, as described above, CGS is obtained. The CGS completely occupies the space initially occupied by the GaP layer, maintaining the same orientation. Remarkably, it is observed that the GaP layer is consumed by such a process according to the invention, to form epitaxially bonded CGS / Si stacks.Such a CuGaS2 (CGS, optical band gap of 2.4 eV) layer thus formed can advantageously serve as an absorber or selective layer for a Cu(In,Ga)S2 (CIGS) layer with a narrower band gap and suitable for the fabrication of tandem solar cells on silicon.

[0019] Preferably, the process includes an additional step (d) of chemical etching to remove the unreacted surface metallic residue; preferably, the chemical etching uses KCN when the transition metal is selected from Cu. Such etching typically removes Cu2S, Cu3PS4, and Cu7PS6 that were deposited on the surface during the growth of the CGS layer.

[0020] The present invention also relates to a multilayer semiconductor system obtained according to the process described above, comprising the following layers: (i) a single-crystal substrate, preferably a single-crystal substrate of Si; (ii) a layer of material M(L)Sx, M being a metal from block d, L an element of column IIIB.

[0021] Preferably said material M(L)SX of the multilayer semiconductor system is Cu(Ga)S2 qualified as CGS.

[0022] The present invention also relates to a multi-junction solar cell containing one or more tunnel junctions, or any other system enabling electrical connection between two sub-cells, comprising a multi-layer semiconductor system as previously presented in the context of the invention.

[0023] The present invention also relates to a use of the multilayer semiconductor system as previously presented in the context of the invention: - in photovoltaic technologies such as solar cells or panels; - in transparent electronics; and - in display technologies such as liquid crystal displays, flat panel displays, plasma displays, touch screens; - in detection technologies, preferably implementing at least one optical sensor; and - in water dissociation technologies to produce hydrogen by electrolysis such as photoelectrochemical cells, or photovoltaic-electrochemical cells.

[0024] Said use of the multilayer semiconductor system being preferably carried out in a photovoltaic technology device comprising tandem photovoltaic cells on silicon.

[0025] The present invention is also described in the detailed description that follows, with reference to the experimental part which details certain embodiments by means of examples, given only by way of illustration and which should not be considered limiting, and the figures briefly described in the part that follows. Experimental section

[0026] Structure of the c-Si / GaP layer as starting material 1:

[0027] The sacrificial layer is an epitaxial layer of GaP deposited on a substrate of Si(001). Figure 1 (X-ray diffraction: Longitudinal scan in co / 20 of the GaP / Si structure, ordinate in arbitrary units) obtained by X-ray diffraction (XRD) shows the GaP(004) line next to the Si(004), indicating the presence of a thin crystalline GaP layer oriented along the GaP

[100]

[001] / / Si

[100]

[001] substrate. Figure 2 shows a surface morphological analysis by AFM (Atomic Force Microscopy), suggesting very low roughness (RMS = 2.1 nm). Figure 3 (ordinate in arbitrary units) shows the experimental X-ray reflectivity (XRR) profile, as well as its fitting by a Layer / GaP / Si type model, taking into account the presence of a very thin surface layer on the GaP surface. These data XRR analysis allows us to evaluate the thickness of the GaP layer and converges to a III-V thickness of 316 Å, for a surface layer thickness of 0.6 nm. Due to its thickness, this surface layer of unknown composition can be interpreted as a native GaP oxide. It should be noted that the thickness of this layer could vary; a priori, this would not affect the reaction mechanism described below. Indeed, if it is a native oxide, then a simple one-minute acid treatment in HCl (3.7%) is sufficient to remove it.

[0028] Reaction involving the consumption of GaP:

[0029] GaP reacts chemically with Cu2S. The evaporation of copper in the presence of sulfur vapor on GaP / Si results in a stacking of which, when analyzed by Raman scattering, the spectrum shown in [Fig. 4] (arbitrary unit on the y-axis) is revealed. This spectrum shows a sharp decrease in the intensity of the peaks associated with GaP after the addition of Cu +S. Conversely, we observe signature peaks of several ternary products, namely CuGaS2, Cu3PS4, and Cu7PS6. In this case, the Ga and P present in these three ternary products result from the consumption of the GaP layer. The chemical reactions involved and their associated Gibbs energies at 800 K are as follows: 2 CuzS 4- GaP 4- 2 S2 -» CuGaSz 4- Cu3PS4 (eq. 1) = -318 kj.mor1 4 Cu^S 4- GaP 4- 2 S2 -* CuGaS2 + Cu^PSg (eq.2) atfG°2(80QK) = -194 kj. mor1

[0030] The compounds Cu2S, Cu3PS4, and Cu7PS6 are chemically decomposed in solution by the action of KCN dissolved in water; it should be noted here that other solutions (HCl, (NH4)2S, etc.) can have the same effect on these copper compounds. After treatment with KCN in aqueous solution (0.3 M, 5 min), Cu2S, as well as Cu3PS4 and Cu7PS6 (products of the reaction with GaP), are no longer detected. Only the Raman peaks of CuGaS2 at 310 and 385 cm⁻¹ persist, demonstrating the effectiveness of KCN for the selective removal of Cu3PS4 and Cu7PS6.

[0031] Structure of c-Si / CGS resulting from the consumption of GaP by Cu+S and stripping of the Cu 2 S, Cu 3 PS 4 and Cu 7 PS 6 phases

[0032] Based on these chemical reactions, the c-Si / GaP is treated with an excess of Cu relative to the amount required to react with all the gallium atoms in the GaP. Before the evaporation of Cu and S, the 31.6 nm thick GaP is deoxidized by an acid treatment with HCl (3.7%) for 1 minute. After evaporation of Cu+S from the GaP, the layer undergoes an etching treatment. chemical reaction with KCN. The Raman spectra shown in [Fig. 5] (Raman spectra of GaP / Si and CuGaS2 resulting from the decomposition of GaP by reaction with Cu2S, ordered in arbitrary units) show that the peaks attributable to GaP have completely disappeared, leaving two characteristic peaks of CuGaS2. This allows us to determine that the GaP layer is completely decomposed. A cross-sectional image of this layer was observed by scanning electron microscopy (SEM) and is shown in [Fig. 6] (scanning electron microscopy image of a slice of a CuGaS2 layer resulting from the decomposition of GaP by reaction with Cu2S); this image illustrates the formation of a thin CuGaS2 layer perfectly adhering to c-Si, with a thickness of approximately 70 nm; The inventors have demonstrated that the thickness of this layer can be controlled from the initial thickness of the GaP layer (i.e. from the amount of gallium atoms available).Moreover, the inventors, through this study and its spectral analyses, demonstrate that the excess Cu provided by the treatment induces the formation of copper compounds exclusively on the surface of the CuGaS2 layer (otherwise the chemical stripping would have damaged the CuGaS2 layer), without altering the integrity of the c-Si.

[0033] An analysis by XRD, shown in [Fig.7] (X-ray diffraction: Longitudinal scan in co / 20 GaP / Si and CuGaS2 from the decomposition of GaP by reaction with Cu2S; ordered in arbitrary units), also demonstrates the disappearance of the peaks of GaP(004) in favor of a peak corresponding to the interplanar distance between the planes (008) of CuGaS2.

[0034] R é suit ats

[0035] Figure 8 schematically illustrates the different steps of conversion of epitaxially treated GaP into epitaxially treated CuGaS₂. 1 / Epitaxial treatment of GaP onto a c-Si substrate. 2 / Deposition of Cu⁺S, preferably by vapor phase co-evaporation under vacuum, and reaction with the GaP. Formation of CuGaS₂ from the GaP layer, as well as Cu₃PS₄ and Cu₇PS₆. 3 / Chemical etching with KCN and removal of the Cu₃PS₄ and Cu₇PS₆ phases. 4 / Obtaining an epitaxially treated CuGaS₂ layer adhered to the Si.

[0036] Table 1 reports the results obtained; [Table 1] Direct growth of CGS on Si Conversion of Cu2-xS / GaP / Si to CGS / Si Adhesion — + Oriented polycrystalline texture (112)(a) Oriented epicrystal texture (001)(b)

[0037] (a) Non-oriented or oriented (112); (b) Oriented crystal (001) or oriented epicrystal (001).

[0038] Extension of the conversion process to other III-V compounds containing In and As

[0039] The deposition of Cu2xS thin films on GaAs (lpm) / Si and on SLG (soda-lime glass); the characterization of the films by Raman spectroscopy is shown in [Fig. 9]. The Raman spectra of the raw GaAs films show the longitudinal and transverse optical phonons of GaAs at 268 and 291 cm⁻¹. On SLG, Cu2xS is revealed by a strong mode at 475 cm⁻¹. Conversely, not all the peaks in the spectrum of the Cu2xS / GaAs / Si stack can be explained solely by GaAs and Cu2xS. In particular, the distinct resonant Al mode of CGS at 310 cm⁻¹ is visible, showing that some of the GaAs reacted with the Cu2xS to form CGS. By analogy with the decomposition chemistry of Cu2 xS / GaP, the released As can form Cu-As-S ternaries. We propose a provisional indexing of the decomposition chemistry of Cu2 xS / GaP.We propose a provisional indexing of the strong mode at 385 cm-1 as being the tennantite compounds Cui2As4Si3. .

[0040] Similarly, Cu2xS reacts with InP(001) to form an In-containing chalcopyrite. The Raman spectra in [Fig. 10] for InP and Cu2xS / SLG show the Raman signature of InP at 302 and 342 cm⁻¹ and of Cu2xS at 475 cm⁻¹, respectively. On the other hand, the Cu2xS / InP structures exhibit the typical signature of CuInS₂ with the modes at 294 and 308 cm⁻¹ corresponding to chalcopyrite and CuInS₂ ordered as CuAu, and show no sign of Cu2xS. This demonstrates that Cu2xS reacts with InP to form a CuInS₂ compound. No sign of ternary compounds containing P is visible.

Claims

Demands

1. A method for preparing a multilayer semiconductor system, comprising the following steps: (a) depositing on a single-crystal substrate a thin layer comprising a material having at least one element of column IIIB and elements of column VB, referred to as IIIB-VB material, which material is epitaxially grown; (b) depositing on the thin layer comprising the IIIB-VB material a metallic source of a d-block transition metal, preferably under an atmosphere of a gas composed of chalcogen, preferably the chalcogen not being oxygen and preferably being sulfur; said metallic source of the d-block transition metal preferably comprising more than 99.9% of said transition metal expressed as a mass percentage relative to the total mass of said metallic source.

2. A preparation method according to claim 1, wherein steps (a) and (b) are independently carried out by a thin film deposition method selected from the following techniques: (i) physical vapor phase deposition, preferably selected from vacuum co-evaporation, vacuum sputtering, and molecular beam epitaxy; (ii) chemical vapor phase deposition, preferably selected from organometallic vapor phase epitaxy and the atomic thin film deposition process.

3. A preparation method according to any one of claims 1 or 2, wherein the single-crystal substrate implemented in step (a) is a single-crystal silicon substrate.

4. A preparation method according to any one of claims 1 to 3, wherein at least one of the following features is verified: the element of column IIIB of the material IIIB-VB is selected from at least one of the elements Ga, In and Al, preferably Ga, and the element of column VB of the material IIIB-VB is selected from at least one of the elements P, As and Sb, preferably P.

5. A preparation method according to any one of claims 1 to 4, wherein the transition metal from block d in step (b) is selected among the elements of column IB, and preferably the transition metal is selected from at least one of the metals Cu and Ag.

6. A preparation method according to any one of claims 1 to 4, wherein the element of column IIIB of the material IIIB-VB is Ga; the element of column VB is P; the transition metal Mt is Cu.

7. A preparation process according to any one of claims 1 to 6, wherein the process comprises a treatment step (c), preferably a heat treatment by raising the layer stack to a temperature below 600°C and above 400°C for a time between 1 second and 1 hour, to react the metallic layer and the sulfur of step (b) with the IIIB-VB layer of step (a), preferably to obtain complete consumption of the IIIB-VB layer.

8. A method for preparing a semiconductor system according to any one of claims 1 to 7, comprising an additional step (d) of chemical etching to remove the surface metallic residue which has not reacted, preferably the chemical etching employs KCN when the transition metal is selected from Cu.

9. Multilayer semiconductor system obtained according to a process according to any one of claims 1 to 8, comprising the following layers: (i) a single-crystal substrate, preferably a single-crystal substrate of Si; (ii) a layer of material M(L)Sx, M being a d-block metal, L an element of column IIIB.

10. Multilayer semiconductor system according to claim 9, wherein the material M(L)SX is Cu(Ga)S2 qualified as CGS.

11. Multi-junction solar cell containing one or more tunnel junctions, or any other system enabling electrical connection between two sub-cells, comprising a multi-layer semiconductor system according to any one of claims 9 or 10.

12. Use of the multilayer semiconductor system according to any one of claims 9 or 10: - in photovoltaic technologies such as solar cells or panels; - in transparent electronics; and - in display technologies such as liquid crystal displays, flat panel displays, plasma displays, touch screens;

13. - in detection technologies, preferably implementing at least one optical sensor; and - in water dissociation technologies to produce hydrogen by electrolysis such as photoelectrochemical cells, or photovoltaic-electrochemical cells. Use of the multilayer semiconductor system according to claim 12, in a photovoltaic technology device comprising tandem photovoltaic cells on silicon.

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