Crack detection device for a semiconductor structure

Abstract

Crack detection device in a semiconductor structure This description relates to a crack detection device (200) adapted to detect a crack in an electronic chip, the crack detection device comprising a first conductive line (201) for detecting a crack in a semiconductor structure (210) located in, and / or on, a semiconductor substrate (211), an interconnection structure (220) being connected to a first face (210A) of the semiconductor structure, the first conductive line being included in the interconnection structure and in the semiconductor structure, and comprising: - at least a first conductive segment (221A) and at least a second conductive segment (221B) of a first level of metallization (M1) of the interconnection structure electrically isolated from each other by an insulating layer (223);- a conductive region (213) buried deep within the semiconductor structure, said buried conductive region being connected to at least one first conducting segment and at least one second conducting segment; - an insulating region (215) positioned between the first face of the semiconductor structure and the buried conductive region. Figure for the abbreviation: Fig. 2;

Description

Title of the invention: Tissue detection device in a semiconductor structure technical field

[0001] The present description relates generally to the detection of defects, such as cracks or delaminations, in an electronic chip, and in particular in a semiconductor structure formed in, and / or on, a semiconductor substrate of the electronic chip.

[0002] The present description relates, for example, to the detection of cracks that can propagate from an edge of an electronic chip to electronic circuits of the electronic chip. Previous technique

[0003] In industry, most electronic devices are manufactured in series. Generally, several copies of an electronic device are manufactured simultaneously in and on the same semiconductor substrate, for example, the same semiconductor wafer. In particular, several electronic chips are usually manufactured in and on the same semiconductor substrate, for example, the same wafer. The electronic chips can then be separated, or individualized, for use, for example, alone or in a more complete electronic device. This individualization is generally achieved by cutting, for example, by laser cutting.

[0004] During this individualization process, for example during the cutting of the semiconductor wafer, structural defects may occur on an edge of an electronic chip. These defects may include cracks, gaps, or delaminations. Such defects can lead to failure of the electronic circuits of the electronic chip.

[0005] Furthermore, even if defects do not appear during manufacturing, some defects may appear during the lifetime of the chip, in particular on an edge of the chip, for example due to temperature changes in the electronic chip.

[0006] To detect a crack, or delamination, in an electronic chip, particularly during manufacturing, individualization, or even during its lifetime, the electronic chip may include a crack detector in its periphery, the crack detector generally being positioned in a sealing ring at the periphery of the electronic chip. One purpose of the crack detector is to detect a crack, or delamination, that could propagate from the edge to a region of electronic circuits of the electronic chip.

[0007] It would be desirable to be able to improve, at least in part, the crack detectors of electronic chips. Summary of the invention

[0008] One embodiment overcomes all or part of the drawbacks of known electronic chip crack detectors.

[0009] One embodiment provides a crack detection device adapted to detect a crack in an electronic chip, the crack detection device comprising a first conductive line for detecting a crack in at least one semiconductor structure located in, and / or on, a semiconductor substrate, an interconnection structure being connected to a first face of the at least one semiconductor structure, the first conductive line being contained within the interconnection structure and within the at least one semiconductor structure, and comprising: - at least one first conductive segment and at least one second conductive segment, said at least one first and second conductive segments being of a first level of metallization of the interconnection structure and being electrically insulated from each other by an insulating layer; and - a conductive region buried deep within each semiconductor structure, said buried conductive region being connected to at least one first conducting segment and at least one second conducting segment, an insulating region being positioned between the first face of the semiconductor structure and the buried conductive region.

[0010] In other words, each semiconductor structure comprises a deep-buried conductive region and an insulating region positioned between the first face of the semiconductor structure and the buried conductive region, and the first conductive line comprises at least one first conductive segment, at least one second conductive segment, and the buried conductive region of each semiconductor structure. The buried conductive region is at a non-zero distance from the first face of the semiconductor structure.

[0011] According to one embodiment, the semiconductor substrate is doped with a first type conductivity, the buried conductive region being a semiconducting region doped with a second type of conductivity opposite to the first type of conductivity.

[0012] According to one embodiment, each semiconductor structure comprises: - a semiconductor box doped with the second type of conductivity, extending in depth from the first face of the semiconductor structure so as to electrically connect said first face and the buried conductive region; - conductive elements connected to the first face of the semiconductor structure, the conductive elements comprising a first conductive element connecting the semiconductor casing to the first conductive segment, and a second conductive element connecting the semiconductor casing to the second conductive segment.

[0013] For example, the insulating region is surrounded by the semiconductor box.

[0014] According to one embodiment, the buried conductive region is at a depth greater than 0.5 pm, for example greater than or equal to 1 pm, or greater than or equal to 3 pm, or even greater than or equal to 5 pm.

[0015] According to one embodiment, each first conductive segment is included in a first metallic stack comprising several levels of metallization of the interconnection structure, and each second conductive segment is included in a second metallic stack comprising several levels of metallization of the interconnection structure.

[0016] According to one embodiment, the at least one semiconductor structure comprises several semiconductor structures, the at least one first conducting segment comprising several first conducting segments and the at least one second conducting segment comprising several second conducting segments, the second conducting segments between two adjacent semiconductor structures among the semiconductor structures being connected to each other in the interconnection structure.

[0017] According to one embodiment, the second conducting segments are connected to each other at the first level of metallization of the interconnecting structure.

[0018] According to one embodiment, the second metallic stacks between the two adjacent semiconductor structures are connected to each other by a third conductive segment of a metallization level of the interconnecting structure higher than the first metallization level.

[0019] According to one embodiment, the first conductive line is also adapted to detect a crack in the interconnection structure.

[0020] According to one embodiment, the device further comprises a second conductive line for detecting a crack in the interconnection structure, said second line being included in the interconnection structure and being distinct from the first conductive line.

[0021] According to one embodiment, the second conducting line comprises: - at least one fourth conducting segment of the first metallization level of the interconnection structure, each fourth conducting segment being isolated from at least one first and at least one second conducting segments by the insulating layer; - at least one fifth conductive segment with a level of metallization of the interconnection structure higher than the first level of metallization; - at least one sixth conductive segment with a level of metallization of the interconnection structure higher than the first level of metallization; each fourth conductive segment connecting one of at least a fifth conductive segment to one of at least a sixth conductive segment, for example via conductive vias of the interconnection structure.

[0022] According to one embodiment, each fifth conductive segment is included in a third metallic stack comprising several levels of metallization of the interconnection structure from the second level of metallization, and / or each sixth conductive segment is included in a fourth metallic stack comprising several levels of metallization of the interconnection structure from the second level of metallization, for example two adjacent fourth metallic stacks being connected to each other at a level of metallization higher than the second level of metallization by a seventh conductive segment.

[0023] According to one embodiment, the second conductive line comprises a first end connected to a first terminal of a second detection circuit and a second end connected to a second terminal of the second detection circuit, so as to measure an electrical signal in said second conductive line to determine the presence of a crack. For example, the first end and / or the second end of the second conductive line is connected to, or corresponds to, at least one-fifth conductive segment.

[0024] According to one embodiment, the first conductive line comprises a first end connected to a first terminal of a first detection circuit and a second end connected to a second terminal of the first detection circuit, so as to measure an electrical signal in said first conductive line to determine the presence of a crack. For example, the first end and / or the second end of the first conductive line is connected to, or corresponds to, at least a first conductive segment.

[0025] According to one embodiment, the second terminal of the second detection circuit is electrically isolated from the second terminal of the first detection circuit, for example the first terminal of the second detection circuit is electrically connected to the first terminal of the first detection circuit.

[0026] According to one embodiment, the insulating layer comprises a material with a low dielectric constant compared to the dielectric constant of silicon dioxide.

[0027] One embodiment provides for an electronic chip comprising: - a semiconductor substrate; - at least one semiconductor structure located in, and / or on, the semiconductor substrate; - an interconnection structure connected to a first face of at least one semiconductor structure; and - a crack detection device as described above.

[0028] According to one embodiment, the at least one semiconductor structure comprises several semiconductor structures, at least one semiconductor structure among said semiconductor structures comprising a vertical gate structure of a buried selector transistor of a trench selector transistor integrated memory cell.

[0029] According to one embodiment, the crack detection device is positioned on the periphery of the electronic chip, for example around a region of electronic circuits of the electronic chip, for example in a sealing ring of the electronic chip.

[0030] One embodiment provides a method for using the crack detection device as described above, the method comprising: - the emission of a first electrical signal at a first end of the first conducting line; - the reception of the first electrical signal at a second end of the first conducting line, and the measurement of a first resistance value of the first electrical signal received; - the comparison of the first measured resistance value with a first lower resistance limit to determine the presence of a crack in the first conductive line.

[0031] According to one embodiment, the process comprises: - the emission of a second electrical signal at a first end of the second conducting line; - the reception of the second electrical signal at a second end of the second conducting line, and the measurement of a second resistance value of the second received electrical signal; - comparing the second measured resistance value with a second lower resistance limit to determine the presence of a crack in the second conductive line; the first lower resistance limit being, for example, greater than the second lower resistance limit.

[0032] One embodiment provides for a method of co-integrating several semiconductor structures in, and / or on, the same semiconductor substrate, the method further comprising the formation of an interconnection structure connected to a first face of the semiconductor structures, and of a crack detection device as described above, at least one semiconductor structure among the semiconductor structures comprising a vertical gate structure of a buried selector transistor of a trench selector transistor integrated memory cell. Brief description of the drawings

[0033] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0034] [Fig.1A] is a schematic and partial top view illustrating an example of an electronic chip comprising a crack detector;

[0035] [Fig.1B] is a schematic and partial cross-sectional view of the electronic chip of [Fig.1A];

[0036] [Fig.1C] is another schematic and partial cross-sectional view of the electronic chip of [Fig.1A];

[0037] [Fig.2] is a schematic and partial cross-sectional view illustrating a crack detection device according to one embodiment;

[0038] [Fig.3] is a schematic and partial cross-sectional view illustrating a crack detection device according to another embodiment;

[0039] [Fig.4] is a schematic and partial cross-sectional view illustrating a crack detection device according to another embodiment;

[0040] [Fig. 5] is a schematic and partial cross-sectional view illustrating a crack detection device according to another embodiment

[0041] [Fig. 6] is a schematic and partial cross-sectional view illustrating a crack detection device according to another embodiment; and

[0042] [Fig.7] is a schematic and partial cross-sectional view illustrating a crack detection device according to another embodiment. Description of the implementation methods

[0043] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0044] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, not all fabrication steps and details of the semiconductor structures are described, as they are feasible with conventional methods for fabricating semiconductor structures in and / or on a semiconductor substrate. Furthermore, the fabrication steps and the Details of the interconnection structures are not described, as they are feasible with the usual manufacturing processes for interconnection structures.

[0045] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0046] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0047] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0048] In the following description, the terms "insulator" and "conductor" mean, respectively, electrically insulating and electrically conductive. Similarly, the term "insulate" means, unless otherwise specified, to insulate electrically.

[0049] In the following description, unless otherwise specified, when a chip is referred to, an electronic chip is referred to; when a via is referred to, a conductive via is referred to; when a substrate is referred to, a semiconductor substrate is referred to; and when a box is referred to, a semiconductor box is referred to.

[0050] In the following description, references to a crack detection device, or for short, a crack detector, referencing a device capable of detecting a structural defect that is not limited to a crack; for example, it could be a breach or delamination. For the sake of brevity, references to a crack may include a breach, delamination, or any other similar structural defect.

[0051] In the following description, "buried" means buried deep within the semiconductor structure.

[0052] In the following description, a first metallization level of an interconnect structure generally corresponds to the metallization level closest to a semiconductor substrate to which the interconnect structure is connected. A second metallization level of the interconnect structure corresponds to a metallization level further from the semiconductor substrate than the first metallization level. More generally, an N+1 metallization level corresponds to a metallization level further away from the semiconductor substrate than the N metallization level.

[0053] Fig. 1A is a schematic and partial top view illustrating an example of an electronic chip 100. Fig. 1B is a schematic and partial cross-sectional view of the electronic chip 100 of Fig. 1A. Fig. 1C is another schematic and partial cross-sectional view of the electronic chip of Fig. 1A. Fig. 1C shows a detail of a crack detector integrated into the electronic chip. The cross-sectional view of Fig. 1B is taken along the section plane AA identified in Fig. 1A. The cross-sectional view of Fig. 1C is taken along the section plane BB identified in Fig. 1A.

[0054] The electronic chip 100 comprises a semiconductor layer 101, which may correspond, for example, to a semiconductor substrate, for example made of silicon, or to the semiconductor layer of a silicon-on-insulator (SOI) substrate. The semiconductor layer 101 may include one or more doped cells.

[0055] Electronic circuits of the chip 100 are arranged in and / or on the semiconductor layer 101, this part of the chip being generally designated as "FEOL", for "front end of line". For clarity, the electronic circuits of the chip 100 are not shown in Figures IA, IB and IC, but are all arranged in an electronic circuit region, or circuit region 102, of the chip 100 delimited by a circumference 102A. In other words, the circuit region 102 comprises all the electronic circuits of the chip 100. The circuit region 102 of the chip 100 is, for example, a central region of the chip 100, as shown in the view of [Fig. 1A].

[0056] The chip 100 further comprises an interconnection structure 105 above the semiconductor layer 101, for example in contact with, or connected to, the semiconductor layer 101. This interconnection structure 105 is generally referred to as the "BEOL" interconnection structure, from the English "back end of line." The interconnection structure 105 comprises a plurality of metallization levels. Five metallization levels, M1, M2, M3, M4, and M5, are shown in Figures IB and IC, although this is not limiting; the number of metallization levels may be less than or greater than five.

[0057] Each metallization level comprises at least one first segment 106A of a conductive layer 106, for example a metallic layer, each first segment 106A forming a conductive track. The conductive tracks 106A of the different metallization levels of the interconnect structure 105 are electrically connected to each other and / or to connection pads 107 and / or to the electronic circuits of the chip 100 by conductive vias 108A, for example metallic vias. The conductive tracks 106A of the different metallization levels The interconnection structure 105 is preferably positioned in the circuit region 102. Thus, the interconnection structure 105 allows the electronic circuits of the chip 100 to be connected to each other and / or to the connection pads 107. The connection pads 107, which can be referred to as "pads" for short, are part of the interconnection structure 105. The pads 107 are arranged at the upper metallization level of the interconnection structure 105 in the example of [Fig.1B], or last metallization level, which corresponds to the metallization level M5 in this example. In other words, the pads 107 are arranged on an upper face 105A (first face) of the interconnect structure 105, a lower face 105B (second face) of the interconnect structure, opposite the first face 105A, being connected to, or in contact with, the semiconductor layer 101.

[0058] The pads 107 can be distributed in a substantially annular manner, here a ring of square shape, in the circuit region 102 of the chip 100 and, more precisely, in a region of the interconnection structure 105 included in the circuit region 102 of the chip 100. Other arrangements can be considered by a person skilled in the art.

[0059] The interconnection structure 105 further includes an insulating layer 109, which is generally a stack of several insulating layers, separating the different levels of metallization, the conductive layers 106 and the conductive vias being embedded in the insulating layer 109. The insulating layer 109 may be made of an oxide, for example a silicon oxide.

[0060] The conductive track 106A at the first metallization level M1 of the interconnecting structure 105 can be connected to the semiconducting layer 101 by a conductor via or by a contact 111 A, or any other electrical connection element.

[0061] The chip 100 includes a sealing region 110, or sealing ring, known as the "seal-ring" in English, on the periphery of the chip 100, that is to say between the circuit region 102 and the edge 103 of the chip 100. Thus, the sealing ring 110 surrounds the circuit region 102 of the chip 100. The sealing ring 110 has an annular shape in top view. The sealing ring 110 is arranged in the interconnect structure 105, at the periphery of the chip 100. The sealing ring 110 is thus part of the interconnect structure 105, although it is not used to connect the electronic circuits of the chip 100 to each other and / or to the pads 107. Preferably, the chip 100 does not include any electronic circuits in the sealing ring 110. In other words, the circuit region 102 of the chip 100 is laterally delimited, in the interconnect structure 105, by the sealing ring 110.

[0062] One intended function of the sealing ring 110 is to prevent the propagation of cracks from the edge 103 of the chip 100 to the circuit region 102 of the chip 100. Another intended function of the sealing ring 110 may be to block the propagation of moisture from outside the chip 100, i.e. from the edge 103 of the chip 100, to the electronic circuits of the circuit region 102 of the chip 100. Another intended function of the sealing ring 110 may be to detect a crack in the electronic chip 100.

[0063] To perform one or more of these functions, the sealing ring 110 may include one or more sealing elements 112, each sealing element having an annular shape in top view. One sealing element is shown in Figures IA, IB, and IC, although there may be several. When there are several sealing elements, they may be substantially concentric. One sealing element may be adapted to stop crack propagation, another sealing element may be adapted to block moisture ingress, and / or one sealing element may be adapted to perform both of these functions of stopping crack propagation and blocking moisture ingress.

[0064] The sealing element 112 extends vertically from the first metallization level M1, above the semiconducting layer 101, to the upper metallization level, level M5 in the example shown, although the upper metallization level may be different from M5, for example M6, M7 or higher, or even M4 or lower.

[0065] The sealing element 112 shown forms a closed loop around the circuit region 102 of the chip 100. In other words, the sealing element 112 completely surrounds the circuit region 102 of the chip 100.

[0066] In the embodiment shown in [Fig. IB], the sealing element 112 comprises second segments 106B of the conductive layers 106 of the interconnecting structure 105. More specifically, the sealing element 112 comprises at least one second segment 106B of the conductive layer 106 of each metallization level M1-M5 of the interconnecting structure 105. The second segments 106B of the different metallization levels are embedded in the insulating layer 109. Each second segment 106B of the conductive layer 106 forms an annular conductive plate at each metallization level. For example, each annular conductive plate 106B extends in a plane substantially parallel to the semiconducting layer 101.

[0067] The successive annular conductive plates 106B of the sealing element 112 are connected vertically to each other by one or more conductive elements, for example: - conductive vias 108B of the interconnection structure 105: the vias may be cylindrical or elongated in the form of bars or lines; and / or - annular conductive strips 113 which extend continuously between two successive annular conductive plates 106B: in other words, the annular conductive strips 113 join two successive annular conductive plates 106B in the Z direction perpendicular to the XY plane of the semiconducting layer 101.

[0068] The sealing element 112 can be connected to the semiconducting layer 101 via the conductive plate 106B of the first metallization level M1 by a conductive via or contact 11 IB, or any other electrically conductive element.

[0069] In order to detect cracks in the chip 100, the sealing ring 110 includes a crack detector 114. The crack detector 114 is thus positioned on the periphery of the chip 100, around the circuit region 102.

[0070] The crack detector 114 is arranged in the interconnection structure 105. In other words, the interconnection structure 105 includes the crack detector 114. The crack detector 114 extends in height from the first metallization level M1, above the semiconducting layer 101, to the upper metallization level M5.

[0071] As shown in [Fig. 1A], the crack detector 114 can be positioned in a region between the edge 103 of the chip 100 and the sealing element 112. Thus, if a crack appears at the edge 103 of the chip 100 and propagates toward the circuit region 102, the crack can be detected by the crack detector 114 before reaching the sealing element 112. Other configurations can be considered by a person skilled in the art, with one or more sealing elements and / or one or more crack detectors, as described later. Preferably, the crack detector detects a crack before it reaches the circuit region 102 of the chip 100.

[0072] The crack detector 114 includes a conductive structure 118, or a conductive line, which preferably forms an open loop. By measuring an electrical parameter, for example, conductivity or electrical resistance, between a first terminal, or node, 115 of the conductive line 118 and a second terminal, or node, 116 of the conductive line 118, cracks can be detected by the crack detector 114. The crack detector 114 may include a detection circuit (not shown), which can be connected to the first and second terminals 115, 116, to detect a change in an electrical parameter in the conductive line 118 indicating the presence of a crack. The detection circuit can be implemented in the electronic chip 100, for example in the circuit region 102, or in a circuit external to the electronic chip 100.

[0073] In the embodiment shown in Figures IB and IC, the conductor line 118 is constructed within the interconnection structure 105, and it comprises several metallic stacks 117, each metallic stack including thirds segments 106C of the conductive layers 106 of the interconnection structure 105 and conductive vias 108C between the third segments 106C of the different metallization levels. The third segments 106C of the different metallization levels are embedded in the insulating layer 109.

[0074] Two adjacent metal stacks 117 are connected to each other by one or more third segments 106C of one of the metallization levels. In the example shown in [Fig. 1C], the adjacent metal stacks 117 are connected to each other by third segments 106C of the first metallization level M1 or by third segments 106C of the last metallization level M5. Four metal stacks 117 of the crack detector 116 are illustrated as an example in [Fig. 1C], but the crack detector 114 can include more, for example, to go around the electronic chip 100.

[0075] The crack detector 114 can be connected to the semiconductor layer 101 via the third segment 106C of the first metallization level M1 by a conductive via or contact 11 IC, or any other electrically conductive element.

[0076] Although not shown in Figures IA, IB, and IC, the sealing ring 110 may include several sealing elements similar to the sealing element 112 described previously, for example, an internal sealing element disposed in the interconnection structure 105 around the circuit region 102 and an external sealing element disposed in the interconnection structure 105 around the internal sealing element. The sealing ring 110 may then include an intermediate crack detector, for example, similar to the crack detector 114 described previously, disposed in the interconnection structure 105 between the internal sealing element and the external sealing element.The presence of internal and external sealing elements and an intermediate crack detector between these two sealing elements allows for the detection of cracks that have propagated from the edge 103 of the electronic chip through the external sealing element. The sealing ring 110 may include an internal crack detector disposed in the interconnection structure 105 around, or on the edges of, the circuit region 102 and surrounded by the sealing element 112, or the internal sealing element. Such an internal crack detector allows for the detection of cracks that have propagated from the edge 103 of the chip 100 through the sealing element(s) and may reach the circuit region 102.

[0077] Known crack detectors, such as those described above, can detect a crack from the first metallization level Ml up to one or more higher metallization levels. Known crack detectors cannot detect a crack below the first metallization level Ml, in particular they cannot detect a crack in the semiconductor layer, or semiconductor substrate, under the interconnect structure.

[0078] The inventors propose a device for detecting cracks in a semiconductor structure that meets the improvement needs described above, and overcomes all or part of the disadvantages of the crack detectors described above.

[0079] In particular, the inventors propose a crack detection device enabling the detection of a crack in the semiconductor substrate, below the interconnection structure, i.e. in the so-called FEOL part, or in a semiconductor structure formed in and / or on the semiconductor substrate.

[0080] It would be advantageous if the crack detection device could also detect a crack in the interconnect structure, i.e., in the BEOL portion. In particular, it would be advantageous if the crack detection device could distinguish a crack in the interconnect structure (BEOL portion) from a crack in the semiconductor substrate (FEOL portion).

[0081] Embodiments of crack detection devices will be described below. The embodiments described are not limiting, and various variations will become apparent to those skilled in the art from the indications in this description.

[0082] Figures 2 to 7 described below illustrate examples of CMOS (Complementary Metal-Oxide-Semiconductor) structures formed in and / or on a semiconductor substrate: for example, a triple-well structure, or a vertical-gate structure with an implant under the gate, for example, to form a trenchless transistor. These examples of semiconductor structures are not limiting; other CMOS structures could be envisioned by a person skilled in the art. Furthermore, several different semiconductor structures can be formed in and / or on the semiconductor substrate.

[0083] In Figures 2 to 7 described below, the semiconductor substrate is typically a P-type doped silicon substrate. In other words, the first type of doping, or conductivity type, is P-type. Alternatively, the semiconductor substrate could be N-type doped, meaning the first type of doping, or conductivity type, could be N-type, in which case those skilled in the art will know how to adapt the doping type of the semiconductor casings, regions, and layers in the devices, structures, and processes described below. The semiconductor substrate could be made of a material other than silicon.

[0084] The detection devices of Figures 2 to 7 are preferably integrated into an electronic chip, for example an electronic chip similar to that of Figures IA and IB. The detection devices of Figures 2 to 7 can then be part of a The interconnection structure of the electronic chip. In particular, the sensing devices shown in Figures 2 through 7 can be positioned at the periphery of the electronic chip, around a region of the chip's electronic circuits. For example, the sensing devices shown in Figures 2 through 7 can be integrated into a sealing ring, in conjunction with one or more sealing elements, similarly to what is described in relation to Figures IA and IB. The various sealing ring variants described in relation to Figures IA and IB can also be applied. Furthermore, in Figures 2 through 7, five metallization levels, M1–M5, are shown in the interconnection structure, although there could be six levels (M1–M6), seven levels (M1–M7), or more, or even fewer than five levels.

[0085] Each of the crack detection devices 200, 300, 400 of Figures 2 to 4 differs from the crack detector 114 of [Fig. 1C] primarily in that the conductive line (first conductive line) of the detection device is not only formed in the interconnect structure, but also includes one or more conductive portions in the semiconductor substrate, or in semiconductor structures formed in and / or on the semiconductor substrate, these conductive portions forming an electrical conduction channel. In particular, each of the crack detection devices of Figures 2 to 4 differs from the crack detector 114 of [Fig. 1C] in that the metal stacks are not connected to each other by segments of the conductive layer of the first metallization level M1, but by the conductive portions in the semiconductor substrate.

[0086] In each of Figures 2 to 4, semiconductor structures are formed in, and / or on, the semiconductor substrate. These are generally CMOS-type semiconductor structures. The conductive line of each of the crack detection devices in Figures 2 to 4 does not pass solely through the interconnect structure, i.e., it does not only include segments of conductive layers of the interconnect structure, but it also includes conductive portions within these semiconductor structures.

[0087] Different semiconductor structures 210, 310, 410 will now be described in Figures 2 to 4 below, as well as different conductive lines 201, 301, 401 which depend on the type of semiconductor structure. In particular, the depth of the conductive line, and thus the crack detection depth, may depend on the type of semiconductor structure.

[0088] In figures 2 to 4, the conducting line 201, 301, 401 (first conducting line) is symbolized by a dashed line which allows visualization of one conducting path, among several possible paths along the conducting line 201, 301, 401. The conducting line 201, 301, 401 is therefore not limited to this dashed line.

[0089] Fig. 2 is a schematic and partial cross-sectional view illustrating a crack detection device 200 according to one embodiment.

[0090] Each semiconductor structure 210 of [Fig.2] is a triple well type structure, known in English as "triple well".

[0091] Each triple box structure 210 allows for the electrical isolation of a semiconductor box 212 (PW) doped with a first type of doping, which is the same type of doping as the semiconductor substrate 211 (PSUB), in the example shown a P-type doping, by means of semiconductor regions 213, 214 doped with the second type of doping opposite to the first type of doping. In the example shown, the second type of doping is N-type.

[0092] The semiconductor regions include: - a buried semiconductor region 213 (N-ISO) doped with the second type of doping, allowing the enclosure 212 to be isolated in depth from the semiconductor substrate 211; and - an annular semiconductor box 214 (NW), or annular semiconductor region, doped with the second type of doping, laterally surrounding the semiconductor box 212 (in the X and Y directions), allowing it to be isolated laterally.

[0093] Throughout the description, the term "ring" refers to a ring shape which is not necessarily circular, but which may be, for example, square or rectangular, more broadly a geometric area delimited by an inner perimeter and an outer perimeter substantially parallel to each other.

[0094] The annular semiconductor box 214 extends from the upper face 211A of the semiconductor substrate 211 in depth, preferably to the buried semiconductor region 213. Thus, the annular semiconductor box 214 is preferably in contact with the buried semiconductor region 213.

[0095] In the example of [Fig.2], the upper face 210A of the semiconductor structure 210 corresponds to the upper face 21 IA of the semiconductor substrate 211.

[0096] Furthermore, an insulating trench 215 (STI), for example of the shallow insulating trench type, known as STI, is located above the semiconductor box 212 and is surrounded by the annular semiconductor box 214. Thus, the semiconductor box 212 is buried and is electrically insulated in its upper portion by the insulating trench 215. The semiconductor box 212 is therefore completely surrounded by regions that electrically insulate it. The insulating trench 215 may extend beyond the semiconductor box 212 into the annular semiconductor box 214.

[0097] A simplified example of a process for forming a semiconductor structure 210 comprises: - an etching from the top face 21 IA of the semiconductor substrate 211 to form a shallow trench in the semiconductor substrate 211, then a filling of this trench, for example with silicon oxide, to form the insulating trench 215; - a deep implantation in the semiconductor substrate 211 to form the buried semiconductor region 213 (N-ISO), this implantation being of the second type of doping, in this example of type N; - an implantation from the upper face 21 IA of the semiconductor substrate 211 to form the annular semiconductor box 214 (NW), this implantation being of the second type of doping, in this example of type N; - an implantation in the semiconductor substrate 211 through the insulating trench 215 and in the central part delimited by the annular semiconductor box 214 to form the semiconductor box 212, this implantation being of the first type of doping, in this example of type P.

[0098] The order of the last two steps can be reversed.

[0099] The annular semiconductor box 214 is preferably implanted with an energy enabling the buried semiconductor region 213 to be reached in depth, so as to form with the buried semiconductor region 213 a continuous N-type semiconductor region to isolate the P-type semiconductor box 212.

[0100] By way of example, the buried semiconductor layer 213 can form a source plane, or a source region, for a vertical transistor, and the semiconductor box 212 can contain a memory cell.

[0101] In such a triple box structure, PN junctions of opposite polarities to the P-type box 212, formed with the N-type semiconductor regions 213, 214, allow the box 212 to be electrically isolated, which is further insulated by the insulating trench 215. The current is therefore conducted through the buried semiconductor region 213 via the annular semiconductor box 214. The semiconductor regions 213, 214 thus form a conductive portion 201 A, or electrical conduction channel, in the semiconductor substrate 211, in each semiconductor structure 210.

[0102] The conductive portion 201A of each semiconductor structure 210 corresponds to a first portion of a conductive line 201 (first conductive line) of the detection device 200. The conductive line 201 therefore includes the semiconductor regions 213, 214 of the semiconductor structures 210, that is to say the buried semiconductor region 213 and the annular semiconductor box 214 of each semiconductor structure 210.

[0103] The conductor line 201 further comprises all or part of several metal stacks 202. The metal stacks 202 are part of a structure interconnection structure 220 (BEOL) positioned above the semiconductor substrate 211. Each metal stack 202 comprises conductive segments 221 at each metallization level M1-M5 of the interconnection structure 220 and conductive vias 222 between the conductive segments 221 of the different metallization levels M1-M5. A conductive segment 221 of a metallization level generally corresponds to a segment, or portion, of a conductive layer, for example a metal layer, formed in that metallization level. The conductive segments 221 and the conductive vias 222 are embedded in an insulating layer 223.

[0104] In the example shown, the portions of the conductive line 201 that are formed in the metal stacks 202 include: - a conductive segment 221A (first conductive segment) of the first metallization level M1 for each of two first metal stacks 202A; and - several conductive segments 221 of several metallization levels connected by conductive vias 222 for each of two second metal stacks 202B.

[0105] The conductive line 201 further comprises contacts 204. The contacts 204 are considered to be part of the interconnection structure 220. The contacts 204 comprise first contacts 204A connecting each of the semiconductor structures 210 to the conductive segment 221A of one of the first metal stacks 202A, and second contacts 204B connecting each of the semiconductor structures 210 to one of the second metal stacks 202B, more precisely to a conductive segment 221B (second conductive segment) of one of the second metal stacks 202B. Each of these contact connections is made at the first metallization level ML. The contacts 204 are connected, for example, to the upper face 210A of the semiconductor structure 210, which here corresponds to the upper face 21 IA of the semiconductor substrate 211.In particular, the contacts 204 are connected, for example linked, to the annular semiconductor boxes 214 of the semiconductor structures 210. Thus, each annular semiconductor box 214 is connected to first and second metal stacks 202A, 202B via the contacts 204. Thus, the first and second metal stacks 202A, 202B are not connected to each other by conductive segments at the first level of metallization M1, as in [Fig.1C], but by the conductive portion 201A in the semiconductor structure 210, i.e. the buried semiconductor region 213 and the annular semiconductor box 214.

[0106] The second metallic stacks 202B between the two semiconductor structures 210 are connected to each other at the last metallization level M5 by a conductive segment 22IC (third conductive segment) which is continuous between these second metal stacks. Thus, a second portion 201B of the conductive line 201 includes all metallization levels M1-M5 of the second metal stacks 202B, i.e. the conductive segments 221 and the conductive vias 222 of all metallization levels, including the continuous conductive segment 22IC between the second metal stacks 202B at the last metallization level M5.

[0107] Guideline 201 thus comprises: - the first portions 201A formed by the N-doped semiconductor regions 213, 214 of the semiconductor structures 210; - the second portion 201B between the first portions 201A, the second portion being formed by the second metallic stacks 202B connected to each other by the conductive segment 221C at the last level of metallization M5 of the interconnection structure 220, the second portion 201B being connected to each of the first portions 201A by one of the second contacts 204B; - the conductive segments 221A of the first metallic stacks 202A each connected to one of the first portions 201A by one of the first contacts 204A.

[0108] The conductive line 201 can be connected to a detection circuit (not shown). For example, a first end 201C of the conductive line 201 can be connected to a first terminal of the detection circuit at the first metallization level M1, and a second end 201D of the conductive line 201 can be connected to a second terminal of the detection circuit at the first metallization level M1, but the connection can be made at any other metallization level. The detection circuit can be configured to detect a change in an electrical parameter in the conductive line 201 indicating the presence of a crack.

[0109] In the example of [Fig.2], one end of each conducting segment 221A may correspond to one of the first 201C and second 201D ends of the 201 conductor line.

[0110] Such a detection device 200 makes it possible to detect a crack at depths of up to a buried semiconductor region of the semiconductor substrate 211, the buried semiconductor region 213 in the example of [Fig. 2]. More broadly, the detection device 200 makes it possible to detect a crack along the conductive line 201, between the buried semiconductor region 213 and the upper metallization level M5. To detect a crack, a change in electrical parameter in the conductive line 201 can be determined, for example, an increase in resistance when the conductive line 201 is damaged by a crack in one of the semiconductor regions 213, 214, or even infinite resistance when the conductive line 201 is interrupted. A lower resistance limit can be defined to determine whether a crack has occurred.

[0111] The buried semiconductor region 213 can be located at a depth of up to 3 pm, or even up to 5 pm in the semiconductor substrate 211. Thus, the detection device 200 can detect a crack up to a depth of 5 pm.

[0112] Fig. 3 is a schematic and partial cross-sectional view illustrating a crack detection device 300 according to another embodiment.

[0113] The crack detection device 300 of [Fig.3] has many elements in common with the crack detection device 200 of [Fig.2] and only the differences between the two crack detection devices are detailed in the following description.

[0114] The crack detection device 300 of [Fig.3] differs from the crack detection device 200 of [Fig.2] mainly in the semiconductor structures 310 which are of the vertical grid structure type, with an implantation region buried under the grid.

[0115] Each semiconductor structure 310 comprises a vertical grid structure 316 which extends deep into the semiconductor substrate 311, from the upper face 311A ​​of the semiconductor substrate 311.

[0116] In the example of [Fig.3], the upper face 310A of the semiconductor structure 310 corresponds to the upper face 31 IA of the semiconductor substrate 311.

[0117] The vertical grid structure 316 includes a conductive trench 317 (Trench), i.e. a trench filled with a conductive material, for example polycrystalline silicon (polysilicon), the bottom and sides of the trench being insulated by an insulating layer 318, for example silicon oxide.

[0118] The conductive trench 317 is surrounded at least partially by an insulating trench 315, for example of the shallow insulating trench type, for example of the same type as the insulating trench 215 of [Fig.2].

[0119] The semiconductor structure 310 further includes a buried semiconductor region 312 (Source) doped with the second type of doping, i.e., opposite to the type of doping of the semiconductor substrate 311. In the example shown, the semiconductor substrate 311 is P-type doped and the buried semiconductor region 312 is N-type doped. The buried semiconductor region 312 extends deep from the bottom of the gate structure 316. Alternatively, this buried semiconductor region 312 could be located around and below the gate structure 316.

[0120] The insulating trench 315 (STI), the conducting trench 317 and the buried semiconductor region 312 are surrounded laterally (in the X and Y directions) by an annular semiconductor box 314 (NW) doped with the second type of doping, in the example shown of type N.

[0121] A simplified example of a process for forming a semiconductor structure 310 comprises: - an etching from the upper face 31 IA of the semiconductor substrate 311 to form a shallow trench in the semiconductor substrate 311, then a filling of this trench, for example with silicon oxide, to form the insulating trench 315; - an etching through the insulating trench 315 from the upper face 31 IA of the semiconductor substrate 311 to form a trench intended to be filled with a conductive material to form the future conductive trench 317; - a deep implantation in the semiconductor substrate 311 under the trench to form the buried semiconductor region 312, this implantation being of the second type of doping, in the example of type N; - an implantation from the upper face 31 IA of the semiconductor substrate 311 to form the annular semiconductor box 314 around the insulating trench 315 and the buried semiconductor region 312, this implantation being of the second type of doping, in the example of type N; - the formation of an insulating layer 318 on the bottom and sides of the trench, then filling the trench covered by the insulating layer 318 with the conductive material, for example polysilicon, to form the conductive trench 317.

[0122] The order of the last two steps can be reversed.

[0123] In each semiconductor structure 310, the current is conducted through the buried semiconductor region 312 via the annular semiconductor box 314, the conductive trench 317 being insulated by the insulating layer 318. Thus, the semiconductor regions 312, 314 form a conductive portion 301A in the semiconductor substrate 311, in each semiconductor structure 310, this conductive portion 301A forming a first portion of a conductive line 301.

[0124] This type of vertical gate structure can correspond to a vertical gate structure of an embedded transistor, used for example as a selection transistor, or access transistor, of a memory cell, for example for an eSTM type memory, from the English "embedded Select in-Trench Memory", integrated memory with trench selection transistor.

[0125] The other features and variants described in relation to [Fig. 2], for example the metal stacks 202, the contacts 204, and the second portion 201B of the conductive line, can be applied to the embodiment of [Fig. 3]. In particular, similarly to the embodiment of [Fig. 2], the conductive line 301 further comprises all or part of the metal stacks 202 forming part of an interconnect structure 220 (BEOL) positioned above the semiconductor substrate 311. Furthermore, similarly to the embodiment of [Fig. 2], a first contact 204A and a second contact 204B, positioned on the annular semiconductor boxes 314 of the semiconductor structures 310, allow to connect each of the semiconductor structures 310 to respectively a first metal stack 202A and a second metal stack 202B, the second metal stacks 202B between the two semiconductor structures 310 being connected to each other at the last metallization level M5, or at any other metallization level.

[0126] Conductor line 301 comprises: - the conductive portions 301A, or first portions, formed by the N-doped semiconductor regions 312, 314 of the semiconductor structures 310; - a second portion 301B between the first portions 301A, the second portion being similar to the second portion 201B described in relation to [Fig.2], the second portion 301B being connected to each of the first portions 301A by one of the second contacts 204B; and - the conductive segments 221A of the first metallic stacks 202A each connected to one of the first portions 301A by one of the first contacts 204A.

[0127] Similar to what is described in relation to [Fig. 2], the conductive line 301 can be connected to a detection circuit (not shown). For example, a first end 301C of the conductive line 301 can be connected to a first terminal of the detection circuit at the first metallization level M1, and a second end 301D of the conductive line 301 can be connected to a second terminal of the detection circuit at the first metallization level M1, but the connection can be made at any other metallization level. The detection circuit can be configured to detect a change in an electrical parameter in the conductive line 301 indicating the presence of a crack. One end of each conductive segment 221A can correspond to one of the first 301C and second 301D ends of the conductive line 301.

[0128] Such a detection device 300 makes it possible to detect a crack at depths up to a buried semiconductor region of the semiconductor substrate 311, the buried semiconductor region 312 in the example of [Fig. 3]. More broadly, the detection device 300 makes it possible to detect a crack along the conductive line 301, between the buried semiconductor region 312 and the upper metallization level M5. To detect a crack, a change in electrical parameter in the conductive line 301 can be determined, for example, an increase in resistance when the conductive line 301 is damaged by a crack in one of the semiconductor regions 312, 314, or even infinite resistance when the conductive line 301 is interrupted. A lower resistance limit can be defined to determine whether a crack has occurred.

[0129] The buried semiconductor region 312 can be located at a depth of up to 0.5 pm, or even up to 1 pm. Thus, the detection device 300 can detect a crack up to a depth of 1 pm.

[0130] Fig. 4 is a schematic and partial cross-sectional view illustrating a crack detection device 400 according to another embodiment.

[0131] The crack detection device 400 of [Fig.4] has many elements in common with the crack detection device 200 of [Fig.2] and only the differences between the two crack detection devices are detailed in the following description.

[0132] The crack detection device 400 of [Fig. 4] differs from the crack detection device 200 of [Fig. 4] primarily in the semiconductor structures 410, each of which comprises an epitaxial layer 417 on the semiconductor substrate 411 in which P-type and N-type implants are carried out, as detailed below. This allows for semiconductor regions to be buried even more deeply than in [Fig. 2].

[0133] Each semiconductor structure 410 includes a first buried semiconductor region 412 (N-BUR) formed in a semiconductor substrate 411 and doped with the second type of doping, opposite to the type of doping of the semiconductor substrate 411. In the example shown, the semiconductor substrate 411 is P-type doped and the first buried semiconductor region 412 is N-type doped. For example, the first buried semiconductor region 412 is flush with the top face 41 IA of the semiconductor substrate 411.

[0134] The semiconductor structure 410 further includes an epitaxial layer 417 (P-EPI) positioned on the upper face 41 IA of the semiconductor substrate 411. The epitaxial layer 417 is weakly doped with the first type of doping, in the example of type P.

[0135] An insulating trench 415, for example of the shallow insulating trench (STI) type, is formed from the upper face 417A of the epitaxial layer 417. The insulating trench 415 is for example of the same type as the insulating trench 215 of [Fig.2].

[0136] In this semiconductor structure 410, the upper face 410A of the semiconductor structure 410 corresponds to the upper face 417A of the epitaxial layer 417, and not to the upper face 41 IA of the semiconductor substrate 411.

[0137] A semiconductor box 416 is located in the epitaxial layer 417 under the insulating trench 415. The semiconductor box 416 is more heavily doped with the first type of doping than the epitaxial layer 417, in the example of type P.

[0138] Under the semiconductor casing 416, between the semiconductor casing 416 and the first buried semiconductor region 412, a portion 417B of the epitaxial layer 417, lightly doped with the first type of doping, is preferably retained, to form a diode blocking the passage of current. The 417B portion is surrounded by a second buried semiconductor region 413 (N-ISO) doped with the second type of doping, in the example of type N.

[0139] The portion 417B of the epitaxial layer 417 is less wide than the first buried semiconductor region 412, and is centered with respect to the first buried semiconductor region 412, so that the second buried semiconductor region 413 includes areas of contact with the first buried semiconductor region 412. Thus, electrical continuity, or an electrical conduction channel, is obtained.

[0140] The insulating trench 415 (STI) and the semiconductor box 416 are surrounded laterally (in the X and Y directions) by an annular semiconductor box 414 (NW) doped with the second type of doping, in the example of type N.

[0141] The annular semiconductor box 414 extends from the upper face 417A of the epitaxial layer 417 deep down to the second buried semiconductor region 413. Thus, the N-type annular semiconductor box 414 is in contact with the second N-type buried semiconductor region 413, which is itself in contact with the first N-type buried semiconductor region 412. Therefore, the N-type doped semiconductor regions 412, 413, and 414 form a conductive portion 401A in each semiconductor structure 410, isolated from the other regions, which are either P-type or insulating. This conductive portion 401A forms a first portion of a conductive line 401.

[0142] Such a semiconductor structure 410 allows for a buried semiconductor region located deeper than previously described semiconductor structures, for example at a depth that can be greater than 5 pm.

[0143] A simplified example of a process for forming a semiconductor structure 410 comprises: - an implantation from the upper face 41 IA of the semiconductor substrate 411 to form the first buried semiconductor region 412, this implantation being of the second type of doping, opposite to the type of doping of the semiconductor substrate 411, in this example the implantation is of type N: this implantation can be preceded by the formation of a mask to mask the areas of the semiconductor substrate 411 which must not be N doped, or even by an alignment mask; - an epitaxial growth from the upper face 41 IA of the semiconductor substrate 411 to form a weakly doped epitaxial layer 417 of the first type of doping, in this example of type P; - an engraving from the upper face 417A of the epitaxial layer 417 to form a shallow trench in the epitaxial layer 417, followed by a filling from this trench, for example in silicon oxide, to form the insulating trench 415; - a deep implantation in the epitaxial layer 417 through the insulating trench 415 to form the semiconductor box 416, this implantation being of the first type of doping, in this example of type P, this implantation being for example carried out so as to retain a portion 417B of the epitaxial layer 417 between the semiconductor box 416 and the semiconductor substrate 411; - a deep implantation in the epitaxial layer 417 down to the semiconductor substrate 411, and around the portion 417B of the epitaxial layer 417, to form the second buried semiconductor region 413, this implantation being of the second type of doping, in this example of type N; - an implantation from the upper face 417A of the epitaxial layer 417 to the second buried semiconductor region 413 and around the insulating trench 415, to form the annular semiconductor box 414, this implantation being of the second type of doping, in this example of type N.

[0144] The other features and variants described in relation to [Fig. 2], for example the metal stacks 202, the contacts 204, the second portion 201B of the conductor line, can be applied to the embodiment of [Fig. 4]. In particular, similarly to the embodiment of [Fig. 2], the conductor line 401 further comprises all or part of the metal stacks 202 forming part of an interconnect structure 220 (BEOL) positioned above the semiconductor substrate 411. Furthermore, similarly to the embodiment of [Fig.2], a first contact 204A and a second contact 204B, positioned on the annular semiconductor boxes 414 of the semiconductor structures 410, allow each of the semiconductor structures 410 to be connected to respectively a first metal stack 202A and a second metal stack 202B, the second metal stacks 202B between the two semiconductor structures 410 being connected to each other at the last metallization level M5, or at any other metallization level.

[0145] Conductor line 401 comprises: - the conductive portions 401A (first portions) formed by the N-doped semiconductor regions 412, 413, 414 of the semiconductor structures 410; - a second portion 401B between the first portions 401A, the second portion being similar to the second portion 201A described in relation to [Fig.2], the second portion 401B being connected to each of the first portions 401A by one of the second contacts 204B; and - the conductive segments 221A of the first metallic stacks 202A each connected to one of the first portions 401A by one of the first contacts 204A.

[0146] Similar to what is described in relation to [Fig. 2], the conductive line 401 can be connected to a detection circuit (not shown). For example, a first end 401C of the conductive line 401 can be connected to a first terminal of the detection circuit at the first metallization level M1, and a second end 401D of the conductive line 401 can be connected to a second terminal of the detection circuit at the first metallization level M1, but the connection can be made at any other metallization level. The detection circuit can be configured to detect a change in an electrical parameter in the conductive line 401 indicating the presence of a crack. One end of each conductive segment 221A can correspond to one of the first 401C and second 401D ends of the conductive line 401.

[0147] Such a detection device 400 makes it possible to detect a crack at depths of up to a buried semiconductor region of the semiconductor structures 410, the first buried semiconductor region 412, or the second buried semiconductor region 413 in the example of [Fig. 4]. More broadly, the detection device 400 makes it possible to detect a crack along the conductive line 401, between the first buried semiconductor region 412 and the upper metallization level M5. To detect a crack, a change in electrical parameter in the conductive line 401 can be determined, for example, an increase in resistance when the conductive line is damaged by a crack in one of the semiconductor regions 412, 413, 414, or even infinite resistance when the conductive line 401 is interrupted. A lower resistance limit can be defined to determine whether a crack has occurred.

[0148] This buried semiconductor region can be located at a depth greater than 4 pm, or even greater than 5 pm. Thus, the 400 detection device can detect a crack up to a depth exceeding 5 pm.

[0149] According to an alternative that can be applied in particular to each of the embodiments of Figures 2 to 4, the second metal stacks 202B between the two semiconductor structures 210, 310, 410 could be connected to each other by a conducting segment at the first metallization level M1, instead of being at the last metallization level M5. For example, the conducting segments 221B of the second metal stacks 202B could be connected to each other, or be a single continuous conducting segment. According to this variant, the second portion 201B', 301B', 401B' of the conducting line 201', 301', 401' would run only at the first metallization level M1, as represented by the dashed line in Figures 2, 3, 4, and would pass between the second metallic stacks 202B at the first metallization level M1. The (first) conducting line 201', 301', 401' could therefore not run higher than the first metallization level. Ml, and no longer up to the last level of metallization M5. This variant can thus allow less doubt as to the location of a crack detected by the conductive line 201', 301', 401' i.e. to be able to detect a crack in one of the semiconductor structures or in the semiconductor substrate, and not in the interconnection structure 220.

[0150] According to a variant that can be applied in particular to each of the embodiments of figures 2 to 4, the second metallic stacks 202B between the two semiconducting structures 210, 310, 410 could be connected to each other by a conductive segment at any other level of metallization.

[0151] In relation to Figures 5 to 7, we will describe other crack detection devices 500, 600, 700. These other crack detection devices differ from crack detection devices 200, 300, 400 in Figures 2 to 4 primarily in that there is not one but two conductive lines: a first conductive line formed in the interconnection structure and in each semiconductor structure, and a second conductive line formed in the interconnection structure (but not in the semiconductor structures). The first conductive line is intended to detect a crack preferentially in the semiconductor substrate or in at least one of the semiconductor structures. The second conductive line is intended to detect a crack preferentially in the interconnection structure. The first and second conductive lines are preferably insulated from each other.The semiconductor structures in Figures 5, 6, 7 are similar respectively to the semiconductor structures in Figures 2, 3, 4, therefore they are not described again, and retain the same numerical references in the figures.

[0152] In Figures 5 to 7, the first conducting line 501, 601, 701 is symbolized by a dashed line, which allows visualization of one conducting path among several possible paths along this first conducting line. The first conducting line 501, 601, 701 is therefore not limited to this dashed line. Similarly, the second conducting line 503, 603, 703 is symbolized by a dashed line, which allows visualization of one conducting path among several possible paths along this second conducting line. The second conducting line 503, 603, 703 is therefore not limited to this dashed line.

[0153] Figure 5 is a schematic and partial cross-sectional view illustrating a device crack detection 500 according to another embodiment.

[0154] The crack detection device 500 of [Fig.5] has many elements in common with the crack detection device 200 of [Fig.2] and only the differences between the two crack detection devices are detailed in the following description.

[0155] The crack detection device 500 of [Fig.5] differs from the crack detection device 200 of [Fig.2] mainly in that the first conductive line 501 passes only through the first metallization level M1 of the interconnecting structure 520, and in that it includes a second conductive line 503 which passes through all the metallization levels M1-M5 of the interconnecting structure 520, but does not pass through the semiconducting structures 210.

[0156] Similar to the interconnection structure 220 of Figures 2 to 4, the interconnection structure 520 comprises conductive segments 521 at each metallization level M1-M5 and conductive vias 522 between the conductive segments 521 of the different metallization levels M1-M5. The conductive segments 521 and the conductive vias 522 are embedded in an insulating layer 523. The conductive segments 521 and the conductive vias 522 from the second metallization level M2 onward are arranged in several metal stacks 502. The metal stacks 502 include third metal stacks 502A and fourth metal stacks 502B.

[0157] The first conductive line 501 includes conductive segments 521A, 521B of the first metallization level M1 and contacts 204, similar to the contacts described in connection with Figures 2 to 4. The contacts 204 include first contacts 204A connecting each of the semiconductor structures 210 to a first conductive segment 521A, and second contacts 204B connecting each of the semiconductor structures 210 to a second conductive segment 521B. Each of these contact links is made at the first level of metallization ML. In other words, the first and second conductive segments 521A, 521B are part of the first level of metallization ML. The contacts 204 are positioned on the upper face 210A of the semiconductor structures 210, which corresponds in [Fig.5] to the upper face 21 IA of the semiconductor substrate 211.In particular, the contacts 204 are positioned on the annular semiconductor boxes 214 of the semiconductor structures 210, so that each annular semiconductor box 214 is connected to first and second conductive segments 521A, 521B.

[0158] The second conducting segments 521B between the two semiconducting structures 210 are connected to each other at the first level of metallization M1, or form a single continuous second conducting segment 521B.

[0159] The first 501 conductor line includes: - the first portions 501A formed by the N-doped semiconductor regions 213, 214 of the semiconductor structures 210, similar to the first portions 201A of [Fig.2]; - a second portion 501B between the first portions 501A, the second portion being formed by the second conductive segment 521B at the first level of metallization M1, similarly to the second portion 20IB' according to the variant described previously in connection with figures 2 to 4, the second portion 501B being connected to each of the first portions 501A by one of the second contacts 204B; and - the first conductive segments 521A connected to the first portions 501A by the first contacts 204A.

[0160] The first conductive line 501 can be connected to a first detection circuit, of which terminals 505A and 505B are shown. For example, a first end 501C of the first conductive line 501 can be connected to a first terminal 505A of the first detection circuit at the first metallization level M1, and a second end 501D of the first conductive line 501 can be connected to a second terminal 505B of the first detection circuit at the first metallization level M1. The first detection circuit can be configured to detect a change in an electrical parameter in the first conductive line 501 indicating the presence of a crack in the semiconductor substrate 211. One end of each conductive segment 521A can correspond to one of the first 501C and second 501D ends of the first conductive line 501.

[0161] The first conductive line 501 uses the conductive segments 521A, 521B only at the first level of metallization M1, so as to detect a crack preferentially in the semiconducting structures 210.

[0162] The first conductive line 501 enables the detection of a crack deep into a buried semiconductor region of the semiconductor substrate 211, the buried semiconductor region 213, similarly to that described in relation to [Fig. 2]. More broadly, the detection device 500 enables the detection of a crack along the first conductive line 501, between the buried semiconductor region 213 and the first metallization level ML. To detect a crack, a change in electrical parameters can be determined in the first conductive line 501, for example, an increase in resistance when the first conductive line 501 is damaged by a crack in one of the semiconductor regions 213, 214, or even infinite resistance when the first conductive line 501 is interrupted. A first lower resistance limit can be defined to determine whether a crack has occurred along the first conductive line 501..

[0163] The second conductive line 503 comprises a conductive segment 521E (fifth conductive segment) of the second metallization level M2 of each third metal stack 502A and a conductive segment 521F (sixth conductive segment) of the second metallization level M2 of each fourth metal stack 502B, and other conductive segments 521 of the third At the final metallization levels M3-M5 for each fourth metal stack 502B, the conductive segments of each fourth metal stack 502B are connected to each other by conductive vias 522. The adjacent fifth and sixth conductive segments 521E, 521F are connected to each other by a conductive segment 521D (fourth conductive segment) of the first metallization level M1 and by conductive vias 522, thus connecting the adjacent third and fourth metal stacks 502A, 502B. The fourth conductive segment 521D is isolated from the first and second conductive segments 521A, 521B that form part of the first conductive line 501. Thus, the second conductive line 503 is isolated from the first conductive line 501.The adjacent fourth metal stacks 502B are connected to each other at the last metallization level M5 by a conductive segment 521C (seventh conductive segment) which is continuous between these fourth metal stacks.

[0164] The second conductive line 503 thus passes between the first metallization level M1 and the last metallization level M5, so as to detect a crack at all metallization levels of the interconnection structure 520.

[0165] Alternatively, the third and fourth adjacent metal stacks 502A, 502B could be connected to each other by a conductive segment of the second metallization level M2. For example, the fifth and sixth adjacent conductive segments 521E, 521F could be directly connected to each other. According to this alternative, the second conductive line 503 could detect a crack between the second metallization level M2 and the last metallization level M5 of the interconnecting structure 520.

[0166] Alternatively, the fourth adjacent 502B metal stacks could be linked together at a level of metallization lower than the last metallization level M5.

[0167] The second conductive line 503 can be connected to a second detection circuit, of which terminals 506A and 506B are shown. For example, a first end 503C of the second conductive line 503 can be connected to a first terminal 506A of the second detection circuit at the second metallization level M2, and a second end 503D of the second conductive line 503 can be connected to a second terminal 505B of the second detection circuit at the second metallization level M2. The second detection circuit could be connected to the second conductive line at a higher metallization level. The second detection circuit can be configured to detect a change in an electrical parameter in the second conductive line 503 indicating the presence of a crack in the interconnecting structure 520. One end of each conductive segment 521E can correspond to one of the first 503C and second 503D ends of the second 503 conductive line.

[0168] To detect a crack, a change in electrical parameter can be determined in the second conductive line 503, for example, an increase in resistance, or even infinite resistance. A second lower resistance limit can be defined to determine whether a crack has occurred along the second conductive line 503.

[0169] The second lower resistance limit may be lower than the first lower resistance limit.

[0170] Fig. 6 is a schematic and partial cross-sectional view illustrating a crack detection device 600 according to another embodiment.

[0171] The embodiment of [Fig.6] differs from the embodiment of [Fig.5] in that the semiconductor structures 310, similar to those of [Fig.3], replace the semiconductor structures 210.

[0172] Thus, the first conductive line 601 comprises: - the first 601A portions formed by the N-doped 312, 314 semiconductor regions of the 310 semiconductor structures, similar to the first 301A portions of [Fig.3]; - a second portion 601B between the first portions 601 A, the second portion being formed by the second conductive segment 521B at the first level of metallization M1, similarly to the second portion 30 IB' according to the variant described previously in connection with figures 2 to 4, the second portion 601B being connected to each of the first portions 601A by one of the second contacts 204B; and - the first conductive segments 521A connected to the first portions 601A by the first contacts 204A.

[0173] The first conductive line 601 uses the conductive segments 521A, 521B only at the first level of metallization M1, so as to detect a crack preferentially in the semiconducting structures 310.

[0174] The first conductive line 601 can be connected to a first detection circuit, of which terminals 505A and 505B are shown. For example, a first end 601C of the first conductive line 601 can be connected to a first terminal 505A of the first detection circuit at the first metallization level M1, and a second end 601D of the conductive line 601 can be connected to a second terminal 505B of the first detection circuit at the first metallization level M1. The first detection circuit can be configured to detect a change in an electrical parameter in the first conductive line 601 indicating the presence of a crack in the semiconductor substrate 311. One end of each segment conductor 521A can correspond to one of the first 601C and second 601D ends of the first 601 conductor line.

[0175] The first conductive line 601 enables the detection of a crack deep into a buried semiconductor region of the semiconductor substrate 311, the buried semiconductor region 312, similarly to what is described in connection with [Fig. 3]. More broadly, the detection device 600 enables the detection of a crack along the first conductive line 601, between the buried semiconductor region 312 and the first metallization level M1. To detect a crack, a change in electrical parameters can be determined in the first conductive line 601, for example, an increase in resistance when the first conductive line 601 is damaged by a crack in one of the semiconductor regions 312, 314, or even infinite resistance when the first conductive line 601 is interrupted.A first lower limit of resistance can be defined to determine if a crack has occurred along the first conductive line 601.

[0176] The second conductive line 503 is similar to that described in connection with [Fig.5], the variants described being applicable.

[0177] Fig. 7 is a schematic and partial cross-sectional view illustrating a crack detection device 700 according to another embodiment.

[0178] The embodiment of [Fig.7] differs from the embodiment of [Fig.5] in that the semiconductor structures 410, similar to those of [Fig.4], replace the semiconductor structures 210.

[0179] Thus, the first 701 guideline comprises: - the first portions 701A formed by the N-doped semiconductor regions 412, 413, 414 of the semiconductor structures 410, similar to the first portions 401A of [Fig.4]; - a second portion 701B between the first portions 701 A, the second portion being formed by the second conductive segment 521B at the first level of metallization M1, similarly to the second portion 40IB' according to the variant described previously in connection with figures 2 to 4, the second portion 701B being connected to each of the first portions 701A by one of the second contacts 204B; and - the first conductive segments 521A connected to the first portions 701A by the first contacts 204A.

[0180] The first conductive line 701 uses the conductive segments 521A, 521B only at the first level of metallization M1, so as to detect a crack preferentially in the semiconducting structures 410.

[0181] The first conductive line 701 can be connected to a first detection circuit, the terminals of which 505A, 505B are shown. For example, a first end 70IC of the first conductive line 701 can be connected to a first terminal 505A of the first detection circuit at the first metallization level M1, and a second end 701D of the first conductive line 701 can be connected to a second terminal 505B of the first detection circuit at the first metallization level M1. The first detection circuit can be configured to detect a change in an electrical parameter in the first conductive line 701 indicating the presence of a crack in at least one of the semiconductor structures 410. One end of each conductive segment 521A can correspond to one of the first 701C and second 701D ends of the first conductive line 701.

[0182] The first conductive line 701 enables the detection of a crack deep into a buried semiconductor region of the semiconductor structures 410, for example, in the first buried semiconductor region 412 or the second buried semiconductor region 413, similarly to what is described in connection with [Fig. 4]. More broadly, the detection device 700 enables the detection of a crack along the first conductive line 701, between the first buried semiconductor region 412 and the first metallization level ML. To detect a crack, a change in electrical parameter can be determined in the first conductive line 701, for example, an increase in resistance when the first conductive line 701 is damaged by a crack in one of the semiconductor regions 412, 413, 414, or even an infinite resistance when the first conductive line 701 is interrupted.A first lower limit of resistance can be defined to determine if a crack has occurred along the first conductive line 701.

[0183] The second conductive line 503 is similar to that described in connection with [Fig.5], the variants described being applicable.

[0184] In the examples in Figures 2 to 7, four metallic stacks are shown by way of example, but there could be more, for example when there are more than two semiconductor structures, or fewer, for example when there is only one semiconductor structure. Many variations of metallic stacks, or even other conductive structures in the interconnection structure, could be considered by a person skilled in the art.

[0185] In all the embodiments described, and more generally for a crack detection device according to one embodiment, or an electronic chip according to one embodiment, the insulating layer of the interconnect structure can be made of an oxide, for example, silicon dioxide. Alternatively, and advantageously, the insulating layer of the interconnect structure can be made of a dielectric material of the 1ow-k type, that is, a material having a low dielectric constant K compared to that of silicon dioxide, or even an ultra-low-K type dielectric material. Indeed, this type of dielectric material can lead to cracking, in which case a detection device is particularly useful.

[0186] Embodiments allow for the detection of deep cracks in the semiconductor substrate, or the semiconductor structure formed in and / or on the semiconductor substrate (FEOL level). Embodiments also allow for the detection of cracks in the interconnect structure (BEOL). Embodiments allow for the differentiation of a crack at the FEOL level from a crack at the BEOL level, without necessarily increasing the surface area occupied by the detection device.

[0187] In the described embodiments, it can be seen that the detection device can be manufactured using microelectronics fabrication techniques, for example, existing production lines based on the manufactured semiconductor structures. For example, the detection device can be manufactured without adding any extra steps, since the interconnect structure and the semiconductor structures are already planned for fabrication.

[0188] The embodiments are adapted to the co-integration of several semiconductor structures, for example, different ones, formed in and / or on the same semiconductor substrate. In particular, all or part of the three semiconductor structures described in Figures 2 to 7 can be co-integrated in and / or on the same semiconductor substrate. For example, the co-integration includes at least one eSTM memory. For example, the triple-well and vertical-gate semiconductor structures of an eSTM memory can be co-integrated.

[0189] The embodiments described below are particularly well suited to detecting cracks in electronic chips, especially during the individualization of electronic chips by cutting, for example by laser cutting, a semiconductor wafer. Thus, the embodiments can find numerous applications.

[0190] The embodiments described above can be used in many types of industrial markets, for example: - the automotive industry, for example in the field of automotive electrification or in the field of advanced driver assistance systems (ADAS); - the industrial sector, for example in the field of green energy, in the field of infrastructure electrification, the Internet of Things (IoT) and Smart Homes; - the personal electronics industry, for example in the field of mobile telephony and the Internet of Things (IoT), as well as in the field of broadband interfaces; - the communications equipment, computer and peripherals industry, for example in the field of infrastructure and data centers (Data Centers), and in the field of low Earth Orbit (LEO) satellites.

[0191] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, two similar semiconductor structures in and / or on the semiconductor substrate through which the (first) conductive line of the sensing device passes are shown. Several other variations can be considered by those skilled in the art. According to one variation, the (first) conductive line of the sensing device could pass through a single semiconductor structure. In this case, the conductive line might only pass as far as the first metallization level of the interconnecting structure.According to another variant, different semiconductor structures could be formed in and / or on the semiconductor substrate, and the (first) conductive line of the detection device could then pass through these different semiconductor structures.

[0192] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A crack detection device (200; 300; 400; 500; 600; 700) adapted to detect a crack in an electronic chip, the crack detection device comprising a first conductive line (201; 301; 401; 501; 601; 701) for detecting a crack in at least one semiconductor structure (210; 310; 410) located in, and / or on, a semiconductor substrate (211; 311; 411), an interconnection structure (220; 520) being connected to a first face (210A; 310A; 410A) of the at least one semiconductor structure, the first conductive line being contained within the interconnection structure and within the at least one semiconductor structure, and comprising: - at least one first conductive segment (221A; 521A) and at least a second conductive segment (221B;521B), said at least one first and second conducting segments being of a first level of metallization (M1) of the interconnect structure and being electrically insulated from each other by an insulating layer (223; 523); and - a buried conducting region (213; 312; 412, 413) deep within each semiconducting structure, said buried conducting region being connected to at least one first conducting segment and at least one second conducting segment, an insulating region (215; 315, 318; 415) being positioned between the first face of the semiconducting structure and the buried conducting region.;

2. Device according to claim 1, wherein the semiconductor substrate (211; 311; 411) is doped with a first type of conductivity, the buried conductive region (213; 312; 412, 413) being a semiconductor region doped with a second type of conductivity opposite to the first type of conductivity.

3. Device according to claim 2, wherein each semiconductor structure (210;310;410) comprises: - a semiconductor box (214; 314; 414) doped with the second type of conductivity, and extending in depth from the first face (210A; 310A; 410A) of the semiconductor structure so as to electrically connect said first face and the buried conductive region (213; 312; 412, 413); - conductive elements (204) connected to the first face of the semiconductor structure, the conductive elements comprising a first conductive element (204A) connecting the semiconductor box to the first conductive segment (221A; 521A), and a second conductive element (204B) connecting the semiconductor box to the second conductive segment (221B; 521B).

4. Device according to any one of claims 1 to 3, wherein the buried conductive region is at a depth greater than 0.5 pm, for example greater than or equal to 1 pm, or greater than or equal to 3 pm, or greater than or equal to 5 pm.

5. Device according to any one of claims 1 to 4, wherein each first conductive segment (221 A) is included in a first metallic stack (202A) comprising several levels of metallization of the interconnection structure, and each second conductive segment (22IB) is included in a second metallic stack (202B) comprising several levels of metallization of the interconnection structure.

6. Device according to any one of claims 1 to 5, wherein at least one semiconductor structure (210;310;410) comprises several semiconductor structures, at least one first conducting segment (221A; 521A) comprising several first conducting segments and at least one second conducting segment (221B; 521B) comprising several second conducting segments, the second conducting segments between two adjacent semiconductor structures among the semiconductor structures being connected together in the interconnection structure (220; 520).

7. Device according to claim 6, wherein the second conducting segments (521B) are connected to each other at the first metallization level (Ml) of the interconnecting structure.

8. Device according to claim 6 in its dependence on claim 5, wherein the second metallic stacks (202B) between the two adjacent semiconductor structures are connected to each other by a third conductive segment (22IC) of a level of metallization of the interconnecting structure higher than the first level of metallization.

9. A device according to any one of claims 1 to 8, wherein the first conductive line (201; 301; 401) is also adapted to detect a crack in the interconnection structure (220).

10. Device according to any one of claims 1 to 8, further comprising a second conductive line (503) for detecting a crack in the interconnection structure (520), said second line being included in the interconnection structure (520) and being separate from the first conductive line (501; 601; 701).

11. Device according to claim 10, wherein the second conductive line (503) comprises: - at least one fourth conductive segment (521D) of the first metallization level (M1) of the interconnection structure (520), each fourth conductive segment being insulated from at least one first and at least one second conductive segments by the insulating layer (523); - at least one fifth conductive segment (521E) of a metallization level of the interconnection structure higher than the first metallization level; - at least one sixth conductive segment (521E) of a metallization level of the interconnection structure higher than the first metallization level; each fourth conductive segment connecting at least one fifth conductive segment to at least one sixth conductive segment, for example via conductive vias (522) of the interconnection structure.

12. Device according to claim 11, wherein each fifth conductive segment (521E) is included in a third metal stack (502A) comprising several levels of metallization of the interconnecting structure (520) from the second level of metallization (M2), and / or each sixth conductive segment (521F) is included in a fourth metal stack (502B) comprising several levels of metallization of the interconnecting structure from the second level of metallization (M2), for example two adjacent fourth metal stacks (502B) being connected to each other at a level of metallization higher than the second level of metallization by a seventh conductive segment (521C).

13. Device according to any one of claims 10 to 12, wherein the second conductive line (503) comprises a first end (503C) connected to a first terminal (506A) of a second detection circuit and a second end (503D) connected to a second terminal (506B) of the second detection circuit, so as to measure an electrical signal in said second conductive line to determine the presence of a crack.

14. A device according to any one of claims 1 to 13, wherein the first conductive line (201; 301; 401; 501; 601; 701) comprises a first end (201C; 301C; 401C; 501C; 601C; 701C) connected to a first terminal (505A) of a first detection circuit and a second end (201D; 301D; 401D; 501D; 601D; 701D) connected to a second terminal (505B) of the first detection circuit, so as to measure an electrical signal in said first conductive line to determine the presence of a crack.

15. Device according to claim 14 in its dependence on claim 13, wherein the second terminal (506B) of the second detection circuit is electrically isolated from the second terminal (505B) of the first detection circuit, for example the first terminal (506A) of the second detection circuit is electrically connected to the first terminal (505A) of the first detection circuit.

16. Device according to any one of claims 10 to 15, wherein the insulating layer (230) comprises a material with a low dielectric constant compared to the dielectric constant of silicon dioxide.

17. Electronic chip comprising: - a semiconductor substrate (211;311;411); - at least one semiconductor structure (210;310;410) located in, and / or on, the semiconductor substrate; - an interconnection structure (220; 520) connected to a first face (210A; 310A; 410A) of the at least one semiconductor structure; and - a crack detection device according to any one of claims 1 to 16.

18. Electronic chip according to claim 17, wherein at least one semiconductor structure (210; 310; 410) comprises several semiconductor structures, at least one semiconductor structure among said semiconductor structures comprising a vertical gate structure of a buried selector transistor of a trench selector transistor integrated memory cell.

19. Electronic chip according to claim 17 or 18, wherein the crack detection device is positioned at the periphery of the electronic chip, for example around a region of electronic circuits of the electronic chip, for example in a sealing ring of the electronic chip.

20. A method of using the crack detection device according to any one of claims 1 to 16, the method comprising: - emitting a first electrical signal at a first end (201C; 301C; 401C; 501C; 601C; 701C) of the first conductive line (201; 301; 401; 501; 601; 701); - receiving the first electrical signal at a second end (201D; 301D; 401D; 501D; 601D; 701D) of the first conductive line, and measuring a first resistance value of the first electrical signal received; - comparing the first measured resistance value with a first lower resistance limit to determine the presence of a crack in the first conductive line.

21. A method of use according to claim 20 for a crack detection device according to any one of claims 10 to 13 and 15, the method comprising: - emitting a second electrical signal at a first end (503C) of the second conductive line (503; 603; 703); - receiving the second electrical signal at a second end (503B) of the second conductive line, and measuring a second resistance value of the second received electrical signal; - comparing the second measured resistance value with a second lower resistance limit to determine the presence of a crack in the second conductive line; the first lower resistance limit being, for example, greater than the second lower resistance limit.

22. A method for co-integrating several semiconductor structures (210; 310; 410) in, and / or on, the same semiconductor substrate (211; 311; 411), the method further comprising the formation of an interconnection structure (220; 520) connected to a first face (210A; 310A; 410A) of the semiconductor structures, and a crack detection device according to any one of claims 1 to 16, at least one semiconductor structure among the semiconductor structures comprising a vertical gate structure of a buried selector transistor of a trench selector transistor integrated memory cell.

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