Step-down switching converter

Abstract

Buck Switching Converter This description relates to a switching converter and a method for controlling the converter. In each pulse frequency modulation cycle, the following steps are implemented. At the beginning of the cycle, a counted number (ClkNb) of clock signal periods is initialized (404), a high-side switch (HSS) is switched to the on state, and a first threshold (TH1) is incremented (406). The counted number (ClkNb) is updated at each clock signal period (412, 416). The high-side switch (HSS) is switched (412) to the off state when the counted number (ClkNb) equals the first threshold (TH1), and the cycle terminates (414) when the counted number (ClkNb) equals a second threshold (TH2). At the end of the cycle, the first threshold (TH1) is initialized if the output voltage is greater than a setpoint, and a new cycle begins if the output voltage is less than the setpoint. See Figure 4 for the abbreviated version.

Description

Title of the invention: Buck switching converter technical field

[0001] This description relates generally to electronic circuits, for example integrated electronic circuits, and, more particularly, to a buck-switched mode power supply and its control method. Previous technique

[0002] Many known systems and applications include a buck-switching converter configured to provide an output voltage at a target value from a supply voltage, both the output voltage and the supply voltage being direct current (DC) voltages. When the target value is lower than the supply voltage, the converter is a buck converter. The output voltage is used to power a load coupled to the converter output.

[0003] There are several ways to control a buck switching converter. In particular, it is known to control a converter using pulse frequency modulation (PFM).

[0004] Generally, the duration for which a high-side switch of a converter is in the conducting state during each operating cycle in pulse frequency modulation of the converter is fixed. This duration can alternatively be variable so that a current in an inductor of the converter reaches the same peak value during each operating cycle, each operating cycle corresponding to a current pulse in the inductor.

[0005] However, known buck switching converters operating in pulse frequency modulation have disadvantages. Summary of the invention

[0006] There is a need to overcome all or part of the disadvantages of known buck switching converters when they operate in pulse frequency modulation.

[0007] There is also a need to overcome all or part of the drawbacks of known pulse frequency modulation control methods for buck switching converters.

[0008] An embodiment overcomes all or part of the disadvantages of known buck switching converters.

[0009] An embodiment overcomes all or part of the disadvantages of known pulse frequency modulation control methods for buck switching converters.

[0010] One embodiment provides a buck converter configured, at each operating cycle in pulse frequency modulation, to: at the beginning of the operating cycle, initialize a counted number of periods of a clock signal and switch a high-side switch to the conducting state; increment a first threshold by one step; update the counted number of clock signal periods at each clock signal period; switch the high-side switch to the blocked state when the counted number equals the first threshold; to end the operating cycle when the counted number equals a second threshold; and At the end of the operating cycle, compare a converter output voltage to a target value, initialize the first threshold to an initialization value if the output voltage is greater than the setpoint value and start a subsequent operating cycle if the output voltage is less than the setpoint value.

[0011] Another embodiment provides a method for controlling a buck switching converter, the method comprising, at each operating cycle where the converter is controlled by pulse frequency modulation: at the beginning of the operating cycle, initialize a counted number of periods of a clock signal and switch a high-side switch to the conducting state; increment a first threshold by one step; update the counted number of clock signal periods at each clock signal period; switch the high-side switch to the blocked state when the counted number equals the first threshold; to end the operating cycle when the counted number equals a second threshold; and At the end of the operating cycle, compare a converter output voltage to a target value, initialize the first threshold to an initialization value if the output voltage is greater than the setpoint voltage and start a subsequent operating cycle if the output voltage is less than the setpoint voltage.

[0012] According to one embodiment, at each operating cycle in pulse frequency modulation, a low-side switch is switched to the conducting state when the high-side switch is switched to the blocked state.

[0013] According to one embodiment, at each operating cycle in pulse frequency modulation, the low side switch is switched to the blocked state at the end of the operating cycle or when an output current of the converter reaches a zero value before the end of the operating cycle.

[0014] According to one embodiment, the converter is configured to operate selectively in pulse frequency modulation or in pulse width modulation.

[0015] According to one embodiment, the second threshold is configured so that the duration of each operating cycle is equal to one period of a pulse-width modulated signal.

[0016] According to one embodiment, the second threshold has a constant value.

[0017] According to one embodiment, the comparison of the output voltage to the value of The instruction is implemented with hysteresis.

[0018] According to one embodiment, the high-side switch couples an internal node of the converter to a converter supply voltage.

[0019] According to one embodiment, an inductor couples the internal node to an output of the converter. Brief description of the drawings

[0020] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0021] Fig. 1 represents, schematically and in block form, an example of a DC-DC step-down converter;

[0022] [Fig.2] illustrates, with timing diagrams, an example of the operation of the converter of [Fig.1];

[0023] [Fig.3] represents, schematically and in block form, an example of an embodiment of a control circuit for a converter of the type of that in [Fig.1];

[0024] [Fig.4] represents, by way of an organizational chart, an example of an embodiment of a control process implemented by the circuit of [Fig.3];

[0025] [Fig. 5] illustrates, with timing diagrams, an example of the operation of a converter implementing the process of [Fig. 4]; and

[0026] [Fig.6] illustrates, with timing diagrams, another example of the operation of a converter implementing the process of [Fig.3];

[0027] [Fig. 7] illustrates, with timing diagrams, yet another example of the operation of a converter implementing the process of [Fig. 3]; and

[0028] [Fig.8] represents, schematically and in block form, another example of an embodiment of a control circuit for a converter of the type of that in [Fig.1]. Description of the implementation methods

[0029] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0031] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0034] Fig. 1 represents schematically and in block form an example of a buck-switching converter 1.

[0035] Converter 1 is configured to receive a continuous supply voltage Vin (DS for "Direct Current") and to provide a continuous output voltage Vout. In other words, converter 1 is a DC-DC converter.

[0036] The output voltage Vout is regulated by converter 1 to a setpoint value determined by a continuous setpoint voltage Vref received by converter 1. In this description, by way of example, the setpoint value for regulating the output voltage Vout is the value of the voltage Vref. In other words, in this example, the output voltage Vout is regulated to the value of the voltage Vref.

[0037] Converter 1 includes a node 100 configured to receive the voltage Vin. The voltage Vout is supplied by converter 1 at an output node 102. The voltage Vref is received by an input of converter 1. By way of example, the voltages Vin, Vout, and Vref are all referenced to a reference potential, by example the GND ground, this reference potential being received by a node 106 of converter 1.

[0038] The converter 1 is configured to supply the voltage Vout to a load to be powered 108. The load 108 is connected between nodes 102 and 106. In the example of [Fig.1], the load 108 is represented by a capacitor CL and a resistor RL connected together in parallel.

[0039] Although not illustrated in [Fig.1], the converter 1 may include a smoothing capacitor connected to node 102, in parallel with the load 108, for example between nodes 102 and 106.

[0040] The converter 1 includes a high side switch (HSS). The HSS switch is connected between node 100 and an internal node 110 of the converter 1. In other words, the HSS switch has one conduction terminal coupled, for example connected, to node 102, and another conduction terminal coupled, for example connected, to node 110.

[0041] The converter 1 includes an inductance L. The inductance L couples node 110 to node 102. For example, the inductance L has a first coupled terminal, for example connected, to node 110, and a second coupled terminal, for example connected, to node 102.

[0042] The HSS switch is controlled by a ctrlH signal which it receives at its control terminal. The ctrlH signal is, for example, a binary signal. As an example, the HSS switch is implemented by a MOS (Metal Oxide Semiconductor) transistor, for example by a P-channel MOS transistor, or PMOS transistor.

[0043] In the example in [Fig. 1], the ctrlH signal is determined by a sigH signal. For example, the ctrlH signal is in a first state when the sigH signal is in a first state, and in a second state when the sigH signal is in a second state. For example, converter 1 includes a close-range driver circuit, referred to as HSSD in [Fig. 1]. The HSSD circuit receives the sigH signal and provides the ctrlH signal.

[0044] In other examples, the HSSD circuit is omitted and the sigH and ctrlH signals are confused.

[0045] Converter 1 includes a PFMCTRL1 control circuit. The PFMCTRL1 circuit is configured to provide the control signal for the HSS switch. For example, the PFMCTRL1 circuit is configured to provide the sigH signal, for example on an output 112 of the PFMCTRL1 circuit.

[0046] The PFMCTRL circuit is configured here so that converter 1 operates in pulse frequency modulation. As an example, the PFMCTRL 1 circuit includes an input 104 configured to receive the Vref voltage and an input 114 configured to receive the Vout voltage.

[0047] In the example of [Fig. 1], the converter 1 further includes a low-side switch (LSS). The LSS is connected between nodes 102 and 106. In other words, the LSS has one coupled conduction terminal, for example, connected to node 102, and another coupled conduction terminal, for example, connected to node 106. The LSS is controlled by a ctrlL signal that it receives at its control terminal. The ctrlL signal is, for example, a binary signal. By way of example, the LSS is implemented by a MOS (Metal Oxide Semiconductor) transistor, for example, an N-channel MOS transistor, or NMOS transistor.

[0048] In the example in [Fig. 1], the ctrlL signal is determined by a sigL signal. For example, the ctrlL signal is in a first state when the sigL signal is in a first state, and in a second state when the sigL signal is in a second state. For example, converter 1 includes a close-range driver circuit, referred to as LSSD in [Fig. 1]. The LSSD circuit receives the sigL signal and provides the ctrlL signal.

[0049] In other examples, the LSSD circuit is omitted and the sigL and ctrlL signals are confused.

[0050] The PFMCTRL1 circuit is configured to provide the control signal for the LSS switch. For example, the PFMCTRL1 circuit is configured to provide the sigL signal, for example on an output 116 of the PFMCTRL1 circuit.

[0051] By way of example, to control the LSS switch, the PFMCTRL1 circuit receives one or more signals that allow it to know when the current IL in the inductor L is zero. For example, in [Fig. 1], the PFMCTRL1 circuit receives a sigZ signal indicating whether the current IL is zero or not. For example, the sigZ signal is received by an input 118 of the PFMCTRL1 circuit. For example, the converter 1 includes a ZCD circuit configured to provide the sigZ signal. For example, the ZCD circuit has a coupled terminal, for example connected, to node 110.

[0052] The converter 1 includes an inductance L. The inductance L couples node 110 to node 102. For example, the inductance L has a first coupled terminal, for example connected, to node 110, and a second coupled terminal, for example connected, to node 102.

[0053] [Fig.2] illustrates, with timing diagrams, an example of the operation of the converter of [Fig.1].

[0054] More specifically, [Fig.2] illustrates the evolution as a function of time t, of the current IL in the inductance L, and the output voltage Vout relative to its corresponding setpoint value, in this example, to the voltage Vref.

[0055] At an instant tO, the voltage Vont is greater than its setpoint value Vref, and the current IL is zero.

[0056] At a time tl after time t0, the voltage Vout falls below its setpoint value Vref. This is detected by the PFMCTRL1 circuit. In response, the PFMCTRL1 circuit switches the HSS switch to the conducting state for a duration TONH. As a result, from time tl on, the current IL in the inductor L increases, and, furthermore, the voltage Vout rises and returns above its setpoint value Vref. Time tl also marks the beginning of an operating cycle of duration Te.

[0057] At a time t2 after time t1, corresponding to the end of the duration TONH, the PFMCTRL1 circuit switches the HSS switch to the blocked state. Furthermore, in this example, the PFMCTRL1 circuit switches the LSS switch to the conducting state for a duration TONL. From time t2 onwards, the current IL decreases, as does the voltage Vout.

[0058] At a time t3 later than time t3, the current IL in the inductor L becomes zero. In response to this, the PFMCTRL1 circuit switches the LSS switch to the blocked state. Time t3 therefore marks the end of the duration TONL.

[0059] At time t3, the voltage Vout is greater than its setpoint value Vref. The PFMCTRL1 circuit therefore does not initiate a new operating cycle.

[0060] The LSS and HSS switches are held blocked for a duration Toff from time t3 until time t4, when the voltage Vref falls below its setpoint value Vref. Time t4 marks the end of the current operating cycle, and therefore the duration Te of this current cycle, and the beginning of a new operating cycle. In other examples, a duration Toff is provided for each operating cycle so that the duration Te of each operating cycle is constant.

[0061] The operation described in relation to the times t1, t2 and t3 is then repeated at the respective times t4, t5 and t6.

[0062] In the example of [Fig.2], the duration TONH is constant. The duration TONH therefore determines, along with the values ​​of the voltages Vin and Vout and the value of the inductance L, the amount of charge that the converter 1 supplies to its output 102, and thus to the load 108, at each operating cycle.

[0063] However, the value of the voltage Vin can vary during the operation of the converter 1, particularly when this voltage Vin is supplied by a battery. For example, the voltage Vin can vary within a range of voltage values ​​from 6 V to 20 V, or even up to 32 V.

[0064] It follows that the average current that the converter 1 can deliver on its output 102, the quantity of load that the converter 1 can deliver in each operating cycle, and the amplitude of the variations of the voltage Vout around its value setpoints depend on the voltage Vin and the voltage Vont, that is to say on the consumption of the load 108.

[0065] It is then difficult, if not impossible, to find a compromise between the amplitude of the variations of the voltage Vout around its setpoint value Vref, which we want to be as small as possible, and the maximum current that the converter 1 can deliver to its load 108, which we want to be as large as possible.

[0066] For example, a short TONH duration limits the amplitude of the variations in the out voltage (Vout) around its setpoint value (Vref), but results in a relatively low maximum current output. Conversely, increasing the TONH duration increases the maximum current that the converter can deliver, but results in an increase in the amplitude of the variations in the out voltage (Vout) around its setpoint value (Vref).

[0067] To overcome the disadvantages of buck switching converters of the type described in relation to figures 1 and 2, that is to say converters in which, in pulse frequency modulation, the duration TONH is constant and identical to each operating cycle, it has been proposed to make the duration TONH dependent on the voltages Vin and Vout.

[0068] However, this implies a more complex control circuit for the high-side switch, resulting in an increase in the converter's surface area and power consumption. Furthermore, the circuits used to make the TONH duration dependent on the Vin and Vout voltages are generally analog circuits comprising resistive and capacitive components with values ​​that determine the TONH duration of each cycle. The values ​​of these resistive and capacitive components depend on variations in the manufacturing process and temperature, which is undesirable. Moreover, even when making the TONH duration dependent on Vin and Vout, the TONH duration has a maximum value determined by a maximum output current value and a maximum amplitude of the Vout voltage variations.This poses a problem during load transients where the consumption of the load 108 varies, for example increases, too rapidly compared to the maximum current value that the converter can deliver.

[0069] The disadvantages described above for known buck switching converters where the TONH duration is dependent on the Vin and Vout voltages are found in other known converters where the TONH duration is not fixed.

[0070] To overcome the drawbacks of known buck-switching converters, for example the drawbacks of converter 1 described in relation to [Fig. 1] and 2, a converter is proposed here in which, when the converter operates in pulse frequency modulation, the value of the TONH duration is increased between each two successive operating cycles when, at the end of the first of the two In successive cycles, the voltage Vont is always lower than its setpoint value Vref. Furthermore, the TONH duration is reset to an initial value when, at the end of an operating cycle, the voltage Vout is greater than its setpoint value Vref. In this description, each operating cycle in pulse frequency modulation comprises a single on-state operation of the converter's high-side switch, i.e., a single TONH duration.

[0071] In the proposed converter, the duration Te of each operating cycle is fixed, it being understood that two successive cycles of fixed duration Te can be separated from each other by a dead time period.

[0072] In the proposed converter, the adaptation of the value of the duration TONH is implemented by a digital circuit, that is to say a circuit clocked by a clock signal, which makes it possible to avoid the disadvantages associated with the use of analog circuits, for example with regard to the dispersions of resistance and / or capacitance values ​​resulting from the manufacturing process and / or temperature variations, or with regard to the consumption of analog circuits.

[0073] More specifically, in the proposed converter, at each pulse frequency modulation operating cycle, the converter, for example its high-side switch control circuit, implements the following operation. At the beginning of the operating cycle, a counted number of clock signal periods is initialized, and the side switch is switched to the on state. In addition, the value of a first threshold is incremented by a given, preferably constant, step. During the operating cycle, the counted number of clock signal periods is updated at each clock signal period, preferably at the beginning of each clock signal period. For example, this number is incremented by one at each new clock signal period. Also during the operating cycle, the high-side switch is switched to the off state when the counted number of clock signal periods reaches the first threshold.Thus, the first threshold determines, for each operating cycle, the TONH duration of the high-side switch's on state. Then, when the counted number of clock signal periods reaches a second threshold higher than the first, the second threshold preferably being fixed and constant for all operating cycles in pulse frequency modulation, the current operating cycle ends. When the operating cycle ends, either the voltage Vout is lower than its setpoint value Vref, and a new operating cycle begins, or the voltage Vout is higher than its setpoint value Vref, and the value of the first threshold is reset to its initial value.

[0074] For example, when the voltage Vont is greater than its setpoint value Vref at the end of an operating cycle, a new operating cycle will begin when the voltage Vout becomes less than its setpoint value Vref.

[0075] By way of example, the comparison of the voltage Vout to its setpoint value is implemented with hysteresis, and the voltage Vout is then lower than the voltage Vref when the voltage Vout falls below a threshold Vref- which is lower than the setpoint value Vref, and is higher than the voltage Vref when the voltage Vout rises above a threshold Vref+ which is higher than the setpoint value Vref. The thresholds Vref+ and Vref- are determined by the setpoint value Vref and the hysteresis value.

[0076] By way of example, when the converter includes a low-side switch, and not a simple diode, at each pulse frequency modulation operating cycle, the low-side switch is switched to the conducting state when the high-side switch is switched to the blocking state. By way of example, this low-side switch is switched back to the blocking state either when the current IL in the inductor L reaches zero before the end of the operating cycle, that is, before the counted number of clock periods reaches the second threshold, or at the end of the current operating cycle if the current IL has not reached zero before the counted number of clock periods reaches the second threshold.

[0077] Figure 3 schematically represents, in block form, an example of an embodiment of a PFMCTRL2 control circuit for a converter of the type shown in Figure 1. This PFMCTRL2 circuit is configured to implement the operation described above when the converter is operating in pulse frequency modulation. In Figure 3, only the PFMCTRL2 circuit is shown; this PFMCTRL2 circuit can be used as a replacement for the PFMCTRL1 circuit in the converter 1 described previously.

[0078] Similar to the PFMCTRL1 circuit, the PFMCTRL2 circuit includes an input 314 configured to receive the voltage Vout (or a voltage image of the voltage Vout, for example obtained with a resistive voltage divider from the voltage Vout), and an input 304 configured to receive a voltage Vref indicating the setpoint value of the voltage Vout.

[0079] In a manner similar to the PFMCTRL1 circuit, the PFMCTRL2 circuit includes an output 312 configured to provide the sigH control signal for the high side switch HS S.

[0080] Furthermore, in this example where the converter under consideration includes a low-side switch (LSS), the PFMCTRL2 circuit includes an output 316 configured to provide the sigL control signal for the LSS switch. As an example, the PFMCTRL2 circuit includes an input 118 configured to receive the sigZ signal indicating when the current IL in the inductor L reaches zero.

[0081] The PFMCTRL2 circuit further includes an input 300 configured to receive a clock signal Clk.

[0082] The PFMCTRL2 circuit is configured to compare the voltage Vout to its setpoint value Vref, and to provide a cmp signal, for example a binary signal, indicating the result of this comparison. For example, the PFMCTRL2 circuit includes a COMP circuit configured to compare the voltage Vout to its setpoint value Vref, and to provide the cmp signal.

[0083] By way of example, the COMP circuit is a comparator, for example implemented from an operational amplifier. Preferably, the COMP circuit is a comparator with hysteresis.

[0084] For example, the COMP comparator has an input receiving the voltage Vout (or a voltage image of the voltage Vout), another input receiving the voltage Vref indicating the setpoint value of the voltage Vout, and an output providing the cmp signal.

[0085] The PFMCTRL2 circuit is configured to count a number ClkNb of periods of the signal Clk. For example, the PFMCTRL2 circuit includes a COUNTER circuit configured to count a number ClkNb of periods of the signal Clk. The COUNTER circuit, for example a counter, includes an input receiving the signal Clk, and an output providing the number ClkNb.

[0086] The COUNTER circuit further includes an initialization input configured to receive an initialization signal initClkNb. When the initClkNb signal, for example a binary signal, is active, the number ClkNb is initialized to an initialization value. For example, the initialization value of the number ClkNb is zero when the COUNTER is configured to increment the number ClkNb at each period of the signal Clk.

[0087] The PFMCTRL2 circuit is configured to set, at each operating cycle, the value of the first threshold, referenced TH1. In particular, the PFMCTRL2 circuit is configured to initialize the value of the threshold TH1 to its initial value when, at the end of an operating cycle, the voltage Vout is greater than its setpoint value, and, at each operating cycle, to increment the value of the threshold TH1 by a given step.

[0088] For example, the PFMCTRL2 circuit includes a REG circuit configured to store the current value of the threshold TH1. The REG circuit includes an input receiving an initialization signal initTH1. When the initTH1 signal, for example a binary signal, is active, the threshold TH1 is initialized to an initialization value. The REG circuit further includes an input receiving an inc signal. For example, with each pulse of the inc signal, for example a binary signal, the value of the threshold TH1 is incremented by the step value. The REG circuit includes an output providing the threshold TH1, that is, the current value of the threshold TH1.

[0089] The PFMCTRL2 circuit implements the operation described above. For example, the PFMCTRL2 circuit includes an FSM circuit, for example a state machine, for example synchronous with the Clk signal, configured to provide the initTHl, inc, and initClkNb signals from the ClkNb, cmp, and TH1 signals and a second threshold TH2. For example, the FSM circuit receives the ClkNb, TH1, TH2, and cmp signals and provides the inc, initClkNb, and initTHl signals. For example, the FSM circuit is further configured to provide the sigH signal from the TH1 and ClkNb signals. For example, the FSM circuit provides the sigH signal. In this example, the FSM circuit is also configured to provide the sigL signal from the TH1, ClkNb, TH1, TH2, and sigL signals. For example, the FSM circuit receives the sigZ signal and provides the sigL signal.As an example, the PFMCTRL2 circuit, for instance its FSM circuit, can be configured, when the voltage Vout falls below its setpoint value Vref and a new operating cycle begins, to activate an oscillator with an ENclk signal from which the Clk signal is obtained. However, this signal can be omitted when the oscillator is continuously activated.

[0090] Figure 4 shows, by way of a flowchart, an example of an embodiment of a control method implemented by the PFMCTRL2 circuit of Figure 3. In other words, Figure 4 shows, by way of a flowchart, an example of a control method for a buck converter operating in pulse frequency modulation, this method being, for example, implemented by the PFMCTRL2 circuit described in relation to Figure 3.

[0091] At step 400 (block "Vout <Vref"), le circuit PFMCTRL2 vérifie si la tension Vout est ou non inférieure à sa valeur de consigne Vref. Par exemple, pour cela, le circuit PFMCTRL2, par exemple son circuit FSM, regarde l'état du signal cmp.

[0092] If the voltage Vout is greater than its setpoint value Vref (output "NO" of block 400), it is not necessary to start a new operating cycle in pulse frequency modulation, and the current value of the threshold TH1 is reset to its initial value during a step 402 ("Initialize TH1" block). The initialization of the threshold TH1 is implemented by the PFMCTRL2 circuit, for example by its FSM circuit via the initTH1 signal.

[0093] Step 402 loops back to step 400, that is to say, is followed by step 400.

[0094] At step 400, if the voltage Vout is less than its setpoint value (output "YES" of block 400), a new operating cycle in pulse frequency modulation begins.

[0095] By way of example, the start of each operating cycle in pulse frequency modulation can be synchronized with the start of a period of the Clk signal, and more particularly with the first period of the Clk signal starting after the voltage Vout has become less than its setpoint value Vref.

[0096] As an alternative example, each operating cycle begins in a non-synchronized manner on the Clk signal, as soon as the voltage Vout becomes less than its setpoint value.

[0097] Each operating cycle begins with a step 404 (block "Start cycle Initialize ClkNb Switch ON HSS").

[0098] At step 404, which marks the beginning of a typical operating cycle, the number NbClk is initialized, for example, to a value of zero. Furthermore, the HSS switch is switched to the on state. For example, the number NbClk is initialized by the PFMCTRL2 circuit, for example, by its FSM circuit via the initClkNb signal. For example, the HSS switch is switched to the on state by the PFMCTRL2 circuit, for example, by its FSM circuit, via the sigH control signal.

[0099] At step 404, or alternatively, at a subsequent step 406 (block "THl=THl+step"), the current value of the threshold TH1 is incremented by the value of the step. In this example, the value of the step is positive, and the value of the threshold TH1 increases during the implementation of step 404.

[0100] In a subsequent step 408 (block "ClkNb=THl"), it is determined whether or not the number ClkNb of periods of the signal Clk counted from the beginning of the current operating cycle is equal to the threshold TH1. This step is implemented by the circuit PFMCTRL2, for example by its FSM circuit, using the signals ClkNb and TH1.

[0101] At step 408, if the number ClkNb is not equal to the threshold TH1 (output "NO" of block 408), for example, if it is less than the threshold TH1, then the number ClkNb is incremented at the beginning of the next period of the signal Clk, at a step 410 (block "ClkNb=ClkNb+1"). Step 410 loops back to step 408. Thus, as long as the number ClkNb is not equal to the threshold TH1, the number ClkNb is incremented at each period of the signal Clk.

[0102] At step 408, if the number ClkNb is equal to the threshold TH1 (output "YES" of block 408), the process continues to a step 412 (block "Switch OFF HSS").

[0103] By way of example, when the converter includes a low-side switch LSS, this LSS switch is switched to the on state during step 412.

[0104] The process continues at step 414 (block "ClkNb=TH2"). Step 410 loops back to step 408. Thus, as long as the number ClkNb is not equal to the threshold TH1, the number ClkNb is incremented at each period of the signal Clk.

[0105] In step 414, it is determined whether or not the number ClkNb of periods of the signal Clk, counted from the beginning of the current operating cycle, is equal to the threshold TH2. This step is implemented by the PFMCTRL2 circuit, for example by its FSM circuit, using the signals ClkNb and TH2. As an example, the threshold TH2 is greater than the threshold TH1 in this example where the number ClkNb is incremented at each new period of the signal Clk.

[0106] At step 412, if the number ClkNb is not equal to the TH2 threshold (output "NO" of block 412), for example, is less than the TH2 threshold, then the number ClkNb is incremented at the beginning of the next period of the signal Clk, at step 416 (block "ClkNb=ClkNb+1"). Step 416 loops back to step 414. Thus, as long as the number ClkNb is not equal to the TH2 threshold, the number ClkNb is incremented at each period of the signal Clk.

[0107] At step 414, if the number ClkNb is equal to the threshold TH2 (output "YES" of block 414), the process continues to a step 418 ("End cycle" block) marking the end of the current operating cycle in pulse frequency modulation.

[0108] By way of example, when the converter includes the low-side switch LSS, at step 414, the PFMCTRL2 circuit checks whether the current IL in the inductor L is zero. If so, the PFMCTRL2 circuit, for example its FSM circuit, switches the LSS switch to the off state via the sigL signal. If not, until the current operating cycle in pulse frequency modulation ends at state 418, the PFMCTRL2 circuit, for example its FSM circuit, switches the LSS switch to the off state at step 418 via the sigL signal.

[0109] Step 418 is followed by step 400. Thus, at the end of a cycle (step 408), if the voltage Vout is still less than its setpoint value Vref, a new operating cycle begins (step 404) without the threshold TH1 having been reset (step 402), from which it follows that the current value of the threshold TH1 will be greater during this new operating cycle than during the preceding operating cycle.

[0110] By way of example, when step 404 is implemented synchronously on the Clk signal, step 408 is, for example, configured to last until the end of the period of the Clk signal that began with the transition of the ClkNb number to the value TH2. Furthermore, in this case, if the converter includes the LSS switch and this switch has not already been switched to the blocked state, this LSS switch is switched to the blocked state at the end of step 418.

[0111] In the example in [Fig.4], the initial value of the threshold TH1 is such that the increment of the threshold TH1 by the value of the step is made before step 408. In another example not shown, the initial value of the threshold TH1 is determined in such a way that the increment of the threshold TH1 by the value of the step can be made at the end of the cycle, i.e. at step 418.

[0112] Figure 5 illustrates, with timing diagrams, an example of the operation of a converter implementing the process of Figure 4. In particular, Figure 5 illustrates the evolution, as a function of time, of the value of the number ClkNb, the signal Clk, the voltage Vout, the value of the threshold TH1, the current IL and the signal cmp.

[0113] More particularly, [Fig. 5] illustrates the case where the consumption of the load 108 is sufficiently low that, at the end of a typical operating cycle, pulse frequency modulation, the voltage Vout is greater than its setpoint value, and that, for example, the next operating cycle begins after a dead time period starting with the end of the current operating cycle and ending when the voltage Vout becomes less than its setpoint value.

[0114] In [Fig. 5], it is assumed by way of example that each pulse frequency modulation operating cycle begins synchronously with the beginning of a corresponding period of the Clk signal, and ends synchronously with the end of a corresponding period of the Clk signal. However, this synchronization of the beginning and end of each pulse frequency modulation operating cycle with the clock signal Clk is not essential to obtain the advantages provided by the converter and the method described here, and a person skilled in the art will be able, from the description in [Fig. 5], to adapt the example in [Fig. 5] to the case where a pulse frequency modulation operating cycle begins as soon as the voltage Vout falls below its setpoint value (step 400) and / or ends as soon as the number ClkNb becomes equal to the threshold TH1 (step 414).

[0115] In [Fig.5], by way of example, the cmp signal is in a high state when the voltage Vout is considered less than its setpoint value Vref, and in a low state when the voltage Vout is considered greater than its setpoint value.

[0116] In [Fig. 5], the comparison of the voltage Vout to its setpoint value is implemented with hysteresis. The voltage Vout is then considered lower than the value Vref if it is below a lower threshold Vref-, and higher than the voltage Vref if it is above a higher threshold Vref+. Furthermore, when the voltage Vout is between the thresholds Vref+ and Vref-, the fact that the voltage Vout is considered higher, respectively lower, than the value Vref results from the fact that the voltage Vout was higher than the threshold Vref+, respectively lower than the threshold Vref-, before being between the thresholds Vref+ and Vref-. However, those skilled in the art will be able to adapt the description given here of [Fig. 5] to the case where the comparison of the voltage Vout to its setpoint value is made without hysteresis.

[0117] At time t0, the voltage Vout is greater than the voltage Vref (cmp in the low state). Furthermore, there is no pulse frequency modulation operating cycle in progress, and the current IL is therefore zero. For example, time t0 corresponds to the implementation of step 400. Thus, since the voltage Vout is less than its setpoint value Vref, the threshold TH1 is initialized (step 402), in this example to a value of zero. As an example, the number ClkNb is equal to the value TH2 that it had reached at the end of a previous pulse frequency modulation operating cycle.

[0118] At a later instant tl, the voltage Vout becomes less than its setpoint value Vref, that is to say, in the example of [Fig.5], the voltage Vout becomes less than the threshold Vref-. As a result, the cmp signal switches, in this example, to the high state.

[0119] A new operating cycle in pulse frequency modulation then begins, in this example at the start of the period of the signal Clk following the instant tl, that is to say at an instant t2 subsequent to the instant tl. The instant t2 corresponds to the beginning of the duration Te of a cycle.

[0120] Thus, at time t2 of the start of the cycle, the threshold TH1 is increased by the value of the step, in this example equal to 1.

[0121] Furthermore, at the start time t2 of the cycle, the HSS switch is switched to the conducting state, which marks the beginning of the duration TONH of the conducting state of the HSS switch.

[0122] Turning the HSS switch on causes the IL current to increase, as does the Vout voltage. In particular, in this example, the Vout voltage becomes greater than its setpoint Vref, i.e., the threshold Vref+ in the example of [Fig. 5], at a time t3 after time t2, but within the duration TONH in this example. At time t3, the emp signal switches, in this example to the low state.

[0123] Furthermore, from time t2 until time t4 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0124] At time t4 after time t2, and, in this example, at time t3, the number NbClk is incremented and becomes equal to 1 (step 410).

[0125] The number NbClk is then equal to the value of the threshold TH1, and the HSS switch is switched to the blocked state (step 412). Thus, for this operating cycle, the duration TONH extends from time t2 to time t4 and is determined by the value of the threshold TH1.

[0126] As an example, at time t4, the LSS switch is switched to the conducting state.

[0127] After time t4, the current IL decreases, as does the voltage Vout.

[0128] Furthermore, at time t4, the number ClkNb is not equal to the value of the threshold TH2. It follows that at each beginning of the period of the signal Clk following time t4, as long as the number ClkNb has not reached the threshold TH2, this number ClkNb is incremented.

[0129] At a time t5 after time t4, the current IL becomes zero. For example, the LSS switch is then switched to the blocked state. In the example in [Fig. 5], the LSS switch is in the conducting state for a duration TONL from time t4 to time t5.

[0130] At a time t6 after time t4, and, in this example, at time t5, a new period of the signal Clk begins and the number ClkNb is incremented and becomes equal to the threshold TH2. The current operating cycle ends, in this example, at a time t7 corresponding to the end of the period of the signal CLK that began at time t6. The duration Te of the operating cycle therefore extends from time t2 to time t7 and is determined by the value of the threshold TH2.

[0131] At the end of the operating cycle, in this example at time t7, since the voltage Vout is still greater than its setpoint value Vref (emp in the low state), The threshold TH1 is initialized to its initial value, which is 0 in this example. Furthermore, a new operating cycle does not begin immediately, and a dead time period starts at time t7.

[0132] After time t7, the voltage Vout continues to decrease until it falls below its setpoint value Vref at a time t8 later than time t7. A new operating cycle then begins, in this example synchronously with the signal Clk at a time t9 later than time t8. Time t9 marks the end of the dead time period that began at time t7, the end of the preceding operating cycle.

[0133] The operation described in relation to the successive instants t1, t2, t3, t4 and t5 is again implemented at the respective successive instants t8, t9, t10, t11 and t12.

[0134] In particular, in the operating cycle starting at time t9, the duration TONH is the same as that of the preceding operating cycle starting at time t2, and corresponds to the minimum value that the duration TONH can have, this minimum value being determined by the initialization value of the threshold TH1. This results in the fact that, before each of the operating cycles starting at the respective times t2 and t9, since the load consumption is relatively low, the voltage Vout was greater than its setpoint value and the value of the threshold TH1 was therefore reset to its initialization value.

[0135] Predicting a minimum TONH duration when load consumption is relatively low allows limiting the amplitude of voltage oscillations Vout.

[0136] Figure 6 illustrates, with timing diagrams, another example of the operation of a converter implementing the process of Figure 4. In particular, Figure 6 illustrates the evolution, as a function of time, of the value of the number ClkNb, the signal Clk, the voltage Vout, the value of the threshold TH1, the current IL and the signal cmp.

[0137] In particular, [Fig.6] illustrates the case where the consumption of the load 108 is such that, at the end of one of the operating cycles in pulse frequency modulation, the voltage Vout is always less than its setpoint value.

[0138] In [Fig. 6], it is considered, by way of example, that each pulse frequency modulation operating cycle begins synchronously with the start of a corresponding period of the Clk signal, and ends synchronously with the end of a corresponding period of the Clk signal. However, this synchronization of the start and end of each pulse frequency modulation operating cycle with the clock signal Clk is not essential to obtain the advantages provided by the converter and the method described here, and a person skilled in the art will be able, from the description in [Fig. 6], to adapt the example in [Fig. 6] to the case where a pulse frequency modulation operating cycle begins as soon as the voltage Vout falls below its setpoint value (step 400) and / or ends as soon as the number ClkNb becomes equal to the threshold TH1 (step 414).

[0139] In [Fig.6], by way of example, the cmp signal is in a high state when the voltage Vout is considered less than its setpoint value Vref, and in a low state when the voltage Vout is considered greater than its setpoint value.

[0140] In [Fig. 6], the comparison of the voltage Vout to its setpoint value is implemented with hysteresis, as in [Fig. 5]. However, a person skilled in the art will be able to adapt the description given here of [Fig. 6] to the case where the comparison of the voltage Vout to its setpoint value is made without hysteresis.

[0141] At time t0, the voltage Vout is greater than the voltage Vref (cmp in the low state). Furthermore, there is no pulse frequency modulation operating cycle in progress, and the current IL is therefore zero. For example, time t0 corresponds to the implementation of step 400. Thus, since the voltage Vout is less than its setpoint value Vref, the threshold TH1 is initialized (step 402), in this example to a value of zero. As an example, the number ClkNb is equal to the value TH2 that it had reached at the end of a previous pulse frequency modulation operating cycle.

[0142] At a later time t1, the voltage Vout becomes less than its setpoint value Vref, that is to say, in the example of [Fig.6], the voltage Vout becomes less than the threshold Vref-. As a result, the cmp signal switches, in this example, to the high state.

[0143] A new operating cycle in pulse frequency modulation then begins, in this example at the beginning of the period of the signal Clk following the instant tl, that is to say at an instant t2 subsequent to the instant tl. The instant t2 corresponds to the beginning of the duration Te of a cycle.

[0144] Thus, at time t2 of the start of the cycle, the threshold TH1 is increased by the value of the step, in this example equal to 1.

[0145] Furthermore, at the start time t2 of the cycle, the HSS switch is switched to the conducting state, which marks the beginning of the duration TONH of the conducting state of the HSS switch.

[0146] Turning the HSS switch on causes the current IL to increase, as does the voltage Vout.

[0147] Furthermore, from time t2 until time t3 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0148] At time t3 after time t2, the number NbClk is incremented and becomes equal to 1 (step 410).

[0149] The number NbClk is then equal to the value of the threshold TH1, and the HSS switch is switched to the blocked state (step 412). Thus, for this operating cycle, the duration TONH extends from time t2 to time t3 and is determined by the value of the threshold TH1.

[0150] For example, at time t3, the LSS switch is switched to the on state. This marks the beginning of the on state duration of the LSS switch for this operating cycle.

[0151] After time t3, the current IL decreases, as does the voltage Vout.

[0152] Furthermore, at time t3, the number ClkNb is not equal to the value of the threshold TH2. It The result is that at each beginning of the period of the signal Clk following the instant t3, as long as the number ClkNb has not reached the threshold TH2, this number ClkNb is incremented.

[0153] At a time t4 after time t3, the current IL becomes zero. For example, the LSS switch is then switched to the blocked state, which marks the end of the TONL duration for this operating cycle. In the example in [Fig. 5], the LSS switch is therefore in the conducting state for a duration TONL from time t3 to time t4.

[0154] At a time t5 after time t3, and, in this example, at time t4, a new period of the signal Clk begins and the number ClkNb is incremented and becomes equal to the threshold TH2. The current operating cycle ends, in this example, at a time t6 corresponding to the end of the period of the signal Clk that began at time t5. The duration Te of the operating cycle therefore extends from time t2 to time t6 and is determined by the value of the threshold TH2.

[0155] At the end of the operating cycle, in this example at time t6, as the voltage Vout is less than its setpoint value Vref (emp in the high state), the threshold TH1 is not reset to its initial value, and furthermore, a new operating cycle in pulse frequency modulation begins at time t6.

[0156] Thus, at time t6, the number ClkNb is initialized to its initial value, which is zero. Furthermore, the threshold value TH1 is incremented by the step value, namely by 1. In addition, the HSS switch is switched to the conducting state, marking the beginning of a new TONH conduction period for the HSS switch. Switching the HSS switch to the conducting state causes the current IL to increase, as does the voltage Vout.

[0157] Furthermore, from time t6 until time t7 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0158] At time t7 after time t6, the number NbClk is incremented and becomes equal to 1 (step 410).

[0159] However, from time t7 until time t9 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0160] At time t9, the number NbClk is incremented and becomes equal to 2 (step 410). The number NbClk is then equal to the value of the threshold TH1, and the HSS switch is switched to the blocked state (step 412). Thus, for this operating cycle, the duration TONH extends from time t6 to time t8 and is determined by the value of the threshold TH1. Since the value of the threshold TH1 is greater for the cycle starting at time t6 that for the cycle starting at time t2, the duration TONH is greater for the cycle starting at time t6 than for the cycle starting at time t2.

[0161] In the example of [Fig.6], at a time t8 between times t7 and t9, the voltage Vout becomes greater than its setpoint value, i.e. to the threshold Vref+ in this example, and the cmp signal switches, in this example to the low state.

[0162] For example, at time t9, the LSS switch is switched to the conducting state, which marks the beginning of the TONL duration of the current operating cycle.

[0163] After time t9, the current IL decreases, as does the voltage Vout.

[0164] Furthermore, at time t9, the number ClkNb is not equal to the value of the threshold TH2. It The result is that at each beginning of the period of the signal Clk following the instant t9, as long as the number ClkNb has not reached the threshold TH2, this number ClkNb is incremented.

[0165] At a time t10 after time t9, the current IL becomes zero. For example, the LSS switch is then switched to the blocked state. In the example in [Fig. 6], the LSS switch is in the conducting state for a duration TONL from time t9 to time t10.

[0166] At a time tl1 subsequent to time t9, and, in this example, at time tl0, a new period of the signal Clk begins and the number ClkNb is incremented and becomes equal to the threshold TH2. The current operating cycle ends, in this example, at a time tl2 corresponding to the end of the period of the signal Clk that began at time tl1. The duration Te of the operating cycle therefore extends from time t6 to time tl2 and is determined by the value of the threshold TH2.

[0167] At the end of the operating cycle, in this example at time tl2, since the voltage Vout is greater than its setpoint value Vref (cmp in the low state), the threshold TH1 is reset to its initial value. A new operating cycle in pulse frequency modulation will start after the voltage Vout has fallen below its setpoint value again, for example at a time tl3 after time tl2.

[0168] Figure 6 shows that, when the load consumes more current than in the example of Figure 5, the TONH duration is increased at each operating cycle until the voltage Vout again exceeds its setpoint value Vref. In other words, Figure 6 shows that the TONH duration is adjusted at each operating cycle in pulse frequency modulation according to the load consumption and, for example, variations in the voltage Vin.

[0169] Figure 7 illustrates, with chronograms, yet another example of operation of a converter implementing the process of [Fig.4]. In particular, [Fig.7] illustrates the evolution, as a function of time, of the value of the number ClkNb, the signal Clk, the signal cmp, the value of the threshold TH1 and the current IL.

[0170] In particular, [Fig.7] illustrates the case of a load transient where the consumption of the load 108 increases significantly and such that, in the absence of adaptation of the duration TONH, the converter would not be able to ensure the regulation of the voltage Vout to its setpoint value Vref.

[0171] In [Fig. 7], it is considered, by way of example, that each pulse frequency modulation operating cycle begins synchronously with the start of a corresponding period of the Clk signal, and ends synchronously with the end of a corresponding period of the Clk signal. However, this synchronization of the start and end of each pulse frequency modulation operating cycle with the clock signal Clk is not essential to obtain the advantages provided by the converter and the method described here, and a person skilled in the art will be able, from the description in [Fig. 7], to adapt the example in [Fig. 6] to the case where a pulse frequency modulation operating cycle begins as soon as the voltage Vout falls below its setpoint value (step 400) and / or ends as soon as the number ClkNb becomes equal to the threshold TH1 (step 414).

[0172] In [Fig.7], by way of example, the cmp signal is in a high state when the voltage Vout is considered less than its setpoint value Vref, and in a low state when the voltage Vout is considered greater than its setpoint value.

[0173] In [Fig.7], although not illustrated, the comparison of the voltage Vout to its setpoint value is, by way of example, implemented with hysteresis, as in Figures 5 and 6. However, the person skilled in the art should implement the case where the comparison of the voltage Vout to its setpoint value is made without hysteresis.

[0174] At time t0, the voltage Vout is greater than the voltage Vref (cmp in the low state). Furthermore, there is no pulse frequency modulation operating cycle in progress, and the current IL is therefore zero. For example, time t0 corresponds to the implementation of step 400. Thus, since the voltage Vout is less than its setpoint value Vref, the threshold TH1 is initialized (step 402), in this example to a value of zero. As an example, the number ClkNb is equal to the value TH2 that it had reached at the end of a previous pulse frequency modulation operating cycle.

[0175] At a later time tl, the voltage Vout becomes less than its setpoint value Vref and the cmp signal switches, in this example, to the high state.

[0176] A new operating cycle in pulse frequency modulation then begins, in this example at the beginning of the period of the signal Clk following the instant tl, that is to say at an instant t2 subsequent to the instant tl. The instant t2 corresponds to the beginning of the duration Te of a cycle.

[0177] Thus, at time t2 of the start of the cycle, the threshold TH1 is increased by the value of the step, in this example equal to 1.

[0178] Furthermore, at the start time t2 of the cycle, the HSS switch is switched to the on state, which marks the beginning of the TONH duration of the on state of the HSS switch.

[0179] Turning the HSS switch on causes the current IL to increase, as does the voltage Vout.

[0180] Furthermore, from time t2 until time t3 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0181] At time t3 after time t2, the number NbClk is incremented and becomes equal to 1 (step 410).

[0182] The number NbClk is then equal to the value of the threshold TH1, and the HSS switch is switched to the blocked state (step 412). Thus, for this operating cycle, the duration TONH extends from time t2 to time t3 and is determined by the value of the threshold TH1.

[0183] For example, at time t3, the LSS switch is switched to the conducting state, which marks the beginning of the TONL period for the current operating cycle.

[0184] After time t3, the current IL decreases, as does the voltage Vout.

[0185] Furthermore, at time t3, the number ClkNb is not equal to the value of the threshold TH2. It The result is that at each beginning of the period of the signal Clk following the instant t3, as long as the number ClkNb has not reached the threshold TH2, this number ClkNb is incremented.

[0186] At a time t4 after time t3, the current IL becomes zero. For example, the LSS switch is then switched to the blocked state. In the example in [Fig. 5], the LSS switch is in the conducting state for a duration TONL from time t3 to time t4.

[0187] At a time t5 after time t3, and, in this example, at time t4, a new period of the signal Clk begins and the number ClkNb is incremented and becomes equal to the threshold TH2. The current operating cycle ends, in this example, at a time t6 corresponding to the end of the period of the signal Clk that began at time t5. The duration Te of the operating cycle therefore extends from time t2 to time t6 and is determined by the value of the threshold TH2.

[0188] At the end of the operating cycle, in this example at time t6, as the voltage Vout is less than its setpoint value Vref (emp in the high state), the threshold TH1 is not reset to its initial value, and furthermore, a new operating cycle in pulse frequency modulation begins at time t6.

[0189] Thus, at time t6, the number ClkNb is initialized to its initial value, which is zero. Furthermore, the threshold value TH1 is incremented by the step value, namely by 1. In addition, the HSS switch is switched to the conducting state, marking the beginning of a new TONH conduction period for the HSS switch. Switching the HSS switch to the conducting state causes the current IL to increase, as does the voltage Vout.

[0190] Furthermore, from time t6 until time t7 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0191] At time t7 after time t6, the number NbClk is incremented and becomes equal to 1 (step 410).

[0192] However, from time t7 until time t8 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0193] At time t8, the number NbClk is incremented and becomes equal to 2 (step 410). The number NbClk is then equal to the value of the threshold TH1, and the HSS switch is switched to the blocked state (step 412). Thus, for this operating cycle, the duration TONH extends from time t6 to time t8 and is determined by the value of the threshold TH1. Since the value of the threshold TH1 is greater for the cycle starting at time t6 than for the cycle starting at time t2, the duration TONH is greater for the cycle starting at time t6 than for the cycle starting at time t2.

[0194] For example, at time t8, the LSS switch is switched to the on state, which marks the beginning of the TONL duration for the current operating cycle.

[0195] After time t8, the current IL decreases, as does the voltage Vout.

[0196] Furthermore, at time t8, the number ClkNb is not equal to the value of the threshold TH2. It The result is that, at each beginning of the period of the signal Clk following the instant t8, as long as the number ClkNb has not reached the threshold TH2, this number ClkNb is incremented.

[0197] At a time t9 after time t8, a new period of the signal Clk begins and the number ClkNb is incremented and becomes equal to the threshold TH2. The current operating cycle ends, in this example, at a time tl0 corresponding to the end of the period of the signal Clk that began at time t9. The duration Te of the operating cycle therefore extends from time t6 to time tl0 and is determined by the value of the threshold TH2.

[0198] Furthermore, at time t10, the current IL is not zero. For example, because the current IL did not become zero between time t8 and time t10, the switch LSS remained conducting, and this switch LSS is switched to the blocked state at the end of the cycle, that is, at time t10. The duration TONL for this current operating cycle therefore extends from time t8 to time t10, corresponding to the end of the current operating cycle.

[0199] At the end of the operating cycle, in this example at time tlO, as the voltage Vout is less than its setpoint value Vref (emp in the low state), the threshold TH1 is not reset to its initial value, and, in addition, a new operating cycle in pulse frequency modulation begins at time tlO.

[0200] Thus, at time t10, the number ClkNb is initialized to its initial value, which is zero. Furthermore, the threshold value TH1 is incremented by the step value, which is 1. In addition, the HSS switch is switched to the conducting state, marking the beginning of a new TONH conduction period for the HSS switch. Switching the HSS switch to the conducting state causes the current IL to increase, as does the voltage Vout.

[0201] Furthermore, from time tl0 until time tl1 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0202] At time tl 1 after time tlO, the number NbClk is incremented and becomes equal to 1 (step 410).

[0203] However, from time tl 1 until time tl2 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0204] At time tl2 after time tl1, the number NbClk is incremented and becomes equal to 2 (step 410).

[0205] However, from time tl2 until time tl3 corresponding to the beginning of the next period of the signal Clk, the number ClkNb is not equal to the threshold TH1, and the HSS switch is kept conducting.

[0206] At time tl3, the number NbClk is incremented and becomes equal to 3 (step 410). The number NbClk is then equal to the value of the threshold TH1, and the HSS switch is switched to the blocked state (step 412). Thus, for this operating cycle, the duration TONH extends from time tl0 to time tl3 and is determined by the value of the threshold TH1. Since the value of the threshold TH1 is greater for the cycle starting at time tl0 than for the cycles starting at times t2 and t6, respectively, the duration TONH is greater for the cycle starting at time tl0 than for the cycles starting at times t2 and t6, respectively.

[0207] For example, at time tl3, the LSS switch is switched to the on state, which marks the beginning of the TONL duration for the current operating cycle.

[0208] Compared to the examples described in relation to Figures 5 and 6, where, in each operating cycle, the current IL reaches zero before the end of the cycle, in the example of [Fig. 7], the current IL does not reach zero during the cycle beginning at time t6. Consequently, during the following cycle beginning at time t9, the current IL increases from a non-zero value. In other words, the converter and the control method proposed here allow operation in continuous conduction mode (CCM), which is not possible in known converters where the start of a new operating cycle in pulse frequency modulation is conditional on a zero current value. IL, these known converters can then only operate in discontinuous conduction mode (DCM). The operation described in relation to [Fig. 7] allows the converter to absorb load transients, that is, it allows the converter to continue regulating the output voltage Vout to its setpoint value Vref even when the load consumption increases abruptly, for example, when the load switches from standby to active mode.

[0209] In the embodiments described above, the converter operates in pulse frequency modulation. The converter then includes, to implement the described operation, for example, a PFMCTRL1 control circuit for the HSS switch, and, when the converter includes it, for the LSS switch.

[0210] In alternative embodiments, the converter is configured to operate selectively in pulse frequency modulation as described above and in pulse width modulation (PWM). In other words, the converter is configured to alternate between phases where the converter operates in pulse frequency modulation as described above, and phases where the converter operates in pulse width modulation.

[0211] By way of example, in this case, to simplify the transitions between pulse frequency modulation (PFM) and pulse width modulation (PWM) operation, the threshold TH2 can be chosen such that the duration Te of each PFM operating cycle is equal to the duration of one period of a PWM signal, this PWM signal being, for example, a control signal for the HSS switch. For example, in this case, the beginnings of the PFM operating cycles are synchronized with the beginnings of the periods of a PWM clock signal. For example, the Clk signal used in PFM is obtained from the PWM clock signal, for example, by frequency division of the PWM clock signal.

[0212] Fig. 8 represents schematically and in block form another example of an embodiment of a CTRL2 control circuit of a converter of the type of that of Fig. 1.

[0213] In this example, the CTRL2 circuit is configured to implement the operation described above when the converter operates in pulse frequency modulation, and, furthermore, to selectively operate in pulse frequency modulation and pulse width modulation. In [Fig. 7], only the CTRL2 circuit is shown; this CTRL2 circuit can be used as a replacement for the PFMCTRL1 circuit in the converter 1 described previously.

[0214] Similar to the PFMCTRL1 circuit, the CTRL2 circuit includes an 814 input configured to receive the voltage Vout (or a voltage image of the voltage Vout, for example obtained with a resistive voltage divider from the voltage Vout), and an 804 input configured to receive a voltage Vref indicating the setpoint value of the voltage Vout.

[0215] Also similar to the PFMCTRL1 circuit, the CTRL2 circuit includes an 812 output configured to provide the sigH control signal for the HSS high side switch.

[0216] Furthermore, in this example where the converter under consideration includes a low-side switch (LSS), the CTRL2 circuit includes an output 816 configured to provide the sigL control signal for the LSS switch. As an example, the CTRL2 circuit includes an input 818 configured to receive the sigZ signal indicating when the current IL in the inductor L reaches zero.

[0217] When the converter operates in pulse frequency modulation, the CTRL2 circuit provides sigH and sigL signals identical to those provided by the PFMCTRL2 circuit. When the converter operates in pulse width modulation, the CTRL2 circuit provides a pulse-width modulated sigH signal, and the sigL signal is, for example, complementary to the sigH signal.

[0218] For example, the CTRL2 circuit includes the PFMCTRL1 circuit and a PWMCTRL circuit. The PFMCTRL1 circuit is configured to provide the sigH and sigL signals when operating in pulse frequency modulation, and the PWMCTRL circuit is configured to provide the sigH and sigL signals when operating in pulse width modulation.

[0219] For example, input 304 of the PFMCTRL2 circuit is coupled, for example connected, to input 804, input 814 being coupled, for example connected, to input 814 and input 318 being coupled, for example connected, to input 818.

[0220] For example, output 312 of the PFMCTRL2 circuit is coupled to output 812, for example by a MUX1 selection circuit, output 316 being coupled to output 816, for example by another MUX2 selection circuit. In the example in [Fig. 8], the signal provided by output 312, respectively 316, is referenced sigHF, respectively sigLF.

[0221] By way of example, the CTRL2 circuit includes a LO oscillator configured to supply the Clk signal to input 300 of the PFMCTRL2 circuit. By way of alternative example, the CTRL2 circuit includes an input configured to receive the Clk signal, this input being coupled, for example connected, to input 300 of the PFMCTRL2 circuit.

[0222] By way of example, the PWMCTRL circuit includes an input 900 configured to receive the voltage Vout (or a voltage image of the voltage Vout, for example obtained with a resistive voltage divider from the voltage Vout), and a Input 904 is configured to receive the Vref voltage, indicating the setpoint value of the Vout voltage. For example, inputs 900 and 902 are coupled, for example connected, to the respective inputs 814 and 804.

[0223] By way of example, the PWMCTRL circuit includes an output 912 configured to provide a sigHW signal corresponding to the sigH signal when the converter is operating in pulse width modulation.

[0224] Furthermore, in this example where the converter under consideration includes a low-side switch LSS, the PWMCTRL circuit includes an output 916 configured to provide a sigLW signal corresponding to the sigL control signal of the LSS switch when the converter is operating in pulse-width modulation.

[0225] For example, output 912 of the PWMCTRL circuit is coupled to output 812, for example by the MUX1 selection circuit, output 916 being coupled to output 814, for example, by the other MUX2 selection circuit. In the example of [Fig.8], the signal provided by output 312, respectively 316, is referenced sigHF, respectively sigLF.

[0226] By way of example, the PWMCTRL circuit includes an input 904 configured to receive a periodic signal Clkl at the frequency of the pulse-width modulated sigHW signal. By way of example, the pulse-width modulated clock signal Clkl is obtained from the signal Clk by dividing the frequency of the signal Clk, for example with a frequency divider circuit DIV.

[0227] By way of example, the CTRL2 circuit includes a CTRL circuit configured to provide a mode signal for selecting the operating mode in pulse-frequency modulation or the operating mode in pulse-width modulation. For example, the mode signal controls the MUX1 and MUX2 circuits so that the sigH and sigL signals receive the respective sigHW and sigLW signals in pulse-width modulation, and the respective sigHF and sigLF signals in pulse-frequency modulation.

[0228] For example, the CTRL circuit includes an input configured to receive the voltage Vout, and switching from one operating mode to another is done at least partly on the basis of the current value of the voltage Vout.

[0229] As an alternative example, the CTRL circuit is omitted, and the CTRL2 circuit includes an input configured to receive the mode signal.

[0230] A person skilled in the art will be able to provide further CTRL2 circuits configured to selectively operate in pulse frequency modulation and pulse width modulation, wherein the pulse frequency modulation operation is implemented in the manner previously described in relation to Figures 3 to 7.

[0231] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0232] In particular, although embodiments and variants have been described in which the converter considered by way of example includes a low-side LSS switch, the operation described above, and, in particular, the control of the high-side HSS switch in pulse-frequency modulation operation, can be implemented in a converter comprising a diode in place of the LSS switch. In this case, output 316 of the PFMCTRL2 circuit and output 816 of the CTRL2 circuit can be omitted.

[0233] By way of example, a converter implementing the pulse frequency modulation operation described above can be used in the automotive industry. For example, this converter can be used in vehicles, for example electric vehicles, to generate a relatively low supply voltage for electronic circuits from a relatively high supply voltage, for example supplied by a vehicle battery.

[0234] By way of another example, a converter implementing the pulse frequency modulation operation described above can be used in industry, for example in the energy industry, for example green energy. For example, such a converter can be used to convert a relatively high DC voltage, for example obtained from a solar panel or a wind turbine, into a relatively low DC voltage, for example to power electronic circuits.

[0235] By way of another example, a converter implementing the pulse frequency modulation operation described above can be used in the field of the Internet of Things (IoT). For example, such a converter can be used to convert a relatively high DC voltage, for example supplied by a battery of an IoT device, into a relatively low DC voltage, for example to power electronic circuits of the IoT device.

[0236] By way of another example, a converter implementing the pulse frequency modulation operation described above can be used in the field of personal wireless devices, for example in mobile phones, for example to convert a relatively high DC voltage, for example supplied by a battery of the device, into a relatively low DC voltage, for example to power electronic circuits of the device.

[0237] In the embodiments and variants described above, at each pulse frequency modulation operating cycle, the COUNTER is initialized at the beginning of the cycle and then incremented at each period of the Clk signal. The threshold TH2 is then greater than the threshold TH1, so that when the number ClkNb reaches the threshold TH2, this corresponds to a greater number of periods of the Clk signal than when the number ClkNb reaches the threshold TH1. Furthermore, in this case, the step value is positive, so that incrementing the threshold TH1 by the step value is equivalent to increasing the TONH duration. However, those skilled in the art will be able to adapt the described examples where the number ClkNb is increasing to examples where, at each pulse frequency modulation operating cycle, the COUNTER is initialized at the beginning of the cycle and decrements the number ClkNb at each period of the Clk signal.In such examples, the TH2 threshold is then lower than the TH1 threshold so that, when the number ClkNb reaches the TH2 threshold, this corresponds to a greater number of periods of the signal Clk than when the number ClkNb reaches the TH1 threshold. Furthermore, in this case, the step value is negative so that incrementing the TH1 threshold by the step value is equivalent to decreasing the value of the TH1 threshold, and therefore increasing the TONH duration.

[0238] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Buck switching converter (1) configured, at each operating cycle in pulse frequency modulation (Te), to: at the beginning of the operating cycle, initialize (404) a counted number (ClkNb) of periods of a clock signal (Clk) and switch (404) a high-side switch (HSS) to the on state (TONH); increment (406) a first threshold (TH1) by one step; update (410, 416) the counted number (ClkNb) of periods of the clock signal (Clk) at each period of the clock signal; switch (412) the high-side switch (HSS) to the off state when the counted number (ClkNb) is equal to the first threshold (TH1); terminate (418) the operating cycle (Te) when the counted number (ClkNb) is equal to a second threshold (TH2);and at the end of the operating cycle (Te), compare (400) an output voltage (Vout) of the converter to a target value (Vref), initialize (402) the first threshold (TH1) to an initialization value if the output voltage is greater than the setpoint value and start a subsequent operating cycle if the output voltage is less than the setpoint value.;

2. Method for controlling a buck-switching converter (1), the method comprising, at each operating cycle (Te) where the converter is controlled by pulse frequency modulation: at the beginning of the operating cycle, initialize (404) a counted number (ClkNb) of periods of a clock signal (Clk) and switch (404) a high-side switch (HSS) to the on state; increment (406) a first threshold (TH1) by one step; update (410, 416) the counted number (ClkNb) of periods of the clock signal (Clk) at each period of the clock signal; switch (412) the high-side switch (HSS) to the off state when the counted number (ClkNb) is equal to the first threshold (TH1); terminate (418) the operating cycle when the counted number (ClkNb) is equal to a second threshold (TH2);and at the end of the operating cycle (Te), compare (400) an output voltage (Vout) of the converter to a target value (vref), initialize (402) the first threshold (TH1) to an initialization value if the output voltage is greater than the setpoint voltage and start a cycle; operation depending on whether the output voltage is lower than the setpoint voltage.

3. Converter according to claim 1 or method according to claim 2, wherein, at each pulse frequency modulation (Te) operating cycle, a low side switch (LSS) is switched to the on state when the high side switch (HSS) is switched to the blocked state.

4. Converter or method according to claim 2, wherein, at each operating cycle in pulse frequency modulation (Te), the low-side switch is switched to the blocked state at the end of the operating cycle (Te) or when an output current (IL) of the converter reaches a zero value (sigZ) before the end of the operating cycle.

5. Converter according to any one of claims 1, 3 and 4, or method according to any one of claims 2 to 4, wherein the converter is configured to operate selectively in pulse frequency modulation or pulse width modulation.

6. Converter or method according to claim 5, wherein the second threshold (TH2) is configured so that a duration of each operating cycle (Te) is equal to a period of a pulse-width modulated signal (sigHW).

7. Converter according to any one of claims 1 and 3 to 6, or method according to any one of claims 2 to 6, wherein the second threshold (TH2) has a constant value.

8. Converter according to any one of claims 1 and 3 to 7, or method according to any one of claims 2 to 7, wherein the comparison of the output voltage (Vout) to the setpoint value (Vref) is implemented with hysteresis.

9. Converter according to any one of claims 1 and 3 to 8, or method according to any one of claims 2 to 8, wherein the high side switch (HSS) couples an internal node (110) of the converter to a supply voltage (Vin) of the converter.

10. Converter or method according to claim 9, wherein an inductance (L) couples the internal node (110) to an output (102) of the converter.

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