Addressing method in a multiplexed network comprising a master node and a plurality of configurable slave nodes with a bus shunt method.

Abstract

An addressing method in a multiplexed network comprising a master node and a plurality of slave nodes, where at least some of the addresses of the slave nodes are configured using a bus shunt method, said addressing method comprises the steps performed by the master node of: sending (201) an address configuration instruction to a slave node configurable by the bus shunt method; receiving (203) a signal acknowledging the configuration by the slave node; in case of failure to receive the signal, iterating the two preceding steps until the acknowledgment signal is received. A program product, a network, a system, and a motor vehicle comprising the system are also described. Figure to be published with the abbreviation: Fig 2

Description

Title of the invention: Addressing method in a multiplexed network comprising a master node and a plurality of configurable slave nodes with a bus shunt method. technical field

[0001] The present invention relates to an addressing method in a multiplexed network comprising a master node and a plurality of configurable slave nodes with a bus shunt method, a computer program product, a communication network, a system and a motor vehicle comprising such a system. State of the art

[0002] A multiplexed communication network of the LIN type (Local Interconnect Network) (LIN is a registered trademark) is a low-complexity, low-cost communication network intended for use in automotive applications. The LIN protocol was standardized under ISO 17987 between 2016 and 2019.

[0003] Such a network essentially comprises a master node and slave nodes. The master node controls the flow of data on the network, and the slave nodes respond to requests from the master node.

[0004] When a slave is added to the LIN network, it must receive a unique identifier as an address in order to communicate with other nodes on the network. The LIN network uses a mechanism commonly referred to as "slave auto-addressing" to allow slaves to obtain an address automatically based on their physical position on the network, thus simplifying network installation and configuration.

[0005] In particular, the LIN network uses a configuration algorithm called "Bus Shunt Method" (BSM) for this self-addressing. The BSM algorithm is described in detail in the document "LIN Bus Shunt Slave Node Position Detection", revision 1.0, December 10, 2008.

[0006] However, the described method does not provide for securing or managing faults during address assignment, which is not suitable for an automotive application.

[0007] One solution to secure the described process would be to supply different references of slave nodes having predefined addresses, which impairs flexibility, requires additional storage space in the factory during production, as well as in after-sales for the maintenance of motor vehicles.

[0008] There is therefore a real need for an addressing configuration process and system which resolves all or part of the aforementioned drawbacks. Description of the invention

[0009] To overcome one or more of the aforementioned drawbacks, according to a first embodiment, an addressing method in a multiplexed network comprising a master node and a plurality of slave nodes, and in which at least a portion of the addresses of the slave nodes is configured using a bus shunt method, said addressing method comprises the steps performed by the master node of: • sending an address configuration instruction to a configurable slave node using the bus shunt method; • reception of a signal acknowledging the configuration by the slave node; • if signal reception fails, iterate the two previous steps until the acknowledgment signal is received.

[0010] Thus, the master node controls the state of the slave nodes and can detect those that are faulty, without an address or with an incorrect address.

[0011] Specific features or embodiments, usable alone or in combination, are: • in case of failure, the iteration is executed up to a maximum number of iterations; • when the maximum number of iterations is reached without receiving the acknowledgement signal, the process further includes a step of memorizing an error message by the master node; • The master node waits for the acknowledgment signal for a predetermined maximum duration; and / or • The steps are repeated successively for each slave node that has an address to configure.

[0012] In a second embodiment, a computer program product includes program code instructions for implementing the above process when the program product is executed on a computer.

[0013] In a third embodiment, a multiplexed communication network comprises a master node and slave nodes, and at least part of the addresses of the slave nodes are configured using a bus shunt method, the master node being able to communicate with each of the slave nodes so as to execute the above method.

[0014] In a fourth embodiment, a system includes a communication network according to the third embodiment.

[0015] In a fifth embodiment, a motor vehicle includes a system according to the fourth embodiment. Brief description of the figures

[0016] The invention will be better understood upon reading the following description, given solely by way of example, and with reference to the figures in the appendix in which: • [Fig. 1] represents a view of a multiplexed network comprising a master node and slave nodes according to one embodiment; • [Fig. 2] represents a flowchart of an addressing method for certain slave nodes of the network of [Fig. 1] according to one embodiment; and • [Fig. 3] represents a state diagram of a detailed embodiment of the addressing method of [Fig.2]. Methods of implementation

[0017] The embodiments presented below refer to a motor vehicle, a car. However, those skilled in the art understand that they are also applicable to other types of vehicles such as vans, trucks, etc.

[0018] With reference to [Fig.1], a LIN type network 101 comprises a master node, 103 and seven slave nodes, 105, 107, 109, 111, 113, 115, 117.

[0019] Among these slave nodes, nodes 105, 109, 115, 117 have a non-configurable address and nodes 107, 111, 113 have a configurable address.

[0020] The configuration of the addresses of these last three nodes uses the bus shunting method referred to below as BSM.

[0021] In [Fig.1], each node is illustrated by the electronic circuit enabling or not the address configuration in BSM.

[0022] The address configuration process described below will detail the dialogue between the master node 103 and the configurable address slave node 107. It is understood that once the process is completed for this node, the steps are repeated for the other slave nodes 111, 113, and more generally for all configurable address slave nodes of the network.

[0023] With reference to [Fig.2], the configuration process includes the following steps implemented by the master node 103.

[0024] At step 201, the master node sends an address configuration instruction to the slave node 107, which can be configured by the bus shunt method.

[0025] At step 203, it waits for the reception of a signal acknowledging the configuration by the slave node 107.

[0026] If it does not receive the acknowledgement signal, it iterates step 201 and step 203.

[0027] If it receives the acknowledgement signal, this means that the slave node 107 has a properly configured address and the process ends with a recording of this address, step 205.

[0028] To prevent the master node 103 from remaining stuck at step 203 if the acknowledgment signal is not received, it is advantageous to start a timer setting a predetermined maximum waiting time. At the end of this time, the master node considers step 203 to have failed.

[0029] Furthermore, it is also advantageous to specify a maximum number of iterations. When the maximum number of iterations is reached, step 207, the process stops and the master node considers that the slave node 107 is in error and it stores an associated error code, step 209.

[0030] In more detail and using the acronyms used in the LIN documentation referenced above, [Fig.3] represents a state diagram of the process described above.

[0031] Before describing the transitions, the states of the diagram are: • Start of function ST_FONC, 301; • BSM initialization BSM_INITIALIZATION 303; • Address of next node NEXT_NAD 305; • Store node address STORE_NAD 307; • Address verification request NAD_CHECK_REQ 309; • NAD_CHECK_RESP address verification response 311; • End of BSM addressing request BSM_FINISHED 313; • End of process BSM_END 315.

[0032] States 303 to 315 are included in the process ST_ASSIGN_NAD 317.

[0033] The transitions between states are then as follows: • Transition 321 is triggered by the launch of the routine. The master node sends a BSM mode frame in a DIAG_REQUEST frame. The ATTEMPT_INDEX counter is initialized to 1. The SLAVE_INDEX counter is initialized to 1. The BSM status is equal to "learning in progress". • Transition 323 is triggered by the BSM mode frame transmission notification. The master node sends the NEXT_NAD request frame to associate the slave node (SLAVE_INDEX) in the DIAG_REQUEST frame. The new NAD field contained in the frame must take the NAD value defined for this SLAVE_INDEX. • Transition 325 is triggered by the NEXT_NAD frame transmission notification. The master node sends the STORE_NAD request in the DIAG_REQUEST frame in order to store the NAD in a non-volatile NVM memory. Transition 327 is triggered by the notification of the transmission of the STORE_NAD frame. The master node sends a session management request in a DIAG-REQUEST frame with NAD equal to SLAVE_INDEX. Transition 329 is triggered by the notification of the transmission of the NAD_CHECK_REQ frame. The master node sends a 0x3D header in order to obtain a response from the last designated slave, SLAVE_INDEX. Transition 331 is triggered by notification of the reception of the NAD_CHECK_RESP frame, and the SLAVE_INDEX counter is strictly less than the number of slaves NB_SLAVE. The SLAVE_INDEX counter is incremented by 1. The master node sends the NEXT_NAD query frame in a DIAG_REQUEST frame to associate the SLAVE_INDEX slave. The new NAD field contained in this frame takes the NAD value defined for this SLAVE_INDEX. Transition 333 is triggered by the SLAVE_INDEX counter being greater than or equal to NB_SLAVE and the notification of receipt of the NAD_CHECK_RESP frame. The master node sends the "BSM Finished" request in a DIAG_REQUEST frame. If the PROG_ERROR flag is set, the default is enabled. The same is true if the "TRANSMISSION_ERROR" flag is set. The BSM_ERROR flag is set to NO_ERROR. Transition 335 is triggered by notification of the transmission of the "BSM Finished" frame or the presence of the TIMEOUT_10 field in BSM_END. The master node switches to the LIN functional programming array (activated in a previous step according to diversity management). The BSM status is initially "learning finished OK," and then, after the BSM_TMP delay, the BSM status changes to "learning not launched." Transition 337 is triggered by the TIMEOUT_10 delay and is in the BSM_INITIALIZATION state. The master node sends the "BSM Finished" request in a DIAG_REQUEST frame. The NB_SLAVE_ERROR index is equal to SLAVE_INDEX and the FINISH_INDEX counter is set to 1. Transition 339 is triggered by the TIMEOUT_10 delay in the NEXT_NAD state. The master node sends the "BSM Finished" request in a DIAG_REQUEST frame. The NB_SLAVE_ERROR counter is equal to SLAVE_INDEX and the FINISH_INDEX counter is set to 1. Transition 341 is triggered by the TIMEOUT_10 delay in the STORE_NAD state. The master node sends a "BSM Finished" request in a DIAG_REQUEST frame. The NB_SLAVE_ERROR counter is equal to SLAVE_INDEX and the FINISH_INDEX counter is set to 1. Transition 343 is triggered by the TIMEOUT_10 delay in the NAD_CHECK_REQ state. The master node sends a "BSM Finished" request in a DIAG_REQUEST frame. The NB_SLAVE_ERROR counter is equal to SLAVE_INDEX and the FINISH_INDEX counter is set to 1. Transition 345 is triggered by the TIME_OUT_NO_ANSWER event in the NAD_CHECK_RESP state. The master node sends a "BSM Finished" request in a DIAG_REQUEST frame. The NB_SLAVE_ERROR counter is set to SLAVEJNDEX and the FINISH_INDEX counter is set to 1. Transition 347 is triggered by the ATTEMP_INDEX counter being strictly less than NB_ATTEMPT and the notification of the transmission of the "BSM_Finished" frame. The SLAVE_INDEX counter is initialized to 1. The ATTEMPT_INDEX counter is incremented by 1. The master node sends a "BSM initialization" request in a DIAG_REQUEST frame. Transition 349 is triggered by TIMEOUT_10 in the BSM_FINISHED state and the FINISH_INDEX counter is strictly less than NB_FINISH. The FINISH_INDEX counter is incremented by 1. The master node sends the BSM initialization request in a DIAG_REQUEST frame. Transition 351 is triggered by TIMEOUT_10 in the BSM_FINISHED state and the FINISH_INDEX counter is greater than or equal to NB_FINISH. If PROG_ERROR is active, the fault is recovered. The "TRANSMISSION-ERROR" fault is active. BSM_ERROR is equal to TRANSMISSION_ERROR. The master node switches to the LIN functional programming board. The BSM status is equal to "learning finished NOK" ("learning finished but failed"), then, after the BSM_TMP timeout, the BSM status becomes "learning not launched" ("learning not started"). Transition 353 is triggered by the ATTEMP_INDEX counter being greater than or equal to NB_ATTEMPT and the notification of frame transmission "BSM_Finished". PROG_ERROR is active. BSM_ERROR is equal to PROG_ERROR. If the "TRANSMISSION_ERROR" fault is active, the fault must be recovered by default. The master node switches to the LIN functional programming table. The BSM status is equal to "learning". finished NOK” (“learning finished by default”), then, after the BSM_TMP delay, the BSM status becomes “learning not launched”.

[0034] Figure 1 illustrates a system according to certain embodiments. The breakdown presented is for pedagogical purposes to highlight the different functions. However, it is understood that each block can be implemented using different means or combinations thereof, such as hardware components, software, one or more computers, and / or electronic circuits. Each component may include at least one computer or a control unit. At least one memory may be included in each component. The memory may include computer program instructions or software code.

[0035] The computers can be implemented by any type of data processing device, such as a central processing unit, a signal processing unit, a specific application integrated circuit, a programmable gate network, etc. The computers can be implemented in the form of a single controller, or a plurality of controllers or computers.

[0036] The different modules are connected to each other by data links adapted to the environment. These can be wired or wireless.

[0037] For the software, the implementation may comprise modules or units distributed in the form of procedures, functions, etc. The memories may be any type of storage circuit. They may be part of the processor circuit, or separate from it and connected via electrical data links. These may be non-volatile memories, hard drives, RAM, flash memory, etc.

[0038] The software product can be downloaded from a communication network and / or stored on a computer-readable medium. It can be directly executable by a processor or be in the form of a high-level language requiring one or more intermediate operations to be executable.

[0039] Thus the program instructions stored in memory and processed by the computers can be any type of program code, for example, a compiled or interpreted program written in a suitable programming language.

[0040] The computer program instructions stored in memory are such that, when executed by the computer, the latter carries out one or more of the steps of the processes described above.

[0041] The invention has been illustrated and described in detail in the drawings and the preceding description. This description is to be considered illustrative and given by way of example and not as limiting the invention to this single description. Numerous embodiments are possible.

Claims

Demands

1. An addressing method in a multiplexed network comprising a master node and a plurality of slave nodes, and in which at least a portion of the addresses of the slave nodes is configured using a bus shunt method, said addressing method comprising the steps performed by the master node of: • sending (201) an address configuration instruction to a slave node configurable by the bus shunt method; • receiving (203) a signal acknowledging the configuration by the slave node; • in case of failure to receive the signal, iterating the two preceding steps until the acknowledgment signal is received.

2. A method according to claim 1, wherein, in case of failure, the iteration is executed up to a maximum number of iterations.

3. A method according to claim 2, wherein when the maximum number of iterations is reached without receiving the acknowledgement signal, the method further comprises a step of memorizing an error message by the master node.

4. A method according to claim 1, 2 or 3, wherein the master node waits for the receipt of the acknowledgement signal for a predetermined maximum duration.

5. A method according to claim 1, 2, 3 or 4, wherein the steps are repeated successively for each slave node having an address to be configured.

6. Computer program product characterized in that it includes program code instructions for implementing the method according to any one of claims 1 to 5 when the program product is executed on a computer.

7. Multiplexed communication network (101) comprising a master node (103) and slave nodes (105, 107, 109, 111, 113, 115, 117) and of which at least a part of the addresses of the slave nodes (107, 111, 113) is configured using a bus shunt method, the master node being able to communicate with each of the slave nodes so as to carry out the method of any one of claims 1 to 5.

8. 9 System comprising a communication network according to claim 7.

9. Motor vehicle comprising a system according to claim 8.

Images