Detection of structural defects in an integrated circuit, for example cracks and / or delaminations

Abstract

The integrated circuit is equipped with an annular wall (MR) comprising, in a first part (Z1), an alternation of elementary modules (MD1, MD2) containing metallic tracks distributed over several metal layers and having an alternately inverted trapezoidal longitudinal cross-section. All these tracks together form at least one electrically conductive path having at least one stepped portion in a second part of the wall. Fault detection means are located in the integrated circuit and connected to semiconductor areas embedded in the substrate beneath the second part of the wall and connected to both ends of said at least one electrically conductive path. Figure for the abbreviation: Fig 5

Description

Title of the invention: Detection of structural defects in an integrated circuit, for example cracks and / or delaminations

[0001] Embodiments and implementation methods relate to integrated circuits, in particular the detection of structural defects in these integrated circuits, for example cracks and / or delaminations.

[0002] Integrated circuits are manufactured simultaneously on locations of a silicon wafer separated by cutting lines.

[0003] Then, once manufactured, the integrated circuits are individualized by cutting, typically by sawing, the wafer along the cutting lines.

[0004] An integrated circuit classically comprises -a part known to those skilled in the art by the Anglo-Saxon acronym "FEOL" ("Front End Of Line" or more simply "front end") comprising the various components, such as transistors, fabricated in and on the semiconductor substrate of the integrated circuit, and -a part known to the person skilled in the art under the Anglo-Saxon acronym "BEOL" ("Back End Of Line" or more simply "back end") comprising a network of metallic tracks and vias embedded in a dielectric material and notably providing an interconnection between the components of the integrated circuit.

[0005] An integrated circuit also generally includes a sealing ring located on the periphery of the integrated circuit.

[0006] A sealing ring conventionally comprises metal tracks interconnected by vias, all embedded in a dielectric material. Furthermore, a passivation layer is located on top of the sealing ring and, in combination with the sealing ring, provides protection against moisture penetration into the integrated circuit, which would impact the reliability of the integrated circuit.

[0007] During the sawing operation of the wafer mentioned above, cracks and / or a delamination phenomenon (i.e. a decohesion of layers) may occur in the BEOL part in particular at the periphery of the integrated circuit.

[0008] These structural defects can in particular affect the sealing ring, which is detrimental.

[0009] Structures already exist that allow the detection of structural defects. However, such structures do not allow the detection of certain crack configurations and / or certain delamination locations.

[0010] There is therefore a need to remedy this drawback.

[0011] According to one embodiment, a new structure is proposed that greatly improves the detection of such structural defects by increasing the detectable locations of cracks and delamination.

[0012] According to one aspect, an integrated circuit is proposed, comprising - a semiconductor substrate, and -an annular wall, located on and around the periphery of the semiconductor substrate.

[0013] This annular wall comprises in a first part, at least one first elementary module and at least one second elementary module, preferably an alternation of first and second elementary modules, adapted to be mutually electrically connected.

[0014] Each first elementary module comprises a stack of first electrically conductive elements (for example, metallic tracks distributed over N, for example 5, metal levels of the integrated circuit) separated by an electrically insulating material and arranged according to a first pattern having a trapezoidal longitudinal section.

[0015] Each second elementary module comprises a stack of electrically conducting second elements (for example, metallic tracks distributed over Nl metal levels and a doped semiconductor layer covering the semiconductor substrate) separated by the electrically insulating material and arranged according to a second pattern having a longitudinal section of the trapezoidal type inverted with respect to the longitudinal section of the first pattern.

[0016] All the first and second electrically conductive elements together forming at least one electrically conductive path having in a second part of the wall two ends.

[0017] Each end of each electrically conductive path is adapted to be electrically connected to a semiconducting area buried in the substrate under the second part of the wall.

[0018] At least one electrically conductive path includes in said second part of the wall a stepped portion.

[0019] The integrated circuit also includes detection means adapted to be connected to said semiconductor areas and configured to detect at least one type of structural defect of the integrated circuit, for example a crack or delamination, by detecting at least one electrical interruption of at least one electrically conductive path of the annular wall.

[0020] The combination of modules with alternately inverted and non-inverted trapezoidal longitudinal section and one or more stepped portions makes it possible to increase the number of detectable locations of defects.

[0021] According to one embodiment, the first electrically conductive elements comprise N first metal tracks respectively located on the first N metal levels of the integrated circuit, N being greater than or equal to 2 and the second electrically conductive elements comprise an electrically conductive layer on the upper surface of the substrate and Nl second metal tracks respectively located on the first Nl metal levels.

[0022] According to one embodiment, all the first and second electrically conducting elements together form N electrically conducting paths respectively located on the first N metal levels of the integrated circuit, and the integrated circuit comprises 2N buried semiconductor areas.

[0023] These N electrically conductive paths are thus connected separately to the detection means.

[0024] According to another possible embodiment allowing the reduction of the number of buried semiconductor zones, all the first and second electrically conductive elements together form N electrically conductive paths respectively located on the first N metal levels of the integrated circuit, the N electrically conductive paths having respectively N first ends respectively connected to N distinct first buried semiconductor zones and N second ends all connected to the same second buried zone.

[0025] Thus in this embodiment the N electrically conductive paths are connected in a star configuration.

[0026] According to an embodiment allowing further reduction of the number of buried semiconductor areas, all the first and second electrically conductive elements together form a single electrically conductive path extending over the first N metal levels of the integrated circuit, the two ends of the path being connected to two buried semiconductor areas.

[0027] In other words, the N electrically conductive paths are here connected in series to form only one electrically conductive path.

[0028] The integrated circuit generally advantageously includes a sealing ring located on and around the periphery of the semiconductor substrate.

[0029] This sealing ring can contain said annular wall.

[0030] Alternatively, said annular wall may rest on either side of the sealing ring.

[0031] Alternatively, the integrated circuit may comprise two annular walls resting respectively on the two sides of the sealing ring.

[0032] According to another aspect, a method is proposed for detecting at least one type of structural defect in an integrated circuit, for example a crack and / or delamination, in which -the integrated circuit is equipped with an annular wall, located on and around the periphery of the semiconductor substrate of the integrated circuit, and comprising in a first part an alternation of first and second elementary modules mutually electrically connected, each first elementary module comprising a stack of first electrically conductive elements separated by an electrically insulating material and arranged according to a first pattern having a trapezoidal longitudinal section and, each second elementary module comprising a stack of second electrically conductive elements separated by the electrically insulating material and arranged according to a second pattern having a trapezoidal longitudinal section inverted with respect to the first pattern, all the first and second electrically conductive elements together forming at least one electrically conductive path having in a second part of the wall two ends,each end of each electrically conductive path being electrically connected to a semiconductor zone buried in the substrate beneath the second part of the wall, at least one electrically conductive path comprising in said second part of the wall a stepped portion, , -a potential difference is applied between the two ends of said at least one electrically conductive path, and -an absence of current flowing in said at least one electrically conductive path is detected.

[0033] Other advantages and features of the invention will become apparent upon examination of the detailed description of implementation and embodiments, which are by no means limiting, and the accompanying drawings in which: - Figures 1 to 9 illustrate methods of implementation and realization of the invention.

[0034] On [Fig. 1] the reference IC designates an integrated circuit represented here very schematically in top view.

[0035] The integrated circuit includes a core CR typically comprising one or more components, for example but not limited to a microcontroller, surrounded by a ring of contact pads PDR, itself surrounded in this embodiment by a sealing ring SR incorporating here an annular wall MR.

[0036] The sealing ring SR and the annular wall MR are located on and around the periphery of the semiconductor substrate of the integrated circuit.

[0037] This annular wall, examples of whose structures will be detailed below, comprises, as will be seen below, at least one electrically conductive path whose two ends are connected to two semiconductor zones W1 and W2, by example of N conductivity type wells, buried under the MR annular wall in the semiconductor substrate, for example of P conductivity type, of the integrated circuit.

[0038] The CR core of the integrated circuit includes MDET detection means connected to said semiconductor areas W1, W2, and configured to detect at least one type of structural defect of the integrated circuit, for example a crack and / or delamination, by detecting at least one electrical interruption of at least one electrically conductive path of the annular wall.

[0039] In this regard, as will be seen in more detail below, the MDET detection means, of classical structure, are configured to apply a potential difference between the two semiconducting areas W1, W2 and therefore between the two ends of the electrically conductive path, and to detect the presence or absence of a current.

[0040] Alternatively, as schematically illustrated in [Fig.2], the MR wall can be located outside the sealing ring SR and rest on the external side of the sealing ring.

[0041] Alternatively, as schematically illustrated in [Fig.3], the MR wall can be located outside the sealing ring SR and rest on the inner side of the sealing ring, i.e. on the side of the core CR.

[0042] Alternatively, as schematically illustrated in [Fig. 4], the integrated circuit may comprise -a first MRI wall located outside the SR sealing ring and resting on the external side of the sealing ring, and - a second wall MR2 located outside the sealing ring SR and resting on the inner side of the sealing ring.

[0043] We now refer more particularly to figures 5 to 8 to describe an example of the structure of the MR wall.

[0044] Figures 5 to 8 are schematic longitudinal sections.

[0045] As illustrated in [Fig.5], the annular wall MR, which is located in the part BEOL of the integrated circuit, comprises in a first part Zl, an alternation of first elementary modules MD1 and second elementary modules MD2 mutually electrically connected.

[0046] Each first elementary module MD1 comprises a stack of first electrically conducting elements distributed over N levels of metal of the integrated circuit, and separated by an electrically insulating material, typically a dielectric DL material.

[0047] More precisely, here, N is equal to 5 and the first electrically conductive elements comprise 5 first metallic tracks PST11, PST12, PST13, PST14 and PST15 respectively located on the first five metal levels M1, M2, M3, M4 and M5 of the integrated circuit.

[0048] These metal tracks are arranged according to a first pattern having a trapezoidal longitudinal section, with track PST 15 forming the large base of the trapezoid and track PST11 forming the small base of the trapezoid.

[0049] Each second elementary module MD2 comprises a stack of electrically conducting second elements distributed over Nl metal levels and an electrically conducting layer CS, for example a metal silicide layer, separated by the electrically insulating material DL.

[0050] More specifically, the second electrically conductive elements comprise 4 metallic tracks PST21, PST22, PST23 and PST24 respectively located on the first four metal levels M1, M2, M3 and M4.

[0051] These four metallic tracks and the CS layer are arranged according to a second pattern having a longitudinal section of the trapezoidal type inverted with respect to the longitudinal section of the first pattern.

[0052] More specifically in the second pattern it is this time the CS layer which forms the large base of the trapezoid and it is the PST24 track which forms the small base of the trapezoid.

[0053] The electrical connection between a first module MD1 and a second module MD2 is made using vias and contacts between the first elements and the second electrically conductive elements.

[0054] More specifically, the V45 vias electrically connect the second PST24 track of a second MD2 module to the first PST15 track of each first MD1 module flanking the second MD2 module.

[0055] The V34 vias electrically connect the second PST23 track of a second MD2 module to the first PST14 track of each first MD1 module flanking the second MD2 module.

[0056] The V23 vias electrically connect the second PST22 track of a second MD2 module to the first PST13 track of each first MD1 module flanking the second MD2 module.

[0057] The V12 vias electrically connect the second PST21 track of a second MD2 module to the first PST12 track of each first MD1 module flanking the second MD2 module.

[0058] The CTI contacts electrically connect the CS layer of a second MD2 module to the first PST11 track of each first MD1 module flanking the second MD2 module.

[0059] The CT2 contacts electrically connect the first PST11 track of a first MD1 module to the CS layer of each second MD2 module adjacent to the first MD1 module.

[0060] Other vias electrically connect respectively the first tracks PST 12-PST15 of a first module MD1 to the second tracks PST21 of each second module MD2 adjacent to the first module MD1.

[0061] Finally, an insulating RIS region, for example a shallow trench, located in the semiconductor substrate SB of the integrated circuit between the contacts CTI and CT2, interrupts the electrical continuity of the CS layer.

[0062] The MR wall also includes a second part Z2 with different examples of structures respectively illustrated in figures 6 to 8.

[0063] In the example of [Fig.6], the integrated circuit comprises ten semiconductor areas W11-W15 and W21-W25 buried in the substrate SB under the second part Z2 of the wall.

[0064] These semiconductor zones are, for example, N-doped wells, the substrate being of type P conductivity.

[0065] Formation of an electrically conductive path CH5

[0066] For the formation of this CH5 path, the wall also includes at the metal level M5, two metal tracks PST50 and PST52 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0067] The PST50 track is connected to the semiconducting area W15 via the metal tracks PST410, PST311, PST212, PST113 respectively located at the metal levels M4, M3, M2 and M1, vias and a contact.

[0068] The PST52 track is connected to the semiconducting area W25 via the metal tracks PST411, PST312, PST213, PST114 respectively located at the metal levels M4, M3, M2 and M1, vias and a contact.

[0069] The PST 15 and PST24 tracks of the MD1 and MD2 modules together with the PST50, PST52, PST410, PST311, PST212, PST113, PST411, PST312, PST213, PST114 tracks and the corresponding vias and contacts, form the electrically conductive path CH5 whose two ends EX 15 and EX25 are connected to the two buried areas W15 and W25.

[0070] Furthermore, as can be seen in the figure, this path CH5 comprises -a first stepped section formed by runway PST410 and the stacking of runs PST311, PST212 and PST113, and - a second stepped section formed by track PST411, track PST312 and the stacking of tracks PST213 and PST114.

[0071] Formation of an electrically conductive path CH4

[0072] For the formation of this CH4 path, the wall also includes at the metal level M4, two metal tracks PST40 and PST42 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0073] The PST40 track is connected to the semiconducting area W14 via the metal tracks PST310, PST211, PST112, respectively located at the metal levels M3, M2 and M1, vias and a contact.

[0074] The PST42 track is connected to the semiconducting area W24 via the metal tracks PST313, PST214, PST115 respectively located at the metal levels M3, M2 and M1, vias and a contact.

[0075] The PST14 and PST23 tracks of the MD1 and MD2 modules together with the PST 40, PST42, PST310, PST211, PST112, PST313, PST214, PST115 tracks and the corresponding vias and contacts form the electrically conductive path CH4, the two ends of which EX14 and EX24 are connected to the two buried areas W14 and W24.

[0076] Moreover, as can be seen in the figure, this path CH4 includes a stepped section formed by tracks PST313, PST214 and PST115.

[0077] Formation of an electrically conductive path CH3

[0078] For the formation of this CH3 path, the wall also includes at the metal level M3, two metal tracks PST30 and PST32 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0079] The PST30 track is connected to the semiconducting area W13 via the metal tracks PST210, PST111 respectively located at the metal levels M2 and M1, vias and a contact.

[0080] The PST32 track is connected to the semiconducting area W23 via the metal tracks PST215, PST116 respectively located at the metal levels M2 and M1, vias and a contact.

[0081] The PST 13 and PST22 tracks of the MD1 and MD2 modules together with the PST30, PST32, PST210, PST111, PST215, PST116 tracks and the corresponding vias and contacts form the electrically conductive path CH3, the two ends of which EX 13 and EX23 are connected to the two buried areas W13 and W23.

[0082] Moreover, as can be seen in the figure, this path CH3 includes a stepped section formed by tracks PST215 and PST116.

[0083] Formation of an electrically conductive path CH2

[0084] For the formation of this CH2 path, the wall also includes at the metal level M2, two metal tracks PST20 and PST22 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0085] The PST20 track is connected to the semiconducting area W12 via the metal track PST 110 located at the metal level Ml, a via and a contact.

[0086] The PST22 track is connected to the semiconducting area W22 via the metal track PST 117 located at the metal level Ml, a via and a contact.

[0087] The PST12 and PST21 tracks of the MD1 and MD2 modules, together with the PST20, PST22, PST110, PST117 tracks and the corresponding vias and contacts, form the path electrically conductive CH2 whose two ends EX 12 and EX22 are connected to the two buried zones W12 and W22.

[0088] Formation of an electrically conductive path CH1

[0089] For the formation of this CH1 path, the wall also includes at the level of metal M1, two metal tracks PST 10 and PST 12 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0090] The PST 10 track is connected to the semiconductor area W11 via a contact.

[0091] The PST12 track is connected to the W12 semiconductor area via a contact.

[0092] The PST11 tracks and the CS semiconductor layer of the MD1 and MD2 modules together with the PST 10, PST 12 tracks and the corresponding vias and contacts, form the electrically conductive path CH1 whose two ends EX11 and EX21 are connected to the two buried areas W11 and W21.

[0093] In the embodiment just described, the five electrically conductive paths CH1-CH5 are individualized and are each intended to receive a potential difference between their two respective ends. They are thus connected separately to the detection means.

[0094] That being said, it is possible, as illustrated in [Fig.7], to reduce the number of buried areas, and therefore the space required on silicon, by creating five electrically conductive paths connected in a star configuration.

[0095] More specifically, in the example of [Fig.7], the integrated circuit comprises six semiconductor areas W11-W15 and W2 buried in the substrate SB under the second part Z2 of the MR wall.

[0096] All electrically conductive paths have one end connected to the area W2.

[0097] Formation of an electrically conductive path CH15

[0098] For the formation of this CH15 path, the wall also includes at the metal level M5, two metal tracks PST50 and PST52 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0099] The PST50 track is connected to the semiconducting area W15 via the metal tracks PST41, PST311, PST212, PST112 respectively located at the metal levels M4, M3, M2 and M1, vias and a contact.

[0100] The PST52 track is connected to the semiconducting area W2 via the metal tracks PST42, PST32, PST22, PST12 respectively located at the metal levels M4, M3, M2 and M1, vias and a contact.

[0101] Tracks PST15 and PST24 of modules MD1 and MD2 form with tracks PST50, PST52, PST41, PST311, PST212, PST112, PST42, PST32, PST22, PST12 and the corresponding vias and contacts, the electrically conductive path CH 15 whose two ends EX 15 and EX2 are connected to the two buried areas W15 and W2.

[0102] Furthermore, as can be seen in the figure, this path CH 15 comprises -a first stepped section formed by the tracks PST41, PST311, PST212 and PST112, and - a second stepped section formed by the tracks PST42, PST32, PST22 and PST12.

[0103] Formation of an electrically conductive path CH14

[0104] For the formation of this CH 14 path, the wall also includes at the level of metal M4, two metal tracks PST40 and PST42 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0105] The PST40 track is connected to the semiconducting area W14 via the metal tracks PST310, PST211, PST111, respectively located at the metal levels M3, M2 and M1, vias and a contact.

[0106] The PST42 track is connected to the semiconducting area W2 via the metal tracks PST32, PST22, PST12 respectively located at the metal levels M3, M2 and M1, vias and a contact.

[0107] The PST14 and PST23 tracks of the MD1 and MD2 modules together with the PST40, PST42, PST310, PST211, PST111, PST32, PST22, PST12 tracks and the corresponding vias and contacts form the electrically conductive path CH 14, the two ends of which EX14 and EX2 are connected to the two buried areas W14 and W2.

[0108] Furthermore, as can be seen in the figure, this path CH14 comprises -a first stepped section formed by tracks PST310, PST211 and PST111, and - a second stepped section formed by tracks PST42, PST32, PST22 and PST12.

[0109] Formation of an electrically conductive path CH13

[0110] For the formation of this CH 13 path, the wall also includes at the level of metal M3, two metal tracks PST30 and PST32 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0111] The PST30 track is connected to the semiconducting area W13 via the metal tracks PST210, PST110, respectively located at the metal levels M2 and M1, vias and a contact.

[0112] The PST32 track is connected to the semiconducting area W2 via the metal tracks PST22, PST12 respectively located at the metal levels M2 and M1, vias and a contact.

[0113] The PST 13 and PST22 tracks of the MD1 and MD2 modules form with the PST30, PST32, PST210, PST110, PST22, PST12 tracks and the vias and contacts corresponding, the electrically conductive path CH 13 whose two ends EX 13 and EX2 are connected to the two buried areas W13 and W2.

[0114] Furthermore, as can be seen in the figure, this path CH 13 comprises - a first stepped section formed by tracks PST210 and PST110, and - a second stepped section formed by tracks PST32, PST22 and PST12.

[0115] Formation of an electrically conductive path CH12

[0116] For the formation of this CH 12 path, the wall also includes at the metal level M2, two metal tracks PST20 and PST22 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0117] The PST20 track is connected to the semiconducting area W12 via the metal track PST 100 located at the metal level Ml, a via and a contact.

[0118] The PST22 track is connected to the semiconducting area W2 via the metal track PST 12 located at the metal level M1, a via and a contact.

[0119] The PST12 and PST21 tracks of the MD1 and MD2 modules together with the PST20, PST22, PST12 tracks and the corresponding vias and contacts, form the electrically conductive path CH 12 whose two ends EX 12 and EX2 are connected to the two buried areas W12 and W2.

[0120] Moreover, as can be seen in the figure, this path CH 12 includes a stepped section formed by tracks PST22 and PST12.

[0121] Formation of an electrically conductive path CHU

[0122] For the formation of this CH11 path, the wall also includes at the level of metal M1, two metal tracks PST 10 and PST 12 which respectively extend on each side the alternation of the first and second modules MD1 and MD2.

[0123] The PST10 track is connected to the W11 semiconductor area via a contact.

[0124] The PST12 track is connected to the semiconductor area W2 via a contact.

[0125] The PST11 tracks and the CS semiconductor layer of the MD1 and MD2 modules together with the PST 10, PST 12 tracks and the corresponding vias and contacts form the electrically conductive path CH11, the two ends of which EX11 and EX2 are connected to the two buried areas W11 and W2.

[0126] In the embodiment just described, the five electrically conductive paths CH11-CH15 are connected in parallel. A reference voltage, for example ground, can be applied to the W2 area and thus to the common end of the five paths CH11-CH15, and an individual voltage, for example 3 volts, can be applied to each of the other ends of the paths.

[0127] That being said, it is possible, as illustrated in [Fig. 8], to further reduce the number of buried zones, and therefore the silicon footprint, by creating a single path electrically conductive CH21 with all traces, CS layer, vias and MR wall contacts.

[0128] More specifically, in the example of [Fig.8], the integrated circuit has two semiconductor areas W1 and W2 buried in the substrate SB under the second part Z2 of the MR wall.

[0129] The wall has in its second part Z2 a metal track PST 10 at the level of metal Ml, connected to the area W1 by a contact.

[0130] The EX11 end of the contact forms a first end of the CH21 path.

[0131] The metal track extends through the tracks of the MD1 and MD2 modules to join the PST12 track.

[0132] The PST 12 track is connected by a via to the PST22 track, located at the metal level M2, which extends through the tracks of the MD1 and MD2 modules to join the PST20 track.

[0133] The PST20 track is connected by a via to the PST30 track, located at the level of metal M3, which extends through the tracks of the MD1 and MD2 modules to join the PST32 track.

[0134] The PST32 track is connected by a via to the PST42 track, located at the metal level M4, which extends through the tracks of the MD1 and MD2 modules to join the PST40 track.

[0135] The PST40 track is connected by a via to the PST50 track, located at the level of metal M5, which extends through the tracks of the MD1 and MD2 modules to join the PST52 track.

[0136] The PST52 track is connected to the buried area W2 by the PST41, PST31, PST21, PST11 tracks (respectively located at metal levels M4, M3, M2, M1), vias and a contact whose end EX12 forms a second end of the CH21 path.

[0137] Furthermore, tracks PST41, PST31, PST21, PST11 form a stepped section of the CH21 path.

[0138] Regardless of the embodiment, the trapezoidal longitudinal section modules, the stepped portion(s), and the vias and contacts ensure good detection of an electrical interruption of the electrically conductive path(s) by vertical cracks and / or horizontal cracks (delamination) appearing in the wall.

[0139] Indeed, the detectability of defects is greatly improved by a large filling of the wall with metal and a reduction of dielectric regions.

[0140] The wall is produced using classic steps employed in the production of the BEOL part of an integrated circuit, namely, in particular, etching, metal deposition, etc.)

[0141] Reference is now made more particularly to [Fig.9] to describe a method of implementing a defect detection process.

[0142] In an S90 step, the integrated circuit IC is equipped with an MR wall of the type described above and comprising, for example, at least one electrically conductive path.

[0143] In a step S91, a potential difference is applied between the two ends EX1 and EX2 of the path.

[0144] In a step S92, the absence or presence of a current in the electrically conductive path is detected.

[0145] If in step S93, the presence of a current is detected, this means an absence of fault.

[0146] If on the contrary an absence of current is detected, this means the presence of at least one fault.

Claims

Demands

1. Integrated circuit, comprising - a semiconductor substrate (SB), - an annular wall (MR), located on and around the periphery of the semiconductor substrate, and comprising in a first part (Z1) at least one first elementary module and at least one second elementary module (MD1, MD2) adapted to be mutually electrically connected, each first elementary module (MD1) comprising a stack of first electrically conducting elements separated by an electrically insulating material (DL) and arranged in a first pattern having a trapezoidal longitudinal section and, each second elementary module (MD2) comprising a stack of second electrically conducting elements separated by the electrically insulating material (DL) and arranged in a second pattern having a trapezoidal longitudinal section inverted with respect to the first pattern,all first and second electrically conductive elements together forming at least one electrically conductive path (CH1-CH5) having in a second part (Z2) of the wall two ends, each end of each electrically conductive path being adapted to be electrically connected to a buried semiconductor zone (W1, W2) in the substrate under the second part of the wall, at least one electrically conductive path comprising in said second part of the wall a stepped portion, and detection means (MDET) adapted to be connected to said semiconductor zones and configured to detect at least one type of structural fault of the integrated circuit by detecting at least one electrical interruption of at least one electrically conductive path of the annular wall.

2. Device according to claim 1, wherein the wall (MR) comprises in the first part (Zl), an alternation of first elementary modules (MD1) and second elementary modules (MD2) adapted to be mutually electrically connected.

3. Integrated circuit according to claim 1 or 2, wherein the first electrically conductive elements comprise the first N metallic tracks (PST11-PST15) respectively located on the N first metal levels (M1-M5) of the integrated circuit, N being greater than or equal to 2 and the second electrically conductive elements comprise an electrically conductive layer (CS) on the top surface of the substrate and Nl second metal traces (PST21-PST24) respectively located on the Nl first metal levels (M1-M4).

4. Integrated circuit according to any one of the preceding claims, wherein all the first and second electrically conducting elements together form N electrically conducting paths (CH1-CH5) respectively located on the first N metal levels of the integrated circuit, and the integrated circuit comprises 2N buried semiconductor areas.

5. Integrated circuit according to any one of claims 1 to 3, wherein all the first and second electrically conductive elements together form N electrically conductive paths (CH11-CH15) respectively located on the first N metal levels of the integrated circuit, the N electrically conductive paths having respectively N first ends respectively connected to N distinct first buried semiconductor areas and N second ends all connected to the same second buried area.

6. Integrated circuit according to any one of claims 1 to 3, wherein all the first and second electrically conductive elements together form a single electrically conductive path (CH21) extending over the first N metal levels of the integrated circuit, the two ends of the path being connected to two buried semiconductor areas (W1, W2).

7. Integrated circuit according to any one of the preceding claims, further comprising a sealing ring (SR) located on and around the periphery of the semiconductor substrate and containing said ring wall (MR).

8. Integrated circuit according to any one of claims 1 to 6, further comprising a sealing ring (SR) located on and around the periphery of the semiconductor substrate and in which said annular wall (MR) rests on either side of the sealing ring.

9. Integrated circuit according to any one of claims 1 to 6, further comprising a sealing ring (SR) located on and around the periphery of the semiconductor substrate and two annular walls (MRI, MR2) resting respectively on the two sides of the sealing ring.

10. Integrated circuit according to any one of the preceding claims, wherein the type of structural defect includes a crack and / or delamination.

11. A method for detecting at least one type of structural defect in an integrated circuit, wherein the integrated circuit is equipped (S90) with an annular wall, located on and around the periphery of the semiconductor substrate of the integrated circuit, and comprising in a first part at least one first elementary module and at least one second elementary module mutually electrically connected, each first elementary module comprising a stack of first electrically conductive elements separated by an electrically insulating material and arranged according to a first pattern having a trapezoidal longitudinal section and, each second elementary module comprising a stack of second electrically conductive elements separated by the electrically insulating material and arranged according to a second pattern having a trapezoidal longitudinal section inverted with respect to the first pattern,all first and second electrically conductive elements together forming at least one electrically conductive path having two ends in a second part of the wall, each end of each electrically conductive path being electrically connected to a semiconducting zone buried in the substrate under the second part of the wall, at least one electrically conductive path having a stepped portion in said second part of the wall, -a potential difference is applied (S91) between the two ends of said at least one electrically conductive path, and -an absence of current flowing in said at least one electrically conductive path is detected (S92, S93).

12. A method according to claim 11, wherein the type of structural defect includes a crack and / or delamination.

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