Integrated circuit and method for detecting a disturbance in an integrated circuit

Abstract

An integrated circuit comprising an analyzer and detection logic gates (TAMP1) including a three-state output (OUT1), consisting of two low-impedance logic states and one high-impedance state. The two low-impedance logic states each have a first and a second state. The detection logic gates (TAMP1) are configured to implement the following first steps: Transition of output (OUT1) to the first state, then transition of output (OUT1) to the high-impedance state while output (OUT1) is in the first state, then a second transition of output (OUT1) to the first state. The analyzer is configured to implement the following second step: Detection of a disturbance if, during the second transition, output (OUT1) transitions to the second state before switching back to the first state. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Integrated circuit and method for detecting a disturbance in an integrated circuit. Technical field

[0001] The present invention relates to the detection of disturbances in an integrated circuit resulting, for example, from laser illumination. Previous technique

[0002] Introducing disturbances into integrated circuits is commonly used to unlawfully attack integrated circuits and secure systems, particularly in the banking, identity, and biometrics sectors. These attacks may aim to gain unauthorized access to a service (e.g., identification) or to extract information from the target (programs, confidential data, cryptographic keys, etc.). Integrated circuits used in a wide range of applications must be protected and certified against these attacks.

[0003] Pulsed lasers provide a practical and easily controlled method for introducing such errors by creating transient currents in PN junctions or in transistor channels via the photoelectric effect. See the publications “Laser pulse injection into SRAM cells: Picosecond versus nanosecond pulses” by Lacruche, M. et al., On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International, and “Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells” by Cyril Roscian et al., 2013 Workshop on

[0004] Fault Diagnosis and Tolerance in Cryptography (FDTC) and “Electrical modeling of the photoelectric effect induced by a pulsed laser applied to an SRAM”. A. Sarafianos et al.,

[0005] Journal Microelectronics Reliability, 2013 deal for example with the injection of laser-induced faults into SRAM memories.

[0006] Furthermore, a transient error in an integrated circuit can be caused by a charged particle in a radiative environment of the circuit, for example aeronautical or space.

[0007] There are a large number of laser attack detectors presented in the literature for more than 20 years, for example the one proposed in the publication “Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well 1”, J.-M. Dutertre et al., Journal Microelectronics Reliability, 2014. Part of the state-of-the-art solutions relies on analog circuits requiring more or less complex calibration and occupying a relatively large silicon area.

[0008] Detector solutions incorporating digital gates are not effective against laser injections because the laser power must exceed a certain threshold to be detected. Indeed, the injection of a fault at a conventional logic gate is induced by the appearance of transient currents that discharge (or charge) a logic node in a circuit (comparable to the charging / discharging of a capacitor by a current). This phenomenon is limited by the existence of pull-up currents that compensate for the transient currents. Therefore, a prior art logic gate does not have good potential for detecting laser illumination, or more generally, a disturbance. Description of the invention

[0009] There is a need to further improve detectors and methods for detecting disturbances in an integrated circuit, particularly in terms of efficiency, reliability and cost. Integrated circuit

[0010] The invention aims to achieve this objective and, according to one of its aspects, relates to an integrated circuit comprising a detector (in other words: a sensor) of a disturbance in the integrated circuit, the disturbance detector comprising an analysis element and an array of at least one logic gate (in other words: a set of logic gates), each detection logic gate of the array of at least one logic gate comprising an output, the output (in other words: said each logic gate) being in three states, the three states comprising two low-impedance logic states (by low impedance, we mean, for example, that the impedance of the output is less than 100 ohms (and for example strictly greater than 0 ohms)) (where the output can take the values ​​0 or 1) and one high-impedance state; by high impedance, we mean, for example,that the output impedance is greater than 10000 ohms (and for example less than 108 ohms)) (the three states being controlled by inputs of said each detection logic gate of the set), the two low-impedance logic states comprising a first state and a second state different from the first state, the high-impedance state comprising a first sub-state and a second sub-state different from the first sub-state, the analyzer being connected (by a logic bus) to the output by a connection, each detection logic gate of the set of at least one logic gate being configured to (in other words: being capable of) implementing the following first steps (during the operation of the integrated circuit): , • First pass of the output through the first state, then • Transition of the output into the high impedance state, while the output is in the first state, then • Maintaining the output in the high-impedance state during a detection period, such that (in other words: so that) each detection logic gate (TAMP1, TAMP1', CCELL2, CCELL3, CCELL4) of the assembly memorizes the first substate,

[0011] And the analyzing unit being configured to implement the following second step: • Detection of a disturbance if the detection element detects that the output (OUT1, OUT2, OUT3, OUT4) has passed into (in other words: through) the second substate during the output holding stage.

[0012] Thus, a disturbance during the detection period is detected by the analysis element if, during the output holding stage, the output passes through the second state ( , in a transient manner), before switching (in other words: passing) into the first state. No disturbance is detected otherwise.

[0013] For example, the disturbance generates a leakage current which causes the output to (transiently) pass into the second substate before passing into said first state, during the second pass.

[0014] During the disturbance, since each detection logic gate has its output in a high impedance state, no compensation current is generated to limit the effect of the disturbance.

[0015] Thus, the detector according to the invention is particularly sensitive to the disturbance, which facilitates the detection of the disturbance.

[0016] Preferably, switching the output into the high impedance state and maintaining the output in the high impedance state is implemented by applying a zero voltage to an input of said each detection logic gate of the assembly.

[0017] Thus, each detection logic gate does not consume electrical energy during the detection period, which reduces the consumption of the integrated circuit.

[0018] Alternatively, this transition and maintenance can be implemented by applying a non-zero voltage.

[0019] By low-impedance output states, we can understand, for example, that the output is connected either to the power supply (of the integrated circuit) or to the ground of the (integrated circuit), for example, via transistors in a conducting state. Conversely, by high-impedance output state, we can understand, for example, that the output is connected neither to the power supply (of the integrated circuit) nor to the ground of the (integrated circuit). The output is connected only to one or more logic gate inputs, that is, only to one or more transistor gates (themselves thus in a high-impedance state).

[0020] Upon detection of the disturbance: • The analysis body can issue an alert message, and / or • The integrated circuit can emit an alert signal. Alternatively, the integrated circuit can take an internal countermeasure (such as erasing the cryptographic key or inhibiting an output).

[0021] Of course, the first transition of the output into the first state, the transition of the output into the high impedance state, the maintenance of the output in the high impedance state, and / or the second transition below can be controlled by one or more logic values ​​received by said each detection logic gate of the assembly on at least one of its inputs, for example, from a detector control element which can be the analysis element or by the output of the function logic gates as defined below.

[0022] For example, the disturbance is caused by radiation, for example from a laser, for example during an attack aimed at discovering a secret stored in the integrated circuit. The disturbance can also be generated by any other element in the circuit's environment, whether intentionally or unintentionally.

[0023] Preferably the integrated circuit includes logic gates called function gates to implement a main function of the integrated circuit different from the disturbance detection function implemented by the detector.

[0024] For example, the integrated circuit includes comb-like nested power rails, with the function logic gates and the detector being powered by the power rails.

[0025] For example, each detection logic gate of the set is between two function logic gates.

[0026] According to one embodiment, the first steps and the second step are repeated, for example once the second step has been completed.

[0027] For example, the aforementioned detection period can last from 100 nanoseconds to 10 milliseconds.

[0028] The output does indeed discharge gradually after a certain time.

[0029] Alternatively, the first and second steps are implemented at the time of implementation of a critical operation by the integrated circuit (for example, encryption from a secret key).

[0030] According to one embodiment, an output voltage in the first state is greater than an output voltage in the second state.

[0031] Thus, for example, the first state is a state where the output is at a logic value equal to 1 (and / or the voltage is equal to 1.5 volts or 3 volts, for example) and the second state is a state where the output is at "0" (at 0 volts, for example).

[0032] In this configuration, each detection logic gate is more sensitive to disturbances.

[0033] According to one embodiment, for each detection logic gate of the assembly, the transition of the output (of the logic gate) into the high impedance state is controlled (in other words: determined) by an activation logic value received by an activation input and said one of the two low impedance logic states is controlled (in other words: determined), by a control logic value received by a control input on the condition (in other words: when) that the output is not in the high impedance state (that is, when the output is in one of the two basic impedance logic states).

[0034] According to one embodiment, the first steps include, following the passage of the output into the high impedance state, a second passage of the output into the first state, the disturbance being detected, during the disturbance detection step, if the analysis element detects that the output passes into the second substate, in a transient manner (that is to say, for a duration which can be between 10 picoseconds and 10 nanoseconds), before switching into the first state, following the second passage.

[0035] This embodiment is particularly interesting when the set of at least one logic gate comprises (in other words: being made up of) a series (in other words: a plurality) of logic gates, the logic gates of the series of logic gates being connected in series to the analysis unit for example by their control inputs and by their outputs, and / or, for example, their activation inputs are controlled by the same logic signal (in other words: to the same control line).

[0036] Thus, the transition to the second state (in a transitional manner) can be propagated through the plurality or series of logic gates to the analysis unit.

[0037] Alternatively, of course, the plurality of logic gates can be controlled and connected to one or more analysis units according to other electronic architectures.

[0038] Generally, the set of at least one logic gate comprises a plurality of logic gates or consists of a single logic gate, for example in the case where it is only a matter of protecting a single sensitive area of ​​an integrated circuit.

[0039] According to one embodiment, each detection logic gate reproduces, at the output, the control logic value when the output is in one of the two low impedance logic states (i.e. when the output is not in a high impedance state).

[0040] Alternatively, each detection logic gate may implement another function such as a logical AND or an inverter.

[0041] According to one embodiment, each detection logic gate comprises: • A transistor bridge comprising a first p-type transistor (i.e., PMOS) and a first n-type transistor (i.e., NMOS) connected in series and linked at their drains by a midpoint defining the output of each logic gate, the gate of the first n-type transistor being connected to the enable input and the gate of the first p-type transistor being connected to the complement of the enable input, • A second p-type transistor (in other words: PMOS) whose drain is connected to the source of the first p-type transistor, the source of the second p-type transistor being connected to the power supply, and the gate of the second p-type transistor being connected to the complementary input of the control input of each detection logic gate, • A second n-type transistor (in other words: NMOS) whose drain is connected to the source of the first n-type transistor, the source of the second n-type transistor being connected to ground, and the gate of the second n-type transistor being connected to the complement of the control input of said each detection logic gate.

[0042] According to one embodiment, said each detection logic gate of the set comprises a request input and an acknowledgment input, the output being in the first state if (and only if) (in other words: when) the request input and the acknowledgment input have the same logic value equal to 0 (i.e., if a zero voltage is applied to the request input and the acknowledgment input), the output being in the second state if (and only if) (in other words: when) the request input and the acknowledgment input have the same logic value equal to 1, the output being in a high impedance state otherwise (when the request input and the acknowledgment input have different logic values).

[0043] This type of gate is similar to a Muller gate used in asynchronous pipelines, but of course other types of gates can be used.

[0044] According to one embodiment, each detection logic gate of the assembly comprises: • A transistor bridge comprising a first p-type transistor (in other words: PMOS) and a first n-type transistor (in other words: NMOS) connected in series and connected at their drains by a midpoint defining the output of said each logic gate, the gate of the first n-type transistor and the gate of the first p-type transistor being connected to the acknowledgment input; • A second p-type transistor (also known as a PMOS) whose drain is connected to the source of the first p-type transistor, the source of the second with the p-type transistor connected to the power supply, and the gate of the second p-type transistor connected to the request input, • A second n-type transistor whose drain is connected to the source of the first n-type transistor, the source of the second n-type transistor being connected to ground, and the gate of the second n-type transistor being connected to the request input.

[0045] According to one embodiment, the set of at least one detection logic gate comprising (in other words: being made up of) a series of logic gates, the request input of a first logic gate in the series of logic gates being the complement of the output of a second logic gate preceding (immediately) the first logic gate in the series of logic gates, the acknowledgment input of the second logic gate being the output of the first logic gate (regardless of the first logic gate in the series of logic gates), the output and acknowledgment input of the last logic gate in the series of logic gates being connected to the analysis element.

[0046] Thus, the series of logic gates is arranged in an asynchronous pipeline (which is also a series arrangement), well known to those skilled in the art.

[0047] Thus, in general (including in the case where the series of logic gates consists of inverters mounted in series) the transition of the output into the second state can propagate through the series of logic gates to the analysis unit.

[0048] Alternatively, of course, the plurality of logic gates can be controlled and connected to one or more analysis units according to other electronic architectures.

[0049] Of course, the integrated circuit according to the invention may have detection logic gates of different architectures. The set of at least one logic gate may, in this case, consist of gates of the same architecture (or of a single gate) from among the different architectures.

[0050] Other types of logic gate architecture and detector arrangement are of course possible. Detection method

[0051] The invention also relates, according to another aspect, to a method for detecting a disturbance in an integrated circuit, implemented by a disturbance detector of the integrated circuit, the disturbance detector comprising an analysis element and a set of at least one logic gate (in other words: a set of logic gates), each detection logic gate of the set of at least one logic gate comprising an output, the output being three-state, the three states comprising two low-impedance logic states (by low impedance, it is understood, for example, that the output impedance is less than 100 ohms (and for example strictly greater than 0 ohms)) (where the output can take the values ​​0 or 1) and a high-impedance state (by high impedance, we mean, for example, that the output impedance is greater than 10000 ohms (and, for example, less than 108 ohms)) (the three states being controlled by inputs of each of said logic gates for detection in the assembly), the two low-impedance logic states comprising a first state and a second state different from the first state, the high-impedance state comprising a first sub-state and a second sub-state different from the first sub-state, the analysis unit being connected (by a logic bus) to the output, the method being characterized in that it comprises: • The following initial steps, implemented by each detection logic gate in the assembly (during the operation of the integrated circuit): • First pass of the output through the first state, then • Transition of the output into the high-impedance state, while the output is in the first state, then • Maintaining the output in the high-impedance state during a detection period, so that (in other words: so that) each detection logic gate in the assembly memorizes the first substate, • A second, subsequent step: • Detection of a disturbance if the detection element detects that the output has passed into (in other words: through) the second substate during the output holding stage.

[0052] The advantages and characteristics of the process are identical to those of the integrated circuit, mutatis mutandis, although they are not repeated here. Brief description of the drawings

[0053] The invention will be better understood upon reading the detailed description that follows, the non-limiting examples of its implementation, and upon examination of the accompanying drawing, on which:

[0054] [Fig-1] The [Fig. 1] is a schematic view of each logic gate of the detector of the [Fig.2];

[0055] [Fig.2] [Fig.2] is a schematic view of a detector of an integrated circuit according to a method of implementing the invention;

[0056] [Fig.3] [Fig.3] schematically illustrates an integrated circuit according to one embodiment of the invention;

[0057] [Fig.4] [Fig.4] schematically represents each logic gate of the detector in [Fig.5];

[0058] [Fig. 5] [Fig. 5] schematically represents a variant of the detector of the [Fig.2];

[0059] [Fig.6] [Fig.6] represents an implementation of the method according to the invention, according to an example of implementation, by the detector of [Fig.2] or the detector of [Fig.5]. Detailed description

[0060] Figure 2 schematically illustrates a detector, DETECT1, comprising an analysis element and 6 logic gates connected in series to the detection element. One of these logic gates, TAMP1, is shown in more detail in Figure 1. The other 5 logic gates are identical to TAMP1.

[0061] The DETECT1 detector is contained in an integrated circuit (not shown).

[0062] As shown [Fig. 1], the logic gate, TAMP1 comprises • A transistor bridge comprising a first p-type PMOS1 transistor and a first n-type NMOS1 transistor connected in series and linked at their drains by a midpoint defining the output OUT1 of the logic gate TAMP1, the gate of the first n-type NMOS1 transistor being connected to the activation input EN1 and the gate of the first p-type PMOS1 transistor being connected to the complementary side of the activation input EN1, • A second p-type PMOS2 transistor whose drain is connected to the source of the first p-type PMOS1 transistor, the source of the second p-type transistor being connected to the power supply, and the gate of the second p-type PMOS2 transistor being connected to the complementary side of the INI control input of the TAMP1 logic gate, • A second n-type NMOS2 transistor whose drain is connected to the source of the first n-type NMOS1 transistor, the source of the second n-type NMOS2 transistor being connected to ground GnDl and the gate of the second n-type NMOS2 transistor being connected to the complement of the INI control input of the logic gate TAMP1.

[0063] Thus, the output OUT1 of the logic gate TAMP1 is in a high impedance state when the enable input EN1 is at 0. When the enable input EN1 is at 1, the logic gate TAMP1 implements the identity function.

[0064] With reference to [Fig.6], at step S00, the logic gate TAMP1 receives, at the activation input EN1, a 1, and at the control input INI, a 1, for example from the analysis unit oal or from other logic gates identical to TAMP1 mounted in series with the logic gate TAMP1 (as illustrated [Fig.2]), which turns the output OUT1 to 1.

[0065] At step S10, the logic gate TAMP1, while in the state of the end of step S00, receives a 0 at the activation input EN1. The output OUT1 then goes into a high impedance state which is maintained for 1 microsecond, for example by maintaining the activation input EN1 at 0.

[0066] At step S30, the logic gate TAMP1 or an area near the logic gate TAMP1 receives a laser flash.

[0067] At step S40, the logic gate TAMP1 again receives, at the activation input EN1, a 1, and at the control input INI, a 1. As a result of the laser flash received at step S30, the logic gate TAMP1 produces at output a 0 for 10 nanoseconds, then a 1 (in accordance with the normal operation of the logic gate TAMP1) which are broadcast to the analysis unit oal via the logic gates (identical to the logic gate TAMP1) located between the logic gate TAMP1 and the analysis unit oal and via the bus BUSl.

[0068] At step S50, the analysis unit detects the 0 for 10 nanoseconds and then the 1, and consequently emits an alert message which triggers a countermeasure implemented by the integrated circuit comprising the DETECTE detector

[0069] Such a visual analysis device is, of course, within the reach of a person skilled in the art. It is not necessary to detail it here.

[0070] For example, steps S00 to S50 can be repeated during the operation of the circuit.

[0071] An integrated circuit HERE is schematically illustrated in [Fig. 3] according to a mode Implementation of the invention. The integrated circuit HERE includes a DETECT3 detector.

[0072] The DETECT3 detector comprises logic gates all identical to the TAMP1' logic gate connected in series. The TAMP1' logic gate differs from the TAMP1 logic gate in that the control input is not inverted.

[0073] Thus, when the activation input EN1 is at 1, the logic gate TAMP1' behaves like an inverter of the control input.

[0074] Steps S00 to S50 are then indicated in this embodiment, except for the input and output values, which are alternately 0 and 1, due to the inverse function. At step S50, the analysis element oa3 then detects a disturbance in the event of the presence of a 0 or a 1 for 10 nanoseconds.

[0075] Such an analytical device oa3 is within the reach of a person skilled in the art. It is not necessary to detail it here.

[0076] The integrated circuit ICI includes, in zones Z2 and Z3, logic gates called function gates to implement a main function of the integrated circuit ICI different from the disturbance detection function implemented by the detector DETECT3, the logic gate TAMP1' being located in a zone ZI between zones Z2 and Z3. Thus, each detection logic gate of the assembly is between two function logic gates.

[0077] For example, the integrated circuit ICI includes power rails RI, R2 nested in a comb, the function logic gates and the detector DETECT3 being powered by the power rails RI, R2.

[0078] In [Fig.3], the DETECT3 detector can be replaced by the DETECT1 detector from [Fig.2] or the DETECT2 from [Fig.5].

[0079] Figure 4 represents a logic gate CCELL3 which includes • A transistor bridge comprising a first p-type PMOS3 transistor and a first n-type NMOS3 transistor connected in series and linked at their drains by a midpoint defining the output OUT3 of the logic gate CCELL3, the gate of the first n-type NM0S3 transistor and the gate of the first p-type PMOS3 transistor being connected to the acknowledgment input ACK3; • A second p-type PMOS4 transistor whose drain is connected to the source of the first p-type PMOS3 transistor, the source of the second p-type PMOS4 transistor being connected to the VDD3 power supply and the gate of the second p-type PMOS4 transistor being connected to the REQ3 request input, • A second n-type transistor NM0S4 whose drain is connected to the source of the first n-type transistor NM0S3, the source of the second n-type transistor NM0S4 being connected to ground GnD3, and the gate of the second n-type transistor NM0S4 being connected to the request input REQ3.

[0080] Thus, the output OUT3 is at 1 if the request input REQ3 and the acknowledgment input ACK3 have the same logical value equal to 0, the output OUT3 being at 0 if the request input REQ3 and the acknowledgment input ACK3 have the same logical value equal to 1 (the reverse is possible as an alternative of course), the output OUT3 being in a high impedance state otherwise (that is, when the request input REQ3 and the acknowledgment input ACK3 have different logical values).

[0081] The logic gate CCELL2 is identical to the gate CCELL3 and functions in the same way as the gate CCELL3, with the request input REQ2, the acknowledgment input ACK2 and the output OUT2.

[0082] The logic gate CCELL4 is identical to the gate CCELL3 and works in the same way as the gate CCELL3, with its request input and acknowledgment input ACK4 and output OUT4.

[0083] Fig. 5 represents the DETECT2 detector which includes the logic gates CCELL2, CCELL3 and CCELL4 arranged in an asynchronous pipeline connected at the output OUT4 of cell CCELL4 to the input of the analysis unit oa2 by the bus BUS2.

[0084] Thus, by way of illustration, the request input REQ3 of the logic gate CCELL3 is the complement of the output OUT2 of the logic gate CCELL2, the acknowledgment input ACK2 of the logic gate CCELL2 being the output OUT3 of the logic gate CCELL3.

[0085] In this embodiment, the process [Fig.6] is adapted as follows.

[0086] Prior to step S00 below, the query input REQ2 is passed to a logical value of 1, so as to reset the asynchronous pipeline.

[0087] At step S00, the query input REQ2 was changed from a logical value of 1 to a logical value of 0, which has the effect of; - Set output OUT2 to 1 due to the acknowledgment input going to 0. - Then, at step S10, to put the output OUT2 into a high impedance state which is maintained for 1 microsecond, (following the setting of ACK2 to 1) for example by maintaining the request input REQ2 at 0.

[0088] At step S30, logic gate CCELL2 or an area near logic gate CCELL2 receives a laser flash.

[0089] At step S40, the request input REQ2 is always held at 0. As a result of the laser flash received at step S30, the logic gate CELL2 produces at output OUT2 a 0 for 10 nanoseconds, then a 1 as a result of the subsequent change of the logic value of ACK2 to 0, this sequence of 0s and 1s being then propagated to the analysis unit oa2 by the asynchronous pipeline via the logic gates CCELL3 and CCELL4 and via the bus BUS2.

[0090] At step S50, the analysis unit detects the 0 for 10 nanoseconds and then the 1, and consequently emits an alert message which triggers a countermeasure implemented by the integrated circuit ICI.

[0091] Such an analytical device oa2 is also within the reach of a person skilled in the art. It is not necessary to detail it here.

Claims

Demands

1. Integrated circuit (ICI) comprising a disturbance detector (DETECT1, DETECT2, DETECT3) of the integrated circuit (ICI), the disturbance detector (DETECT1, DETECT2) comprising an analyzer (OA1, OA2, OA3) and a set of at least one logic gate, each detection logic gate (TAMP1, TAMP1', CCELL2, CCELL3, CCELL4) of the set of at least one logic gate comprising a three-state output (0UT1, 0UT2, 0UT3, 0UT4), the three states comprising two low-impedance logic states and one high-impedance state, the two low-impedance logic states comprising a first state and a second state different from the first state, the high-impedance state comprising a first substate and a second substate different from the first substate, the analyzer being connected to the output (0UT1, 0UT2, 0UT3, 0UT4), each detection logic gate (TAMP1, CCELL2, CCELL3,CCELL4) of the set of at least one logic gate being configured to implement the following initial steps:, • First passage of the output (0UT1, 0UT2, 0UT3, 0UT4) through the first state, then • Transition of the output to the high impedance state, while the output is in the first state, then • Maintaining the output in a high-impedance state during a detection period, so that each detection logic gate (TAMP1, TAMP1', CCELL2, CCELL3, CCELL4) in the assembly memorizes the first substate, And the analytical unit is configured to implement the following second step: • Detection of a disturbance if the analysis unit detects that the output (0UT1, 0UT2, 0UT3, 0UT4) has passed into the second substate during the output holding stage.

2. Integrated circuit (ICI) according to the preceding claim in which the first and second steps are repeated.

3. Integrated circuit (ICI) according to claim 1 or 2 wherein a voltage of the output (OUT1, 0UT2, 0UT3, 0UT4) in the first state is greater than a voltage of the output (0UT1, 0UT2, 0UT3, 0UT4) in the second state.

4. Integrated circuit (ICI) according to any one of claims 1 to 3, the first steps comprising, following the transition of the output (0UT1, 0UT2, 0UT3, 0UT4) into the high impedance state, a second transition of the output into (0UT1, 0UT2, 0UT3, 0UT4) into the first state, the disturbance being detected, during the disturbance detection step, if the analysis element detects that the output (0UT1, 0UT2, 0UT3, 0UT4) passes into the second substate, before switching back into the first state, following the second transition.

5. Integrated circuit (ICI) according to any one of the preceding claims wherein, the set of at least one logic gate comprising a series of logic gates, the logic gates of the series of logic gates are connected in series to the analyzer element (o1, oa2, oa3).

6. Integrated circuit (ICI) according to any one of the preceding claims wherein, for each detection logic gate (TAMP1) of the assembly, the transition of the output into the high impedance state is controlled by an enable logic value received by an enable input (EN1) and said one of the two low impedance logic states is controlled by a control logic value received by a control input (INI) provided that the output is not in the high impedance state.

7. Integrated circuit (ICI) according to the preceding claim wherein each detection logic gate (TAMP1) reproduces at output (0UT1) the control logic value (INI) when the output (0UT1) is in one of the two low impedance logic states.

8. Integrated circuit (ICI) according to the preceding claim, wherein each detection logic gate (TAMP1) comprises: • A transistor bridge including a first p-type transistor (PM0S1) and a first n-type transistor (NM0S1) connected in series and connected at their drains by a midpoint defining the output (0UT1) of said each logic gate (TAMP1), the gate of the first n-type transistor (NM0S1) being connected to the enable input (EN1), and the gate of the first p-type transistor (PM0S1) being connected to the complementary side of the activation input (EN1), • - A second p-type transistor (PM0S2) whose drain is connected to the source of the first p-type transistor (PM0S1), the source of the second p-type transistor (PM0S2) being connected to the power supply (VDD), and the gate of the second p-type transistor (PM0S2) being connected to the complement of the control input (INI) of said each detection logic gate (TAMP1), • A second n-type transistor (NM0S2) whose drain is connected to the source of the first n-type transistor (NM0S1), the source of the second n-type transistor (NM0S2) being connected to ground (GnDl), and the gate of the second n-type transistor (NM0S2) being connected to the complement of the control input (INI) of said logic gate (TAMP1).

9. Integrated circuit (ICI) according to any one of claims 1 to 5, said each logic detection gate (CCELL2, CCELL3, CCELL4) of the assembly comprising a request input (REQ2, REQ3) and an acknowledgment input (ACK2, ACK3, ACK4), the output (0UT2, 0UT3, 0UT4) being in the first state if the request input (REQ2, REQ3) and the acknowledgment input (ACK2, ACK3, ACK4) have the same logic value equal to 0, the output (OUT2, OUT3, OUT4) being in the second state if the request input (REQ2, REQ3) and the acknowledgment input (ACK2, ACK3, ACK4) have the same logic value equal to 1, the output (OUT2, OUT3, OUT4) being in a high impedance state otherwise.

10. Integrated circuit (ICI) according to the preceding claim, wherein each detection logic gate (CCELL3) of the assembly comprises: • A transistor bridge comprising a first p-type transistor (PMOS3) and a first n-type transistor (NMOS3) connected in series and linked at their drains by a midpoint defining the output (OUT3) of said logic gate (CCELL3), the gate of the first transistor

11.

12. of type n (NM0S3) and the gate of the first type p transistor (PM0S3) being connected to the acknowledgment input (ACK3); • A second p-type transistor (PM0S4) whose drain is connected to the source of the first p-type transistor (PM0S3), the source of the second p-type transistor (PM0S4) being connected to the power supply (VDD3), and the gate of the second p-type transistor (PM0S4) being connected to the request input (REQ3), • A second n-type transistor (NM0S4) whose drain is connected to the source of the first n-type transistor (NM0S3), the source of the second n-type transistor (NM0S4) being connected to ground (GnD3), and the gate of the second n-type transistor (NM0S4) being connected to the request input (REQ3). - Integrated circuit (ICI) according to claim 9 or 10, the set of at least one detection logic gate comprising a series of logic gates, the request input (REQ3) of a first logic gate (CCELL3) of the series of logic gates being the complement of the output (OUT2) of a second logic gate (CCELL2) preceding the first logic gate (CCELL3) in the series of logic gates, the acknowledgment input (ACK2) of the second logic gate (CCELL2) being the output (OUT3) of the first logic gate (CCELL3), the output (OUT4) and the acknowledgment input (ACK4) of the last logic gate of the series of logic gates being connected to the analyzer element (oa2).Method for detecting a disturbance in an integrated circuit (ICI), implemented by a disturbance detector (DETECT1, DETECT2) of the integrated circuit (ICI), the disturbance detector (DETECT1, DETECT2) comprising an analysis element (oal, oa2) and a set of at least one logic gate, each detection logic gate (TAMP1, CCELL2, CCELL3, CCELL4) of the set of at least one logic gate comprising a three-state output (OUT1, OUT2, OUT3, OUT4), the three states comprising two low-impedance logic states and one high-impedance state, the two low-impedance logic states comprising a first state and a second state different from the first state, the high-impedance state. comprising a first substate and a second substate different from the first substate, the analysis element being connected to the output (0UT1, 0UT2, 0UT3, 0UT4), the process being characterized in that it comprises: • The following initial steps, implemented by each detection logic gate (TAMP1, CCELL2, CCELL3, CCELL4) of the assembly: • First passage of the output (0UT1, 0UT2, 0UT3, 0UT4) through the first state, then • Transition of output (0UT1, 0UT2, 0UT3, 0UT4) into the high impedance state, while output (0UT1, 0UT2, 0UT3, 0UT4) is in the first state, then • Maintaining the output (0UT1, 0UT2, 0UT3, 0UT4) in the high impedance state during a detection period, so that each detection logic gate (TAMP1, TAMP1', CCELL2, CCELL3, CCELL4) of the assembly memorizes the first substate, • One, a second, next step: • Detection of a disturbance if the analysis unit detects that the output (0UT1, 0UT2, 0UT3, 0UT4) has passed into the second substate during the output holding stage.

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