IMPROVED STACK STRUCTURE FOR RETAINING HIGHLY (HRS) AND LOWLY (LRS) RESISTANT STATES OF AN OXIDE-BASED RANDOM ACCESS MEMORY (OxRAM)

Abstract

Resistive stack (Stck) for a random-access resistive memory cell, the resistive stack comprising: a first electrode (El1); a second electrode (El2); a dielectric layer (Diel) interposed between the first electrode (El1) and the second electrode (El2), the dielectric layer comprising: a first dielectric layer (Diel1) formed of an oxide of a first transition metal; a second dielectric layer (Diel2) formed of an oxide of a second transition metal; and a diffusion barrier layer (DiffBar) interposed between the first dielectric layer (Diel1) and the second dielectric layer (Diel2), and formed of a material having a barrier property against oxygen vacancies that is superior to the barrier properties against oxygen vacancies of the oxide of the first transition metal and the oxide of the second transition metal. Fig. 4

Description

Title of the invention: IMPROVED STACK STRUCTURE FOR RETAINING HIGH (HRS) AND LOW (LRS) RESISTANT STATES OF AN OXIDE-BASED RANDOM ACCESS MEMORY (OxRAM) FIELD OF INVENTION

[0001] The technical field of the invention is that of resistive random access memory, or Resistive Random Access Memory (ReRAM), each of which comprises an element whose resistive state defines a bit of information. More specifically, the invention relates to the structure of the material stack forming the active part of an oxide-based ReRAM, also called OxRAM. CONTEXT OF THE INVENTION

[0002] Non-volatile memory (NVM) is a type of computer memory capable of retaining information even when its power supply is turned off. Examples of non-volatile memories include read-only memories (ROM), erasable read-only memories (EPROM), flash memories, ferroelectric random-access memories (FRAM), magnetoresistive random-access memories (MRAM), phase-change memories (PCM), and resistive random-access memories (ReRAM).

[0003] This latter type of memory, ReRAM, is typically formed by a stacking matrix Stck of a Diel layer made of a solid-state dielectric material and two electrodes Eli and E12 between which the Diel layer is interposed, as illustrated in [Fig. 1]. Such a structure constitutes a binary memory element and typically functions by modifying the electrical resistance of the Diel layer. The solid-state dielectric material can be, for example, a chalcogenide, a perovskite, or an oxide of a transition metal such as hafnium oxide (HfOx). A memory is formed from an array of such memory elements, each forming the core of a bit cell. The present application relates to a ReRAM using transition metal oxides to form the solid-state dielectric material, i.e., to form an OxRAM.

[0004] Fig. 1 illustrates the operation of an OxRAM memory element, consisting of a Stck stack comprising a pair of electrodes Eli and E12 between which is interposed an active dielectric layer Diel.

[0005] During a Set write operation, the application of a writing current and a writing voltage Vset, along with an associated electric field in a first direction between the two electrodes Eli and E12, can lead to the formation of an electrically conductive filament Fil in the otherwise electrically resistive Diel layer, due to the formation and diffusion of oxygen ion pairs Oxy and oxygen vacancies VOxy within the volume of the Diel dielectric layer. The binary element is then placed in a low resistance state (LRS). The higher the writing current, the thicker the filament and the lower the resistance of the binary element.

[0006] Conversely, during a Reset operation, a reset electrical current flowing between the two electrodes Eli and E12 in a second direction, opposite to the first direction, and likewise applying a voltage Vreset opposite to Vset between the two electrodes, can dissolve the electrically conductive filament Fil created during the Set write operation, thus increasing the electrical resistance of the binary element. The binary element is then placed in a high resistance state or HRS.

[0007] Each of the LRS and HRS states can be associated with a bit value in a digital memory. During a read operation, a read voltage Vread is applied between the electrodes, and a read current is measured. The read current is lower than the write and reset currents and flows between the two electrodes. Measuring the read current allows the resistive state of the binary element, and therefore the associated binary value, to be evaluated.

[0008] Here, electrode Eli is inert, insofar as it does not play an active role in the structure, but passively transports electrons. In contrast, electrode E12 is active, acting as an oxygen reservoir that can capture oxygen ions from the dielectric layer during writing operations and release oxygen ions from the dielectric layer during resetting operations.

[0009] The filament formation and dissolution processes and its final configuration, which determines the resistance of the memory element in the LRS, are stochastic in nature. In other words, the characteristics of the bit cells vary over ranges. In this context, [Fig. 2] illustrates the resistances of a collection of bit cells from the same matrix.

[0010] Figures 2(A) and (B) illustrate the probability Pr for each bit cell of a matrix of taking a given resistance value R(Q), in an ideal case and in a more realistic case, respectively. In the ideal case, only two values ​​are possible: a first unique value for the resistance of the low resistance state LRS and a second unique value for the resistance of the high resistance state HRS.

[0011] In the ideal model, only these two states are accessible to the bit cells and each has a unique and well-defined resistance value. However, in practice, the resistance values ​​extend over ranges which can each be described as a probability density having the form of a peak centered on a given value (Ro.lrs and Rq hrs for the two states LRS and HRS, respectively) and having a standard deviation 0 (similar distributions for LRS and HRS in this example, for the sake of simplicity of explanation), as illustrated by [Fig.2](B).

[0012] As illustrated in [Fig.2](B), the two states LRS and HRS can in fact be close to each other. The distributions of these two states can even overlap, which complicates the control of the memory cell's state. In particular, a problem of information retention arises in a memory: over time, the state (LRS or HRS) of a given binary element can gradually move away from the one that was initially written (by writing or resetting), and can become difficult to determine during a read operation: does the measured resistance value correspond to an LRS state or an HRS state?

[0013] Retention problems are known to be related to the migration of oxygen ions and oxygen vacancies in the dielectric layer, as well as to the release of trapped oxygen ions from the active electrode to the dielectric layer. Indeed, the state of a binary element is determined by the presence of oxygen vacancies in the dielectric layer and their positioning: do they form a conductive filament or not? The migration of oxygen vacancies (VOxy) can dissolve a filament formed by a write operation, thus creating a low-resistance state conservation problem. Conversely, the migration of oxygen ions (Oxy) can rebuild a filament dissolved by a reset operation, thus creating a high-resistance state conservation problem. The oxygen ions can originate from the electrode (Eli). These phenomena are exacerbated by temperature.

[0014] It is therefore necessary to improve the retention characteristics of OxRAM memories, particularly for high-temperature applications. SUBJECT OF THE INVENTION

[0015] In the context described above, the inventors propose a memory element structure capable of limiting the occurrence of an undesirable reformation of the filament, and which thus provides better retention characteristics to a memory based on such a memory element, in particular HRS retention. Summary of the invention

[0016] To this end, a first aspect of the invention relates to a resistive stack for a random-access resistive memory cell, the resistive stack comprising: a first electrode; a second electrode; an interposed dielectric layer between the first electrode and the second electrode, the dielectric layer comprises: a first dielectric layer formed of an oxide of a first transition metal; a second dielectric layer formed of an oxide of a second transition metal; and a diffusion barrier layer interposed between the first dielectric layer and the second dielectric layer, and formed of a material having a barrier property with respect to oxygen vacancies, which is superior to the barrier properties with respect to oxygen vacancies of the oxide of the first transition metal and the oxide of the second transition metal.

[0017] The diffusion barrier interposed between the two dielectric layers prevents the reformation of a dissolved filament by blocking oxygen vacancies, which provides a first advantage in terms of stack stability, and therefore in terms of retention capacity for a memory using this stack as a memory element.

[0018] The second advantage is that the diffusion barrier layer widens the resistance gap between the LRS and the HRS, which makes it easier to distinguish between the LRS and the HRS of the memory.

[0019] According to other non-limiting features of the first aspect of the invention, whether taken in isolation or in any technically possible combination:

[0020] - the first electrode can be an inert electrode and the second electrode can be an active electrode, capable of trapping oxygen ions from the dielectric layer;

[0021] - the second dielectric layer may have a migration energy greater than the migration energy of the first dielectric layer;

[0022] - the second dielectric layer can have a thickness between 20% and 60% of the combined thicknesses of the first dielectric layer, the diffusion barrier and the second dielectric layer;

[0023] - the first dielectric layer can be formed from hafnium oxide;

[0024] - the first dielectric layer can have a thickness between 1 and 4 nm, preferably between 2 and 3 nm;

[0025] - the second dielectric layer can be formed from zirconium oxide;

[0026] - the second dielectric layer can have a thickness between 1 and 4 nm, preferably between 2 and 3 nm;

[0027] - the diffusion barrier layer can be made of aluminium oxide;

[0028] - the diffusion barrier layer can consist of C, SiO2, Si, TaSiN, TaCN or TiSiN;

[0029] - the diffusion barrier layer can have a thickness between 0.2 and 2 nm, preferably between 0.4 and 1 nm;

[0030] - at least the first dielectric layer and the second dielectric layer can be doped with a trivalent element at an atomic concentration between 1% and 15%;

[0031] - the trivalent element can be chosen from Ti, Al and La;

[0032] - at least the first dielectric layer and the second dielectric layer can each be doped with silicon at an atomic concentration between 1% and 15%, preferably between 2% and 6%; and

[0033] - the dielectric layer may further comprise a second diffusion barrier interposed between the second dielectric layer and the second electrode.

[0034] The invention extends to a memory device comprising a bit cell matrix, each cell comprising the stacking according to the first aspect of the invention as a variable resistor, and to an integrated system comprising the memory device in communication with a microprocessor. Brief description of the drawings

[0035] Many other features and advantages of the present invention will become apparent from the following detailed description, considered together with the accompanying drawings, in which:

[0036] [Fig-1] - The [Fig.1] illustrates the operating principle of an OxRAM;

[0037] [Fig.2] - Fig.2 illustrates the distribution of resistivities of the bit cells of a resistive memory;

[0038] [Fig.3] - Fig.3 illustrates a mechanism leading to the absence of state retention high resistivity of an OxRAM memory element;

[0039] [Fig.4] - Fig.4 illustrates a memory element that solves the problem illustrated by the [Fig.3];

[0040] [Fig.5] - Fig.5 presents graphs comparing retention performance memory elements illustrated by figures 3 and 4;

[0041] [Fig.6] - Fig.6 represents a diagram of a manufacturing process of the memory element illustrated by [Fig.4];

[0042] [Fig.7] - Fig.7 illustrates variants of the memory element illustrated by the [Fig.4];

[0043] [Fig.8] - Figure [Fig.8] illustrates an OxRAM memory matrix incorporating the element of memory illustrated by [Fig. 4]; and

[0044] [Fig.9] - Fig.9 illustrates an embedded system incorporating the memory matrix OxRAM illustrated by [Fig.8].

[0045] DETAILED DESCRIPTION OF A FIRST EMBODIMENT OF THE INVENTION

[0046] An embodiment of the invention will be described below, with reference to Figures 1 to 9.

[0047] Figure 3 illustrates a stack of stacks forming a memory element of an OxRAM. The stack comprises a first inert electrode Eli and a second active electrode E12 capable of trapping oxygen ions, with a layer The Diel dielectric layer is interposed between the two electrodes. The Diel dielectric layer comprises a first dielectric layer, Diell, formed from an oxide of a first transition metal located on the side of the first electrode, and a second dielectric layer, Diel2, formed from an oxide of a second transition metal located on the side of the second electrode, which has a higher migration energy than the first metal oxide. The first electrode, Eli, can be an inert titanium nitride (TiN) electrode. The first Diell layer and the second Diel2 layer of the Diel dielectric layer can be composed of a hafnium oxide dielectric (HfO2) and a zirconium oxide dielectric (ZrO2), respectively. The second electrode, E12, can be composed of an oxygen-trapping titanium (Ti) layer.

[0048] OxRAM memory cells employing such a structure have been studied by the applicant of this application. It has been found that they exhibit insufficient retention, particularly of the high resistivity state (HRS). The HRS state is obtained by dissolving a filament Fil composed of oxygen vacancies VOxy. The hypothesis was then put forward that a filament dissolved after a reset operation could reform due to the mobility of the oxygen vacancies within the HfO2 layer, the ZrO2 layer sufficiently immobilizing them due to its high migration energy. This situation is illustrated in [Fig. 3], the arrows symbolizing the migration of the oxygen vacancies VOxy tending to reform a dissolved filament DisFil in the second dielectric layer Diel2.

[0049] As a countermeasure, the applicant proposed interposing a diffusion barrier between the two dielectric layers Diell and Diel2, with the aim of preventing oxygen vacancies from diffusing and reforming the dissolved filament, and thus improving the retention capacity of the memory element.

[0050] Figure 4 illustrates the general structure of an OxRAM stack according to the invention, which differs from the structure illustrated in Figure 3 solely by the presence of the DiffBar diffusion barrier layer interposed between the two dielectric layers Diell and Diel2. Advantageously, the diffusion barrier layer prevents the reformation of the dissolved filament by blocking oxygen vacancies. The effectiveness of this structure was confirmed by comparing the retention of the structures illustrated in Figures 3 and 4, respectively, with an aluminum oxide diffusion barrier layer.

[0051] Fig. 5 shows in (A) and (B) two graphs illustrating measurement results for OxRAM memories based on memory cells using identical structures, except for the presence of a DiffBar diffusion barrier layer made of aluminum oxide A12O3 between the HfO2 and ZrO2 layers for the test graph (B) while this diffusion barrier layer is absent for the reference graph (A).

[0052] The graphs represent the distribution of memory cells as a function of their respective resistances for the LRS and HRS states. The graphs have a common X-axis expressing the resistance R of a memory cell in ohms and Y-axes expressing the cumulative probability Cum.Pr of having a given resistance, arranged to easily visualize the proximity of the HRS and LRS states, i.e. the proportions of LRS and HRS states that are close to each other and can lead to loss of retention and errors during read operations.

[0053] Graphs (A) and (B) show the two sets of results. The first set, labeled Init, corresponds to the resistance of the memory cells immediately after the write or reset operations that define their LRS and HRS states. A second set, labeled Init+210°C / 2h, shows the resistance of the same memory cells after the write or reset operations and an additional heat treatment at 210°C for 2 hours. The heat treatment tests the memory cells' ability to retain information, that is, the LRS and HRS states stored within them.

[0054] As shown in the reference graph (A), memory cells based on an HfO2 / ZrO2 structure, without an A12O3 diffusion barrier, exhibit a significant Sh shift (as indicated by an arrow) from their HRS states to the LRS states after heat treatment, drastically reducing the resistance gap ARef separating the HRS and LRS states for cumulative probabilities of 10⁴.

[0055] On the other hand, as shown in Figure (B), memory cells based on an HfO / Al2O2 / ZrO2 structure, comprising an A12O3 diffusion barrier layer, exhibit a reduced shift from HRS states to LRS states, drastically limiting the reduction of the Alnv resistance gap separating the HRS and LRS states for cumulative probabilities of 10⁴. It should also be noted that the resistance gap is initially (before heat treatment) larger.

[0056] The introduction of the DiffBar diffusion barrier between the dielectric layers Diell and Diel2 appears advantageous in two respects. First, the HRS states appear more stable, which is positive for the retention capacity of OxRAM memories. Second, it is easier to distinguish the LRS and HRS states of the memory.

[0057] Additional features of the Stck stack according to the invention and illustrated by [Fig.4] are explained below, with the help of [Fig.6] which illustrates a method 100 of manufacturing the Stck stack comprising the successive steps SI 10 to S160.

[0058] In this description, it must be understood that when a layer is formed from a given material, this layer comprises that material at an atomic concentration of more than 50%.

[0059] In the first SI step 10, the first electrode Eli is, for example, formed on a base substrate (not shown in the figures) by sputtering in a vacuum deposition chamber, preferably having a thickness of 5 nm or more. Preferably, the first electrode is chemically inert in the stack and does not react with oxygen ions or mobile oxygen vacancies in the dielectric layers. In the present embodiment, the first electrode Eli can be formed from titanium nitride (TiN) by reactive sputtering. The first electrode can also be formed by chemical vapor deposition.

[0060] At step S120, the first dielectric layer Diell is formed on the first electrode Eli.

[0061] In the present embodiment, the Diell dielectric layer is a hafnium oxide dielectric layer such as HfO2, with a thickness between 1 and 4 nm, preferably between 2 and 3 nm, typically 2 nm. A Diell layer that is too thin leads to an excessively small read margin, while a Diell layer that is too thick can degrade the switching between the LRS and HRS states and generate resistance tails.

[0062] At step S130, the diffusion barrier layer is formed on the first dielectric layer Diell.

[0063] In the present embodiment, the DiffBar diffusion barrier layer is a dielectric layer of aluminum oxide such as Al₂O₃, with a thickness between 0.2 and 2 nm, preferably between 0.4 and 1 nm. The appropriate thickness is chosen so that the layer is thin enough not to introduce excessive electrical resistance into the stack, and thick enough to adequately perform its function. The active material layer can be deposited by sputtering, physical vapor deposition (PVD), or ion beam deposition (IBD), for example.

[0064] The invention is not limited to aluminum oxide, as other materials fulfilling the same function of blocking VOxy oxygen vacancies can be used instead, such as C, SiO2, Si, TaSiN, TaCN, or TiSiN, for example. In any case, the material chosen to form the DiffBar layer exhibits a barrier property with respect to oxygen vacancies that is superior to the barrier properties of the Diell and Diel2 layers.

[0065] At step S140, the second dielectric layer Diel2 is formed on the diffusion barrier layer DiffBar.

[0066] In the present embodiment, the dielectric layer Diel2 is a zirconium oxide dielectric layer such as ZrO2, with a thickness between 1 and 4 nm, preferably between 2 and 3 nm. The dielectric layer Diel2 preferably has The thickness should be between 20% and 60% of the combined thickness of the Diell, DiffBar, and Diel2 layers. A Diel2 layer that is too thick can degrade switching between LRS and HRS states and generate resistance tails. If the Diel2 layer is too thin, the combined Diel2 and DiffBar structure does not provide a significant retention gain for the ReRAM.

[0067] In this embodiment, the Diell, DiffBar, and Diel2 layers are preferably deposited so as to have substantially constant thicknesses at every point. In this description, "substantially constant thickness" means a thickness that does not vary by more than 20%, preferably by more than 10%, and even more preferably by more than 5%.

[0068] With regard to the formation method, in this embodiment, the Diell, DiffBar and Diel2 layers are deposited by an atomic layer deposition (ALD) method. Alternatively, these layers can be deposited by sputtering, physical vapor deposition (PVD), or ion beam deposition (IBD), independently, for example.

[0069] Figure 7(A) illustrates a variant of the structure of Figure 4. This structure is the same as that of Figure 4, except that the dielectric layer Diel includes an additional diffusion barrier layer DiffBar' interposed between the second dielectric layer Diel2 and the second electrode E12. The Diel3 layer is formed of a semiconductor, preferably Si, or a semiconductor oxide or a metal oxide, preferably silicon dioxide SiO2 or aluminum oxide Al12O3. The DiffBar' layer serves to provide an additional barrier between electrode E12 and the other layers forming Diel. Its function is to help establish equilibrium in the movement of oxygen ions to allow for a reset operation while improving the retention of LRS states.

[0070] In step S150, as a first alternative, the layers forming the Diel dielectric layer are doped with a trivalent element by ion implantation in at least the first dielectric layer Diell and the second dielectric layer Diel2, so as to control the migration energy of oxygen and oxygen vacancies. The trivalent dopant can be Ti, Al, La, or similar. As a second alternative, in order to create defects in the dielectric layers, silicon, argon, or nitrogen can be implanted. These defects are intended to promote the movement of oxygen vacancies and facilitate switching between the LRS and HRS states. An excessively high concentration of silicon can degrade the resistance margin.

[0071] In both cases, direct implantation can take place by implanting the selected dopant element, for example, at a doping energy between 1.5 keV and 3.5 keV, typically 3 keV, and at a dose between 1.1015 and 5.1015 atoms / cm, preferably between 2.10 and 3.10 atoms / cm, typically 2.10 atoms / cm. The dopant element represents between 1% and 15%, preferably between 2% and 7%, of the atoms present in the layers forming the Diel layer. Too high a concentration of defects can degrade the retention of LRS states by ReRAM.

[0072] Other methods can also be used without departing from the scope of the disclosed embodiments. For example, doping can be carried out during layer formation.

[0073] In step S160, the second electrode E12 is formed on the second dielectric layer Diel2, for example, formed by sputtering in a vacuum deposition chamber to have a thickness of approximately 5 nm. The second electrode can be an oxygen-trapping layer, which participates in the formation and retention of a conductive filament made up of oxygen vacancies during a writing operation, by capturing and neutralizing oxygen species, preventing them from recombining with the oxygen vacancies of the filament and thus dissolving the filament. In the present embodiment, the second electrode E12 is preferably made of titanium (Ti), but it could also be made of another transition metal, and could, for example, be made of TaN, Hf, or Ta. As an alternative to sputtering, the first electrode can be formed by chemical vapor deposition or by ion beam deposition.

[0074] A variant of the second electrode E12 of [Fig. 4] is illustrated in [Fig. 7](B). This Stck structure is the same as that of [Fig. 4], except that the second electrode E12 has a composite structure, comprising a first electrode layer E12a on the side of the second dielectric layer Diel2 and a second electrode layer E12b on the opposite side. The first electrode layer E12a is preferably an oxygen-trapping layer in direct contact with the second dielectric layer and can be made of Ti, Hf, or Ta, with a thickness between 3 nm and 20 nm, for example. The second electrode layer E12b is made of a conductive material comprising a transition metal and serves to prevent complete oxidation of the first electrode layer E12a and to allow electrical contact to be established with the electrode E12. E12b can be formed from TiN, TaN or W, for example.

[0075] After the stacking is complete, and before its regular use as a binary element of an OxRAM memory, the stack undergoes a "training" initialization step, which consists of forming an initial filament. The voltage used to train this initial filament is higher than the setpoint voltage Vset. The initialization step occurs only once during the lifetime of each bit cell in the memory.

[0076] In this description, two directly adjacent layers are in direct physical contact with each other, unless otherwise indicated.

[0077] The Stck stack described above can constitute the active elements of an OxRAM MEM memory. Write, reset, and read operations can be applied to bit cells integrated into an ARR matrix, each bit cell comprising a Stck stack. Figure 8 illustrates a basic conventional structure of a resistive MEM memory. Such a memory is described, for example, in US patent 11735260B2.

[0078] Typically, as illustrated in [Fig.8](C), each bit cell BC of the ARR matrix comprises (i) a stack-up Stck which forms a variable resistance VarR (see [Fig.8](B)) and fulfills the function of binary memory element for each bit cell, and (ii) a SelTr selection transistor having a source and a drain connected in series with the variable resistance.

[0079] An ARR bit cell matrix generally comprises columns and rows of bit cells, as illustrated in [Fig. 1](A). Each column comprises (i) a bit line BL connected to a source and drain of the SelTr transistor through the variable resistor VarR for each of the bit cells in the column, and (ii) a source line SL connected to the bit line BL through the source and drain of the SelTr transistor and the variable resistor VarR. Each row of bit cells comprises a word line WL connected to the gate of the SelTr selector transistor for each of the bit cells in the row. The bit lines BL and the source lines SL are each connected to and controlled by a column multiplexer circuit SL / BL-Mux. The word lines WL are each connected to and controlled by a line driver circuit WL-Drv.

[0080] Figure 9 illustrates an EmbSys embedded system integrating OxRAM in communication with a CPU microprocessor. Such a system can be a portable semiconductor device configured to process digital data. Generally speaking, any embedded device conventionally using flash memory can use resistive memory instead. OxRAM can benefit from the improved retention capacity of the Stck stacking described above, making it particularly suitable for high-temperature applications such as transportation applications.

[0081] Other variants of the disclosed embodiments can be understood and carried out by persons competent in the practice of the claimed invention, from the study of the drawings, the disclosure and the attached claims.

Claims

Demands

1. Resistive stack (Stck) for a resistive random access memory (ReRAM) cell, the resistive stack comprising: - a first electrode (Eli); - a second electrode (E12); - a dielectric layer (Diel) interposed between the first electrode (Eli) and the second electrode (E12), the dielectric layer comprising: - a first dielectric layer (Diell) formed of an oxide of a first transition metal; - a second dielectric layer (Diel2) formed of an oxide of a second transition metal; and - a diffusion barrier layer (DiffBar) interposed between the first dielectric layer (Diell) and the second dielectric layer (Diel2), and formed of a material having a barrier property with respect to oxygen vacancies, which is superior to the barrier properties with respect to oxygen vacancies of the oxide of the first transition metal and the oxide of the second transition metal.

2. Resistive stack according to claim 1, wherein the first electrode (Eli) is an inert electrode and the second electrode (E12) is an active electrode, capable of trapping oxygen ions from the dielectric layer (Diel).

3. Resistive stack according to claim 1 or claim 2, wherein the second dielectric layer (Diel2) has a migration energy greater than the migration energy of the first dielectric layer (Diell).

4. Resistive stack according to any one of claims 1 to 3, wherein the second dielectric layer (Diel2) has a thickness between 20% and 60% of the combined thicknesses of the first dielectric layer (Diell), the diffusion barrier (DiffBar) and the second dielectric layer (Diel2).

5. Resistive stack according to any one of claims 1 to 4, wherein the first dielectric layer (Diell) is formed of hafnium oxide.

6. Resistive stack (Stck) according to claim 5, wherein the first dielectric layer (Diell) has a thickness between 1 and 4 nm, preferably between 2 and 3 nm.

7. Resistive stack according to any one of claims 1 to 6, wherein the second dielectric layer (Diel2) is formed of zirconium oxide.

8. Resistive stack (Stck) according to claim 7, wherein the second dielectric layer (Diel2) has a thickness between 1 and 4 nm, preferably between 2 and 3 nm.

9. Resistive stacking according to any one of claims 1 to 8, wherein the diffusion barrier layer (DiffBar) is formed of aluminum oxide.

10. Resistive stack according to any one of claims 1 to 8, wherein the diffusion barrier layer (DiffBar) is formed of C, SiO2, Si, TaSiN, TaCN or TiSiN.

11. 1 Resistive stack (Stck) according to any one of claims 1 to 10, wherein the diffusion barrier layer (DiffBar) has a thickness between 0.2 and 2 nm, preferably between 0.4 and 1 nm.

12. 12. Resistive stacking according to any one of claims 1 to 11, wherein at least the first dielectric layer (Diell) and the second dielectric layer (Diel2) are doped with a trivalent element at an atomic concentration of between 1% and 15%.

13. 13. Resistive stacking (Stck) according to claim 12, wherein the trivalent element is chosen from Ti, Al and La.

14. 4Resistive stacking according to any one of claims 1 to 13, wherein at least the first dielectric layer (Diell) and the second dielectric layer (Diel2) are each doped with silicon at an atomic concentration of between 1% and 15%, preferably between 2% and 6%.

15. Resistive stack according to any one of claims 1 to 14, wherein the dielectric layer further comprises a second diffusion barrier layer (DiffBar') interposed between the second dielectric layer (Diel2) and the second electrode (E12).

16. 6Memory device (MEM) comprising an array (ARR) of bit cells (BC) each comprising the stack (Stck) according to any one of claims 1 to 15 as a variable resistor (VarR).

17. 17. Embedded system (EmbSys) comprising the device for memory (MEM) according to claim 16 in communication with a microprocessor (CPU).