INTERMEDIATE SUBSTRATE FOR THE FABRICATION OF A SUBSTRATE FOR A HIGH ELECTRON MOBILITY TRANSISTOR

Abstract

The present invention relates to an intermediate substrate (100) for the fabrication of a high electron mobility transistor (HEMT), comprising: a support substrate (10) made of polycrystalline silicon carbide having an electrical resistivity between 1 Ω.cm and 10 kΩ.cm, and a seed layer (20) made of monocrystalline GaN, said intermediate substrate (100) comprising a direct bonding interface (15) between the silicon carbide of the support substrate (10) and the seed layer (20). Figure for the abstract: Fig. 2

Description

Title of the invention: INTERMEDIATE SUBSTRATE FOR THE MANUFACTURE OF A SUBSTRATE FOR A HIGH ELECTRON MOBILITY TRANSISTOR FIELD OF INVENTION

[0001] The present invention relates to an intermediate substrate for the fabrication of a high electron mobility transistor and a transistor fabricated from such an intermediate substrate. The invention also relates to a method for the fabrication of an intermediate substrate and a high electron mobility transistor. STATE OF THE ART

[0002] High electron mobility transistors (HEMTs) are power transistors based on a type IILV semiconductor, particularly gallium nitride (GaN). Since bulk gallium nitride substrates do not exist, HEMTs are typically fabricated on a GaN layer deposited by epitaxy on a silicon substrate. A known HEMT transistor is described, for example, in document EP2983195 AL

[0003] Silicon exhibits different structural and mechanical properties than GaN, particularly in terms of its crystal lattice and coefficient of thermal expansion. This results in a significant accumulation of stress in GaN, which increases as the thickness of the GaN layer increases. To compensate for these differences, intermediate layers are added between the silicon substrate and the GaN layers. These intermediate layers typically comprise aluminum nitride (AIN) and gallium aluminum nitride (AlGaN). However, these intermediate layers exhibit significant electrical and thermal conductivity, which negatively impacts the operation of the HEMT transistor.

[0004] Figure 1 schematically illustrates a known HEMT. The HEMT comprises, from its base to its surface, a silicon substrate 11 having a plurality of intermediate layers 21, a GaN buffer layer 31, a GaN channel 41, and an AlGaN barrier layer 51. The channel and the barrier layer form a heterojunction allowing the formation of a two-dimensional electron gas confined within the channel. The source electrode 61 and drain electrode 62 are formed on the channel 41. The gate electrode 63 is arranged on the barrier layer 51.

[0005] The blocking voltage of the HEMT depends on the total thickness of the layers arranged between the substrate 11 and the barrier layer 51, i.e., the sum of the thicknesses of the intermediate layers 21, the buffer layer 31, and the channel 4L. To obtain For a HEMT with a high blocking voltage, a very thick GaN buffer layer would be necessary. For example, fabricating a HEMT with a known geometry and a blocking voltage greater than or equal to 1200 V would require a GaN layer approximately 8 pm thick in total, including a possible seed layer and / or intermediate layers21 for thermomechanical adaptation. The thickness of the GaN layer is limited by the difference in coefficient of thermal expansion between silicon and GaN despite the intermediate layers, and deposition of a GaN layer thicker than 8 pm would lead to substrate failure.

[0006] The blocking voltage also depends on the distance LGD between the gate electrode 63 and the drain electrode 62. Another solution to increase the blocking voltage would therefore be to considerably increase the distance LGD between the gate electrode 63 and the drain electrode 62. However, the distance between the gate electrode and the drain electrode is limited by the dimensions of the transistor.

[0007] It is not currently possible to obtain a HEMT exhibiting a blocking voltage of approximately 1200 V from such a structure. Description of the invention

[0008] An object of the invention is to make available a substrate for the manufacture of a gallium nitride-based HEMT having a high blocking voltage, in particular greater than 1200 V.

[0009] To this end, the invention proposes an intermediate substrate for the fabrication of a high electron mobility transistor, comprising: • a polycrystalline silicon carbide substrate with an electrical resistivity between 1 Q.cm and 10 kQ.cm, and • a single-crystal GaN seed layer,

[0010] said intermediate substrate comprising a direct bonding interface between the silicon carbide of the support substrate and the seed layer.

[0011] Silicon carbide has very good thermal conductivity, allowing for limiting heating during transistor operation.

[0012] Moreover, polycrystalline SiC has a coefficient of thermal expansion close to that of gallium nitride, allowing the deposition of a GaN layer up to 10 pm thick while minimizing the risk of substrate failure.

[0013] The band gap of polycrystalline SiC makes it possible to fabricate a HEMT with a particularly high blocking voltage relative to its dimensions. In particular, a HEMT with a high blocking voltage can be fabricated with a polycrystalline SiC support substrate having a relatively low electrical resistivity.

[0014] Furthermore, it is possible to obtain a high blocking voltage with a buffer layer thickness lower than the thickness of buffer layers applied on silicon substrates.

[0015] Preferably, the support substrate has a thickness of between 300 and 500 pm.

[0016] Advantageously, the germ layer has a thickness between 10 nm and 1 pm.

[0017] Advantageously, the direct bonding interface is a bonding layer arranged between the support substrate and the seed layer.

[0018] The invention also relates to a substrate for a high electron mobility transistor, said substrate comprising, from its base to its surface: • an intermediate substrate as described above, • a first epitaxial layer of single-crystal GaN or single-crystal AlGaN, the first epitaxial layer and the seed layer together forming a buffer layer of single-crystal GaN or single-crystal AlGaN, • a second unintentionally doped epitaxial layer of GaN configured to form a channel of the transistor.

[0019] Preferably, the buffer layer has a thickness between 3.5 and 5.5 pm.

[0020] The buffer layer can be made of carbon-doped GaN or of unintentionally doped GaN.

[0021] The invention also relates to a high electron mobility transistor, comprising • an intermediate substrate as described above, • a first epitaxial layer of single-crystal GaN or single-crystal AlGaN, the first epitaxial layer and the seed layer together forming a buffer layer, • a GaN channel arranged on the buffer layer, • a barrier layer forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel, • a source electrode and a drain electrode electrically connected to the channel, • a grid electrode formed on the barrier layer so that the grid electrode is physically isolated from the channel.

[0022] The barrier layer can be made of Alo.25Gao.75N.

[0023] The invention also relates to a method for manufacturing an intermediate substrate as described above, said method comprising the following steps: • the formation of a weakening zone by the implantation of ionic species in a single-crystal GaN donor substrate, • the bonding of said donor substrate onto a polycrystalline silicon carbide support substrate, so as to form a direct bonding interface between the support substrate and the donor substrate, • the detachment of the donor substrate along the embrittlement zone so as to transfer a seed layer of single-crystal GaN onto the support substrate.

[0024] The gate-drain distance guarantees a blocking voltage of 1200 V, without having to increase the surface area of ​​the transistor.

[0025] In some embodiments, the bonding step includes the deposition of a bonding layer on the support substrate and / or on the donor substrate.

[0026] In other embodiments, the donor substrate is glued onto the support substrate without the addition of any material.

[0027] The invention also relates to a method for manufacturing a high electron mobility transistor as described above, said method comprising the following steps: • the manufacture of an intermediate substrate by a process such as described above, • the formation of a first epitaxial layer of single-crystal GaN or AlGaN on the seed layer, • the formation, by epitaxy, of a transistor channel on the first epitaxial layer, • the formation by epitaxy of a barrier layer forming a heterojunction with the canal, • the formation of a cover layer on the barrier layer, • the formation of a source electrode and a drain electrode electrically connected to the canal, • the formation of a grid electrode on the cover layer. DESCRIPTION OF THE FIGURES

[0028] Fig. 1 is a cross-sectional view of a known high electron mobility transistor.

[0029] Figure 2 is a cross-sectional view of a high electron mobility transistor manufactured from a substrate according to the invention.

[0030] Fig. 3 illustrates the arrangement of the electrodes on the top face of the transistor.

[0031] Figure 4 illustrates a first embodiment of an intermediate substrate according to the invention.

[0032] Figure 5 illustrates a second embodiment of an intermediate substrate according to the invention.

[0033] Figure [Fig. 6A] illustrates a first step in manufacturing an intermediate substrate according to the invention.

[0034] Figure [Fig. 6B] illustrates a second manufacturing step of an intermediate substrate according to the invention.

[0035] Figure 6C illustrates a third manufacturing step of an intermediate substrate according to the invention.

[0036] Fig. 7 illustrates a substrate comprising a GaN buffer layer.

[0037] Figure 8 illustrates a substrate for a high electron mobility transistor.

[0038] Fig. 9 is a comparison of the response curves of a HEMT transistor based on a known substrate and of a HEMT according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0039] A HEMT transistor is shown in [Fig. 2]. The transistor comprises, from its base to its surface, a support substrate 10 made of polycrystalline silicon carbide (SiC), a buffer layer 35 made of single-crystal gallium nitride (GaN) or single-crystal gallium aluminum nitride (AlGaN), a channel 40 made of single-crystal GaN, and a barrier layer 50 made of Al₂₅Ga₇₅N over the channel and forming a heterojunction with the channel 40. A cover layer 70, typically a thin layer of gallium nitride or silicon nitride (SiN) with a thickness between one monolayer and 100 nm, can be arranged on the barrier layer. The cover layer is a passivation layer and also prevents oxidation of the barrier layer 50.

[0040] Source electrodes 61, drain electrode 62 and grid electrode 63 are arranged on the channel 40. The grid electrode 63 is arranged on the cover layer 70 between the source electrodes 61 and drain electrode 62. Typically, the LGD distance between the grid and the drain is greater than the LGs distance between the grid and the source.

[0041] Figure 3 illustrates the arrangement of the barrier layer 50 and the source electrode 61, drain electrode 62 and gate electrode 63 on the top face of the transistor. Each electrode typically has a rectangular or elongated shape extending along a transverse axis y perpendicular to the longitudinal axis x in a plane of the main surface of the substrate.

[0042] Due to the heterojunction, a two-dimensional electron gas forms at the interface between the channel 40 and the barrier layer 50. This two-dimensional electron gas serves as a conduction channel within the HEMT transistor. The buffer layer 35 helps to limit lateral and vertical leakage currents in the transistor and to better confine the two-dimensional electron gas of the heterojunction.

[0043] The transistor according to the invention has a blocking voltage greater than or equal to 1200 V, which is higher than the blocking voltage of known HEMTs. The blocking voltage is to be understood as the voltage with reference to ground. For example, a blocking voltage of 1200 V corresponds to 2 kV floating voltage, that is, without electrical connection between the HEMT source and the circuit ground plane.

[0044] In general, the blocking voltage of a HEMT transistor can be increased by increasing the LGD distance between the gate and the drain and / or the gate length LG, by increasing the thickness of the buffer layer, and / or by increasing the resistivity of the supporting substrate.

[0045] For a transistor of typical dimensions, the LGD distance between the gate and the drain is limited to a value between 10 and 15 pm. The thickness of the buffer layer is limited due to the risk of failure due to thermal expansion. Therefore, the blocking voltage should be considered as a function of the LGD distance between the gate and the drain and the resistivity of the substrate.

[0046] Regarding the support substrate, it should be noted that the band gap of SiC, which is greater than that of silicon, is closer to the band gap of the buffer layer material, namely GaN or AlGaN, than the band gap of silicon.

[0047] Surprisingly, in a HEMT on a SiC substrate with resistivities above a saturation value, the blocking voltage does not increase, or increases very little, with increasing resistivity. A saturation effect of the blocking voltage is thus observed as a function of substrate resistivity. This effect is unexpected and does not exist in current HEMTs based on silicon substrates, in which the blocking voltage increases continuously with increasing resistivity. Simulations in the context of the present invention have shown that the saturation value is typically between 0.36 and 3.6 Q·cm. It is suggested that this effect is related to the proximity of the band gaps of the substrate and buffer materials.

[0048] Moreover, the value of this resistivity is remarkably low for HEMTs exhibiting a high blocking voltage.

[0049] Beyond the saturation value, the impact of the increase in electrical resistivity on the blocking voltage of the transistor is therefore negligible: an increase in the resistivity of the substrate beyond the saturation value contributes almost nothing to the increase in the blocking voltage of the transistor.

[0050] Table 1 shows the results of simulations demonstrating the effect of electrical resistivity and the distance between the gate and the LGD drain on the blocking voltage of a HEMT on a polycrystalline SiC substrate. In these simulations, values ​​of

[0051] Electrical resistivity of the substrate between 0.072 Q.cm and 3600 Q.cm were used in combination with grid-to-drain LGD distances of 10, 15, 20 and 30 pm. Electrical resistivity [Q.cm] Blocking voltage [V] for Lgd= 10 pm Blocking voltage [V] for LGd= 15 pm Blocking voltage [V] for Lgd= 20 pm Blocking voltage [V] for Lgd= 30 pm 3600 1310 1870 2260 3010 360 1300 1860 2240 2990 36 1300 1860 2240 2990 3.6 1100 1860 2240 2990 0.36 930 1650 2000 2750 0.26 930 1400 1650 2300 0.16 930 930 930 930 0.072 930 930 930 930

[0052]

[0053]

[0054] A blocking voltage exceeding 1200 V can be achieved even with a gate-to-drain LGD distance of 10 pm when the substrate electrical resistivity is 36 Ω·cm or higher. For a gate-to-drain LGD distance of 15 pm, a substrate electrical resistivity of 0.26 Ω·cm is sufficient. In all configurations, saturation occurs above an electrical resistivity of approximately 3.6 V or 36 V. In particular, for a resistivity beyond the saturation value and a gate-drain distance Lgd of 15 pm, a blocking voltage significantly greater than 1200V can be obtained, which is the desired blocking voltage for high-performance power electronic components. To obtain high blocking voltages on a polycrystalline SiC substrate, it is therefore not necessary to use a substrate with very high electrical resistivity, as is the case with known HEMTs fabricated on a silicon substrate. It is sufficient to provide a resistivity greater than or equal to the saturation value, and typically close to the saturation value. Consequently, the substrate 10 has an electrical resistivity between 1 Ω·cm and 10 kΩ·cm, preferably between 1 Ω·cm and 1000 Ω·cm, and more preferably between 10 Ω·cm and 1000 Ω·cm, and even more preferably between 100 Ω·cm and 1000 Ω·cm, at room temperature, i.e., approximately 20°C. In the case of a SiC substrate polycrystalline, such electrical resistivity is sufficient to obtain the desired transistor blocking voltage.

[0055] The low constraints on electrical resistivity allow for the choice of a SiC support substrate that is easy to manufacture. For example, the support substrate can be made of unintentionally doped polycrystalline SiC. The use of an unintentionally doped material eliminates the doping steps, thus reducing the cost and manufacturing constraints of the support substrate compared to a substrate doped for high resistivity, for example, a vanadium-doped substrate.

[0056] Furthermore, polycrystalline SiC has a coefficient of thermal expansion close to that of GaN and AlGaN. Consequently, the risk of failure at the interface between the support substrate 10 and the buffer layer 35 is greatly reduced. It is therefore possible to deposit thick layers of GaN or AlGaN on a polycrystalline SiC support substrate with a lower risk of failure than with a silicon support substrate. Thus, the GaN or AlGaN layer on a polycrystalline SiC support substrate can reach a thickness of up to 10 pm without increasing the risk of failure due to thermal expansion.

[0057] The use of a polycrystalline SiC support substrate therefore makes it possible simultaneously to lower the resistance of the support substrate required to obtain a transistor with a high blocking voltage, and to form relatively thick layers of GaN or AlGaN directly on the support substrate, making it possible to further increase the blocking voltage of the transistor without increasing the dimensions of the transistor.

[0058] Furthermore, the use of a polycrystalline SiC support substrate allows for a further reduction in the buffer layer thickness compared to known HEMTs. The buffer layer 35 of a HEMT according to the invention has a thickness between 3.5 and 5.5 pm. Simulations have demonstrated that, in the case of a SiC support substrate, such a thickness is sufficient to guarantee a transistor blocking voltage of 1200 V for a HEMT with a gate-drain LGD between 10 pm and 15 pm.

[0059] At the same time, mechanical stresses in the substrate are minimized due to the relatively small thickness and the similarity of the coefficients of thermal expansion of SiC, GaN, and AlGaN. A buffer layer thickness of between 3.5 and 5.5 pm therefore makes it possible to obtain a HEMT with typical dimensions and a blocking voltage of 1200V, while minimizing the risk of substrate failure due to thermal expansion.

[0060] The LGd distance between the grid and the drain is between 10 pm and 15 pm, preferably 12 pm. For a polycrystalline SiC support substrate and a buffer layer with a thickness between 3.5 and 5.5 pm, such an LGD distance This allows for a transistor blocking voltage greater than or equal to 1200 V, while also optimizing the current density per cm2. The result is a transistor with both optimized blocking voltage and current density, and a low risk of failure.

[0061] The distance LGS between the grid and the source is between 1 pm and 3 pm, preferably equal to 2 pm. The length LG of the grid is between 1 pm and 3 pm, preferably equal to 2 pm.

[0062] The HEMT transistor is made from an intermediate substrate 100, shown in [Fig.4]. The intermediate substrate comprises the polycrystalline silicon carbide (SiC) support substrate and a single-crystal gallium nitride (GaN) seed layer 20.

[0063] The polycrystalline SiC substrate typically has a thickness of between 300 and 900 pm, preferably between 300 and 500 pm.

[0064] The seed layer 20 is a thin layer of single-crystal GaN, bonded via a direct bonding interface 15 to the upper face of the support substrate 10.

[0065] A direct bonding interface is defined as a bonding interface with or without the addition of material. Such direct bonding requires that the two surfaces to be bonded be sufficiently smooth and free from particles or contamination. In this case, the attractive forces between the two surfaces become high enough to cause molecular adhesion between them.

[0066] With reference to [Fig. 4], the seed layer can be bonded to the substrate without the addition of material, for example by vacuum bonding. Such bonding avoids the introduction of dopants that could alter the electrical properties of gallium nitride.

[0067] Alternatively, with reference to [Fig.5], the direct bonding interface 15 can consist of a bonding layer 21 interposed between the support substrate 10 and the seed layer 20.

[0068] The bonding layer is made of a material whose electrical resistivity is equal to or greater than the electrical resistivity of the polycrystalline silicon carbide which constitutes the support substrate.

[0069] It is particularly useful to use a bonding layer having good thermal conductivity and a very thin thickness, for example less than 10 nm.

[0070] Thus, a thermal transparency effect is obtained, meaning that the conduction of heat from the heterojunction to the substrate is not modified by the adhesive layer during transistor operation. Silicon nitride (SiN) is particularly well-suited for use as an adhesive layer, due to its bonding properties and its high thermal conductivity. Another example of a material for the bonding layer is silicon oxide (SiO2).

[0071] In some cases, the bonding layer material can bond with one of the materials present at the bonding interface. In other cases, the bonding layer can fracture into nodules between which the supporting substrate and the seed layer are in direct contact.

[0072] Typically, the seed layer has a thickness between 10 nm and 1 pm. This thickness is easily transferred according to the method described below and allows the growth of a uniform, single-crystal buffer layer on the surface of the substrate.

[0073] The level and nature of the seed layer doping are chosen according to the desired properties of the transistor to be fabricated. In some embodiments, the seed layer is made of unintentionally doped GaN, for example, with a residual doping level of up to 5-10¹⁵ or 10¹⁶ at.cm³. Embodiments in which the seed layer is made of GaN with p-type doping are also considered. An example of GaN seed layer doping is carbon doping of 2-10¹⁹ cm³.

[0074] We will now describe the manufacturing steps of such a HEMT transistor.

[0075] The process begins by providing a donor substrate from which the single-crystal GaN seed layer will be formed. The donor substrate is typically a heterosubstrate, for example, a single-crystal GaN substrate on sapphire or a single-crystal GaN substrate on SiC. Such heterosubstrates are easier to fabricate than bulk substrates, especially for diameters greater than 4 inches (approximately 100 mm). Alternatively, a bulk single-crystal GaN substrate can be used.

[0076] According to a particular embodiment, the donor substrate is fabricated by transferring a layer of GaN onto a temporary substrate, for example, polycrystalline SiC. The transfer is carried out, for example, by a SmartCut®-type process or by laser detachment. The donor substrate thus obtained can be used directly or after increasing the thickness of the GaN layer by epitaxial growth.

[0077] Preferably, the free GaN face of the donor substrate is a [000-1] face, also called the nitrogen face because it has nitrogen atoms in the outermost lattice of the crystal lattice. Thus, the top face of the transferred seed layer will be a gallium face (with gallium atoms in the outermost lattice) since the transfer involves an inversion of the transferred layer.

[0078] With reference to [Fig. 6A], as schematically indicated by the arrows, an implantation of ionic species, such as hydrogen and / or helium, is implemented, so that to form a weakening zone 21 in the donor substrate 200. Said weakening zone 21 defines a layer 20 of single-crystal GaN to be transferred.

[0079] With reference to [Fig. ôB], the weakened donor substrate 200 is bonded to a support substrate 10 via a bonding interface 15. The donor substrate can be bonded directly to the base substrate as illustrated in [Fig. ôB], or via a bonding layer as described above. The bonding layer can be applied to the donor substrate 200 and / or to the support substrate 10 before bonding (not shown).

[0080] With reference to [Fig. 0C], the donor substrate 200 is then detached along the embrittlement zone 21, leading to the transfer of the seed layer 20 of single-crystal gallium nitride onto the support substrate 10, thus forming the intermediate substrate 100 as shown in [Fig. 4] or [Fig. 5]. The remaining 201 of the donor substrate can be reused for the transfer of one or more other layers of single-crystal GaN onto other support substrates.

[0081] Subsequently, with reference to [Fig. 7], a first epitaxial layer is deposited on the seed layer 20. The first epitaxial layer is typically made of GaN. In some embodiments, the first epitaxial layer may be made of AlGaN. The first epitaxial layer 30 is intended to form, together with the seed layer 20, the buffer layer 35. The surface of the single-crystal seed layer 20 promotes the growth of a GaN layer 30 with a single-crystal structure. Epitaxial growth makes it possible to obtain a thick single-crystal GaN layer 30 rapidly and at low cost. After the GaN grows on the seed layer, the single-crystal structure of the seed layer 20 and the deposited layer is homogeneous and exhibits no boundary between the two layers. The germ layer 20 and the epitaxial layer 30 thus form a single homogeneous buffer layer 35 of single-crystal GaN or single-crystal AlGaN.

[0082] In a preferred embodiment, the epitaxial layer 30 is made of unintentionally doped single-crystal GaN or carbon-doped single-crystal GaN. Carbon doping increases the electrical resistivity of the buffer layer. The carbon doping level can, for example, be between 10¹⁷ and 5–10¹⁹ at.cm³. Preferably, the carbon doping level is between 10¹⁸ and 2–10¹⁹ at.cm³. It should be noted that the doping level of the GaN layer 30 deposited by epitaxy can be different from the doping level of the seed layer 20 without affecting the crystal structure.

[0083] The thickness of the epitaxial layer 30 is approximately 3.4 to 5.5 pm to obtain a buffer layer 35 as described above.

[0084] After the formation of the buffer layer 35, with reference to [Fig. 8], a second layer of single-crystal GaN is deposited by epitaxy. Advantageously, This second deposition is performed in the same epitaxial chamber to avoid additional process steps and prevent substrate contamination. The second GaN layer is intended to form channel 40 of the transistor. This second layer is unintentionally doped GaN, which may have a residual doping level of 5-10¹⁵ or 10¹⁶ at.cm³ or lower. During this second deposition, any additional dopants must be removed to obtain an unintentionally doped GaN layer, possibly with a low residual doping level.

[0085] The thickness of the second epitaxial layer corresponds to the thickness of the channel and is advantageously about 300 nm. A barrier layer 50 is then deposited on the channel 40 as illustrated in [Fig. 3]. Thanks to this barrier layer 50, which forms a heterojunction with the channel, a two-dimensional electron gas will be generated at the interface between the barrier 50 and the channel 40, allowing electron conduction within the transistor. The barrier layer 50 extends only partially over the surface of the transistor and typically has an elongated rectangular shape along a longitudinal axis x.

[0086] A cover layer (not shown) can then be deposited on the barrier layer 50. The cover layer is, for example, a p-doped GaN layer for a standard HEMT, or a thin layer of GaN and / or SiN for a HEMT for radio frequency applications.

[0087] In a manner known per se, the source electrodes 61 and drain electrodes 62 are deposited on the barrier layer 50 and the channel 40 or on either side of the barrier layer 50, for example by etching through a mask, and then are subjected to annealing to form an ohmic contact with said barrier layer 50. The grid electrode 63 is typically deposited on the cover layer on the upper face of the barrier layer 50.

[0088] Figure 9 illustrates the effect of the substrate material on the performance of the HEMT. Curve 9A represents the drain current as a function of the voltage applied to the gate of a HEMT based on a known silicon substrate, as illustrated in Figure 1. Curve 9B shows the response of a HEMT fabricated on a polycrystalline silicon carbide substrate as described above, and exhibiting a resistivity of 100 Ω·cm. Both HEMTs have identical lateral dimensions, with a width LT of 140 mm, a gate length LG of 2 pm, a gate-to-drain distance LGd of 10 pm, and a gate-to-source distance LGS of 2 pm. The on-state resistance of the transistor according to the invention is increased by approximately 10% compared to the transistor on a silicon substrate.

[0089] Furthermore, the heat transfer of the transistor on a polycrystalline SiC substrate according to the invention is increased compared to the transistor on a silicon substrate. This allows for more efficient heat dissipation and consequently optimizes the performance of the HEMT.

[0090] The maximum on-state current performance of this transistor is 0.56 A / mm. The channel width is defined according to the desired current rating for the component. For example, a transistor width W = 140 mm results in a maximum current of 78 A. REFERENCES

[0091] EP2983195 Al

Claims

Demands

1. Intermediate substrate (100) for the fabrication of a high electron mobility transistor (HEMT), comprising: • a support substrate (10) of polycrystalline silicon carbide having an electrical resistivity between 1 Q.cm and 10 kQ.cm, and • a seed layer (20) of monocrystalline GaN, said intermediate substrate (100) comprising a direct bonding interface (15) between the silicon carbide of the support substrate (10) and the seed layer (20).

2. Intermediate substrate according to claim 1, wherein the supporting substrate (10) has a thickness between 300 and 500 pm.

3. Intermediate substrate according to claim 1 or claim 2, wherein the seed layer (20) has a thickness between 10 nm and 1 pm.

4. Intermediate substrate according to any one of the preceding claims, wherein the direct bonding interface (15) is a bonding layer (21) arranged between the support substrate (10) and the seed layer (20).

5. Substrate for high electron mobility transistor, said substrate comprising, from its base to its surface: • an intermediate substrate (100) according to any one of claims 1 to 4, • a first epitaxial layer (30) of single-crystal GaN or single-crystal AlGaN, the first epitaxial layer (30) and the seed layer (20) together forming a buffer layer (35) of single-crystal GaN or single-crystal AlGaN, • a second epitaxial layer of unintentionally doped GaN configured to form a channel (40) of the transistor.

6. Substrate according to claim 5, wherein the buffer layer (35) has a thickness between 3.5 and 5.5 pm.

7. Substrate according to claim 5 or claim 6, wherein the buffer layer (35) is made of carbon-doped GaN or of unintentionally doped GaN.

8. High electron mobility transistor, comprising • an intermediate substrate (100) according to any one of claims 1 to 4, • a first epitaxial layer (30) of single-crystal GaN or single-crystal AlGaN, the first epitaxial layer (30) and the seed layer (20) together forming a buffer layer (35), • a GaN channel (40) arranged on the buffer layer (35), • a barrier layer (50) forming a heterojunction with the channel, adapted to generate a two-dimensional electron gas in the channel, • a source electrode (61) and a drain electrode (62) electrically connected to the channel (40), • a gate electrode (63) formed on the barrier layer (50) such that the gate electrode (63) is physically isolated from the channel (40).

9. Transistor according to claim 8, wherein the barrier layer (50) is made of Alo.25Gao.75N.

10. A method for manufacturing an intermediate substrate (100) according to any one of claims 1 to 4, said method comprising the following steps: • the formation of a embrittlement zone (21) by implanting ionic species in a donor substrate (200) of monocrystalline GaN, • the bonding of said donor substrate (200) onto a support substrate (10) of polycrystalline silicon carbide, so as to form a direct bonding interface (15) between the support substrate (10) and the donor substrate (200), • the detachment of the donor substrate (200) along the embrittlement zone (21) so as to transfer a seed layer (20) of monocrystalline GaN onto the support substrate (10).

11. A method for manufacturing an intermediate substrate (100) according to claim 10, wherein the bonding step comprises the deposition of a layer of adhesive (21) on the support substrate (10) and / or on the donor substrate (200).

12. A method for manufacturing an intermediate substrate (100) according to claim 10, wherein the donor substrate is bonded to the support substrate without the addition of material.

13. A method for manufacturing a high electron mobility transistor according to claim 8 or claim 9, said method comprising the following steps: • manufacturing an intermediate substrate (100) by a method according to any one of claims 10 to 12, • forming a first epitaxial layer (30) of single-crystal GaN or single-crystal AlGaN on the seed layer (20), • forming by epitaxy a channel (40) of the transistor on the first epitaxial layer (30), • forming by epitaxy a barrier layer (50) forming a heterojunction with the channel (40), • forming a cover layer on the barrier layer (50), • forming a source electrode (61) and a drain electrode (62) electrically connected to the channel (40), • forming a gate electrode (63) on the cover layer.

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