Manufacturing process for a 3D assembly

Abstract

Method for manufacturing a 3D assembly. This description relates to a method comprising the following steps: - providing several assemblies, each comprising a donor substrate (10) covered by a functional block (100, 200) successively comprising a first interconnecting layer (110), a functional layer (130) and a second interconnecting layer (120), the functional layer comprising one or more electronic components, the interconnecting layers (110, 120) comprising a dielectric material (111, 121) in which conductive elements (112, 122) are formed, a first surface of the first interconnecting layer (110) in contact with the donor substrate (10) and the free surface of the second interconnecting layer (120) being planarized so as to be compatible with subsequent direct bonding, - transferring, successively, onto a receiving substrate (20) the functional blocks (100, 200), by direct bonding,to form a 3D assembly comprising a receiving substrate (20) covered by a stack of two functional blocks (100, 200). Figure for the abstract: Fig. 1E,

Description

Title of the invention: Method for manufacturing a 3D assembly technical field

[0001] This description relates generally to the field of microelectronics, and more particularly to 3D assembly processes and the resulting 3D assemblies. Previous technique

[0002] Microelectronics refers to all the technologies for manufacturing components that use electrical currents to transmit, process, or store information. Microelectronic technologies are largely responsible for the tremendous progress made in recent decades in fields such as computing, telecommunications, and imaging.

[0003] Microelectronic technologies have, in particular, made it possible in recent years to introduce new objects onto the market (telephone ('SmartPhone'), electric car, etc.) offering users new systems (connected screens, integrated circuits, etc.) incorporating new components (micro-LEDs, transistors, etc.) with improvements each year in terms of functionality (for example: memory size, number of processor cores, miniaturization, etc.).

[0004] This 'functional' evolution of the microelectronics sector is currently having negative repercussions on the environment. In particular, one can cite the use of natural resources: rare metals, water consumption, increased energy consumption through the adoption of new devices, waste production, etc.

[0005] To reduce the environmental impact of microelectronics, companies can individually rely on ISO 14004 and ISO 14006 standards, which provide guidelines to help organizations establish, document, implement, maintain and continuously improve their eco-design management and its implementation.

[0006] Significant research and development (R&D) efforts are currently underway worldwide to expand the range of technologies available for component assembly. This research is primarily focused on 3D (or 2.5D or 3.5D) assembly, which involves stacking substrates or chips vertically, using chip thinning techniques, with the aim of achieving increasingly sophisticated integration. These 3D techniques make it possible to increase performance (for example, the bandwidth between a processor and memory) and reduce power consumption by replacing long horizontal connections. By using a short vertical connection, production costs can be reduced by choosing the technology best suited to the desired function. It is therefore a key tool in an eco-design approach for microelectronics, but one that faces both technological and organizational challenges.

[0007] The 3D assembly is based on different technologies of fine pitch vertical interconnections ('Fine Pitch Interconnects'): direct bonding of Metal-Dielectric structured surfaces (hybrid bonding), high density through-silicon vias (TSV for 'Through-Silicon Via' or TDV for 'Through-Dielectric Via'), Damascene level ('ReRouting') or redistribution layer ('ReDistribution Layer' or RDL).

[0008] These 3D assembly technologies are well known and mastered at the substrate (or 'wafer') scale, i.e., at the scale of a silicon substrate measuring 200 mm or 300 mm, for a small number of assemblies (on the order of 2 to 3 stacks). However, they are very difficult to apply for a large number of assemblies at the substrate scale, and even more so at the chip scale.

[0009] Indeed, all these 3D assembly technologies rely on Damascus-type processes, which include at least one step of planarizing the component surfaces by chemical-mechanical polishing (CMP). However, planarization CMP is a process that induces significant edge effects (VCMP at the Wafer Edge - Modeling the Interaction between Wafer Edge Geometry and Polish Performance (2005) Materials Research Society symposia proceedings. Materials Research Society 867). Each 3D assembly thus leads to degradation of the edges of the wafers or chips through a local erosion phenomenon, making it difficult or even impossible to add the next stack.It is also a very important process for the reliability of devices because it induces intra- and inter-layer microcracks, a phenomenon that increases with the number of Damascus levels ('Impact of the CMP Process on the Multilevel Stock Mechanical Reliability' (2008) Other Electronics Packaging Technology Conference).

[0010] Hybrid bonding also requires a CMP step to activate the surfaces to be bonded, creating dangling bonds, and to control the relative heights of the metal pads and the dielectric matrix (EP 2863420 Bl).

[0011] Moreover, new objects from microelectronics are currently manufactured in a very segmented way. Each microelectronic component company (for example, of the 'fabless' type, or IDM (Integrated Device Manufacturer)) develops and manufactures one or more semiconductor components having a basic function (RF, memory, logic, ...), according to its own design, with a suitable material, in a manufacturing plant of its choice (foundry, IDM, ...), according to its own technological and environmental roadmap. The substrates on which these components are manufactured are generally silicon wafers with a diameter of 200 mm or 300 mm. To assemble, package, and test the resulting integrated systems (IC chips, microdisplays, etc.), semiconductor manufacturers primarily rely on companies specializing in outsourced semiconductor assembly and testing (OSATs), with the exception of a few IDM manufacturers that own their own assembly plants. For this assembly process, the wafers with their components are sliced ​​into chips, and the chips are then microsoldered onto a package substrate using contacts made of tin-, nickel-, or gold-plated copper alloy, which are then molded in plastic.

[0012] In this context, the 3D assembly of chips or substrates is very complex because it poses numerous incompatibility problems: at the substrate level (materials of different diameters, nature, for example), at the design level (different chip sizes, functions not optimized for use, particularly assembly), and at the manufacturing technology level (different alignment marks depending on the foundry, testing methods, materials used for functions and connections). Summary of the invention

[0013] There is a need for a manufacturing process for a 3D assembly, easy to implement, the 3D assembly being able to have several functional blocks while exhibiting good mechanical strength, a small footprint and good performance.

[0014] This goal is achieved by a method for manufacturing a 3D assembly comprising the following steps: - to provide at least two assemblies, each comprising a donor substrate covered by a functional block comprising successively a first interconnection layer, a functional layer and a second interconnection layer, the functional layer comprising one or more electronic components, the first interconnection layer and the second interconnection layer comprising a dielectric material in which conductive elements are formed, preferably copper, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with subsequent direct bonding, - to transfer, successively, onto a receiving substrate the functional blocks, by direct bonding, the conductive elements of the first interconnection layer of the first functional block being opposite and in contact with the conductive elements of the second interconnection layer of the second functional block, whereby we obtain a 3D assembly comprising a receiving substrate covered by a stack of two functional blocks.

[0015] According to a particular embodiment, at least 5 functional blocks, preferably at least 10 functional blocks, are transferred successively onto the receiving substrate during step iv).

[0016] According to a particular embodiment, after the transfer of the functional blocks, the process comprises the following steps: - gluing the 3D assembly onto an adhesive, - cutting the receiving substrate and the functional blocks and removing the receiving substrate, thereby obtaining several stacks of individualized functional blocks, - optionally, gluing the different stacks of individualized functional blocks onto an external element, such as a printed circuit board or a laminated substrate.

[0017] According to a particular embodiment, one of the functional blocks partially covers the donor substrate, interconnection blocks being arranged on the donor substrate on each side of said functional block and, during step iv), said functional block and the interconnection blocks are transferred simultaneously onto the receiving substrate.

[0018] According to a particular embodiment, at least one of the assemblies provided in step i) is obtained according to the following steps: - provide a temporary substrate covered by the functional layer, - form the first interconnection layer on a first face of the functional layer, and planarize it, - transfer the first interconnection layer and the functional layer onto the donor substrate, by gluing the donor substrate onto the functional layer and separating the temporary substrate, - to form the second interconnection layer on a second face of the functional layer, - Planarize the second interconnection layer.

[0019] According to a particular embodiment, some or all of the functional blocks include electronic chips.

[0020] This objective is also achieved by a method for determining the steps of a manufacturing process for a 3D assembly, the determination method comprising the following steps: - Define the functions of the 3D assembly, the 3D assembly comprising a substrate and a stacking of different functional blocks, - simulate the 3D assembly by choosing different types and / or dimensions of the substrate and / or functional blocks and / or by choosing different stackings of functional blocks, thereby selecting a first manufacturing process for the 3D assembly.

[0021] According to a particular embodiment, at least one other manufacturing process for the 3D assembly is defined and compared to the first manufacturing process for the 3D assembly, according to several criteria, for example in terms of feasibility, technical risk, functionality, cost and / or environmental impact, so as to choose the most suitable manufacturing process for the 3D assembly.

[0022] This goal is also achieved by a 3D assembly comprising a receiving substrate on which are stacked at least two functional blocks, preferably at least 5 functional blocks, even more preferably at least 10 functional blocks, each functional block comprising a functional layer, comprising one or more electronic components, arranged between two interconnecting layers, the interconnecting layers comprising a dielectric material in which conductive elements are formed, preferably copper, each functional block being planar.

[0023] According to a particular embodiment, each functional block includes an electronic chip.

[0024] This goal is also achieved by an assembly comprising a donor substrate covered by a functional block comprising successively a first interconnection layer, a functional layer and a second interconnection layer, the functional layer comprising one or more electronic components, the first interconnection layer and the second interconnection layer comprising a dielectric material in which conductive elements are formed, preferably in copper, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with subsequent direct bonding. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0026] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D] and [Fig.1E] schematically represent different stages of a manufacturing process for a 3D assembly, according to a particular embodiment of the invention;

[0027] [Fig.2A], [Fig.2B] and [Fig.2C] schematically represent, in section and side view, a 3D assembly, according to different particular embodiments of the invention;

[0028] Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D, Fig. 3E and Fig. 3F schematically represent different stages of a manufacturing process of a donor substrate covered by a functional block, according to a particular embodiment of the invention;

[0029] Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 4E, Fig. 4F, Fig. 4G, Fig. 4H, Fig. 4I, Fig. 4J, Fig. 4K and Fig. 4L schematically represent different stages of a manufacturing process for a donor substrate covered by a functional block, according to another particular embodiment of the invention;

[0030] Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D and Fig. 5E represent, schematically, in section and in side view, a temporary substrate, according to different particular embodiments of the invention;

[0031] [Fig.6] schematically represents, in cross-section and side view, a receiving substrate, according to a particular embodiment of the invention;

[0032] [Fig.7A], [Fig.7B] and [Fig.7C] schematically represent different stages of a cutting process of a receiving substrate covered by several functional blocks, according to a particular embodiment of the invention;

[0033] [Fig.8] schematically represents, in top view, the receiving substrate of [Fig.7C];

[0034] [Fig.9A], [Fig.9B], [Fig.9C] and [Fig.9D] schematically represent different stages of a process for assembling electronic chips on a final substrate, according to a particular embodiment of the invention;

[0035] [Fig.1OA], [Fig.1OB] and [Fig.1OC], schematically represent a 3D assembly method of functional blocks from different plates, each covered by a functional block, according to another particular embodiment of the invention;

[0036] [Fig.llA], [Fig.llB], [Fig.llC], [Fig.llD], [Fig.llE], [Fig.llF] and [Fig. 11G], schematically represent a 3D assembly method from donor substrates covered by functional blocks comprising 'HBM DRAM' chips, according to another particular embodiment of the invention;

[0037] [Fig.12A], [Fig.12B], [Fig.12C], [Fig.12D], [Fig.12E] and [Fig.12F] schematically represent a method for manufacturing a 3D assembly comprising a 'Compute' functional block, functional blocks comprising 'HBM DRAM' chips, and a 'Logic' functional block, according to a particular embodiment of the invention;

[0038] Fig. 13 represents, schematically and in cross-section, part of a processor for artificial intelligence according to a particular embodiment of the invention;

[0039] [Fig. 14] schematically and in cross-section represents a receiving substrate comprising an 'ASIC' block, according to a particular embodiment of the invention;

[0040] [Fig. 15A], [Fig. 15B] and [Fig. 15C] schematically represent a method for manufacturing a 'DRAM' functional block, according to another particular embodiment of the invention;

[0041] [Fig.10A], [Fig.10B] and [Fig.10C] schematically represent a method for manufacturing a 'Photonic' functional block, according to another particular embodiment of the invention;

[0042] [Fig.17A], [Fig.17B], [Fig.17C] and [Fig.17D] schematically represent a method for manufacturing a 3D assembly comprising a functional block 'ASIC', a functional block 'DRAM' and a functional block 'Photonic', according to a particular embodiment of the invention;

[0043] [Fig. 18] and [Fig. 19] schematically represent, respectively in top view and in section, part of a heterogeneous assembly for radio frequency, according to a particular embodiment of the invention;

[0044] [Fig.20A], [Fig.20B] and [Fig.20C] schematically represent a manufacturing process for a functional block 'DHBT', according to a particular embodiment of the invention;

[0045] [Fig.21] represents, schematically and in cross-section, a receiving substrate according to a particular embodiment of the invention;

[0046] [Fig.22A], [Fig.22B] and [Fig.22C] schematically represent different stages of a chip manufacturing process, according to another particular embodiment of the invention;

[0047] [Fig.23] schematically and in cross-section represents a device comprising the receiving substrate of [Fig.21] onto which the functional block 'DHBT' of [Fig.20C] and the chips of Figure 22C have been transferred, according to a particular embodiment of the invention.

[0048] The different elements are not necessarily represented at a uniform scale to make the figures more legible. Description of the implementation methods

[0049] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional, and material properties. By For example, the different donor substrates have the same reference, even if they themselves may be different. Similarly, the first interconnection layers of the different functional blocks have the same reference, even if they may be different. The same applies to the second interconnection layers of the different functional blocks.

[0050] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0051] For better readability of the figures, the functional blocks may sometimes be represented as a single block in order to avoid representing all the layers of the stack forming said functional block.

[0052] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0053] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0054] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean at 10%, preferably at 5%.

[0055] By between X and Y, we mean that the bounds X and Y are included.

[0056] By compatible with direct bonding, it is meant that the RMS roughness of the surface the thickness to be glued is between 0 and 1.5 nm, and preferably less than or equal to 1 nm, and the topography (difference in height between the metal pads and the dielectric material) is between 0 and 30 nm, preferably less than 20 nm.

[0057] The manufacturing process for a 3D assembly comprises the following steps: - to provide at least two assemblies, each comprising a donor substrate 10 covered by a functional block 100, 200 comprising successively a first interconnection layer 110, a functional layer 130, and a second interconnection layer 120, the functional layer comprising one or more electronic components as well as through-vias, preferably of copper, the first interconnection layer and the second interconnection layer 110, 120 comprising a dielectric material 111, 121 in which conductive elements 112, 122 are formed, preferably of copper, a first surface of the first interconnection layer 110 in contact with the donor substrate 10 and the free surface of the the second interconnection layer 120 being planarized so as to be compatible with subsequent direct bonding, - to transfer, successively, onto a receiving substrate 20 the functional blocks 100, 200, by direct bonding, the conductive elements 112 of the first interconnection layer 110 of the first functional block 100 being opposite and in contact with the conductive elements 122 of the second interconnection layer 120 of the second functional block 200, thereby obtaining a 3D assembly comprising a receiving substrate 20 covered by a stack of two functional blocks 100, 200.

[0058] The process can allow stacking more than 2 functional blocks, for example more than 5 functional blocks, preferably more than 10 functional blocks, even more preferably more than 20 functional blocks, even more preferably more than 50, or even more than 100 functional blocks.The conductive elements of one of the interconnection layers of a functional block are arranged opposite and in contact with the conductive elements of one of the functional layers of the adjacent functional block.

[0059] This 3D assembly method for microelectronics consists of stacking several functional blocks whose two main surfaces are flat to be compatible with direct gluing.

[0060] The various functional blocks were planarized (i.e., made flat) one by one on both surfaces before being assembled. Thus, the blocks are not planarized after assembly on the receiving substrate. This avoids edge effects and localized erosion phenomena, resulting in assemblies with a higher integration density and improved performance.

[0061] Such a process allows the 3D assembly of any type of component and thus opens the way to a very large number of stacking variants (materials, functions, sizes, etc.).

[0062] We will now describe in more detail the manufacturing process of the 3D assembly, first referring to Figures IA to 1E. The process comprises the following steps: (i) provide an assembly comprising a first donor substrate 10 covered by a first functional block 100 comprising successively from the first donor substrate 10: a first interconnection layer 110, a functional layer 130, a second interconnection layer 120, the functional layer comprising one or more electronic components as well as through-vias preferably of copper, the interconnection layers 110, 120 comprising a dielectric material 111, 121 in which conductive elements 112, 122 are formed, preferably of copper ([Fig. 1 A]), the surface of the first interconnection layer 110 in contact with the donor substrate having been planarized so as to be compatible with subsequent direct bonding, ii) perform a planarization step on the second interconnection layer 120, so as to make it compatible with a subsequent direct bonding, whereby the first donor substrate 10 is covered by a first planarized functional block 100 (figures IB), iii) repeat steps a) and b) to form a second donor substrate 10 covered by a second functional block 200 comprising a functional layer 230 disposed between two interconnection layers 110, 120, iv) transfer onto a recipient substrate 20 by direct bonding and removal of the donor the first functional block 100 and then the second functional block 200, whereby a 3D assembly is obtained comprising a recipient substrate 20 covered by two functional blocks 100, 200 (figures 1D and 1E).

[0063] The functional blocks 100, 200 stacked on the receiving substrate 20 can be identical ([Fig.2A]) or different ([Fig.2B]). Step iii) is repeated as many times as necessary to obtain the desired number of functional blocks 100, 200, 300, 400, 500 (for example, 5 functional blocks are shown in [Fig.2C]).

[0064] According to a first embodiment, for example shown in Figures 3A to 3F, the assembly provided in step i) can be obtained by the following steps: ia) provide an initial temporary substrate 30 comprising a functional layer 130 and its associated contacts ([Fig.3A]), ib) form the first interconnecting layer 110 on the free face of the functional layer 130, and planarize it ([Fig.3B]), ic) transfer the first interconnecting layer 110 and the functional layer 130 onto the donor substrate 10: - by gluing the donor substrate 10 onto the first interconnection layer 110 ([Fig.3C]) and, - by separating all or part of the initial temporary substrate 30 from the assembly formed by the donor substrate 10, the first interconnection layer 110 and the functional layer 130 ([Fig.3D]), - possibly remove the remaining portion of the initial temporary substrate 30 from the assembly formed by the donor substrate 10, the first interconnection layer 110 and the functional layer 130, id) form through vias in the functional layer 130 as well as a second interconnection layer 120 on a second face of the functional layer 130, and planarize it, thereby obtaining a donor substrate 10 covered by a functional block 100 having its two surfaces ready for assembly by direct gluing (figures 3E and 3F).

[0065] According to another embodiment, for example shown in Figures 4A to 4L, the assembly provided in step i) can be obtained according to the following steps: i.a') provide a first initial temporary substrate 30 comprising a first functional layer and its associated contacts 130 ([Fig.4A]), i.b') form a first interconnection layer 110 on a first face of the functional layer 130, and planarize it ([Fig.4B]), i.c') transfer the first interconnection layer 110 and the functional layer 130 to a second temporary substrate 40: - by gluing the second temporary substrate 40 onto the functional layer 130 ([Fig.4C]) and, - by separating all or part of the initial temporary substrate 30 ([Fig.4D]), - possibly by removing the part of the initial temporary substrate 30 remaining from the assembly formed by the temporary substrate 40, the interconnection layer 110 and the functional layer 130, i.d') form through vias in the functional layer 130 as well as a second interconnection layer 120 on a second face of the functional layer 130, and planarize it whereby a temporary substrate 40 is obtained covered by a functional block 100 having its two surfaces ready for assembly by direct gluing (figures 4E, 4F and 4G), i.e') to single out the functional block 100 into several parts (for example, into several chips in the case where the functional block comprises several chips), for example by sticking the functional block 100 onto an adhesive 60 ([Fig.4H]), cutting out the second temporary substrate 40 and the functional block 100, and then removing the second temporary substrate 40 ([Fig.41]), i.f') transfer one or more parts of the functional block 100 onto a donor substrate 10 ([Fig.4J]), for example by direct chip-to-wafer bonding ('die to wafer' or D2W), i.g') deposit a dielectric material 140 on each side of the bonded functional block parts 100 ('Inter Die Gap Fill') ([Fig.4K]), the thickness of the dielectric material 140 being greater than the thickness of the functional block parts, then form vias and fill them with a metal 142 to form a Damascus level, and planarize the resulting dielectric material / functional block surface ([Fig.4L]).

[0066] The initial temporary substrates 30 used can be chosen from the following substrates, depending on the desired function and assembly: - a massive substrate 30 (Silicon, Germanium, InP, GaAs, Glass, LiTaO3,...), for example with a diameter of 100mm, 150mm, 200mm, or 300mm ([Fig.5A]), - an 'X-On-Insulator' type substrate 30 (for example, an SOI, GeOI, InPoSi, POI, GaNOI, etc. substrate) comprising a support substrate 31 covered by a buried oxide layer (BOX or 'buried oxide') 32 ([Fig. 5B]), which can, for example, be obtained using Smart Cut™ technology; the use of an 'X-On-Insulator' substrate allows for better control of the shrinkage of the support substrate 31, - a substrate 30 of the 'X-On-Insulator-On-Insulator' type ([Fig.5C]) to facilitate the removal of part of the initial temporary substrate 30, particularly in the case where this substrate 30 includes elements (for example a BOX 32, a semiconductor layer 33, in particular silicon, a cavity 35, for example a thermal cavity, optical resonators,...) located between the upper face of the substrate 30 and an insulating layer 34, covering the support substrate 31, - a substrate 30 of the Removable Substrate type including a buried fragile interface 36 for example located under a BOX or directly under the functional layer for the subsequent removal of the support substrate 31 ([Fig.5D]); the buried fragile interface 36 can be a controlled bonding interface, a porous layer, a nitrided layer, a delamination layer such as a Ti (100m thickness) / Pt (100nm thickness) deposit.

[0067] The functional layer 130 can completely cover the initial substrate 30 (Figures 5A, 5B, 5C and 5D) or a portion of the initial substrate 30 ([Fig. 5E]). When the functional layer 130 partially covers the temporary substrate, a dielectric material 37 is positioned on the substrate on either side of the functional layer, in a coplanar manner, so as to have a flat dielectric / functional layer surface covering the temporary substrate 30.

[0068] In this case, the functional layer 130 can be formed using methods well known to those skilled in the art. By way of illustration and without limitation, it can be formed by localized etching (related to the design), by manufacturing a rebuilt wafer substrate followed by surface planarization by dielectric deposition and chemical-mechanical polishing. The thickness of a functional layer is typically on the order of a few hundred nanometers to a few millimeters, or even a few tens of millimeters.

[0069] The topography of the temporary substrates 30 is preferably less than 200nm or even less than 100nm, compatible with the subsequent formation of the functional and interconnecting layers.

[0070] The donor substrate 10 can be chosen from: - a solid substrate, preferably a low-cost silicon substrate or a substrate adapted to the initial substrate in terms of thermo-mechanical behavior (for example, a donor substrate having a coefficient of thermal expansion close to that of the initial temporary substrate), - a substrate comprising a layer implanted with H+ and / or He ions as described in Smart Cut™ technology - a substrate with a buried fragile layer or interface, for example a SOI substrate with a low-adhesion bonding interface, - a substrate comprising a fragile surface layer, for example a porous layer formed by anodizing Silicon and / or a separation layer (of the Ti lOnm + Pt lOOnm type for example), - a substrate with alignment marks for bonding, in order to limit deformation of the assembly formed by one of the temporary substrates with the donor substrate before the removal of part of one of the temporary substrates, - a substrate having a constrained layer on the back face (for example 60nm of SiN), in order to limit the deformation of the assembly of one of the temporary substrates with the donor substrate before the removal of part of one of the temporary substrates.

[0071] The donor substrate 10 can be a removable substrate. It can be a silicon substrate that has been subjected to a hydrogen implantation step ('Smart Cut™' process), or a substrate chosen so that the bonding energy between the donor substrate 10 and the functional block is less than the bonding energy between the functional block and the recipient substrate 20 or the bonding energy between the functional block and another functional block (depending on the position of the functional block in the stack covering the recipient substrate 20).

[0072] It may also be a composite substrate comprising a support substrate covered by a release layer. For example, the release layer is an adhesive layer whose adhesion properties can be reduced by the application of ultraviolet radiation or by applying a heat treatment.

[0073] According to an alternative method, the donor substrate 10 can comprise one or more metal-dielectric levels forming the BEOL of the function, the first metal level formed on the donor then corresponds to the connection layer 110.

[0074] During steps Le) and Le'), the transfer step implements a direct bonding step followed by a separation step. Direct bonding is a bonding technique that does not require the addition of material.

[0075] The functional layer 130 is bonded to the donor substrate 10 or to the second temporary substrate 40 by direct bonding. This type of bonding consists of bringing the surfaces to be bonded into contact without the addition of any material, using the following preparations: mechano-chemical surface activation polishing and / or chemical cleaning and / or mechanical cleaning (Megpie®, 'scrubber') and / or plasma activation (He or N2, for example) and / or SAB (surface activated bonding). These preparations allow the bonding of the composite metal-dielectric surface to the substrate. The direct bonding can be followed by annealing to consolidate the bond in the range of 100-500°C.

[0076] When the temporary substrate 30, 40 is separated, all or part of the substrate 30, 40 can be removed. For example, as part of the implementation of the technology With Smart Cut™, only a portion of the substrate 40 is separated. The implanted portion remains bonded to the functional layer 120. The remaining portion can be retained or removed.

[0077] The removal of the temporary substrate 30, 40 can be achieved by mechanical and / or chemical thinning from the face opposite the functional layer 130. In the case of an SOI substrate, the temporary substrate 30, 40, made of silicon, can be removed by selective silicon etching of the buried oxide layer: for example, dry etching using SF6 or wet etching using TMAH. In the case of a substrate 30, 40 including a buried brittle interface 36, the removal of the temporary substrate 30, 40 is carried out by fracturing at the brittle zone, by applying mechanical stresses to the bonded structure (blade insertion, traction, peeling, etc.).

[0078] During step i.e'), the width and length of the parts of the functional blocks are defined by the cutting lines according to the defined 3D stacking.

[0079] Preferably, each cut-out portion corresponds to an electronic chip. The thickness of the reported chip can vary between 0.5 µm and 30 µm, preferably between 2 µm and 1 µm depending on the intended application.

[0080] During step iv), the bonding is a direct metal-dielectric bond. The planarization performed for steps Le), Le'), and Id) remains compatible, after removal of the donor, with the bonding of two mixed metal-dielectric surfaces. In the case of plate-to-plate bonding, the interconnection pitch at the bond pads can reach 400 nm or even 50 nm. The thickness of each plate is, for example, on the order of 300 µm to 1000 µm. In the case of chip-to-plate bonding, the interconnection pitch can reach 1 µm or even 200 nm using chip self-assembly techniques. The chip thickness is, for example, on the order of 1 µm to 1000 µm, or even 2 µm to 1000 µm. The direct bonding can be followed by annealing to consolidate the bond in the 100–500°C range.In the case of a heterogeneous assembly involving different materials, bonding can be assisted by SAB ('Surface Activated Bonding') to limit the overall thermal budget of the assembly, as SAB allows for very good adhesion of the layers even at room temperature.

[0081] It is possible to obtain a dense stacking of ultra-fine functions.

[0082] During step i.g'), the dielectric may include TDV ('Through-Dielectric-Vias') type Vias.

[0083] Thus, we obtain a donor substrate 10 of which a first face is covered by a functional block 100 comprising the functional layer 130, arranged between the first interconnection layer 110 and the second interconnection layer 120, the surfaces of each interconnection layer being planarized.

[0084] Each interconnecting layer 110, 120 comprises a dielectric material 111, 121 in which conductive elements 112, 122 are formed. The conductive elements 112, 122 form electrically conductive tracks. The conductive elements are preferably made of copper. The dielectric layer 111, 121 is, for example, made of an oxide or a nitride. In particular, the dielectric layer is made of SiO2.

[0085] The functional layer 130 comprises a functional part and electrical contacts for connecting the functional part to the interconnection layers. It could also comprise several functional parts.

[0086] Functional layer 130 comprises one or more active electronic components. It may include active electronic components (transistors, diodes, etc.) and / or passive electronic components (resistors, capacitors, etc.).

[0087] The function of the functional layer is a microelectronic function, for example a computing function, memory, RF filters, optical amplifiers, etc.

[0088] The electrical contacts are chosen according to the functional part. They are developed using known microelectronic technologies.

[0089] The first interconnection layer 110 may comprise one or more damascene levels. For example, the first interconnection layer 110 may consist of a so-called 'VIA' ('Hybrid Bonding Via') level connected to the contacts of the functional layer 130, and then a so-called 'METAL' ('Hybrid Bonding Metal') level formed above the VIA level. The so-called 'METAL' level forms the hybrid bonding surface. It may comprise electrical metal pads (connected to the vias) and so-called 'dummies' pads (not connected to the vias) such that the metal density on the surface of the first interconnection layer 110 is on the order of 25%.

[0090] The dimensions of the pads are, for example, in the range of 100 nm to 100 µm, advantageously in the range of 500 nm to 5 µm. This density allows for homogeneous polishing of the composite metal / dielectric surface to be bonded. Advantageously, the layers that make up the first interconnecting layer are manufactured in such a way as to limit planarization CMPs, for example by using the well-known double-Damascene process. The first interconnecting layer may include alignment marks for bonding.

[0091] The second interconnection layer 120 may comprise a single TSV level or a TSV level and one or more Damascus levels. The TSV level enables connection to the contacts of the functional layer 130 and / or to a higher level (for example, with the first interconnection layer 110). The Damascus level(s) that form the second interconnection layer 120 may be constructed in the same way as those of the first interconnection layer 110. In particular, the metal density on the bottom surface of the second The interconnecting layer 120 is approximately 25%, and the pad dimensions are, for example, in the range of 100 nm to 100 µm, advantageously in the range of 500 nm to 5 µm. The second interconnecting layer 120 may also include alignment marks for bonding.

[0092] The interconnection layers 110, 120 described in this application can be obtained by a Damascus-type process and / or a 'via formation' (TSV, TDV) type process.

[0093] Typically, the Damascus process can include the following technological steps: - deposition of a layer of a dielectric material, for example with a thickness between 50nm and 50pm, - formation of through-vias in this layer of dielectric material, by photolithography and etching of the dielectric material. - deposition of a stack comprising sub-layers (adhesion sub-layer, diffusion barrier sub-layer, metal seed), - filling of vias by electrochemical deposition (ECD for 'ElectroChemical Deposition') of the metal, - Chemical-mechanical polishing (CMP or 'Chemical-Mechanical Polishing') of the metal until a mixed metal-dielectric surface is obtained.

[0094] This sequence of steps can be used to realize the BEOL ('Back-End-Of-Line') of microelectronic components.

[0095] During step iii), step i) is repeated to form another functional block 200. Step iii) can be implemented once or several times.

[0096] Each functional block 100, 200, 300, 400, 500 may include identical or different functional parts, contacts and / or connections. The choice of functional blocks 100, 200, 300, 400, 500 depends on the defined 3D stacking.

[0097] In step iv), the functional blocks 100, 200, 300, 400, 500 formed are transferred from the temporary donor substrate to a receiving substrate 20. The functional blocks 100, 200, 300, 400, 500,... are transferred one after the other onto the receiving substrate 20. It is possible to use a donor substrate 10 comprising a stack of several functional blocks. During the transfer step, the stack of functional blocks from the donor substrate is transferred to the receiving substrate 20. At the end of step iv), a 3D assembly is obtained comprising a receiving substrate 20 and a stack comprising N functional blocks, with N an integer greater than or equal to 2 ([Fig. 7A]).

[0098] The receiving substrate 20 can be covered by an interconnecting layer 150 comprising a dielectric material 151 in which conductive elements 152 are formed ([Fig. 6]). The functional active block is then transferred onto the layer interconnection layer 150 covering the receiving substrate 20. The first interconnection layer 110 of the functional block 100 being arranged opposite and in contact with the interconnection layer 150 of the receiving substrate 20.

[0099] The receiving substrate 20 can be covered by one or more functional blocks before the implementation of step iv). The receiving substrate 20 can be of the same nature as the donor substrate 10. The receiving substrate 20 can subsequently play the role of donor substrate, i.e. the stack formed on the receiving substrate can then be transferred to another receiving substrate.

[0100] The transfer of the functional blocks onto the receiving substrate 20 can be carried out according to the following steps: - assemble the donor substrate 10 with the recipient substrate 20, by direct bonding of the functional block 100 of the donor substrate 10 onto the recipient substrate 20, or, where appropriate, onto the interconnecting layer 150 of the recipient substrate 20, or if the recipient substrate 20 is already covered by a functional block, onto the functional block, - separate the donor substrate 10 from the assembly thus obtained.

[0101] Direct bonding is applied to heterogeneous dielectric / metal surfaces (interconnection surfaces) and to homogeneous surfaces (dielectric or donor substrate surface).

[0102] The removal of the donor substrate 10 can be achieved by mechanical and / or chemical thinning from the face opposite the functional layer 120. In the case of a substrate 10 having a layer implanted with H+ and / or He ions, the removal can be achieved by applying thermal and / or mechanical stresses, for example by annealing in the 200°C-500°C range followed by the insertion of a blade. In the case of a donor substrate having a buried or surface brittle layer, the removal is achieved by fracturing at the level of the brittle zone, by applying mechanical stresses to the bonded structure (blade insertion, tension, peeling, etc.).

[0103] According to one embodiment, it is possible to transfer onto the receiving substrate 20, in addition to the functional blocks previously described, one or more blocks having optical functions (LEDs, imagers, photovoltaic cell, etc.) as described in European patent EP 3 769 339 Bl.

[0104] According to one embodiment, as shown in Figures 7A to 7C, the method may include a subsequent step in which the receiving substrate 20 and the resulting stack of active blocks 100, 200, 300, 400 ([Fig. 7A]) are transferred onto a temporary support 60 ([Fig. 7B]), for example, an adhesive support ('tape'). The assembly is then cut into chips ([Fig. 7C]). For example, this could be done mechanically, in particular by sawing. [Fig. 8] shows a top view of the cut device.

[0105] The receiving substrate 20 can then be removed. It is possible to remove all or part of the receiving substrate before cutting the chips.

[0106] This embodiment is particularly advantageous when chips comprising an assembly of 120 functional layers need to be assembled with other electronic chips. The cutting step leads to the individualization of the chips. The size of the chips (length, width) is defined by the cutting lines according to the defined 3D stacking.

[0107] The resulting stacks of chips 1000 ([Fig. 9A]) can then be transferred from the adhesive support 60 onto a final substrate 70 ([Fig. 9B]), in particular a packaging substrate. The substrate 70 can be, for example, a laminated substrate or a printed circuit board. However, the final assembly of the chips onto the substrate 70 is achieved, for example, by metal-dielectric bonding (direct bonding and / or bonding with added material). Metal-dielectric bonding with added material is an assembly process in which the stack of chips is assembled onto copper pads 72 of the substrate 70, using a solder 73, for example, made of a CuNiAu alloy or a tin-based alloy, in particular the SnAg alloy. The soldering step can be carried out at a temperature in the range of 100-300°C.

[0108] It is possible to repeat the steps to obtain several stacks of different chips themselves made up of an assembly of functions, which can have different sizes and / or different thicknesses ([Fig.9B]).

[0109] Following the final assembly of the chips 1000 on the packaging substrate, the chips 1000 can be protected by encapsulating them in a layer of insulating material 80 ([Fig. 9C]). The insulating material 80 can be deposited by dispensing or by molding. The insulating material can be a polymer or a resin. The final routing can be achieved, for example, by forming a non-Damascene redistribution layer 81 ([Fig. 9D]).

[0110] The process described above makes it possible to manufacture a 3D assembly comprising a receiving substrate 20 on which are stacked at least two functional blocks 100, 200, preferably at least 5 functional blocks, even more preferably at least 10 functional blocks, each functional block 100, 200 comprising a functional layer 130, comprising one or more electronic components, arranged between two interconnecting layers 110, 120, the interconnecting layers 110, 120 comprising a dielectric material 111, 121 in which conductive elements are formed, preferably of copper.

[0111] Each functional block 100, 200 is planar. In other words, its principal faces are planar and parallel to each other.

[0112] The assembly may comprise more than 20 functional blocks, or even more than 50 functional blocks stacked on top of each other.

[0113] The pitch of the interconnections is less than 10 pm, preferably less than 5 pm. It can be on the order of 1 pm. The pitch can be smaller. For example, it is less than 200 nm, or even less than 100 nm. With a reduced pitch, the 3D assembly exhibits a high interconnection density, for example, up to 1 million connections per mm² for a pitch of 1 pm. This makes it possible to miniaturize the electronic devices.

[0114] It is thus possible to assemble features from different materials without creating thermal stresses during assembly by using a suitable donor and cold hybrid bonding (SAB). The entire assembly is carried out cold, which is particularly advantageous when the features are made from different materials (for example, InP and Silicon,...).

[0115] The 3D stacking obtained, based on the multiple transfer of active layers having structured Metal-Dielectric connections from removable substrates, for the assembly and interconnection of electronic components can be used in many fields.

[0116] The process described above opens up new perspectives. For example, it makes it possible to create new, original and efficient assemblies, in particular by combining a 3D assembly control system with the described technology called HSA (Hybrid Smart Assembly technology).

[0117] From the functions to be assembled for the intended application, it is possible to determine in advance several possible assemblies and to choose one according to particular criteria.

[0118] The method for determining the steps in a manufacturing process for a 3D assembly includes, for example, the following steps: - Define the functions of the desired 3D assembly, - to simulate the assembly of the different elements of the 3D assembly, with different types and dimensions of the different functional blocks and / or substrates, and / or with different stacking orders of the functional blocks, thereby selecting a first manufacturing process for the 3D assembly.

[0119] At least one other manufacturing process for the 3D assembly is obtained and compared to the first potential manufacturing process for the 3D assembly, according to several criteria, for example in terms of feasibility, technical risk, functionality, cost and / or environmental impact, so as to retain the most suitable manufacturing process for the 3D assembly.

[0120] Several potential processes can thus be determined and compared.

[0121] The technology described above allows the assembly of any type of function according to an adapted methodology and manufacturing chain.

[0122] The final 3D assembly (object or system) is known and defined beforehand. In particular, the desired functions and connections are defined.

[0123] The size of the final chips is defined in relation to the functions to be assembled and the desired purpose. For example, for an imager integrating 3 functions (logic, memory and image capture), the size of the assembled chip will be defined by that of the image capture chip in order to optimize optical efficiency.

[0124] HSA technology is described in specific Design Kits ('Design Kits' or DKs), for example chosen from: 'Process Design Kit', 'Assembly Design Kit', 'Chiplet Design Kit', and 'Material Design Kit'.

[0125] A Design Kit specific to eco-design is included, which compiles Life Cycle Assessment (LCA) data related to the manufacturing of interconnects (Damascene, vias, bonding, shrinkage, etc.). LCAs related to the manufacturing of components can be added to this DK.

[0126] The assembly of functions is simulated with different scenarios: - Adapting the designs / technological nodes to adjust each function to the final chip size, - adaptation of HSA technology: choice of substrates, type of connection, stacking order, thicknesses, etc.

[0127] For example, for an imager, the logic chip can be chosen with a relaxed node to be the same size as the image capture chip while being inexpensive (rather than an advanced node that produces smaller and more expensive chips). The memory chip can be in an advanced node, smaller than the image capture chip, with connections at the edge of the memory function.

[0128] Each scenario is evaluated in terms of feasibility, technical risk, functionality, cost and environmental impact

[0129] For example, in the case of a GaN LED-based emissive screen, a scenario incorporating a photovoltaic layer whose absorption is adjusted to the emission wavelength of the LED is compared to a scenario without this PV layer, in order to quantify the environmental and economic impact of this layer: material consumption, cost and impact of manufacturing a photovoltaic cell versus the reduction in the system's energy consumption,...

[0130] The manufacturing of the chips is then carried out according to the selected scenario.

[0131] It is therefore possible to have one or more functional layers manufactured by different microelectronic component companies (such as fabless, IDM, etc.) according to their own design, using a suitable material, in a factory of manufacturing of its choice according to its own technological and environmental roadmap.

[0132] The functional layers 130, 230, 330, 430 are supplied by the manufacturers on initial substrates 91, 92, 93, 94 ([Fig. 1OA]). A first interconnecting layer is formed on each functional layer 130, 230, 330, 430, then the first interconnecting layer and the functional layer 130 are transferred onto a donor substrate 10, according to the steps previously described, for example shown in Figures 3A to 3F or 4A to 4L. The initial substrates 91, 92, 93, 94 play the role of initial temporary substrate 30. After formation of the second interconnection layer and planarization, the functional blocks 100, 200, 300, 400 are formed ([Fig.1OB]) and can be transferred onto the same receiving substrate 20 ([Fig.1OC]).

[0133] In this context, the 3D assembly of chips or substrates ('wafers') is greatly facilitated, because the process makes it possible to overcome the incompatibility problems that can be found with different substrates and / or different manufacturing technologies.

[0134] In this context, the incompatibility problems which currently limit the adoption of 3D assembly are addressed upstream and the assembly of multiple functions according to HSA technology is feasible.

[0135] It is therefore possible to optimize assemblies from their design stage, while integrating environmental control.

[0136] The 3D assembly control system optimizes the functionality and costs of assemblies from the design stage. Furthermore, within an eco-design approach, the environmental impact can be taken into account and significantly reduced.

[0137] It is thus possible to integrate a 3D assembly control system from chip design to the production of systems or objects. This control of the design and manufacturing chain makes it possible, in particular, to reduce the impacts on the natural environment, resource consumption, and human health, while also reducing manufacturing costs.

[0138] The different stages can be handled by specific software using artificial intelligence. This is interesting because the data to be processed for effective control of the 3D assembly at all levels is very large: feasibility, functionality, cost, environmental impact, etc.

[0139] Illustrative and non-limiting example(s)

[0140] 1st example: High-bandwidth memory

[0141] In this example, a high-bandwidth memory (HBM) is manufactured. For this purpose, HBM chips with dynamic random access memory are used. Synchronous DRAM chips are manufactured. These chips are called HBM DRAM chips (or 'HBM DRAM Die'). Functional blocks called 'compute' and 'logic' can be associated with HBM memory, for example, to form a graphics card.

[0142] By way of example, according to the current process, HBM DRAM chips containing TSVs are connected together using conventional component assembly technologies (for example, by 'micro-bumps' or 'Pick-And-Place' technologies).

[0143] The memory chips, 'compute' and 'logic', are connected by means of an interposer incorporating TSVs. This interposer is assembled onto the final substrate by means of copper bumps. The total surface area is at least equal to that of the HBM chip + that of the compute chip + that of the logic chip. The thickness of the HBM chip is limited to 775 µm, which corresponds to a maximum of 16 levels of DRAM currently available.

[0144] We will now describe in more detail the manufacturing process of the high-bandwidth memory according to a particular embodiment of the invention, by referring, firstly, to figures 1 IA to 1 IG.

[0145] The DRAM functional layers are fabricated from 300mm SOI 30 substrates having a BOX 38 layer using 22nm FDSOI technology. So-called NO DUM areas, i.e., areas without silicides, are provided for the subsequent passage of TSVs. The DRAM functional layers are fabricated up to their contact levels. The thickness of a DRAM functional layer is, for example, on the order of 1 to 3 µm. The silicon support substrate 31 is thus covered with a SiO2 38 layer and the DRAM functional layer 130 comprising one or more DRAM chips ([Fig. 11 A]).

[0146] A first interconnection layer 110 is formed on the functional layer 130. The interconnection layer 110 comprises a first interconnection level formed on a first face of the functional layer and a second interconnection level formed on the first interconnection level using a double-Damascene Copper technology. The interconnection levels are chosen such that the first interconnection level connects the DRAM contacts and certain metal pads of the second interconnection level. The second interconnection level includes alignment marks for bonding and its Cu density is approximately 25%. The size of the metal pads of the second interconnection level is approximately 200 nm to 1 Opm ([Fig. 1 IB]).

[0147] The DRAM 130 functional layer and the interconnect levels are transferred onto a silicon donor substrate 10 by direct bonding and removal of the SOI substrate (for example, by means of mechanical polishing and liquid etching, for example with a TMAH solution) ([Fig.1 IC]).

[0148] The second interconnection layer 120 is then formed on the SiO2 layer 38. TSVs are formed from the SiO2 layer 38 to the first interconnection layer 110. These TSVs traverse the SiO2 layer 38 of the SOI, and the silicon functional layer 130 in which the DRAMs are fabricated (the TSVs traverse at the NO DUM areas), and the first interconnection level 110. An interconnection level is then formed on the TSV level so that it is connected to certain pads of the first interconnection layer 110. This interconnection level 120 includes alignment marks for bonding and its Cu density is on the order of 25%. The size of the metallic pads is on the order of 200 nm to 1 Opm.

[0149] The assembly thus formed corresponds to the first functional block DRAM1 on a Silicon donor ([Fig. 11D]). This assembly then acts as the receiving substrate.

[0150] Collectively, 64 assemblies comprising a donor substrate and a DRAM functional block are formed (DRAM1 to DRAM64) and are thus manufactured.

[0151] Each interconnection layer 110, 120 has been subjected to 2 CMP planarization. Each functional block has its two surfaces (upper and lower) ready for bonding.

[0152] The assembly of the HBM takes place in several stages.

[0153] In a first step, the hybrid bonding of the DRAM2 functional block is carried out on the DRAM1 functional block and then the donor substrate 10 of DRAM2 is removed ([Fig.llE]).

[0154] Bonding is achieved using Cu-SiO2 activation CMP such that the roughness is less than 6 nm RMS and the height difference between the SiO2 and Cu is less than 15 nm, with the Cu level located below that of the SiO2. The surfaces are then cleaned with a rinse combined with ultrasonics and NaOH-type chemistry. The substrates are brought into contact in a hybrid industrial bonding system equipped with an alignment module. Annealing at 200°C is applied to consolidate the structure. The silicon substrate is removed by mechanical thinning to a thickness of 20 µm, followed by TMAH etching. This results in a stack of two functional blocks, DRAM1 and DRAM2, on a substrate 20 µm. These steps are repeated to form other stacks of functional blocks.

[0155] In a second step, hybrid bonding of two stacks of two functional blocks is carried out ([Fig. 11F]), followed by the removal of the silicon donor substrate 10. This yields recipient substrates 20 covered with 4 functional blocks (for example, DRAM1 to DRAM4 in [Fig. 11G]).

[0156] The gluing steps are repeated until a stack of 64 functional DRAM blocks is obtained on the Silicon substrate 20, i.e. 6 block transfers (6 gluings + 6 withdrawals). The thickness of the 64 levels composing the HBM memory is on the order of 200 µm. The silicon substrate can typically have a thickness of 500 µm to 700 µm.

[0157] Donor substrates 10 comprising Compute functional blocks and Logic functional blocks are manufactured in the same way as the DRAM blocks previously described (Figures 12A, 12B, 12C and 12D).

[0158] The DRAM functional block stack is transferred to the COMPUTE functional block, and the silicon donor substrate 20 on which the DRAM functional block stack was placed is removed. The LOGIC functional block is transferred to the DRAM functional block stack, and the silicon substrate on which the LOGIC functional block was placed is removed ([Fig. 12E]).

[0159] The assembly is cut and assembled with a final substrate 70 by means of brazing alloy pads 73 ('bumps') ([Fig. 12F]).

[0160] The structure thus formed allows for a closer proximity of the components, an increase in the number of memory layers, an increase in the interconnection density which are advantageous for increasing its performance (in particular power consumption) and functionality.

[0161] It also allows a reduction in the amount of metal used, a decrease in electricity consumption, a reduction in the materials composing the structure (therefore a reduction in its heating) which are advantageous for reducing the environmental impact.

[0162] 2nd example: Processor for artificial intelligence

[0163] In this example, integrated circuits (ASICs), approximately 20 mm x 30 mm in size, specialized for 1TA, are manufactured by a primary foundry on a 300 mm wafer using known microelectronic technologies, at an advanced node (5 nm or 7 nm) to optimize component density. Depending on the foundry's design and manufacturing processes, each circuit is typically separated from the others by slitting paths with a width of 10 to 100 pm. However, the 300 mm substrate can be used as a single chip of approximately 25 cm x 25 cm to obtain a substrate-scale chip, easily integrated into data center racks.

[0164] To increase system performance (heat dissipation, latency, etc.), it may be advantageous to use optical rather than electrical links to improve the connection between circuits on the surface of the final chip. This requires connecting the ASIC circuits to photonic circuits. Further to increase performance, it may be beneficial to add a memory layer to support the calculations performed by the ASIC circuits. This requires connecting the ASIC circuits to memory circuits.

[0165] The stacking and design of the components is simulated using the control system in order to determine the manufacturing technologies for the ASIC, memory and functions photonics (technological node,...), the order in which these functions should be stacked and what type of connection (size, spacing, ...) should be used to optimize the performance, cost and ecological footprint of the processor made up of the 3 functions.

[0166] In this example, the optimal system is considered to be that represented in [Fig.13].

[0167] The receiving substrate 20 comprises a silicon substrate 21, an ASIC circuit 22, and an interconnect layer 150. The ASIC circuit 22 and the interconnect layer 150 form the block denoted 'ASIC'. The ASIC circuit 22 is fabricated by a first foundry on a solid silicon substrate 21 ([Fig. 14]). To be compatible with the invention, the last metal layer MZ of the ASIC circuit 22 is designed to be connected to a DRAM memory functional block by hybrid copper-SiO2 bonding. It therefore includes alignment marks for bonding and its Cu density is approximately 25%. The connection pads are complemented by unconnected 'dummies' pads (denoted D in [Fig. 14]), which allow for the most favorable Cu density for hybrid bonding. The dimension of the metal studs of the MZ level is 400nm.

[0168] In parallel, a functional layer 130 comprising a DRAM memory circuit is fabricated by a second foundry on an SOI 30 substrate ([Fig. 15A]), with NO DUM areas free of silicide at the level of the subsequent TSVs. A first interconnect layer 110 (denoted 'Metal 1') is formed on the front end of the line (FEOL for 'front end of line') of the DRAM circuit, and then several routing levels are fabricated, with a design adapted on the last DRAM1 level to be subsequently connected to a photonic functional block (denoted 'Photonic') by hybrid Copper-SiO2 bonding. Again, the last DRAM1 level includes alignment marks for bonding, 5 µm dimension connection pads, and a Cu density of 25% obtained by active connection pads and 'dummies' pads ([Fig. 15A]).The assembly is then bonded to a donor Si substrate 10 by direct bonding. The Silicon 31 substrate of the initial SOI 30 substrate is removed by mechanical and / or chemical thinning, stopping at the BOX 38 of the SOI ([Fig.15B]). TSVs are formed by etching the BOX, the SOI at the NO DUM areas, and the first Metal 1 level so as to contact the Metal 1 level. An interconnect layer 120, obtained by creating a routing Damascus layer and DRAM2 connections, is then created on the TSVs, whose design is adapted to be connected to the MZ level of the ASIC functional block ([Fig.15C]).

[0169] In parallel, a photonic functional layer 230, comprising in particular functions for transforming electrical signals into optical signals, functions for transporting light, for data processing, for example at The means of laser components, waveguides, and data conversion elements ('serdes') is fabricated on a double-SOI 30 substrate, for example, 300 mm thick, by a third foundry. The double-SOI 30 substrate comprises: a bulk Si substrate 31, a first buried oxide layer 32 (BOX) 3 µm thick, a resistive silicon layer 33 30 µm thick, a second buried oxide layer 34 2 µm thick, and a crystalline silicon layer 220 nm thick ([Fig. 10A]). The photonic FEOL includes NO DUM zones at the subsequent TSVs. Interconnection levels 110 are obtained by performing a BEOL damascene on the photonic functional layer 130 and then covered with a planarizing oxide layer. The photonic substrate is then glued by direct bonding onto a Silicon donor substrate 10 having a slightly rough oxide surface in order to obtain a low bonding energy, less than 1 J / m2.The bulk Si substrate 31 is removed by mechanical thinning and selective chemical etching of the Silicon, stopping at the 3µm thick BOX ([Fig. 10B]). TSVs are formed in the 3µm thick BOX 32, in the 30µm thick resistive Si 33, in the second BOX 34 (2µm thick), and in the photonic FEOL 230 at the NO DUM zones up to the Metal 2 level of the BEOL, so as to connect it. An interconnection layer 120 is obtained by creating a Damascus routing and connection level on the TSVs, the design of which is adapted to be connected to the DRAM1 level of the DRAM donor ([Fig. 16C]).

[0170] This yields: - an ASIC 20 substrate ready for assembly, - a functional DRAM block on a donor substrate 10 ready for assembly, - a functional Photonic block on a donor substrate 10 ready for assembly.

[0171] The DRAM block is transferred to the ASIC block by hybrid aligned bonding ([Fig. 17A]) and mechanical removal of the Si donor ([Fig. 17B]). The photonic block is then transferred to the DRAM block by hybrid aligned bonding ([Fig. 17C]) and breaking of the weak bond interface ([Fig. 17D]) by the application of mechanical stresses (insertion of a blade, etc.).

[0172] The desired stacking is obtained. Local etching of the oxide above the last metal level of the photonic BEOL allows the contacts to be re-established.

[0173] Example 3: Heterogeneous assembly for RF

[0174] In this example, an industrial method is proposed for integrating InP-based double heterojunction bipolar transistors (DHBTs) on a Silicon digital circuit for ultra-high frequency (THz) RF applications.

[0175] One problem with InP-based active circuits is the very high cost of the InP material. Significant efforts are being made to limit the amount of material used, by using very small chips (down to 0.5 x 0.5 mm²) mounted on Si. The active InP portion used (DHBT area) has a total thickness of The InP thickness required for the RF circuit fabrication is on the order of 500 to 700 µm. An antenna is then applied to the free surface of the InP chip, formed, for example, by a stack of metal / dielectric layers, and connected to the InP chip. CMOS logic circuits are also required to drive the entire assembly.

[0176] The stacking and design of the components is simulated using the control system to determine the manufacturing technologies for the logic, digital, and RF functions (technology node, materials, etc.), the order in which these functions should be stacked, and what type of connection (size, spacing, etc.) should be used to optimize the performance, cost, and environmental footprint of the processor composed of the three functions. Particular attention is paid to reducing the consumption of InP material, with both environmental and economic objectives in mind.

[0177] Here, the optimal system is considered to be that represented in [Fig. 18] and [Fig. 19].

[0178] The DHBT function has dimensions of Ixlmm2, the CMOS functions 2x5mm2 and the passive RF functions on high resistivity Si substrate have dimensions of 5.5 x 5.5mm2.

[0179] According to one embodiment, DHBT transistors are fabricated from an advanced 200 mm diameter substrate consisting of a solid 30 sapphire wafer with InP vignettes measuring 1 x 1 mm² and 0.5 µm thick. Since InP substrates are not available in a 200 mm diameter, and to reduce material consumption, these vignettes can be obtained using known technologies such as rebuilt wafer (with Si substrates containing unprocessed InP chips) and film transfer (application of Smart Cut™ technology to the rebuilt wafer). The InP vignettes are spaced 5.5 mm apart to allow for the subsequent integration of CMOS functions without blocking the RF signals emitted by the DHBT. The Sapphire 30 substrate comprises a Sapphire 31 bulk substrate covered by sacrificial nitride layers 36 compatible with substrate removal according to the Laser Lift Off (LLO) technique.A first Damascus interconnection level 110 is implemented to connect the InP transistors, followed by a second routing and connection level DHBT1, the design of which is adapted for connection to the last metal layer of the CMOS ([Fig. 20A]). The connection pitch is on the order of Ipm. The DHBT function is transferred to a 200 mm sapphire donor 10 (comprising a solid sapphire substrate 11 covered by a nitride layer 12) by direct oxide-oxide bonding and removal of the initial sapphire substrate 30 by LLO (laser beam exposure of the back face of the sapphire 31, which degrades the nitride layers 36). The direct oxide-oxide bonding includes the insertion of nitride layers onto the sapphire donor ([Fig. 20B]). TSVs are then formed through the bonding oxide layers used for Smart CutTM and through ITnP and an interconnection layer 120 formed from a damascene routing and connection level. DHBT2 is then implemented on the TSVs, whose design is adapted for connection to the digital function ([Fig. 20C]). A functional block labeled 'DHBT' is thus obtained. The connection pitch is approximately 5 pm.

[0180] In parallel, a digital circuit 24 is formed on a 200 mm high resistivity Si substrate 21, so as to limit RF losses in the final substrate 20 ([Fig. 21]). The last metal layer of the digital circuit is adapted to be connected to the DHBT function.

[0181] In parallel, CMOS circuits are formed on a 200 mm SOI 30 substrate to form a functional layer 230. The Si layer 33 located above the buried oxide 32 has a thickness of 1 µm, while the CMOS components have a thickness on the order of 1 to 2 µm. A first interconnection layer 110, comprising a CMOS1 routing and connection Damascus level, is connected to the CMOS circuits. Its design is adapted for connection to the DHBT function ([Fig. 22A]). TSVs are formed from the FEOL of the CMOS to the BOX. The CMOS function is then transferred to a Silicon donor substrate 10 by bonding and removing the Si 31 located under the BOX 32 ([Fig.22B]) and a second interconnection layer 120 formed of a damascene routing and CMOS connection level is then made on the TSVs, whose design is adapted for the final packaging connections.The assembly is placed on a 60 adhesive substrate ('tape'), thinned to the BOX and cut into 1000 chips of 2x5mm2 ([Fig.22C]). .

[0182] This gives us: - a functional DHBT block on a 10mm sapphire donor substrate, 200mm, ready for assembly, - a functional CMOS block on a 200mm Si 10 donor substrate, ready for assembly, - a Digital RF 20 receiver substrate in Si 200mm ready for assembly.

[0183] The DHBT block is transferred to the Digital block at wafer scale by SAB-assisted hybrid aligned bonding and LLO-assisted sapphire removal. The SAB bonding is performed at room temperature. The implementation of SAB bonding eliminates the need for bond consolidation annealing thanks to the efficiency of surface activation. The transfer of InP DHBT chips from a sapphire substrate to a Si substrate can therefore be carried out entirely at room temperature. This process thus eliminates thermo-mechanical stresses during and after assembly, thereby avoiding cracking and even delamination problems that can be observed in the case of direct InP-on-Silicon transfer.

[0184] The cut and thinned CMOS blocks are then attached to the DHBT block by hybrid bonding aligned in a chip-to-plate manner. The CMOS chips on tape are assembled onto the DHBT / digital stack using a so-called 'pick and place' device. compatible with direct bonding (i.e. without particles, including surface cleaning, ...) and Ipm pitch chip alignment.

[0185] This gives us a CMOS / DHBT / Digital stack on a high resistivity Si substrate ([Fig.23]).

[0186] The classic RF packaging steps are then applied: dispensing of BCB resins, formation of a redistribution layer ('Redistribution Layer') in the BCB layers, cutting into 5.5x5.5mm2 chips for packaging.

[0187] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0188] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing a 3D assembly comprising the following steps: - providing at least two assemblies, each comprising a donor substrate (10) covered by a functional block (100, 200) successively comprising a first interconnecting layer (110), a functional layer (130, 230) and a second interconnecting layer (120), the functional layer comprising one or more electronic components, the first interconnecting layer and the second interconnecting layer (110, 120) comprising a dielectric material (111, 121) in which conductive elements (112, 122) are formed, preferably of copper, a first surface of the first interconnecting layer (110) in contact with the donor substrate (10) and the free surface of the second interconnecting layer (120) being planarized so as to be compatible with subsequent direct bonding, - transferring, successively,on a receiving substrate (20) the functional blocks (100, 200), by direct bonding, the conductive elements (112) of the first interconnection layer (110) of the first functional block (100) being opposite and in contact with the conductive elements (122) of the second interconnection layer (120) of the second functional block (200), thereby obtaining a 3D assembly comprising a receiving substrate (20) covered by a stack of two functional blocks (100, 200).

2. A method according to the preceding claim, wherein at least 5 functional blocks (200, 300, 400, 500), preferably at least 10 functional blocks, are transferred successively onto the receiving substrate (20).

3. A method according to any one of the preceding claims, wherein after the transfer of the functional blocks (100, 200), the method comprises the following steps: - gluing the 3D assembly onto an adhesive (60), - cutting the receiving substrate (20) and the functional blocks (100, 200) and removing the receiving substrate (20), thereby obtaining several stacks of individualized functional blocks (100, 200), - optionally, stick the different stacks of individualized functional blocks (100, 200) onto an external element, such as a printed circuit board or a laminated substrate.

4. A method according to any one of the preceding claims, wherein one of the functional blocks (100, 200) partially covers the donor substrate (10), interconnection blocks (140) being arranged, on the donor substrate (10), on each side of said functional block (100, 200) and wherein said functional block (100, 200) and the interconnection blocks (140) are transferred simultaneously onto the receiving substrate (20).

5. A method according to any one of the preceding claims, wherein at least one of the assemblies is obtained by the following steps: - providing a temporary substrate (30) covered by the functional layer (130, 230), - forming the first interconnection layer (110) on a first face of the functional layer (130, 230), and planarizing it, - transferring the first interconnection layer (110) and the functional layer (130, 230) onto the donor substrate (10), by gluing the donor substrate (10) onto the functional layer (130, 230) and separating the temporary substrate (30), - forming the second interconnection layer (120) on a second face of the functional layer (130, 230), - planarizing the second interconnection layer (120).

6. A method according to any one of the preceding claims, wherein some or all of the functional blocks (100, 200, 300, 400, 500) comprise electronic chips.

7. A method for determining the steps of a manufacturing process for a 3D assembly, the determination method comprising the following steps: - defining the functions of the 3D assembly, the 3D assembly comprising a substrate (20) and a stack of different functional blocks (100, 200, 300, 400, 500), each functional block (100, 200, 300, 400, 500) comprising a functional layer (130, 230, 330, 430, 530), comprising one or more electronic components, arranged between two interconnecting layers (110, 120), the interconnecting layers (110, 120) comprising a dielectric material (111, 121) in which conductive elements (112, 122) are formed, preferably made of copper, each functional block (100, 200, 300, 400, 500) being planar, - simulate the 3D assembly by choosing different natures and / or dimensions of the substrate (20) and / or of the functional blocks and / or by choosing different stackings of functional blocks, thereby selecting a first manufacturing process of the 3D assembly.

8. A method according to the preceding claim, wherein at least one other method for manufacturing the 3D assembly is defined and compared to the first method for manufacturing the 3D assembly, according to several criteria, for example in terms of feasibility, technical risk, functionality, cost and / or environmental impact, so as to choose the most suitable method for manufacturing the 3D assembly.

9. A 3D assembly comprising a receiving substrate (20) on which are stacked at least two functional blocks (100, 200), preferably at least five functional blocks (100, 200, 300, 400, 500), more preferably at least ten functional blocks, each functional block (100, 200, 300, 400, 500) comprising a functional layer (130, 230, 330, 430, 530), comprising one or more electronic components, arranged between two interconnecting layers (110, 120), the interconnecting layers (110, 120) comprising a dielectric material (111, 121) in which are formed conductive elements (112, 122), preferably of copper, each functional block (100, 200, 300, 400, 500) being planar.

10. Assembly according to the preceding claim, wherein each functional block (100, 200, 300, 400, 500) comprises an electronic chip.

11. An assembly comprising a donor substrate (10) covered by a functional block (100) successively comprising a first interconnection layer (110), a functional layer (130) and a second interconnection layer (120), the functional layer comprising one or more electronic components, the first interconnection layer and the second interconnection layer (110, 120) comprising a dielectric material (111, 121) in which conductive elements (112, 122), preferably of copper, are formed, a first surface of the first interconnection layer (110) in contact with the donor substrate (10) and the free surface of the second interconnecting layer (120) being planarized so as to be compatible with subsequent direct bonding.