Controlled inrush current capacitive energy reserve and on-board equipment equipped with such a capacitive energy reserve

Abstract

A capacitive energy reserve (108) for an onboard device (100) comprises: a series of reserve capacitors (3, 4, 5, 6) connected in parallel, each having a capacitance of less than 25,000 µF; a buffer capacitor (2) of lower capacitance; a switch (20) for connecting / disconnecting the buffer capacitor from a power supply (102) to the device; switches (30, 40, 50, 60) for connecting / disconnecting each reserve capacitor from the preceding capacitor; and a sequencer (8) configured to measure the voltage across the buffer capacitor and the reserve capacitors and, upon power-up of the device, to control the various switches according to an initial charging process comprising a series of charge / discharge cycles of the buffer capacitor (2) through the series of reserve capacitors. Figure for the abstract: Fig. 1

Description

Title of the invention: Controlled inrush current capacitive energy reserve and embedded equipment equipped with such a capacitive energy reserve technical field

[0001] The present application relates to a capacitive energy reserve with controlled inrush current, a method for managing this energy reserve, and an on-board equipment equipped with such an energy reserve.

[0002] The invention applies more particularly to the field of transport, in particular to aeronautics - civil or military - and railways, and to the field of space, the energy reserve being intended to power an on-board equipment or system. Previous Art

[0003] To ensure the proper functioning of onboard equipment in the event of a micro-interruption in its power supply, a capacitive energy reserve implemented using capacitors is provided. This energy reserve is designed to power the onboard equipment when the input voltage is interrupted, for a period known as the transparency time, which is typically 200 ms. It should be noted that such energy reserves are also used in the nuclear field, for shorter transparency times.

[0004] The capacitive energy reserve is recharged when the equipment is powered on. Due to the very low internal series resistance of the capacitors, powering on the equipment and its energy reserve induces a very high current inrush.

[0005] In order to limit this inrush current, in most cases, the management of the capacitive energy reserve of the on-board equipment is carried out using a management circuit comprising one or more series resistors and one or more diodes.

[0006] The drawback of this solution is that it is not robust enough with regard to the current values ​​involved. Furthermore, given these current values, it requires one or more high-current and / or high-power resistors and diodes (between 50W and 100W), the size of which poses a problem. For example, a 50W resistor such as the one marketed under the name RH-50 by VISHAY® measures 50mm x 28mm. Similarly, a 43mF capacitor such as the one marketed under the reference ALS80A433NF100 by KEMET® is cylindrical, 105mm long and 77mm in diameter.

[0007] Therefore, neither the capacitive energy reserve nor its management circuit can be formed on the printed circuit board of the onboard equipment. The aforementioned resistors and diodes are oversized for circuit boards; they are mounted in the management circuit by screwing and tightened using lugs.

[0008] In general, known capacitive energy reserve charge management circuits that use diodes and resistors have a significant size and weight which penalizes their use in embedded equipment.

[0009] Besides their own bulk, the aforementioned components have the major disadvantage of generating significant heat, which prohibits their implementation in unventilated embedded equipment or requires the provision of additional means (heat sink) to dissipate the heat that these components generate.

[0010] More advanced solutions exist, such as the use of specific current limiting components, such as a bidirectional converter. The drawback of these solutions is that they are single-source, meaning they are developed and offered by a single supplier and therefore entirely dependent on that supplier. Consequently, a defective or obsolete component cannot be replaced quickly or at a controlled cost. Any single-source solution is therefore considered unsustainable.

[0011] Another, simpler solution would be to increase the power supply's capacity to provide the necessary current during the capacitor charging phase, but this solution is not feasible for a system embedded in an aircraft. Indeed, not only is this solution incompatible with aeronautical standards, but it would also lead to an undesirable increase in the power supply's size, generally incompatible with the available space. Providing a "large" power supply, from 100W to 300W for example, solely to ensure the charging phase of the energy reserve is not satisfactory.

[0012] The invention aims to overcome at least one of the aforementioned drawbacks by providing a capacitive energy reserve for on-board equipment that is not single-source and / or generates sufficiently little heat to be suitable for unventilated on-board equipment and / or has a reduced volume. Description of the invention

[0013] To this end, the invention proposes a capacitive energy reserve for embedded equipment, said capacitive energy reserve comprising:

[0014] - an input terminal for connecting the capacitive energy reserve to a power supply for on-board equipment,

[0015] - an output terminal, for connecting the capacitive energy reserve to a bus of voltage of the on-board equipment,

[0016] - a series of capacitors, called reserve capacitors, connected in parallel and each having a capacitance of less than 25,000 pF, for example on the order of 10,000 pF, the succession of reserve capacitors comprising a first reserve capacitor, a last reserve capacitor and optionally one or more intermediate reserve capacitors,

[0017] - a switch, called the output switch, located between the last capacitor of reserve and the exit terminal,

[0018] - a charge management circuit between the input terminal and the first capacitor of reserve.

[0019] The capacitive energy reserve according to the invention is characterized in that:

[0020] - the charge management circuit includes a capacitor, referred to as a buffer capacitor, of lower capacitance than the reserve capacitors, said buffer capacitor being connected on one side to the input terminal of the capacitive energy reserve, and on the other side to an input of the succession of reserve capacitors,

[0021] - the load management circuit includes a switch, called a load switch of the buffer capacitor, located between the input terminal and the buffer capacitor, and allowing the buffer capacitor to be connected / disconnected from the equipment's power supply when the input terminal is connected to said power supply;

[0022] - the capacitive energy reserve comprises, for each of the capacitors of reserve, a charge switch for said reserve capacitor, located upstream of the reserve capacitor and allowing said reserve capacitor to be connected / disconnected with the preceding reserve capacitor and / or the buffer capacitor,

[0023] - the load management circuit includes a sequencer, configured to measure the voltage across the buffer capacitor and across each of the reserve capacitors, and to, when the equipment is powered on, control the various switches of the capacitive energy reserve according to an initial charging process during which the output switch remains open, said initial charging process comprising a succession of charge / discharge cycles of the buffer capacitor, each of said cycles comprising: — a buffer capacitor charging stage, in which the buffer capacitor charging switch is closed and the first reserve capacitor charging switch is open, the charge management circuit thus being isolated from the succession of reserve capacitors while the buffer capacitor is powered, — a discharge stage of the buffer capacitor in the succession of reserve capacitors, in which the charge switch of the buffer capacitor is open and the charge switch of the first reserve capacitor is closed, - when the voltage (V3) across the first reserve capacitor equals the voltage (V2) across the buffer capacitor, the succession of reserve capacitors is disconnected from the charge management circuit by opening the charge switch (30) of the first reserve capacitor, which ends said charge / discharge cycle of the buffer capacitor.

[0024] Note that, throughout the description, the terms "upstream" and "downstream", "previous" and "next", "first" and "last", etc., are understood in relation to the direction of flow of the current delivered by the equipment's power supply in the capacitive energy reserve.

[0025] The invention extends to a method of charge management of the capacitive energy reserve, characterized by the initial charging process defined above.

[0026] According to particular embodiments of the invention, the capacitive energy reserve and / or the charge management method thereof also have the following characteristics, implemented individually or according to any technically possible and operational combination.

[0027] In certain embodiments, the charge management circuit further includes a current limiter connected to the input terminal, which current limiter is configured to impose a predetermined limited current value at its output. The buffer capacitor is thus supplied with a limited current. Since its capacitance is chosen to be relatively low, this current limitation does not prevent the buffer capacitor from being fully and efficiently charged. At the same time, the current limitation helps to limit the heat dissipated by the charge management circuit, which, combined with the use of reserve capacitors with relatively small capacitances, makes the capacitive energy reserve according to the invention compatible with unventilated equipment.

[0028] In certain embodiments, the sequencer is configured to, during each buffer capacitor charging step, keep the charging switches of all reserve capacitors closed except for the charging switch of the first reserve capacitor (the latter allowing the succession of reserve capacitors to be isolated from the charge management circuit during the charging of the buffer capacitor), for the purpose of balancing the charges between the reserve capacitors.

[0029] Thus, while the buffer capacitor is charging, the charges accumulated during the previous cycles in the succession of reserve capacitors are distributed among the various reserve capacitors until equilibrium is reached; in other words, The first reserve capacitor, which has accumulated additional charges (compared to the other reserve capacitors) during the discharge stage of the buffer capacitor of the previous cycle, discharges in cascade into the following reserve capacitors, until all the reserve capacitors have the same amount of energy.

[0030] In certain embodiments, the initial recharging process of the capacitive energy reserve includes:

[0031] - an indirect charging phase using the buffer capacitor, which phase of Indirect charging includes the previously defined charge / discharge cycles of the buffer capacitor.

[0032] - and a direct charging phase, in which the charging switch (20) of the The buffer capacitor and the load switches (30, 40, 50, 60) of all the reserve capacitors are closed. During this phase, the reserve capacitors are therefore connected to the equipment's power supply and directly charged by it.

[0033] If the spare capacitors were not at least partially charged by the preceding indirect charging phase, their connection to the equipment's power supply would generate a large, undesirable inrush current. Since they are already partially charged, this inrush current is limited and acceptable.

[0034] In order to ensure that this current draw is truly limited, and for example less than a given value, the sequencer can be configured to:

[0035] - at the end of each charge / discharge cycle of the buffer capacitor (in phase of indirect charge), determine a charge rate of the first reserve capacitor, defined as the ratio (V3 / Vaiim) between the voltage (V3) across the first reserve capacitor and the voltage (Vaiim) of the equipment's power supply,

[0036] - and switch from the indirect charging phase to the direct charging phase if the rate of The charge of the first capacitor exceeds a predetermined threshold value. This threshold value can be between 70% and 90%; for example, it is equal to 80%, or a new charge / discharge cycle of the buffer capacitor is started (i.e., the indirect charging phase continues) otherwise.

[0037] Alternatively, the sequencer can be configured to switch from the indirect charging phase to the direct charging phase after a predetermined number of charge / discharge cycles of the buffer capacitor.

[0038] In some embodiments, the load management circuit includes a protection filter arranged between the current limiter and the buffer capacitor, for example between the current limiter and the buffer capacitor charging switch.

[0039] In some embodiments, the capacitive energy reserve includes an ideal diode between the output switch and the output terminal.

[0040] In some embodiments, the succession of reserve capacitors comprises four capacitors each having a capacitance of 10 OOOpF, and the buffer capacitor has a capacitance of 2 200pF.

[0041] The invention extends to embedded equipment comprising a voltage bus and a power supply, the voltage bus being connected to the power supply by a power supply circuit. The embedded equipment according to the invention is characterized in that it comprises a capacitive energy reserve as previously described, arranged in parallel with said power supply circuit, the input terminal of the capacitive energy reserve being connected to the power supply of the embedded equipment and the output terminal of the capacitive energy reserve being connected to the voltage bus of the embedded equipment. Brief description of the drawings

[0042] The invention, according to an exemplary embodiment, will be better understood and its advantages will become more apparent upon reading the following detailed description, given by way of example and in no way limiting, with reference to the accompanying drawings in which: • [Fig.1] is an electrical diagram representing an example of the implementation of equipment equipped with a capacitive energy reserve according to the invention; • [Fig.2] represents part of the capacitive energy reserve of [Fig.1] during a charging step of its buffer capacitor; • [Fig.3] represents part of the capacitive energy reserve of figures 1 and 2 during a discharge stage of said buffer capacitor. Detailed description

[0043] Identical elements represented in the aforementioned figures are identified by identical numerical references.

[0044] [Fig. 1] represents equipment 100, which is for example equipment installed in an aircraft or a spacecraft. This equipment 100 comprises: - a power supply 102, which is for example a 32V power supply delivering direct current, - a secure voltage bus 104, electrically powered by the power supply 102 via a power supply circuit 106 comprising an ideal diode 1062 which ensures that the current can only flow in the direction from the power supply 102 to the voltage bus 104 of the equipment; - a capacitive energy reserve 108 according to the invention.

[0045] This capacitive energy reserve 108 comprises an input terminal 1081 through which it is connected to the equipment's power supply 102, and an output terminal 1082 through which it is connected to the equipment's voltage bus 104. It should be noted that the term "terminal" here does not imply the presence of an electrode or other connector or physical contact; it simply designates a point in the circuit.

[0046] The capacitive energy reserve 108 further comprises:

[0047] - a series of 3 to 6 reserve capacitors connected in parallel. The Spare capacitors are chosen from commercially available standard capacitors to avoid dependence on a single supplier, and are small enough to be mounted directly on the printed circuit board that serves as the equipment's control unit. These spare capacitors also have the advantage of not dissipating heat. The number and capacitance of the spare capacitors are chosen based on the total capacity required to ensure proper equipment operation in the event of a brief power interruption, and also on construction constraints such as available space, acceptable heat dissipation, etc. In the example shown, the capacitive energy reserve comprises four spare capacitors, 3, 4, 5, and 6, each with a capacitance of 10,000 µF.In this example, the series of reserve capacitors therefore has a capacitance of 40 OOPoF. Each reserve capacitor is connected to the circuit by a load switch 30, 40, 50, 60. Given the architecture of the circuit and the position of said load switches 30-60, the reserve capacitors are connected in parallel and their capacitances add up when all the load switches 30-60 are closed, and opening the load switch of one of the reserve capacitors (for example the load switch 40) isolates from the circuit not only said reserve capacitor (in the example capacitor 4) but also the reserve capacitors that follow in the circuit architecture (i.e. capacitors 5 and 6); .

[0048] - an output switch 70, between the last reserve capacitor 6 and the terminal of output 1082, in order to be able to connect / disconnect the succession of reserve capacitors 3 to 6 with the voltage bus 104 of the equipment;

[0049] - a buffer capacitor 2, having a capacitance of 2200pF for example, which buffer capacitor is mounted in parallel and upstream of the series of reserve capacitors 3 to 6; its capacitance being less than the capacitance of each of the reserve capacitors and the total capacitance of the series of reserve capacitors, the charge of this buffer capacitor (when it is separated from the series of reserve capacitors) generates a current inrush much lower than that which the series of reserve capacitors would generate if it were directly connected to the power supply 102; the capacitance of the buffer capacitor is chosen low enough to generate an acceptable current inrush, according to the power supply 102 and the environment of the equipment;

[0050] - a current limiter 10 immediately downstream of the input terminal 1081 of the capacitive energy reserve; this current limiter 10 limits the intensity of the current, supplied by the power supply 102, which enters the capacitors of the capacitive energy reserve 108, and in particular the buffer capacitor 2;

[0051] - a protective filter 12 arranged between the current limiter 10 and the switch charge 20 of buffer capacitor 2,

[0052] - a voltage control and measurement sequencer 8, which is configured for control the load switches 20, 30, 40, 50, 60 of each of the capacitors (reserve and buffer) as well as the output switch 70, via control wires 22, 32, 42, 52, 62 and 72 respectively; the sequencer is also configured to measure the voltage across each of the capacitors (reserve and buffer) via measurement wires 24, 34, 44, 54, 64.

[0053] The capacitive energy reserve 108 may also include an ideal diode 14 between the output switch 70 and the output terminal 1082 in order to ensure that current can only flow in the direction from the capacitive energy reserve 108 to the voltage bus 104.

[0054] The circuit formed by the current limiter 10, the protection filter 12, the buffer capacitor 2, the load switch 20 thereof and the sequencer 8 constitutes a load management circuit which allows the management of the charging (and discharging in the equipment) of the energy reserve.

[0055] When the equipment is powered on, i.e. when its connection to the power supply 102 is activated, an initial recharging process of the capacitive energy reserve, managed by the sequencer 8, begins.

[0056] This process comprises two phases: an indirect charging phase and a direct charging phase. Throughout the initial charging process of the capacitive energy reserve, the output switch 70 is held open by the sequencer 8 in order to disconnect the capacitive energy reserve from the voltage bus 104.

[0057] The indirect charging phase consists of using the buffer capacitor 2 to progressively charge the succession of reserve capacitors 3 to 6, in the manner of communicating vessels, by repeating charge / discharge cycles of the buffer capacitor.

[0058] Each cycle begins with a charging step for buffer capacitor 2, illustrated in [Fig. 2]. To initiate this step, the sequencer 8 commands the opening of the charging switch 30 for the first reserve capacitor and the closing of the charging switch 20 for the buffer capacitor. The circuit upstream of the series of reserve capacitors is then closed and isolated from said series of reserve capacitors. Buffer capacitor 2 is supplied by the equipment's power supply 102. Current flows only in the upstream portion of the capacitive energy reserve, located to the left (in the figure) of the charging switch 30. The flow of current is represented by a dotted line. The intensity of This current is limited due to the low capacitance of buffer capacitor 2. Sequencer 8 monitors the voltage across the buffer capacitor. The charging of said buffer capacitor is complete when this voltage reaches the voltage imposed by the power supply 102, i.e., 32V in this case.

[0059] At this point, a discharge step of buffer capacitor 2 into the series of reserve capacitors, illustrated in [Fig. 3], begins. To initiate this step, as soon as the voltage across buffer capacitor 2 reaches 32V, the sequencer 8 commands the opening of the charge switch 20 of the buffer capacitor and the closing of the charge switch 30 of the first reserve capacitor. The current generated during this discharge step of the buffer capacitor is shown in the figure by a dashed line. The charges accumulated in buffer capacitor 2 discharge into the first reserve capacitor 3, as long as the voltage across buffer capacitor 2 is greater than the voltage across the first reserve capacitor 3.When these voltages balance, in order to prevent the charges transferred to the reserve capacitor 3 from flowing in the other direction, the sequencer 8 opens the charge switch 30, ending the discharge phase of the buffer capacitor 2.

[0060] As the indirect charging phase of the reserve capacitors progresses, the reserve capacitor 3 fills, and the voltage difference between the terminals of the buffer capacitor 2 and those of the first reserve capacitor 3 at the beginning of the cycle decreases. The discharge stage of buffer capacitor 2 into the first reserve capacitor 3 therefore becomes shorter and less efficient. Since the voltage difference decreases as the process progresses, a stage is reached where the voltage across buffer capacitor 2 at the end of the charging stage does not exceed the voltage across reserve capacitor 3, making any discharge into this capacitor impossible.

[0061] The buffer capacitor 2 can then no longer be used to charge the succession of reserve capacitors, and the initial charging process continues with the direct charging phase, in which the reserve capacitors are directly connected to the power supply 102. To this end, the sequencer 8 commands the closing of the charge switch 20 of the buffer capacitor and the charge switches 30, 40, 50 and 60 of all the reserve capacitors.

[0062] Since the reserve capacitor series is already partially charged, the current surge generated during the direct charging phase is lower compared to that which would be generated in the absence of a prior indirect charging phase. However, in order to further limit this current surge, the indirect charging phase is preferably optimized as follows. In addition, the presence of the current limiter 10 ensures that the current flowing in the capacitive energy reserve remains limited.

[0063] During the charging stages of buffer capacitor 2, the charging switches 40, 50, 60 of all the reserve capacitors are closed except for the charging switch 30 of the first reserve capacitor, which is open. The charges accumulated in the succession of reserve capacitors during the previous charge / discharge cycles of the buffer capacitor are then distributed equally among all the reserve capacitors, which limits the amount of charge present in the first capacitor 3 and consequently maintains, for a certain number of cycles, a voltage difference between the buffer capacitor and the first reserve capacitor (difference measured at the end of the buffer capacitor charging stage) sufficient to allow the charges accumulated in the buffer capacitor during the charging stage to be discharged, at least in part, to the first reserve capacitor.

[0064] During the indirect charging phase, at the end of each charge / discharge cycle of the buffer capacitor, the voltage V3 across the first reserve capacitor 3 is measured and compared to the supply voltage 102 Vaiim (here 32V). If the charge ratio V3 / Vaiim of the first reserve capacitor at the end of the cycle, which also corresponds to the ratio V3 / V2 at the end of the charging step of the following cycle (where V2 denotes the voltage across buffer capacitor 2), is greater than or equal to a predetermined threshold value, for example 80%, it is estimated that the indirect charging will no longer be sufficiently efficient in the following cycle, and the process continues with the direct charging phase. So if at the end of a V3 / Vaiimest cycle it has passed above 80%, the sequencer 8 closes switches 20, 30, 40, 50 and 60 so that all the spare capacitors are connected to the power supply 102 and charge directly.

[0065] When the voltage measured across each of the reserve capacitors 3 to 6 reaches 32V, the initial charging process of the capacitive energy reserve is complete; said reserve is operational and the sequencer 8 commands the opening of the output switch 70 so that the stored energy can be delivered to the voltage bus 104 of the equipment in the event of a micro-interruption of the equipment's supply voltage. The charging switches of the reserve capacitors and the buffer capacitor remain closed.

Claims

1. Demands Capacitive energy reserve (108) for on-board equipment (100), said capacitive energy reserve comprising: - an input terminal (1081) for connecting the capacitive energy reserve to a power supply (102) of the on-board equipment, - an output terminal (1082) for connecting the capacitive energy reserve to a voltage bus (104) of the on-board equipment, - a series of capacitors, called reserve capacitors, connected in parallel and each having a capacitance of less than 25 0000F, for example on the order of 10 0000F, the series of reserve capacitors comprising a first reserve capacitor (3), a last reserve capacitor (6) and optionally one or more intermediate reserve capacitors (4, 5), - a switch (70), called the output switch, located between the last reserve capacitor (6) and the output terminal (1082), - a charge management circuit (110) between the input terminal (1081) and the first reserve capacitor (3), characterized in that: - the charge management circuit (110) includes a capacitor (2), called a buffer capacitor, of lower capacitance than the reserve capacitors (3-6), said buffer capacitor being connected, on the one hand, to the input terminal (1081), and on the other hand, to an input of the succession of reserve capacitors (3-6), - the load management circuit (110) includes a switch (20), called the buffer capacitor load switch, located between the input terminal (1081) of the equipment and the buffer capacitor (2) and allowing the buffer capacitor (2) to be connected / disconnected from the equipment's power supply (102) when the input terminal is connected to said power supply, - the capacitive energy reserve includes, for each of the reserve capacitors (3, 4, 5, 6), a load switch (30, 40, 50, 60) for said reserve capacitor, located upstream of the reserve capacitor and allowing said reserve capacitor to be connected / disconnected with the preceding reserve capacitor and / or the buffer capacitor, - The charge management circuit (110) includes a sequencer (8), configured to measure the voltage across the capacitor buffer (2) and across each of the reserve capacitors (3-6), and to, when the equipment (100) is switched on, control the various switches (20, 30, 40, 50, 60, 70) of the capacitive energy reserve according to an initial charging process during which the output switch (70) remains open, said initial charging process comprising a succession of charge / discharge cycles of the buffer capacitor (2), each of said cycles comprising: — a charging stage of the buffer capacitor (2) in which the charging switch (20) of the buffer capacitor is closed and the charging switch (30) of the first reserve capacitor is open, the charge management circuit being thereby isolated from the succession of reserve capacitors while the buffer capacitor is energized, — a discharging stage of the buffer capacitor (2) into the succession of reserve capacitors (3-6),in which the charging switch (20) of the buffer capacitor is open and the charging switch (30) of the first reserve capacitor is closed, - when the voltage (V3) across the first reserve capacitor equals the voltage (V2) across the buffer capacitor, the succession of reserve capacitors is disconnected from the charge management circuit (110) by opening the charging switch (30) of the first reserve capacitor, thus ending said charge / discharge cycle of the buffer capacitor.

2. Capacitive energy reserve according to claim 1, characterized in that the charge management circuit (110) includes a current limiter (10) connected to the input terminal (1081), which current limiter is configured to impose a predetermined limited current value on its output.

3. Capacitive energy reserve according to any one of claims 1 or 2, characterized in that the sequencer (8) is configured to, during each charging step of the buffer capacitor (2), keep the charging switches (40, 50, 60) of all the reserve capacitors closed except for the charging switch (30) of the first reserve capacitor, for the purpose of balancing the charges between the reserve capacitors (3-6).

4. Capacitive energy reserve according to any one of claims 1 to 3, characterized in that the initial charging process comprises: - an indirect charging phase using the buffer capacitor, which indirect charging phase includes the charge / discharge cycles of the buffer capacitor, - and a direct charging phase, in which the charge switch (20) of the buffer capacitor and the charge switches (30, 40, 50, 60) of all the reserve capacitors are closed.

5. Capacitive energy reserve according to claim 4, characterized in that the sequencer (8) is configured to: - at the end of each charge / discharge cycle of the buffer capacitor, determine a charge rate of the first reserve capacitor (3), defined as the ratio (V3 / Vaiim) between the voltage (V3) across the first reserve capacitor and the voltage (Vaiim) of the equipment supply, - and switch from the indirect charging phase to the direct charging phase if the charge rate of the first capacitor (V3 / Vaiim) is greater than a predetermined threshold value or start a new charge / discharge cycle of the buffer capacitor otherwise.

6. Capacitive energy reserve according to claim 4, characterized in that the sequencer (8) is configured to switch from the indirect charging phase to the direct charging phase after a predetermined number of charge / discharge cycles of the buffer capacitor.

7. Capacitive energy reserve according to claim 2, characterized in that the charge management circuit includes a protection filter (12) arranged between the current limiter (10) and the buffer capacitor (2).

8. Capacitive energy reserve according to any one of claims 1 to 7, characterized in that it comprises an ideal diode (14) between the output switch (70) and the output terminal (1082).

9. Capacitive energy reserve according to any one of claims 1 to 8, characterized in that the succession of reserve capacitors comprises four reserve capacitors (3, 4, 5, 6) each having a capacitance of 10 OOOjaF, and in that the buffer capacitor (2) has a capacitance of 2200pF.

10. On-board equipment (100) comprising a voltage bus (104) and a power supply (102), the voltage bus being connected to the power supply by a power supply circuit (106), characterized in that it comprises a capacitive energy reserve (108) according to any one of claims 1 to 9, arranged in parallel with said power supply circuit, the input terminal (1081) of the capacitive energy reserve being connected to the power supply (102) of the on-board equipment and the output terminal (1082) of the capacitive energy reserve being connected to the voltage bus (104) of the on-board equipment.

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