Controlled inrush current capacitive energy reserve and on-board equipment equipped with such a capacitive energy reserve

The capacitive energy reserve system with parallel capacitors and sequencer-controlled charging addresses high inrush currents and heat issues, ensuring compact and reliable operation in on-board equipment.

FR3166767A1Active Publication Date: 2026-03-27LATELEC
4 Cites 0 Cited by

Patent Information

Application Number
FR2024010304
Authority / Receiving Office
FR · FR
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-09-26
Publication Date
2026-03-27
Estimated Expiration
2044-09-26

AI Technical Summary

Technical Problem

Existing capacitive energy reserves for on-board equipment suffer from high inrush currents due to low internal series resistance, requiring large and heavy resistors and diodes, which are unsuitable for compact and unventilated environments, and are often single-source, leading to reliability issues.

Method used

A capacitive energy reserve system with parallel capacitors, a buffer capacitor, and a sequencer-controlled charge management circuit that includes a current limiter and switches, allowing for controlled charging and reduced heat generation, enabling compact and reliable operation.

Benefits of technology

The system effectively manages inrush currents, reduces heat dissipation, and avoids single-source dependencies, making it suitable for unventilated and space-constrained environments.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

A capacitive energy reserve (108) for an onboard device (100) comprises: a series of reserve capacitors (3, 4, 5, 6) connected in parallel, each having a capacitance of less than 25,000 µF; a buffer capacitor (2) of lower capacitance; a switch (20) for connecting / disconnecting the buffer capacitor from a power supply (102) to the device; switches (30, 40, 50, 60) for connecting / disconnecting each reserve capacitor from the preceding capacitor; and a sequencer (8) configured to measure the voltage across the buffer capacitor and the reserve capacitors and, upon power-up of the device, to control the various switches according to an initial charging process comprising a series of charge / discharge cycles of the buffer capacitor (2) through the series of reserve capacitors. Figure for the abstract: Fig. 1
Need to check novelty before this filing date? Find Prior Art