Device for detecting thinning on the back side of an electronic device

Abstract

Device for detecting thinning on the back side of an electronic device. This description relates to an electronic device (10) comprising an electronic circuit (11) and a detection device (100) comprising: - a buried semiconductor region (111) from a first face (101A) of a semiconductor substrate (101) of a first type of conductivity, the buried semiconductor region being of the second type of conductivity and being between a second face (101B) of the semiconductor substrate and the electronic circuit; - a first semiconductor region (115A, 116A) of the second type of conductivity in an epitaxial layer (102) having a first face (102A), and a second face (102B) on the first face of the semiconductor substrate, the first semiconductor region connecting the buried semiconductor region to a first node (141) of a detection circuit (140) by the first face of the epitaxial layer;- a second semiconductor region (115B, 116B) of the second type of conductivity in the epitaxial layer, the second semiconductor region connecting the buried semiconductor region to a second node (142) of the detection circuit via the first face of the epitaxial layer; the detection circuit being adapted to detect an open circuit between the first and second nodes. Figure for the abstract: Fig. 1B;

Description

Title of the invention: Device for detecting thinning on the back side of an electronic device. Technical field

[0001] This description relates generally to electronic devices, for example integrated circuits. This description relates in particular to the detection of a possible attack from the back side of an electronic device, for example an integrated circuit.

[0002] This description applies for example to any attack implementing a technique for thinning a portion of the rear face of the integrated circuit, for example before projecting a beam of electrically charged particles (electrons or ions) onto the thinned portion. Previous technique

[0003] An integrated circuit is susceptible to attacks by computer hackers, who aim to determine the structure of the integrated circuit, extract sensitive data from it, or even modify its operation. Examples of sensitive data include codes or pieces of code, encryption keys, or other data processed during a cryptographic operation.

[0004] An attack can be carried out from the rear side of an integrated circuit equipped on the front side with electronic components such as transistors, diodes, capacitors, these electronic components being able to form an electronic circuit, or several electronic circuits, to be protected.

[0005] The front face is conventionally the face of the semiconductor substrate of the integrated circuit on which and / or from which the electronic components are fabricated, and above which is typically an interconnect structure (usually designated by the acronym BEOL, from the English "Back End Of Line"). The rear face of the semiconductor substrate is the face opposite the front face of the semiconductor substrate. The semiconductor substrate may consist of one or more semiconductor layers.

[0006] During an etching process, a portion of the back face of the semiconductor substrate can first be etched (thinned). Then, a smaller cavity, which can reach, for example, a surface area of ​​20 x 20 pm, can be created in the etched (thinned) area towards the front face. The cavity can typically be created by projecting a beam of electrically charged particles (electrons or ions) into the thinned portion from the back face. The beam can be an electron beam (E-beam). This is then referred to as the E-beam technique. The beam can also be an ion beam, for example, positive ions in a focused ion beam (FIB). (Focused Ion Beam, or FIB). Typically, multiple cavities are created to access several electronic components or circuits. These cavities can extend approximately to the level of the casings in which the electronic components are formed, to the level of the electronic components themselves, or to conductive traces connected to the electronic components. Electrical contacts with the electronic components or conductive traces can then be created within these cavities, and hackers can use these contacts to analyze the operating electronic circuit.

[0007] To access certain sensitive data, attacks must generally be carried out while the integrated circuit is activated, or at least while the targeted electronic circuit is activated, i.e., in operation.

[0008] Detection devices have already been proposed for detecting the presence of such attacks during operation. When an attack is detected by such a detection device, a countermeasure can be triggered, which may, for example, involve the destruction of sensitive data and / or the disabling of the attacked electronic circuit. The electronic circuit may even be permanently disabled if, for example, a certain number of attacks are detected within a relatively short period of time.

[0009] One disadvantage of existing detection devices for detecting attacks is that they tend to be ineffective for certain types of attacks, and / or to occupy a relatively large area in the integrated circuit.

[0010] It would be desirable to be able to improve, at least in part, the known devices for detecting attacks on integrated circuits.

[0011] Advantageously, it would be desirable to have a detection device adapted to detect an attack on the back side of an integrated circuit, which is effective regardless of the attack, and which occupies the smallest possible area within the integrated circuit. Summary of the invention

[0012] An embodiment overcomes all or part of the drawbacks of known integrated circuit attack detection devices.

[0013] One embodiment provides an electronic device comprising at least one electronic circuit and a detection device comprising: - a semiconductor region buried from a first face of a semiconductor substrate of a first type of conductivity, the buried semiconductor region being of the second type of conductivity opposite to the first type of conductivity, the buried semiconductor region being between a second face of the semiconductor substrate, opposite to the first face of said semiconductor substrate, and at least one electronic circuit; - at least one first semiconductor region of the second type of conductivity in an epitaxial semiconductor layer having a first face, and a second face opposite to the first face of said epitaxial semiconductor layer and positioned on the first face of the semiconductor substrate; said at least one first semiconductor region connecting the buried semiconductor region to a first node of a detection circuit by the first face of the epitaxial semiconductor layer; - at least one second semiconductor region of the second type of conductivity in the epitaxial semiconductor layer; said at least one second semiconductor region connecting the buried semiconductor region to a second node of the detection circuit by the first face of the epitaxial semiconductor layer; and - the detection circuit, adapted to apply a voltage level or a current to the first node and to detect by the second node the presence of an open circuit between the first and second nodes, so as to detect a thinning of the buried semiconductor region.

[0014] According to one embodiment, at least a first semiconductor region comprises: - a first semiconductor box of the second type of conductivity positioned from the first face of the epitaxial semiconductor layer to a first non-zero depth in the epitaxial semiconductor layer; and - a first buried semiconductor box of the second type of conductivity extending in the epitaxial semiconductor layer from the first depth to the first face of the semiconductor substrate, the first buried semiconductor box being in contact with the first semiconductor box and the buried semiconductor region; And at least one second semiconductor region includes: - a second semiconductor chamber of the second type of conductivity positioned from the first face of the epitaxial semiconductor layer to the first depth within the epitaxial semiconductor layer; and - a second buried semiconductor box of the second type of conductivity extending into the epitaxial semiconductor layer from the first depth to the first face of the semiconductor substrate, the second buried semiconductor box being in contact with the second semiconductor box and the buried semiconductor region; at least one electronic circuit being for example at a level located between the first and second buried semiconductor boxes and the first face of the epitaxial semiconductor layer.

[0015] The first depth is less than the thickness of the epitaxial semiconductor layer, so that the first and second semiconductor boxes are at a non-zero distance from the second face of the epitaxial semiconductor layer.

[0016] According to one embodiment, the first and second buried semiconductor boxes are isolated from each other by a semiconductor portion of the epitaxial semiconductor layer which extends to the first face of the semiconductor substrate, at least one electronic circuit being for example positioned between the semiconductor portion and the first face of the epitaxial semiconductor layer.

[0017] According to one embodiment, the first and second semiconductor boxes are isolated from each other by another semiconductor box of the first type of conductivity, and, for example also by an insulating trench included between the first face of the epitaxial semiconductor layer and the other semiconductor box.

[0018] According to one embodiment, the semiconductor portion is located between the other semiconductor box and the buried semiconductor region.

[0019] According to one embodiment, at least a second semiconductor region is electrically isolated from at least a first semiconductor region.

[0020] According to one embodiment, at least one electronic circuit is positioned in the epitaxial semiconductor layer.

[0021] According to one embodiment, the buried semiconductor region is below at least one electronic circuit.

[0022] According to one embodiment, the detection device comprises: - a first electrical contact at the first face of the epitaxial semiconductor layer connecting at least one first semiconductor region to the first node; - a second electrical contact at the first face of the epitaxial semiconductor layer connecting at least one second semiconductor region to the second node.

[0023] According to one embodiment, the first electrical contact is in contact with the first semiconductor box, and the second electrical contact is in contact with the second semiconductor box.

[0024] According to one embodiment, the buried semiconductor region, at least one first semiconductor region and at least one second semiconductor region: - are included in a semiconductor structure located in the semiconductor substrate and in the epitaxial semiconductor layer; and / or - form an electrical conduction channel connected to the first and second nodes of the detection circuit, an open circuit between the first and second nodes being an open circuit in the electrical conduction channel, preferably in the buried semiconductor region.

[0025] According to one embodiment, the buried conductive region extends to a depth greater than 2 pm, for example greater than or equal to 3 pm, for example greater than or equal to 4 pm.

[0026] According to one embodiment, the at least one electronic circuit comprises a plurality of electronic circuits configured in a network, the buried semiconductor region having a shape configured so that said buried semiconductor region runs under each of the electronic circuits of the network.

[0027] According to one embodiment, the buried conductive region has a zigzag shape, with a first end connected to at least one first semiconductor region and a second end connected to at least one second semiconductor region.

[0028] According to one embodiment, the electronic device is an integrated circuit.

[0029] One embodiment provides a method for using the detection device The previously described usage process includes: - the emission of a voltage level or a current at the first node; - the detection by the second node of the presence of an open circuit between the first and second nodes, so as to detect a thinning of the buried semiconductor region, for example in the event of an attack by the second face of the semiconductor substrate.

[0030] According to one embodiment, if the open circuit is detected, the detection circuit sends a signal to at least one electronic circuit to deactivate it.

[0031] One embodiment provides a method for manufacturing an electronic device, the manufacturing method comprising: - an implantation step from a first face of a semiconductor substrate of a first type of conductivity, so as to form a buried semiconductor region of the second type of conductivity opposite to the first type of conductivity, the buried semiconductor region being formed between a second face of the semiconductor substrate, opposite to the first face of said semiconductor substrate, and at least one electronic circuit; - an epitaxial growth step on the first face of the semiconductor substrate so as to form an epitaxial semiconductor layer doped with the first type of conductivity, said epitaxial semiconductor layer having a first face and a second face opposite to the first face of said epitaxial semiconductor layer and positioned on the first face of the semiconductor substrate; - at least one implantation step in the epitaxial semiconductor layer so as to form at least one first semiconductor region of the second type of conductivity between the first face of the semiconductor substrate and the first face of the epitaxial semiconductor layer and at least one second semiconductor region of the second type of conductivity between the first face of the semiconductor substrate and the first face of the epitaxial semiconductor layer, said at least a first and at least a second semiconductor region being connected each to the buried semiconductor region; a linking step of at least a first semiconductor region to a first node of a detection circuit by the first face of the epitaxial semiconductor layer and of at least a second semiconductor region to a second node of the detection circuit by the first face of the epitaxial semiconductor layer. Brief description of the drawings

[0032] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0033] [Fig.1A] is a schematic and partial cross-sectional view illustrating a detection device according to an embodiment, adapted to detect an attack from the rear face of an integrated circuit;

[0034] [Fig.1B] is a schematic and partial cross-sectional view illustrating an integrated circuit according to an embodiment, integrating the detection device of [Fig.1A] and an electronic circuit to be protected;

[0035] [Fig.1C] is a schematic and functional view illustrating the integrated circuit of [Fig.1B];

[0036] [Fig. 2] is a very schematic and partial top view illustrating an integrated circuit according to another embodiment; and

[0037] [Fig.3] illustrates schematically and in a simplified manner an example of a manufacturing process for the semiconductor structure of [Fig.1A]. Description of the implementation methods

[0038] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0039] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, not all fabrication steps and details of the semiconductor structure are described, as they can be carried out using conventional methods for manufacturing semiconductor structures formed in and / or on a semiconductor substrate. Furthermore, the fabrication steps and details of the interconnect structure are not described, as they can be carried out using conventional methods for manufacturing interconnect structures.

[0040] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0041] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0042] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0043] In the following description, the terms "insulator" and "conductor" mean, respectively, electrically insulating and electrically conductive. Similarly, the term "insulate" means, unless otherwise specified, to insulate electrically.

[0044] In the following description, unless otherwise specified, when reference is made to a substrate, it refers to a semiconductor substrate, when reference is made to a box, it refers to a semiconductor box, and when reference is made to a region, it refers to a semiconductor region.

[0045] In the following description, unless otherwise specified, when reference is made to an epitaxial layer, reference is made to a semiconductor layer obtained by epitaxy, or epitaxial semiconductor layer.

[0046] In the following description, when reference is made to an attack detection device, or for short a detection detector, reference is made to a device capable of detecting an attack on an electronic circuit, in particular an attack through the back side of the integrated circuit in which an electronic circuit to be protected from such an attack is integrated.

[0047] In the following description, "buried" means buried deep within the semiconductor structure, i.e., at a non-zero distance from the top face of the semiconductor structure, which may be buried deep within the semiconductor substrate or within the epitaxial layer.

[0048] In the following description, one can refer interchangeably to a type of doping or a type of conductivity, which designate either the P type or the N type.

[0049] Fig. 1A is a schematic and partial cross-sectional view illustrating a detection device 100 according to an embodiment adapted to detect an attack from the rear side of an integrated circuit 10. Fig. 1B is a schematic cross-sectional view and Partial illustration of an integrated circuit 10 incorporating the detection device 100 of [Fig. 1A] and an electronic circuit 11 to be protected. [Fig. 1C] is a schematic and functional view illustrating the integrated circuit 10 of [Fig. 1B].

[0050] In the example shown in Figures IA and IB, the detection device 100 comprises a semiconductor structure 110 made in a semiconductor substrate 101 (P-SUB) and in an epitaxial layer 102 (P-EPI) of a semiconductor material, positioned on the upper face 101A of the semiconductor substrate 101. The lower face 102B of the epitaxial layer 102 is in contact with the upper face 101A of the substrate 101. The lower face 101B of the semiconductor substrate 101 corresponds to the lower face, or back face, 110B of the semiconductor structure 110. This also corresponds to the back face of the integrated circuit 10.

[0051] The upper face 110A, or front face, of the semiconductor structure 110 corresponds to the upper face 102A of the epitaxial layer 102, which is the face opposite the lower face 102B of the epitaxial layer 102. The upper face 110A of the semiconductor structure 110 corresponds to the face from which an interconnection structure 120, described later, is positioned and / or on which electrical contacts 123A, 123B, described later, are positioned.

[0052] The semiconductor substrate 101 is for example made of silicon, or corresponds to the semiconductor layer of a substrate of the silicon on insulator type, or "SOI", from the English "Silicon On Insulator".

[0053] The semiconductor substrate 101 is doped with a first type of conductivity, in the example of type P.

[0054] The epitaxial layer 102 is for example made of silicon.

[0055] The epitaxial layer 102 is doped, for example weakly doped, with the first type of doping, in the example of type P.

[0056] The semiconductor structure 110 can be a silicon structure.

[0057] The semiconductor structure 110 comprises a buried semiconductor region 111 (N-BUR) formed in the semiconductor substrate 101 and doped with the second type of doping, as opposed to the first type of doping. In the example shown, the second type of doping is type N.

[0058] For example, the buried semiconductor region 111 is flush with the upper face 101A of the semiconductor substrate 101. For example, the buried semiconductor region 111 extends to a depth less than the thickness of the semiconductor substrate 101, i.e. has a thickness el less than the thickness of the semiconductor substrate 101.

[0059] The semiconductor structure 110 further comprises, in the epitaxial layer 102: - an insulating trench 112 (STI), for example of the shallow insulating trench type, known as STI, for "Shallow Trench Isolation" in English, formed from the upper face 102A of the epitaxial layer 102: the depth pl of the insulating trench 112 is less than the thickness of the epitaxial layer 102; - a semiconductor box 113 (PW) located in the epitaxial layer 102 under the insulating trench 112: the semiconductor box 113 is more strongly doped with the first type of doping than the epitaxial layer 102, in the example of type P; - a semiconductor portion 114 of the epitaxial layer 102, doped with the first type of doping, between the semiconductor box 113 and the buried semiconductor region 111; - buried semiconductor boxes 115A, 115B (N-ISO) from a non-zero depth p3 of the upper face 102A of the epitaxial layer 102, the buried semiconductor boxes 115A, 115B being doped with the second type of doping, in the example of type N, and being on either side, for example around, the portion 114 of the epitaxial layer 102; and - Semiconductor boxes 116A, 116B (NW) doped with the second type of doping, in the example of type N, around the insulating trench 112 and the semiconductor box 113.

[0060] Preferably, the buried semiconductor enclosures 115A, 115B are insulated from each other. Preferably, the semiconductor enclosures 116A, 116B are insulated from each other.

[0061] The P-type semiconductor box 113 is, for example, less wide than the insulating trench 112, and, for example, centered with respect to the insulating trench 112, but this is not limiting.

[0062] Each buried semiconductor box 115A, 115B is positioned on, and in contact with, the buried semiconductor region 111. For example, the semiconductor portion 114 is narrower than the buried semiconductor region 111, so that each buried semiconductor box 115A, 115B includes areas of contact with the buried semiconductor region 111. In the example shown in Figures IA and IB, the buried semiconductor boxes 115A, 115B are substantially centered with respect to the buried semiconductor region 111. Alternatively, the buried semiconductor boxes 115A, 115B could be off-center with respect to the buried semiconductor region 111.

[0063] Each semiconductor enclosure 116A, 116B is in contact with one of the buried semiconductor enclosures 115A, 115B: the semiconductor enclosure 116A is in contact with the buried semiconductor enclosure 115A, and the semiconductor enclosure 116B is in contact with the buried semiconductor enclosure 115B. In the example shown in Figures IA and IB, each semiconductor enclosure 116A, 116B extends from the upper face 102A of the epitaxial layer 102 in depth (depth p3) down to the level of the buried semiconductor boxes 115A, 115B.

[0064] The semiconductor boxes 116A, 116B, the buried semiconductor boxes 115A, 115B and the buried semiconductor region 111, which are all N-doped, form an electrical continuity, or an electrical conduction channel of the detection device 100, as explained later.

[0065] The semiconductor boxes 116A, 116B, the buried semiconductor boxes 115 A, 115B and the buried semiconductor region 111 are therefore configured to ensure electrical continuity.

[0066] Each semiconductor enclosure 116A, 116B can have various shapes, for example a square or rectangular shape, an oval or circular shape, a U-shaped shape.

[0067] Each buried semiconductor box 115A, 115B can have various shapes, for example a square or rectangular shape, an oval or circular shape, a U-shaped shape.

[0068] For example, each buried semiconductor enclosure 115A, 115B has a square shape with sides of 1.8 pm, giving it a surface area of ​​3.24 pm². For example, two buried semiconductor enclosures 115A and 115B can be used, having a total surface area of ​​2 x 3.24 pm², or slightly less than 6.5 pm². The semiconductor enclosures 116A, 116B can be configured to have a smaller surface area than the buried semiconductor enclosures 115A, 115B.

[0069] The buried semiconductor region 111 can have various shapes, for example, an annular or partially annular shape, a U-shaped shape, a spiral shape, a zig-zag shape, a square or rectangular shape. The buried semiconductor region 111 is preferably continuous.

[0070] The lower face 11 IB of the buried semiconductor region 111 is for example at a depth p2 between 3.6 and 5 pm below the upper face 110A of the semiconductor structure 110. The buried semiconductor region 111a for example has a thickness el between 1 and 3 pm.

[0071] Each buried semiconductor box 115A, 115B has, for example, a thickness e2 between 1 and 3 pm, and each semiconductor box 116A, 116B has, for example, a thickness e3 between 1 and 2 pm. The thickness e3 is equal to the depth p3.

[0072] The depth p1 of the insulating trench 112 is, for example, between 0.3 and 0.5 pm. The thickness e4 of the semiconductor casing 113 is, for example, between 0.3 and 1.3 pm. The semiconductor portion 114 has a thickness e5, for example, greater than or equal to 1 pm.

[0073] In the semiconductor structure 110, PN junctions of opposite polarities to the P-type semiconductor box 113 and the P-type semiconductor portion 114, formed respectively with the N-type semiconductor boxes 116A, 116B and the N-type buried semiconductor boxes 115A, 115B, allow the P-type semiconductor box 113 and the P-type semiconductor portion 114 to be electrically isolated, the P-type semiconductor box 113 being further isolated by the insulating trench 112. This gives rise to an electrical conduction channel 130 which includes the semiconductor box 116A, the buried semiconductor box 115A, the buried semiconductor region 111, the buried semiconductor box 115B and the semiconductor box 116B.In other words, the N-type semiconductor regions 111, 115A, 115B, 116A, 116B, isolated from the other regions which are either P-type or insulating, form an isolated electrical conduction channel 130 in the semiconductor structure 110.

[0074] The electrical conduction channel 130 is symbolized by a dotted path which allows visualization of one conductive path, among several possible paths along the electrical conduction channel 130. The electrical conduction channel 130 is therefore not limited to this dotted path.

[0075] Such a semiconductor structure 110 allows for a buried semiconductor region 111 which reaches a significant depth, typically greater than 2 pm, for example greater than 3 pm, for example between 3.6 pm and 5 pm, and which is included in the electrical conduction channel 130, which channel may include contact points on the upper face 110A of the semiconductor structure 110, at the level of the semiconductor boxes 116A, 116B. As explained later, this allows the detection of a deep attack through the back face of the integrated circuit 10, well before the electronic circuit 11 is reached, the electronic circuit 11 to be protected being above the buried semiconductor region 111, the buried semiconductor region 111 therefore being below the electronic circuit 11 to be protected, i.e. between the back face 101B of the integrated circuit 10 and the electronic circuit 11.

[0076] Fig. 3 illustrates schematically and in a simplified manner an example of a manufacturing process 300 of the semiconductor structure 110 of Fig. 1A.

[0077] The manufacturing process 300 comprises: - an implantation step 302 (SUBSTRATE IMPLANTATION) from the upper face 101A of the semiconductor substrate 101 to form the buried semiconductor region 111, this implantation being of the second type of doping, opposite to the type of doping of the semiconductor substrate 101, in this example the implantation is of type N: this implantation can be preceded by the formation of a mask to mask the areas of the semiconductor substrate 101 that should not be N-doped; - an epitaxial growth step 304 (EPI LAYER ON SUBSTRATE) from the upper face 101A of the semiconductor substrate 101 to form the doped epitaxial layer 102, for example weakly doped, of the first type of doping, in this example of type P; - an etching step 306 (EPI LAYER TRENCH ETCHING) from the upper face 102A of the epitaxial layer 102 to form a shallow trench in the epitaxial layer 102, then a filling of this trench, for example with silicon oxide, to form the insulating trench 112; - a deep implantation step 308 (first DEEP IMPLEMENTATION EPI LAYER) in the epitaxial layer 102 through the insulating trench 112 to form the semiconductor box 113, this implantation being of the first type of doping, in this example of type P, this implantation being carried out for example so as to preserve the semiconductor portion 114 of the epitaxial layer 102 between the semiconductor box 113 and the buried semiconductor region 111; - a deep implantation step 310 (2nd DEEP EPI LAYER IMPLEMENTATION) in the epitaxial layer 102, from the lower level of the semiconductor box 113 to the upper face 101A of the semiconductor substrate 101, and around the semiconductor portion 114 of the epitaxial layer 102, to form the buried semiconductor boxes 115A, 115B, this implantation being of the second type of doping, in this example of type N; - an implantation step 312 (SURFACIAL IMPLEMENTATION EPI LAYER) from the upper face 102A of the epitaxial layer 102 to the buried semiconductor boxes 115A, 115B, around the insulating trench 112 and the semiconductor box 113, to form the semiconductor boxes 116A, 116B, this implantation being of the second type of doping, in this example of type N.

[0078] The semiconductor boxes 116A, 116B are implanted with an energy enabling them to reach the buried semiconductor boxes 115A, 115B in depth, so as to form with the buried semiconductor boxes 115A, 115B continuous N-type semiconductor regions isolating the P-type semiconductor box 113.

[0079] An interconnection structure 120 can be positioned above the semiconductor structure 110, above the epitaxial layer 102, for example on the upper face 102A of the epitaxial layer 102. The interconnection structure is generally designated as a "BEOL" interconnection structure, from the English "back end of line".

[0080] A metallization level Ml of the interconnection structure 120 is shown, which generally comprises a plurality of metallization levels. This metallization level Ml comprises several conductive segments 121A, 121B of a conductive layer 121, for example a metallic layer, each conductive segment 121A, 121B forming a conductive track, for example a metallic track.

[0081] The interconnection structure 120 further includes an insulating layer 122, which is generally a stack of several insulating layers, separating the different metallization levels and the different conductive tracks of the same metallization level, the conductive tracks 121 A, 121 B being thus embedded in the insulating layer 122. The insulating layer 122 can be made of an oxide, for example a silicon oxide.

[0082] Each conductive track 121A, 12IB of the interconnection structure 120 is connected to the semiconductor structure 110 by an electrical contact 123A, 123B (contact), or any other electrical connection element, for example, a conductor via. For example, the contacts 123A, 123B are part of the interconnection structure 120.

[0083] The contacts 123A, 123B are connected, for example connected, to the upper face 110A of the semiconductor structure 110, which corresponds to the upper face 102A of the epitaxial layer 102. In particular, the contacts 123A, 123B are connected, for example connected, each to one of the semiconductor boxes 116A, 116B of the semiconductor structure 110. Thus, each semiconductor box 116A, 116B is connected to one of the conductive tracks 121A, 121B of the interconnection structure 120 via one of the contacts 123A, 123B.

[0084] The electrical conduction channel 130 formed by the N-type semiconductor regions 111, 115, 116 of the semiconductor structure 110 is thus connected to the conductive tracks 121A, 121B via the contacts 123A, 123B. The connection at the first metallization level M1 has been shown, but a connection at any other metallization level could be considered.

[0085] As shown in [Fig.1B], the integrated circuit 10 comprises an electronic circuit 11 positioned above the buried semiconductor region 111.

[0086] The electronic circuit 11 includes, for example, standard cells, transistors, diodes, resistors and / or capacitors.

[0087] In the example shown in [Fig. IB], the electronic circuit 11 is positioned at a height just above the level of the buried semiconductor boxes 115A, 115B (these buried semiconductor boxes 115A, 115B being positioned laterally on either side of the electronic circuit 11), and the P-type semiconductor portion 114 is located below the electronic circuit 11. The P-type semiconductor portion 114 can provide insulation between the buried semiconductor region 111 and the electronic circuit 11, which can be advantageous. if for example the electronic circuit 11 is formed in an N type enclosure, for example of type N-ISO.

[0088] The semiconductor boxes 116A, 116B are for example formed substantially at the level of the electronic circuit 11, for example on either side of the electronic circuit 11.

[0089] In addition, the electronic circuit 11 can be positioned within the P-type semiconductor box 113 and the insulating trench 122, so as to be also insulated, for example if it is formed in an N-type box, for example of type N-ISO.

[0090] The conductive tracks 121A, 121B, and thus the electrical conduction channel 130, can be connected to a detection circuit 140, shown in Figures IB and IC. For example, the conductive track 121A can be connected to a first node 141 of the detection circuit 140, and the conductive track 12IB can be connected to a second node 142 of the detection circuit 140. For example, the conductive track 121A forms an input (IN) from the detection circuit 140 and the conductive track 12IB forms an output (OUT) to the detection circuit 140.

[0091] The detection circuit 140 is connected to a voltage supply VDD to power the electrical conduction channel 130 via the conductive tracks 121 A, 121 B.

[0092] Alternatively, the detection circuit 140 can be directly connected to contacts, for example contacts 123A, 123B, to the semiconductor housings 116A, 116B, without these contacts necessarily being part of an interconnection structure. For example, contact 123A forms an input (IN) from the detection circuit 140 and contact 123B forms an output (OUT) to the detection circuit 140.

[0093] The detection circuit 140 can be configured to detect a break in electrical continuity in the electrical conduction channel 130, which may be due to thinning, for example by etching, in the buried semiconductor layer 111. Thus, the detection circuit 140 is configured to detect an attack from the back side.

[0094] In operation, a supply voltage VDd is applied by the detection circuit 140 to the input IN, inducing a current in the electrical conduction channel 130, and the detection circuit 140 detects at the output OUT the break in electrical continuity.

[0095] The break in electrical continuity can be detected by measuring the resistance in the electrical conduction channel 130. For example, the detection circuit can be configured to detect an increase in resistance in the electrical conduction channel 130 when a thinning attack of the buried semiconductor layer 111 is undertaken, or even infinite resistance when the The buried semiconductor layer 111 is etched through its entire thickness, interrupting the electrical conduction channel 130 in the semiconductor structure 110. An upper resistance limit can be defined to determine if an attack occurs.

[0096] According to one embodiment, several electrical conduction channels of the type of electrical conduction channel 130 could be connected, each between two inverters, to form a ring oscillator whose frequency would be measured. A fault in one of these electrical conduction channels would induce an increase in its resistance, which would lead to a decrease in the oscillation frequency of the ring oscillator. If one of these electrical conduction channels were completely destroyed, the resistance of that channel would become infinite, and the oscillator frequency would drop to zero. It would also be possible to define a low frequency, above which the channel would be considered faulty.

[0097] In the event of detection of a change in the electrical parameter, the detection circuit 140 can send a DISABLE signal to the electronic circuit 11 to deactivate it, and / or to delete sensitive data.

[0098] As mentioned earlier, the buried semiconductor region can reach a depth greater than 2 pm, or 3 pm, or even greater than 3.6 pm, for example, up to 5 pm. Thus, the detection device 100 can detect an attack at a depth of up to 5 pm, or at least well before the electronic circuit 11 is reached. Indeed, an Ebeam-type attack, or even a FIB-type attack, cannot generally be carried out to a depth greater than about 1 pm, which requires thinning, or etching, from the back side to reach this depth. The detection device 100 can therefore detect an attack by detecting thinning from the back side.

[0099] Furthermore, a relatively large detection area for an attack, for example an Ebeam or even FIB type attack, can be covered with a limited surface area of ​​the detection device 100. For example, a detection length L of up to 200 pm can be covered. For example, two buried semiconductor boxes 115A, 115B, having a surface area of ​​slightly less than 6.5 pm2 as described above, can be formed, connected to the buried semiconductor region 111 whose length is equal to the detection length L plus a contact length with each buried semiconductor box 115A, 115B, this contact length being less than or equal to twice the side of the buried semiconductor boxes 115A, 115B, i.e. 3.6 pm.

[0100] The inventors determined that, for a buried semiconductor layer 111 with a width of 0.75 pm and a length of 200 pm, the total resistance of the buried semiconductor layer was less than 15 kOhms, which allows for a significant detection length, on the order of 200 pm, without creating too much resistance in the electrical conduction channel 130.

[0101] Figures IA and IB illustrate an example of a semiconductor structure formed in a semiconductor substrate and in an epitaxial layer on the semiconductor substrate. This example of a semiconductor structure is not limiting; other semiconductor structures formed in a semiconductor substrate and in an epitaxial layer on the semiconductor substrate could be considered by a person skilled in the art.

[0102] Fig. 2 is a very schematic and partial top view illustrating an integrated circuit 20 according to another embodiment.

[0103] The integrated circuit 20 of [Fig.2] has many elements in common with the integrated circuit 10 of [Fig.1B] and only the differences between the two integrated circuits are detailed in the description that follows.

[0104] The integrated circuit 20 of [Fig. 2] differs from the integrated circuit 10 of [Fig. 1B] primarily in that it comprises several electronic circuits 21, instead of a single electronic circuit 11 in [Fig. 1B]. The electronic circuits 21 in the figure are arranged in an array 22, in this example a 4x4 matrix, although this is not limiting. The length L of the matrix is, for example, equal to 20 pm. The width 1 of the matrix is, for example, equal to 20 pm. Thus, [Fig. 2] could correspond to a top view of [Fig. 1B], with the electronic circuit 11 then representing the array 22 of electronic circuits 21 of [Fig. 2].

[0105] In addition, instead of the conductive tracks 121A, 121B, the contacts 123A, 123B have been represented directly.

[0106] The contacts 123A, 123B can be formed on the semiconductor boxes 116A, 116B described in connection with [Fig. 1A], themselves in contact with the buried semiconductor boxes 115A, 115B described in connection with [Fig. 1A], themselves in contact with the buried semiconductor region 211, which is shown in transparency and with dashed lines, under the network 22 of electronic circuits 21. In this example, the buried semiconductor region 211 has a zigzag, or meander, shape, with one end 21 IC connected to the contact 123A (via the buried semiconductor box 115A and the semiconductor box 116A) and another end 21D connected to the contact 123B (via the buried semiconductor box 115B and the semiconductor box). 116B), so that it can be below each electronic circuit 21. The electrical conduction channel 230 follows the buried semiconductor region 211 in a zig-zag shape.An attack from the rear side of the integrated circuit 20 in any electronic circuit 21 can thus be detected.

[0107] The detection device 200 of this embodiment makes it possible to cover the entire network 22 of electronic circuits 21, for example over an area of ​​20 pm x 20 pm, making it possible for example to thwart an Ebeam attack.

[0108] A person skilled in the art may consider other types of electronic circuit networks, and other suitable detection devices, in particular other forms of buried semiconductor region.

[0109] The embodiments make it possible to detect deep attacks through the back face of an electronic device, for example an integrated circuit, by positioning an electronic circuit to be protected above a buried semiconductor layer formed in a semiconductor substrate.

[0110] In the described embodiments, it can be seen that the detection device can be made using microelectronic manufacturing techniques, for example, existing production lines for manufacturing the described semiconductor structure, by positioning the electronic circuit to be protected above the buried semiconductor layer. For example, the detection device can be made with few additional steps, or even none at all, since the described semiconductor structure is already planned for fabrication.

[0111] The embodiments described below are particularly suited to the detection of an attack on the back side of an integrated circuit, in particular any attack implementing a technique of thinning a portion of the back side of the integrated circuit, for example before projecting a beam of electrically charged particles (electrons or ions) onto the thinned portion.

[0112] The embodiments described above can be used in many types of industrial markets, particularly for embedded security systems. The embedded security market is evolving rapidly, shifting from a traditional smart card business to a wide range of connected devices associated with a rapidly expanding communications infrastructure. In this booming digital economy, data is becoming a strategic asset. But as data travels from sensors to gateways, servers, and finally to clouds, it is increasingly exposed to new threats. These new challenges require new security approaches in various sectors, such as: - the automotive industry, for example in the area of ​​securing access to the car, the secure electronic portal, wireless charging...; - the industrial sector, for example in the field of embedded security, secure connections or secure authentication, in the field of infrastructure electrification, the Internet of Things (IoT) and Smart Homes; - the personal electronics industry, for example in the fields of banking, identification, mobile telephony and the Internet of Things (IoT), as well as in the field of broadband interfaces; - the communications equipment industry, brand protection, computers and peripherals, for example in the field of infrastructure and data centers, and in the field of low Earth Orbit (LEO) satellites.

[0113] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art. For example, while an N-type buried semiconductor region in a P-type silicon semiconductor substrate has been described (i.e., the first type of doping, or conductivity type, is P-type), it will become clear to a person skilled in the art that, in alternative embodiments, the opposite types of conductivity could be used for the buried semiconductor region and the semiconductor substrate, the buried semiconductor region then being P-type and the semiconductor substrate being N-type (i.e., the first type of doping, or conductivity type, is N-type).A skilled professional will know how to adapt the type of doping for the semiconductor cells and regions within the semiconductor structure. For example, the electrical conduction channel would then be of the P type, instead of the N type.

[0114] For example, the embodiments describe an integrated circuit, although it could be any other electronic device incorporating at least one electronic circuit to be protected from attack.

[0115] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic device (10; 20) comprising at least one electronic circuit (11; 21) and a detection device (100; 200) comprising: - a buried semiconductor region (111; 211) from a first face (101A) of a semiconductor substrate (101) of a first type of conductivity, the buried semiconductor region being of the second type of conductivity opposite to the first type of conductivity, the buried semiconductor region being between a second face (101B) of the semiconductor substrate, opposite to the first face of said semiconductor substrate, and at least one electronic circuit (11; 21); - at least one first semiconductor region (115A, 116A) of the second type of conductivity in an epitaxial semiconductor layer (102) having a first face (102A), and a second face (102B) opposite to the first face of said epitaxial semiconductor layer and positioned on the first face (101A) of the semiconductor substrate (101);said at least a first semiconductor region connecting the buried semiconductor region (111; 211) to a first node (141) of a detection circuit (140) via the first face (102A) of the epitaxial semiconductor layer (102); - at least a second semiconductor region (115B, 116B) of the second type of conductivity in the epitaxial semiconductor layer; said at least a second semiconductor region connecting the buried semiconductor region (111; 211) to a second node (142) of the detection circuit (140) via the first face (102A) of the epitaxial semiconductor layer (102); and - the detection circuit (140), adapted to apply a voltage level or a current to the first node and to detect by the second node the presence of an open circuit between the first and second nodes, so as to detect a thinning of the buried semiconductor region.

2. An electronic device according to claim 1, wherein: at least a first semiconductor region (115A, 116A) comprises: - a first semiconductor box (116A) of the second type of conductivity positioned from the first face (102A) of the epitaxial semiconductor layer (102) to a first non-zero depth (p3) in the epitaxial semiconductor layer; and - a first buried semiconductor box (115A) of the second type of conductivity extending in the epitaxial semiconductor layer from the first depth (p3) to the first face (101A) of the semiconductor substrate (101), the first buried semiconductor box being in contact with the first semiconductor box and the buried semiconductor region (111;211); and at least a second semiconductor region (115B, 116B) comprises: - a second semiconductor box (116B) of the second type of conductivity positioned from the first face (102A) of the epitaxial semiconductor layer (102) to the first depth (p3) in the epitaxial semiconductor layer;and - a second buried semiconductor box (115B) of the second type of conductivity extending in the epitaxial semiconductor layer from the first depth (p3) to the first face (101A) of the semiconductor substrate (101), the second buried semiconductor box being in contact with the second semiconductor box and the buried semiconductor region (111;211); at least one electronic circuit (11; 21) being, for example, at a level located between the first and second buried semiconductor boxes (115A, 115B) and the first face (102A) of the epitaxial semiconductor layer (102).;

3. Electronic device according to claim 2, wherein the first and second buried semiconductor boxes (115A, 115B) are isolated from each other by a semiconductor portion (114) of the epitaxial semiconductor layer (102) which extends to the first face (101A) of the semiconductor substrate (101), at least one electronic circuit (11; 21) being for example positioned between the semiconductor portion (114) and the first face (102A) of the epitaxial semiconductor layer (102).

4. Electronic device according to claim 2 or 3, wherein the first and second semiconductor boxes (116A, 116B) are isolated from each other by another semiconductor box (113) of the first type of conductivity, and, for example also by an insulating trench (112) included between the first face (102A) of the epitaxial semiconductor layer (102) and the other semiconductor box (113).

5. Electronic device according to claim 4 in its dependence on claim 3, wherein the semiconductor portion (114) is included between the other semiconductor box (113) and the buried semiconductor region (111).

6. Electronic device according to any one of claims 1 to 5, wherein: - at least a second semiconductor region is electrically isolated from at least a first semiconductor region; and / or - at least one electronic circuit (11; 21) is positioned in the epitaxial semiconductor layer; and / or - the buried semiconductor region (111; 211) is below at least one electronic circuit (11; 21).

7. Electronic device according to any one of claims 1 to 6, wherein the detection device (100; 200) comprises: - a first electrical contact (123A) to the first face (102A) of the epitaxial semiconductor layer (102) connecting the at least one first semiconductor region (115A, 116A) to the first node (141); - a second electrical contact (123B) to the first face (102A) of the epitaxial semiconductor layer (102) connecting the at least one second semiconductor region (115B, 116B) to the second node (142).

8. Electronic device according to claim 7 in its dependence on any one of claims 2 to 5, wherein the first electrical contact (123A) is in contact with the first semiconductor box (116A), and the second electrical contact (123B) is in contact with the second semiconductor box (116B).

9. Electronic device according to any one of claims 1 to 8, wherein the buried semiconductor region (111), at least one first semiconductor region (115A, 116A) and at least one second semiconductor region (115B, 116B): - are included in a semiconductor structure (110) located in the semiconductor substrate (101) and in the epitaxial semiconductor layer (102); and / or - form an electrical conduction channel (130; 230) connected to the first and second nodes of the sensing circuit (140), an open circuit between the first and second nodes being an open circuit in the electrical conduction channel (130), preferably in the buried semiconductor region (111).

10. Electronic device according to any one of claims 1 to 9, wherein the buried conductive region (111; 211) extends to a depth greater than 2 pm, for example greater than or equal to 3 pm, or to 4 pm.

11. Electronic device according to any one of claims 1 to 10, wherein the at least one electronic circuit comprises a plurality of electronic circuits (21) configured in an array (22), the buried semiconductor region (211) having a shape configured so that said buried semiconductor region runs below each of the electronic circuits of the array.

12. Electronic device according to any one of claims 1 to 11, wherein the buried conductive region (211) has a zigzag shape, with a first end (21 IC) connected to at least a first semiconductor region (115A, 116A) and a second end (211D) connected to at least a second semiconductor region (115B, 116B).

13. Electronic device according to any one of claims 1 to 12, the electronic device being an integrated circuit.

14. Method of using the detection device in an electronic device according to any one of claims 1 to 13, the method of use comprising: - the emission of a voltage level or a current at the first node (141); - the detection by the second node (142) of the presence of an open circuit between the first and second nodes, so as to detect a thinning of the buried semiconductor region (111; 211), for example in the event of an attack by the second face (101B) of the semiconductor substrate (101).

15. A method of use according to claim 14, wherein, if an open circuit is detected, the detection circuit (140) sends a signal (DIS AB LE) to at least one electronic circuit (11; 21) to disable it.

16. A manufacturing method (300) for an electronic device (100), the manufacturing method comprising: - an implantation step (302) from a first face (101A) of a semiconductor substrate (101) of a first type of conductivity, so as to form a buried semiconductor region (111) of the second type of conductivity opposite to the first type of conductivity, the buried semiconductor region being formed between a second face (101B) of the semiconductor substrate, opposite to the first face of said semiconductor substrate, and at least one electronic circuit (11);- an epitaxial growth step (304) on the first face of the semiconductor substrate so as to form an epitaxial semiconductor layer (102) doped with the first type of conductivity, said epitaxial semiconductor layer having a first face (102A) and a second face (102B) opposite to the first face of said epitaxial semiconductor layer and positioned on the first face of the semiconductor substrate;- at least one implantation step (310, 312) in the epitaxial semiconductor layer (102) so as to form at least one first semiconductor region (115A, 116A) of the second type of conductivity between the first face of the semiconductor substrate and the first face of the epitaxial semiconductor layer and at least one second semiconductor region (115B, 116B) of the second type of conductivity between the first face of the semiconductor substrate and the first face of the epitaxial semiconductor layer, said at least one first and at least one second semiconductor regions being connected each to the buried semiconductor region (111);a step of linking at least a first semiconductor region to a first node (141) of a detection circuit (140) by the first face of the epitaxial semiconductor layer and at least a second semiconductor region to a second node (142) of the detection circuit (140) by the first face of the epitaxial semiconductor layer.;

Images