Electronic chip incorporating a crack detection device

Abstract

Electronic chip comprising a crack detection device. This description relates to an electronic chip comprising a crack detection device formed in and on a substrate or on the substrate, the device comprising a conductive path having an alternation of lower (201) and upper (203) conductive bands, the path comprising, for each lower band: a first (205A) and a second (205B) conductive vias in contact with the lower band, a third (207A) and a fourth (207B) conductive vias in contact with respectively one upper band and another upper band, at least a first (209A) and a second (209B) conductive tracks connecting respectively the first and third vias and the second and fourth vias, the first and second vias being located perpendicular respectively to a first and a second end of the lower band,the third and fourth being located directly above one end of the band and the other upper band respectively. Figure for the abbreviation: Fig. 2A,

Description

Title of the invention: Electronic chip incorporating a crack detection device. Technical field

[0001] This description relates generally to electronic chips, or integrated circuits, and in particular to an electronic chip comprising a crack detection device, for example integrated into a sealing ring, known as a "seal-ring" in English. Previous technique

[0002] In industry, most electronic devices are manufactured in series. Several electronic chips are thus usually manufactured in and on the same semiconductor substrate, for example, a single semiconductor wafer or slice. The electronic chips can then be separated, or individualized, for use, for example, alone or in an electronic device containing other components. This individualization is generally carried out by cutting, for example, using a saw.

[0003] During this individualization process, for example during the cutting of a semiconductor wafer, a crack may form on an edge of an electronic chip and propagate through the chip. Such a crack may lead to a failure of the electronic circuits of the electronic chip.

[0004] In addition, cracks may form during the lifetime of the chip, in particular on an edge of the chip, for example due to temperature changes in the electronic chip.

[0005] To protect an electronic chip, particularly during manufacturing, individualization, or use, the electronic chip may include a sealing ring around its periphery. One purpose of the sealing ring is to prevent cracks from propagating from the edge to a region of the chip's electronic circuits. Another purpose of the sealing ring is to prevent moisture from penetrating the chip's active regions. However, the sealing ring does not always prevent crack formation and propagation within the electronic chip. Thus, an electronic chip may include a crack detection device, for example, integrated into a sealing ring. The crack detection device can be used to test the chip's integrity during manufacturing, for example, after the dicing step, or during chip use.

[0006] It would be desirable to be able to improve, at least in part, electronic chips, and in particular the crack detection devices integrated into the electronic chips. Summary of the invention

[0007] To this end, one embodiment provides an electronic chip comprising a semiconductor substrate and a crack detection device formed in and on the semiconductor substrate or on the semiconductor substrate, the crack detection device comprising, between the first and second electrical connection terminals of the device, a serpentine conductive path having an alternation of lower conductive bands and upper conductive bands connected in series, wherein the conductive path comprises, for each lower conductive band: - a first conductor via and in contact with the lower conductive strip, - a second conductor via and in contact with the lower conductive strip, - a third conductor via and in contact with an overlying upper conductive strip, - a fourth conductor via a conductor under and in contact with another, higher, overlying conductive strip, - at least one first intermediate conductive track connecting the first and third conductive vias, and - at least one second intermediate conductive track connecting the second and fourth conductive vias, the first via conductor being located directly above one end of the lower conductive strip and the second via conductor being located directly above one end of the lower conductive strip, the third via conductor being located directly above one end of the upper conductive strip above, and the fourth via conductor being located directly above one end of the other upper conductive strip above, at least 80% of the length of the crack detection device being occupied, in top view, by the upper conductive strips and at least 80% of the length of the crack detection device being occupied, in bottom view, by the lower conductive strips, and in which the lower conductive bands are made of a doped semiconductor material and the upper conductive bands are made of metal.

[0008] According to one embodiment, in the crack detection device: - the first via conductor is located directly above a central part of the overlying upper conductive strip; - the second via conductor is located directly above a central part of the other upper conductive strip above; - the third conductor via is located directly above a central portion of the lower conductive strip; and - the fourth conductor via is located directly above said central part of the lower conductive strip.

[0009] According to one embodiment, in the crack detection device, the fourth conductive via is aligned with the second conductive via, the fourth conductive via being located vertically above said second end of the lower conductive layer and the second conductive via being located vertically above said end of the other overlying upper conductive strip.

[0010] According to one embodiment, in the detection device, the third conductor via is located vertically above an intermediate part of the lower conductive strip located in the vicinity of the second end of the lower conductive strip, said intermediate part being located between the central part and the second end of the lower conductive strip.

[0011] According to one embodiment, for each lower conductive strip, the first via is entirely located vertically at the 20%, preferably the 10%, of the strip length furthest from the second end of said lower conductive strip, and the second via is entirely located vertically at the 20%, preferably the 10%, of the lower conductive strip length furthest from the first end of said lower conductive strip.

[0012] According to one embodiment, for each lower conductive strip, said central part of the lower conductive strip occupies less than 50%, preferably less than 30%, and more preferably less than 20% of the length of said lower conductive strip.

[0013] According to one embodiment, the lower conductive strip is made of silicon.

[0014] According to one embodiment, the chip is delimited by an edge and the device of Crack detection is arranged between the edge of the electronic chip and a region of electronic circuits of the electronic chip.

[0015] According to one embodiment, the semiconductor substrate comprises a doped portion of a first type of conductivity, the lower conductive band being entirely formed in the portion of the semiconductor substrate.

[0016] According to one embodiment, the lower conductive strips are separated in pairs by insulation trenches.

[0017] According to one embodiment, the third and fourth conductor vias connected to the same upper conductive strip are associated with two consecutive lower conductive strips, the third conductor via being associated to a lower conductive strip and the fourth via conductor being associated with another lower conductive strip.

[0018] According to one embodiment, the lower conductive band is separated from the other lower conductive band by a distance of between 5 nm and 10 pm.

[0019] According to one embodiment, the upper conductive band is separated from the other upper conductive band by a distance of between 20 nm and 10 pm.

[0020] According to one embodiment, the crack detection device comprises several sections, each section having a first and a second electrical connection terminal of the device.

[0021] Another embodiment provides a method for manufacturing an electronic chip, comprising a step of forming a crack detection device in and on a semiconductor substrate or on the semiconductor substrate, the crack detection device comprising, between the first and second electrical connection terminals of the device, a serpentine conductive path comprising alternating lower and upper conductive bands connected in series, wherein the conductive path comprises, for each lower conductive band: - a first conductor via and in contact with the lower conductive strip, a second conductor via and in contact with the lower conductive strip, - a third conductor via and in contact with an overlying upper conductive strip, - a fourth conductor via a conductor under and in contact with another, higher, overlying conductive strip, - at least one first intermediate conductive track connecting the first and third conductive vias, and - at least one second intermediate conductive track connecting the second and fourth conductive vias, the first via conductor being located directly above one end of the lower conductive strip, the second via conductor being located directly above one end of the lower conductive strip, the third via conductor being located directly above one end of the upper conductive strip above, and the fourth via conductor being located directly above one end of the other upper conductive strip above, the length of the crack detection device being occupied, in top view, 80% by the upper conductive strips and, in bottom view, 80% by the lower conductive strips, and in which the lower conductive bands are made of a doped semiconductor material and the upper conductive bands are made of metal.

[0022] According to one embodiment, the method includes a step of testing the electrical conductivity between the first terminal of the crack detection device and the second terminal of the crack detection device, so as to detect a possible crack cutting the conductive path. Brief description of the drawings

[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0024] [Fig.1A], [Fig.1B] and [Fig.1C] are partial and schematic views of an example of an electronic chip;

[0025] [Fig. 2A] and [Fig. 2B] are partial and schematic views of an example of an electronic chip according to one embodiment; and

[0026] [Fig.3] is a partial and schematic cross-sectional view of an example of an electronic chip according to another embodiment. Description of the implementation methods

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, not all manufacturing steps and details of the electronic chips are described, as the described embodiments are compatible with conventional electronic chip manufacturing processes. Similarly, the electronic circuits of the electronic chips are not detailed, as the embodiments are compatible with different electronic circuits within a single electronic chip. Furthermore, not all manufacturing steps and details of the sealing rings and crack detectors are described, as the described embodiments are feasible with conventional manufacturing processes for sealing rings and crack detectors.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0030] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to Orientation qualifiers, such as the terms "horizontal", "vertical", etc., refer to the orientation of the figures unless otherwise specified.

[0031] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0032] In the following description, the terms "insulator" and "conductor" mean, respectively, electrically insulating and electrically conductive. Similarly, the term "insulate" means, unless otherwise specified, to insulate electrically.

[0033] In the following description, unless otherwise specified, references to a chip refer to an electronic chip, and references to a via refer to a conductive via. Furthermore, in the following description, the term via does not necessarily refer to a single unit but may, for example, be composed of several elements enabling the electrical connection function.

[0034] In the following description, reference is made to a crack detection device, or for short, a crack detector, and is meant to be a device capable of detecting a structural defect that is not limited to a crack; for example, it could be a breach or delamination. For the sake of brevity, when a crack is referred to, this may include a breach, delamination, or any other similar structural defect.

[0035] In the following description, a first metallization level of an interconnect structure generally corresponds to the metallization level closest to a semiconductor substrate on which the interconnect structure is formed and to which it is connected. A second metallization level of the interconnect structure corresponds to a metallization level further from the semiconductor substrate than the first metallization level. More generally, an N+1 metallization level corresponds to a metallization level further from the semiconductor substrate than the N metallization level.

[0036] Fig. 1A, Fig. 1B and Fig. 1C are schematic partial views of an example of an electronic chip 100. In particular, Fig. 1A is a top view, Fig. 1B is a sectional view along section plane BB of Fig. 1A and Fig. 1C is a sectional view along section plane CC of Fig. 1A.

[0037] In Figures IA to IC, the electronic chip 100 is shown already individualized. However, in practice, this description can also apply to a non-individualized chip, when the chip is still part of a semiconductor wafer comprising, for example, a plurality of chips.

[0038] The chip 100 comprises a semiconductor substrate 101, for example made of silicon, for example made of monocrystalline silicon. The chip 100 comprises, for example, circuits Electronic circuits are formed on and within the substrate 101. In top view, the electronic circuits are formed within an electronic circuit region 105, or circuit region, of the chip 100. For example, in top view, the circuit region 105 is located in a central portion of the chip 100. The region 105 is, for example, delimited by a circumference 105L. As an example, the circuit region 105 comprises all the electronic circuits of the chip 100.

[0039] By way of example, the circuit region 105 of the chip 100 is laterally surrounded by a sealing structure 107 or seal ring. In other words, the sealing structure 107 is formed on the periphery of the chip 100, that is, between the circuit region 105 and an edge 110 of the chip 100. The sealing structure 107 has, for example, an annular shape in top view. By way of example, the chip 100 includes electrical connections between the circuit region 105 and the sealing structure 107.

[0040] In this example, the sealing structure 107 is formed within an interconnection structure 102 disposed above the semiconductor substrate 101, for example, in contact with the semiconductor substrate 101. This interconnection structure 102 is also referred to as the "back end of line" interconnection structure, or for short, the "BEOL" interconnection structure. The interconnection structure 102 may include, for example, in a central portion of the chip, metallic interconnection elements for the electronic circuits of the chip.

[0041] The sealing structure 107 is arranged in the interconnection structure 102, at the periphery of the chip 100.

[0042] The interconnection structure 102 comprises, for example, a plurality of metallization levels. In Figures IB and IC, six metallization levels M1, M2, M3, M4, M5, M6 are shown. In practice, the number of metallization levels may differ from six.

[0043] By way of example, within the circuit region 105, the metallization levels each comprise at least one portion 103C of a conductive layer 103. By way of example, each portion 103C corresponds to a conductive element in the form of a conductive track, or conductive line.

[0044] The conductive layer 103 is for example a metallic layer, for example made of copper.

[0045] The portions 103C of the different metallization levels are, for example, electrically connected to each other by conductive vias 106. By way of example, the upper metallization level, for example the metallization level M6, is connected, via its upper face, to a connecting pad 104. By way of example, the pads 104 are arranged on an upper face 102A of the interconnection structure 102, a lower face 102B of the interconnection structure, opposite the upper face 102A, being in contact with the semiconductor substrate 101.

[0046] The pads 104 are for example distributed in a substantially annular manner, here a ring of square shape, in the circuit region 105 of the chip 100. The embodiments described are not limited however to this particular arrangement.

[0047] The pads 104 are configured to be in contact with conductive elements located outside the chip 100, so as to electrically connect the chip to an external system.

[0048] The metallization levels of the interconnection structure 102 are, for example, surrounded by insulating layers, which are all designated by the same and unique reference 111.

[0049] One intended function of the sealing structure 107 is to prevent the propagation of cracks from the edge 110 of the chip 100 to the circuit region 105 of the chip 100.

[0050] Another intended function of the sealing structure 107 may be to block the propagation of moisture from outside the chip 100, i.e. from the edge 110 of the chip 100, to the electronic circuits of the circuit region 105 of the chip 100.

[0051] To fulfill one or more of these functions, the sealing structure 107 may include one or more sealing elements 108, each sealing element 108 having an annular shape in top view.

[0052] Each sealing element 108 extends vertically from the semiconductor substrate 101 through all or part of the metallization levels M1-M6 of the interconnecting structure 102, for example through one or more lower metallization levels of the interconnecting structure 102. For protection against moisture, however, it is preferable that the sealing element 108 extends up to the upper metallization level, here level M6.

[0053] The sealing element 108 shown forms a closed loop around the circuit region 105 of the chip 100, or, in other words, the sealing element 108 completely surrounds the circuit region 105 of the chip 100.

[0054] In the embodiment shown in [Fig. 1B], the sealing element 108 forms an annular wall comprising other portions 103A of the conductive layers 103 of the interconnecting structure 102. More specifically, the sealing element 108 comprises a portion 103A of the conductive layer 103 from each metallization level M1-M6 of the interconnecting structure 102. Each portion 103A of the conductive layer 103 forms an annular conductive plate at each metallization level. The successive annular conductive plates 103A of the element sealing plates 108 are connected to each other by one or more annular conductive strips 112 which extend continuously between two successive annular conductive plates 103A.

[0055] As shown in [Fig.1B], the successive annular conductive plates 103A of the sealing element 108 can further be connected to each other by conductive vias 106 of the interconnecting structure 102, allowing for example to increase the mechanical resistance of the sealing element 108 against crack propagation.

[0056] The sealing element 108 can form a protective wall against the propagation of moisture towards the circuit region 105 of the chip 100.

[0057] As shown in [Fig. 1B], the sealing element 108 may include a dummy stud 104A, which is, for example, formed at the same time as the studs 104. The dummy stud 104A rests on the annular conductive plate 103A at the upper metallizations M6 of the interconnecting structure 102. The dummy stud 104A may be arranged in a substantially annular configuration; here it forms a square ring. There may be several dummy studs.

[0058] To detect cracks in the chip 100, the sealing structure 107 may include a crack detection device 116, or crack detector. In this example, the crack detector 116 is formed on the semiconductor substrate, in the interconnecting structure 102. As shown in Figures IA, IB, and IC, the crack detection device 116 may be located in a region between the edge 110 of the chip 100 and the sealing element 108. Thus, if a crack appears at the edge 110 of the chip 100 and propagates toward the circuit region 105, the crack can be detected by the crack detection device 116 before reaching the sealing element 108. Other configurations are also possible.

[0059] By way of example, the crack detection device 116 is placed between two separate sealing elements 108. The crack detection devices 116 and the sealing elements 108 are not limited to those described. Furthermore, the number of crack detection devices 116 and sealing elements 108 is not limited. Thus, several examples of crack detection devices 116 and sealing elements 108 can be provided in the sealing structure 107.

[0060] The crack detection device 116 corresponds to a conductive structure that forms a conductive path, preferably an open loop, between a first terminal, or node 118, for example a first end of the detection device 116, and a second terminal 119, for example a second end of the detection device 116. By testing the electrical conductivity between the first terminal 118 of the detection device 116 and the second terminal 119 of the detection device 116, cracks can be detected by the detection device 116. Alternatively, The crack detection device 116 comprises several sections not electrically connected to each other, each section having two terminals.

[0061] In the exemplary embodiment shown in Figures IB and IC, the crack detection device 116 comprises a plurality of metal stacks 109, each comprising other portions 103B of the conductive layers 103 connected by conductive vias 106 of the interconnection structure 102. The metal stacks 109 are, for example, arranged along the crack detection device 116. More specifically, each metal stack 109 extends vertically in the Z direction perpendicular to the XY plane of the semiconductor substrate 101 through all or part of the metallization levels M1-M6 of the interconnection structure 102, in the example shown up to the upper metallization level M6. As an example, the 109 metal stacks each have two facing vertical parts, for example identical, connected to each other only by the upper level of metallization, for example level M6.The metal stacks 109 each have the shape of a bridge whose feet or pillars are the two vertical parts and whose deck corresponds to the conductive layer 103 of the metallization level M6. .

[0062] In the example shown, the neighboring feet of two neighboring metal stacks 109 are connected only by a metal layer 114 formed in the metallization level ML. Thus, the crack detection device 116 has, in cross-sectional view, according to the cross-sectional plane of [Fig.1C], a crenellated serpentine shape whose vertical parts correspond to the vertical pillars of the metal stacks 109 and whose horizontal parts are, alternately, portions of the lower layer 114 of the lower metallization level M1 and portions of the layer 103 of the upper metallization level M6.

[0063] The inventors have observed that cracks can propagate in the sealing structure 107, or even cross through the sealing structure, without being detected by the crack detector 116.

[0064] In particular, some vertical cracks are likely to propagate through the crack detection device 116, possibly deforming the lower metal layer 114 but without breaking it due to the ductile nature of the layer 114. These cracks thus do not cause a break in the conductive path between the terminals 118 and 119 of the detection device 116, and are therefore not detected.

[0065] In addition, horizontal cracks propagating under the sealing structure 107, and more particularly between layer 114 and substrate 101, may also not be detected.

[0066] Fig. 2A and Fig. 2B are partial and schematic views of an example of an electronic chip 200 according to an embodiment, Fig. 2B being an illustrative top view photograph and Fig. 2A being a schematic cross-sectional view along the section plane AA of Fig. 2B.

[0067] The electronic chip 200 is for example similar to the electronic chip 100 illustrated in figures IA to IC except that the chip 200 includes a crack detection device 216 different from the crack detection device 116.

[0068] Like the device 116 in Figures IA to IC, the device 216 includes an electrically conductive path, for example in the form of an open loop laterally surrounding the active parts of the chip, between two connection terminals (not visible in Figures 2A and 2B) corresponding, for example, to terminals 118 and 119 of the device 116. In top view, the arrangement of the crack detection device 216 is, for example, similar to that of the device 116. Similar to what has been described in relation to Figures IA to IC, the crack detection device 216 may include several sections connected by additional terminals. Thus, the number of terminals within the crack detection device 216 is not limited to two.

[0069] The detection device 216 of Figures 2A and 2B comprises a serpentine conductive path having an alternation of lower conductive bands 201 and upper conductive bands 203 connected in series between the connection terminals of the device.

[0070] According to one aspect of the described embodiments, the lower conductive bands are made of a doped semiconductor material, for example doped silicon.

[0071] In one embodiment, each lower conductive band 201 is formed by a doped region of the substrate 101 such that the bands 201 are flush, by their upper faces, with the upper face of the substrate 101. By way of example, the bands 201 extend into the substrate 101 over a depth in a range from a few nm, for example 10 nm, to 100 nm.

[0072] Alternatively, the conductive strips 201 are embedded in the substrate 101. In this embodiment, each conductive strip 201 is extended to the upper surface of the substrate 101, at least at both ends, for example, at both ends only. By way of example, the extension of the strips 201 is achieved by means of another conductive layer. Thus, the conductive layer 201 does not extend onto the upper surface of the substrate 101, and only the extensions in the other conductive layer extend onto the upper surface of the substrate 101.

[0073] By way of example, the substrate 101 includes a 101P portion doped with a first type of conductivity, for example of type P.

[0074] By way of example, the first part 101P of the substrate 101 extends deeper than the conductive bands 201. That is to say, the conductive bands 201 are entirely formed in the upper part 101P of the substrate 101.

[0075] The lower conductive bands 201 are, for example, doped with a second type of conductivity opposite to that of the 101P region. As an example, the lower conductive bands 201 are N-type doped.

[0076] This configuration ensures electrical isolation of the 201 strips from each other and from the substrate.

[0077] By way of example, the conductive strips 201 are made of a semiconductor material. By way of example, the conductive strips 201 are made of a non-ductile material (i.e., a material that cannot be elongated, stretched or extended without breaking), for example less ductile than the metals of the interconnecting structure.

[0078] Alternatively, the lower conductive bands 201 are formed on the substrate 101, for example in a conductive grid formation level of doped polycrystalline silicon. More generally, the lower conductive bands 201 can be formed in any other formation level present below the metallization level M1.

[0079] The conductive strips 201 are, for example, aligned along a longitudinal axis of the conductive path of the crack detector, and not directly connected to each other. For example, the conductive strips 201 are separated in pairs by insulating trenches 202 made of an insulating material, for example, silicon oxide. For example, the trenches 202 extend deeper than the conductive strips 201. The trenches 202 are, for example, formed simultaneously with other insulating trenches formed, for example, around transistors in the circuit region 105. The trenches 202 are, for example, STI (Shallow Trench Isolation) type trenches. Alternatively, the trenches 202 are, for example, DTI (Deep Trench Isolation) type trenches.

[0080] By way of example, the distance between two adjacent bands 201 is greater than 5 nm. The distance between two adjacent bands 201 is, for example, less than 10 pm. The distance between two adjacent bands 201 is, for example, less than 5 pm. Indeed, the reliability of the crack detection device 216 depends, among other things, on the distance between two adjacent bands 201; this distance must therefore be as small as possible in order to increase the reliability of the device.

[0081] The upper conductive bands 203 are, for example, aligned along a longitudinal axis of the conductive path of the crack detector, parallel to the lower conductive bands 201, and not directly connected to each other. They are by example spaced two by two by a thin region in a dielectric material of the interconnecting structure.

[0082] By way of example, the distance between two adjacent bands 203 is greater than 20 nm. The distance between two adjacent bands 203 is, for example, less than 10 pm. The distance between two adjacent bands 203 is, for example, less than 5 pm. Indeed, similarly to what has been described for the distance between the bands 201, the reliability of the crack detection device 216 depends, among other things, on the distance between two adjacent bands 203; this distance must therefore be as small as possible in order to increase the reliability of the device.

[0083] By way of example, the lower conductive bands 201 are mostly covered by the upper conductive bands 203. That is to say, a majority of the surface of the lower conductive bands 201 is covered by the upper conductive bands 203.

[0084] By way of example, the lower bands 201 are formed below and opposite the upper bands 203. The lower bands 201 are, however, offset relative to the upper bands 203 such that a central portion of an upper band 203 is vertically aligned with a separation region between two consecutive lower bands 201, and a central portion of a lower band 201 is vertically aligned with a separation region between two consecutive upper bands 203. The lower conductive bands 201 and the upper conductive bands 203 are, for example, substantially the same length. Alternatively, the lower conductive bands 201 and the upper conductive bands 203 may have different lengths.

[0085] Each of the lower conductive strips 201 is connected to a first conductive via 205A, each of the first vias 205A being formed on and in contact with the conductive strip 201 to which it is connected.

[0086] Each first via conductor 205A is located directly above a first end of the lower conductive strip 201 to which it is connected. By way of example, each first via 205A is thus entirely located directly above the 20%, preferably the 10%, of the length of the lower conductive strip 201 furthest from a second end of the lower conductive strip 201, opposite the first end. Furthermore, each first via 205A is, in the embodiment illustrated in [Fig. 2A], located directly above a central portion of the overlying upper conductive strip 203.

[0087] Each of the lower conductive strips 201 is further connected to a second conductive via 205B, each of the second vias 205B being formed on and in contact with the conductive strip 201 to which it is connected.

[0088] Each second via conductor 205B is located directly above the second end of the lower conductive strip 201 to which it is connected. By way of example, each second via 205B is thus entirely located directly above the 20%, preferably the 10%, of the length of the lower conductive strip 201 furthest from the first end of said lower conductive strip 201. Furthermore, each second via 205B is, in the embodiment illustrated in [Fig. 2A], located directly above a central portion of the overlying upper conductive strip 203.

[0089] By way of example, the vias 205A and 205B associated with the same lower conductive strip 201 are covered by two consecutive upper conductive strips 203. In the example of [Fig. 2A], the via 205A is covered by the upper strip 203 and is formed opposite a central portion of the upper strip 203. In the example of [Fig. 2A], the via 205B is covered by the upper strip 203' and is formed opposite a central portion of the upper strip 203'.

[0090] By way of example, the central part of an upper conductive strip 203, directly above which are located a first 205A and a second 205B via, occupies less than 50%, preferably less than 30%, and more preferably less than 20% of the length of said upper conductive strip 203.

[0091] The crack detection device 216 further comprises, opposite each conductive strip 201, a third conductive via 207A. The third via 207A is formed under and in contact with an overlying upper conductive strip 203.

[0092] Each third via conductor 207A is located directly above a first end of the upper conductive strip 203 to which it is connected. By way of example, each third via 207A is thus entirely located directly above the 20%, preferably the 10%, of the length of the upper conductive strip furthest from a second end of said upper conductive strip 203, opposite the first end. Furthermore, each third via 207A is, in the embodiment illustrated in [Fig. 2A], located directly above a central portion of the underlying lower conductive strip 201.

[0093] The crack detection device 216 further comprises, opposite each conductive strip 201, a fourth conductive via 207B. The fourth via 207B is formed under and in contact with an overlying upper conductive strip 203.

[0094] The vias 207A and 207B are formed under two consecutive upper conductive bands 203. In the example of [Fig. 2A], the via 207A is formed under the upper band 203. In the example of [Fig. 2A], the via 207B is formed under the upper band 203'.

[0095] Each fourth via conductor 207B is located directly above a first end of the upper conductive strip 203' above. By way of example, each fourth via 207B is thus entirely located directly above the 20%, preferably 10% of the length of the upper conductive strip furthest from a second end of said upper conductive strip 203, opposite the first end. Furthermore, every fourth via 207B is, in the embodiment illustrated in [Fig. 2A], located directly above a central portion of the underlying lower conductive strip 201.

[0096] By way of example, the central part of the lower conductive strip 201, directly above which the third 207A and fourth 207B vias are located, occupies less than 50%, preferably less than 30%, and more preferably less than 20% of the length of said lower conductive strip 201.

[0097] By way of example, each upper conductive strip, for example strip 203' in [Fig. 2A], is connected: - to a fourth conductor via, for example via 207B in [Fig.2A], and - to a third conductor via, for example via 207A' in [Fig.2A], the third and fourth conductor via being formed opposite two consecutive lower bands.

[0098] The crack detection device 216 further comprises, in line with each lower band 201, at least one first intermediate conductive track 209A connecting the first 205A and third 207A conductive vias, and at least one second intermediate conductive track 209B connecting the second 205B and fourth 207B conductive vias.

[0099] By way of example, the first via conductor 205A is connected to the first intermediate conductive track 209A directly above a first end of the first track 209A. By way of example, the third via 207A is connected to the first intermediate conductive track 209A directly above a second end of the first track 209A, opposite the first end of the first track 209A.

[0100] Similarly, by way of example, the second via conductor 205B is connected to the second intermediate conductive track 209B directly above a first end of the second track 209B. By way of example, the fourth via 207B is connected to the second intermediate conductive track 209B directly above a second end of the second track 209B, opposite the first end of the second track 209B.

[0101] By way of example, the serpentine conductive path of the crack detection device 216 comprises the succession of upper conductive strips 203, 203', 203”, third conductive vias 207A, 207A', 207A”, first intermediate conductive tracks 209A, 209A', 209A”, first conductive vias 205A, 205A', 205A”, lower conductive strips 201, 201', 201”, second conductive vias 205B, 205B', second intermediate conductive tracks 209B, 209B' and fourth conductive vias 207B, 207B'.

[0102] The upper conductive bands 203 are made of metal or a metal alloy. By way of example, the bands 203 are made of copper, aluminum, or a copper-aluminum alloy.

[0103] The third 207A and fourth 207B via conductors are for example made of metal, for example copper, aluminium or a mixture of copper and aluminium.

[0104] The first 205A and second 205B via conductors are for example made of a metallic material, for example tungsten or tantalum, or a mixture of copper and tantalum.

[0105] By way of example, although not shown in [Fig.2A], the conductive vias 207A and 207B can each correspond to a conductive stack formed of other conductive intermediate tracks and vias connecting the intermediate tracks.

[0106] In this example, the conductive vias formed between intermediate conductive tracks are formed directly above one of the ends of the overlying and underlying conductive tracks or opposite a central part of these intermediate conductive tracks.

[0107] By way of example, the vias connecting two intermediate conductive tracks are aligned vertically.

[0108] Alternatively, the vias connecting two intermediate conductive tracks are not vertically aligned.

[0109] As shown in [Fig. 2B], the sealing structure 107 may include an internal crack detection device 2161 disposed in the interconnection structure 102 around, or on the edges of, the circuit region 105 and be surrounded by the sealing element 108, or the internal sealing element. The internal crack detection device 2161 allows the detection of cracks that have propagated from the edge 110 of the chip 100 through the sealing element(s) and may reach the circuit region 105.

[0110] As shown in [Fig.2B], the sealing structure 107 may further include an external crack detection device 216E disposed in the interconnecting structure 102 around the sealing element 108.

[0111] As an alternative, either of the crack detection devices 2161 and 216E may be omitted. In addition, the sealing element 108 may be omitted.

[0112] Fig. 3 is a partial, schematic cross-sectional view of an example of an electronic chip 300 according to another embodiment.

[0113] The electronic chip 300 comprises, for example, the same elements as the chip 200 illustrated in Figures 2A and 2B. The chip 300 further comprises a crack detection device 316 similar to the crack detection device 216, except that the structure, formed by the vias 205A, 205B, 207A and 207B, the lower band 201, upper bands 203 and 203' and tracks 209A and 209', is not symmetrical.

[0114] In this embodiment, vias 205B and 207B are aligned.

[0115] In this embodiment, each via 207B is located directly above a via 205B. In this embodiment, each of the vias 205B and 207B is located directly above the second end of the lower conductive strip 201 below. Furthermore, in this embodiment, each of the vias 205B and 207B is located directly above the first end of the upper conductive strip 203' above.

[0116] By way of example, the third via conductor 207A is located directly above an intermediate portion situated in the vicinity of the second end of the underlying lower conductive strip 201, the intermediate portion being situated between the second end and the central portion of the lower conductive strip 201.

[0117] By way of example, the first via conductor 205A is located directly above an intermediate part situated in the vicinity of a second end of the upper conductive strip 203 above, the intermediate part being situated between the second end and the central part of the upper conductive strip 203.

[0118] More generally, the conductive tracks 201 and 203 may have arrangements other than those described in relation to Figures 2A and 3. According to one aspect of the described embodiments, at least 80%, preferably at least 90%, of the length of the crack detection device is occupied, in top view or in a horizontal section plane FF in the upper metallization level of the conductive strips 203, 203', 203”, by the upper conductive strips 203, 203', 203”.

[0119] Similarly, according to one aspect of the described embodiments, at least 80%, preferably at least 90%, of the length of the crack detection device is occupied, viewed from below, or in a horizontal section plane BB in the lower conductive strips 201, 201', 201”, by the lower conductive strips 201, 201', 201”.

[0120] An advantage of the described embodiments is related to the shape of the coil constituting the conductive path of the crack detection device 216, comprising a succession of nested head-to-tail loops, offering good coverage of the detection surface by both the upper conductive bands 203 and the lower conductive bands 201. This makes it possible to increase the detection sensitivity.

[0121] The small distance separating the consecutive lower conductive bands 201, and the small distance separating the consecutive upper conductive bands 203 also makes it possible to increase the detection sensitivity.

[0122] Another advantage of the described embodiments is that the presence of intermediate conductive tracks makes it possible to detect intermetallic delaminations.

[0123] Another advantage of the described embodiments is related to the use of a semiconductor material, non-ductile (i.e. a material that cannot be elongated, stretched or extended without breaking) or less ductile than the metals of the interconnecting structure, to form the lower conductive bands 201. This allows better detection of vertical cracks or delaminations between the metallization levels and the semiconductor substrate.

[0124] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to them. In particular, although not shown in Figures 2A and 2B, it can be foreseen that each conductive via 205A, 205B, 207A, and 207B corresponds to a set of several grouped conductive vias, i.e., conductive vias formed in close proximity to one another.

[0125] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

1. Demands Electronic chip (200; 300) comprising a semiconductor substrate (101) and a crack detection device (216; 316) formed in and on the semiconductor substrate or on the semiconductor substrate (101), the crack detection device (216; 316) comprising, between first (118) and second (119) electrical connection terminals of the device, a serpentine conductive path comprising alternating lower conductive bands (201, 201', 201") and upper conductive bands (203, 203', 203") connected in series, wherein the conductive path comprises, for each lower conductive band (201): - a first via conductor (205A) on and in contact with the lower conductive strip (201), - a second via conductor (205B) on and in contact with the lower conductive strip (201), - a third via conductor (207A) under and in contact with an overlying upper conductive strip (203), - a fourth conductor via (207B) below and in contact with another upper conductor strip (203') above, - at least one first intermediate conductive track (209A) connecting the first (205A) and third (207A) conductive vias, and - at least one second intermediate conductive track (209B) connecting the second (205B) and fourth (207B) conductive vias, the first via conductor (205A) being located directly above one end of the lower conductive strip (201) and the second via conductor (205B) being located directly above one end of the lower conductive strip (201), the third via conductor (207A) being located directly above one end of the overlying upper conductive strip (203), and the fourth via conductor (207B) being located directly above one end of the other overlying upper conductive strip (203'), at least 80% of the length of the crack detection device (216; 316) being occupied, in top view, by the upper conductive strips (203, 203', 203”) and at least 80% of the length of the crack detection device being occupied, in view from below, by the lower conductive bands (201, 201', 201”), and wherein the lower conductive bands (201) are made of a doped semiconductor material and the upper conductive bands (203, 203', 203”) are made of metal.

2. Electronic chip according to claim 1, wherein, in the crack detection device (216): - the first via conductor (205A) is located above a central portion of the upper conductive strip (203) above; - the second via conductor (205B) is located above a central portion of the other upper conductive strip (203') above; - the third via conductor (207A) is located above a central portion of the lower conductive strip (201); and - the fourth via conductor (207B) is located above said central portion of the lower conductive strip (201).

3. Electronic chip according to claim 1, wherein, in the crack detection device (316), the fourth via conductor (207B) is aligned with the second via conductor (205B), the fourth via conductor (207B) being located vertically above said second end of the lower conductive layer (201) and the second via conductor (205B) being located vertically above said end of the other upper conductive strip (203') above.

4. Electronic chip according to claim 3, wherein, in the detection device (316), the third via conductor (207A) is located in line with an intermediate portion of the lower conductive strip (201) located in the vicinity of the second end of the lower conductive strip (201), said intermediate portion being located between the central portion and the second end of the lower conductive strip (201).

5. Electronic chip according to any one of claims 1 to 4, wherein, for each lower conductive strip (201), the first via (205A) is entirely located directly above the 20%, preferably the 10%, of the strip length furthest from the second end of said lower conductive strip (201), and the second via (205B) is entirely located directly above the 20%, preferably the 10%, of the conductive strip length lower (201) furthest from the first end of said lower conductive strip (201).

6. Electronic chip according to any one of claims 1 to 5, wherein, for each lower conductive strip (201), said central part of the lower conductive strip (201) occupies less than 50%, preferably less than 30%, and more preferably less than 20% of the length of said lower conductive strip (201).

7. Electronic chip according to any one of claims 1 to 6, wherein the lower conductive strip (201) is made of silicon.

8. Electronic chip according to any one of claims 1 to 7, delimited by an edge (110), the crack detection device (216; 316) being disposed between the edge (110) of the electronic chip (200) and an electronic circuit region (105) of the electronic chip.

9. Electronic chip according to any one of claims 1 to 8, wherein the semiconductor substrate (101) comprises a portion (101P) doped with a first type of conductivity, the lower conductive band (201) being entirely formed in the portion (101P) of the semiconductor substrate (101).

10. Electronic chip according to any one of claims 1 to 9, wherein the lower conductive strips (201, 201', 201”) are separated two by two by insulation trenches (202).

11. Electronic chip according to any one of claims 1 to 10, wherein the third via conductor (207A) and the fourth via conductor (207B) connected to the same upper conductive strip (203) are associated with two consecutive lower conductive strips, the third via conductor (207A) being associated with a lower conductive strip (201) and the fourth via conductor being associated with another lower conductive strip (201').

12. Electronic chip claim 11, wherein the lower conductive strip (201) is separated from the other lower conductive strip (201') by a distance of between 5 nm and 10 pm.

13. Electronic chip according to any one of claims 1 to 12, wherein the upper conductive strip (203) is separated from the other upper conductive strip (203') by a distance between 20 nm and 10 pm.

14. Electronic chip according to any one of claims 1 to 13, wherein the crack detection device (216; 316) comprises several sections, each section having a first (118) and a second (119) electrical connection terminals of the device.

15. A method for manufacturing an electronic chip, comprising a step of forming a crack detection device (216; 316) in and on a semiconductor substrate (101) or on the semiconductor substrate, the crack detection device (216; 316) having, between first (118) and second (119) electrical connection terminals of the device, a serpentine conductive path comprising alternating lower conductive strips (201, 201', 201") and upper conductive strips (203, 203', 203") connected in series, wherein the conductive path comprises, for each lower conductive strip (201): - a first via conductor (205A) on and in contact with the lower conductive strip (201), a second via conductor (205B) on and in contact with the lower conductive strip (201), - a third via conductor (207A) under and in contact with an overlying upper conductive strip (203),- a fourth conductor via (207B) below and in contact with another upper conductor strip (203') above, - at least one first intermediate conductor track (209A) connecting the first (205A) and third (207A) conductor vias, and - at least one second intermediate conductor track (209B) connecting the second (205B) and fourth (207B) conductor vias, the first conductor via (205A) being located above a first end of the lower conductor strip (201), the second conductor via (205B) being located above a second end of the lower conductor strip (201), the third conductor via (207A) being located above one end of the upper conductor strip (203) above, and the fourth conductor via (207B) being located above a, end of the other upper conducting strip (203') above, the length of the crack detection device (216; 316) being occupied, in top view, 80% by the upper conducting strips (203, 203', 203") and, in bottom view, 80% by the lower conducting strips (201, 201', 201"), and wherein the lower conducting strips (201) are made of a doped semiconductor material and the upper conducting strips (203, 203', 203") are made of metal.

16. A method of using the electronic chip (200) according to any one of claims 1 to 14, comprising a step of testing the electrical conductivity between the first terminal (118) of the crack detection device (216; 316) and the second terminal (119) of the crack detection device (216; 316), so as to detect a possible crack cutting the conductive path.

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