Method for creating interconnections
The use of a structured etching stop layer with S2i:3o selectivity addresses etching residue issues in interconnection formation, improving yield and efficiency by simplifying the process and reducing defects.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-26
AI Technical Summary
Existing methods for forming interconnections in microelectronics, such as the 'double Damascus' process, suffer from defects due to etching residues caused by TiN-based masks, leading to decreased production yield and efficiency.
A method involving a structured etching stop layer with S2i:3o selectivity is used between dielectric layers, allowing precise control of etching depth and eliminating the need for a TiN-based mask, thereby reducing etching residues and simplifying the process.
This method improves reproducibility and reduces defects, enhancing the efficiency and reliability of interconnection formation by limiting the number of process steps and preventing residue formation.
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Abstract
Description
Title of the invention: Method for creating interconnections technical field
[0001] The present invention relates to the technical field of interconnections for microelectronics. Its particularly advantageous application is the formation of vias and interconnection lines. STATE OF THE ART
[0002] The interconnections, which are typically formed by so-called "back end of line" or "BEOL" (acronym for "Back End of Line") processes, comprise different levels of metallic lines and metallic vias generally based on copper, in a dielectric matrix.
[0003] A widely adopted solution for forming the different levels of metallic lines and vias is known as the "double Damascus" method. This method involves first forming the various etching masks defining the line and via patterns, one on top of the other, on a thick dielectric layer. This then allows the cavities intended to receive the lines and vias to be formed in the dielectric layer in a single sequence of etching steps. The filling of the cavities with a metal, typically copper, is also carried out in a single deposition sequence. This process is particularly effective for producing interconnected metallic lines and vias.
[0004] However, defects may appear in the metallic lines and vias. These defects are primarily due to etching residues forming in the cavities before the metal is filled. One cause of the formation of these residues is related to the presence of a TiN-based etching mask. The etching residues lead to a decrease in the production yield of functional lines and vias.
[0005] An object of the present invention is to propose a method for forming interconnection lines and vias which at least partially overcomes the disadvantages mentioned above.
[0006] In particular, one object of the present invention is to provide an alternative method for forming interconnect lines and vias. Another object of the present invention is to provide a method for forming interconnect lines and vias that limits or eliminates etching residues. Another object of the present invention is to provide a method for forming interconnect lines and vias that has a limited number of steps. SUMMARY
[0007] To achieve this objective, according to one embodiment, a manufacturing process for an interconnection level is provided, comprising at least one metallic line and at least one metallic via, said process comprising: • the supply of a substrate including at least one connection pad, • the formation, on the substrate, of a first dielectric layer, • the formation, on the first dielectric layer, of a stop layer etching exhibiting S2i:3o selectivity at the etching stage with respect to the first dielectric layer, • a structuring of the etching stop layer, by means of at least one first mask, such that the etching stop layer has at least one first line pattern), said at least one first line pattern comprising at least one via opening, • the formation, on the etching stop layer comprising at least one via opening, of a second dielectric layer, • the formation, on the second dielectric layer, of a second mask defining at least a second line pattern directly above at least a first line pattern, • an etching of the second dielectric layer, said etching being configured to form an upper cavity by partially stopping on the etching stop layer and, • an etching of the first dielectric layer through at least one via opening, said etching being configured to form a lower cavity by stopping at at least one substrate connection pad, • a filling of the lower and upper cavities with at least one metallic material so as to form at least one metallic line in the upper cavity and at least one metallic via in the lower cavity, said at least one metallic line being connected to said at least one metallic via through at least one via opening, and said at least one metallic via being connected to said at least one substrate connection pad.
[0008] This process uses a structured etching stop layer buried between the first and second dielectric layers. This intercalated etching stop layer advantageously allows the dielectric layer(s) to be etched successively, for example in a single step or in a chained fashion, as is the case for the double Damascus process. The number of steps in the process is thus limited. Unlike the double Damascus process, the etching stop layer here allows precise control of the etching depth of the upper cavity, intended to form at least one metallic line. The reproducibility of the process is improved. The cavities defined by the line and via patterns are also advantageously completed in a single step. The number of steps in the process is thus limited.
[0009] Unlike the known double Damascus process, the process according to the invention separates the formation of the first and second etching masks. The first and second etching masks are not directly superimposed. Therefore, it is not necessary to use an etching mask called a hard mask, typically based on TiN, unlike in the double Damascus process. The etching stop layer can act as a hard mask integrated into the stack of dielectric layers. According to an advantageous option, the second mask is based solely on organic materials. The first mask can, for example, be based on one of SiCN, HfO2, SiC, or SiON. This prevents the formation of etching residues in the cavities. Filling defects are thus significantly reduced. The efficiency of the manufacturing process for the interconnecting layers is improved.
[0010] The invention also provides, according to a second aspect, a device typically resulting from this manufacturing process. This device comprises, stacked along a direction z: • a substrate including at least one connection pad, • an interconnection level comprising: • at least one metallic via within a first dielectric layer, said at least one metallic via being connected to said at least one connection pad, • at least one metallic line within a second dielectric layer, said at least one metallic line being connected to said at least one metallic via,
[0011] Advantageously, the device includes, interposed between at least one via and at least one line, an etch stop layer having an etch selectivity S2i:3o with respect to the first dielectric layer, said etch stop layer comprising at least one via opening such that at least one via and at least one line are connected through said at least one via opening.
[0012] The advantages described above with regard to the method apply mutatis mutandis to the device according to the invention. BRIEF DESCRIPTION OF THE FIGURES
[0013] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:
[0014] [Fig. 1] [Fig. 2] [Fig. 3] [Fig. 4] [Fig. 5] [Fig. 6] [Fig. 7] [Fig. 8] [Fig. 9] [Fig. 10] Figures 1 to 10 illustrate, in an xz plane, cross-sections representing different stages of the manufacturing process of an interconnection level according to an embodiment of the present invention.
[0015] [Fig. 11] The [Fig. 11] schematically illustrates in top view a step of the manufacturing process according to an embodiment of the present invention.
[0016] [Fig. 12] [Fig. 13] [Fig. 14] [Fig. 15] [Fig. 16] Figures 12 to 16 schematically illustrate in an xz plane, cross-sections representing different stages of the manufacturing process of an interconnection level according to an embodiment of the present invention.
[0017] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the thicknesses and / or dimensions of the different layers and patterns are not representative of reality. DETAILED DESCRIPTION
[0018] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:
[0019] According to one example, the etching stop layer has an etching selectivity S2i:3o with respect to the first dielectric layer greater than or equal to 5:1.
[0020] According to one example, the structuring of the etching stop layer comprises the following sub-steps: • the formation of the first mask on the etching stop layer, said first mask directly defining at least one first line pattern comprising at least one via opening, • a partial removal of the etching stop layer, only in areas of the etching stop layer not covered by the first mask, so as to expose the first dielectric layer outside the areas covered by the first mask, • the removal of the first mask.
[0021] In this example, the parts covered by the first mask correspond to the first line pattern.
[0022] According to one example, the formation of the first mask is achieved by double lithography. This well-known lithography process makes it possible to optimize, or even overcome, the resolution limitations of conventional lithography exposure equipment. Another solution is to use higher-resolution lithography equipment, for example, extreme UV or electron beam lithography. The formation of the first mask may include a first lithography followed by a second lithography, then an engraving. Alternatively, the formation of the first mask may include a first lithograph followed by a first engraving, then a second lithograph followed by a second engraving.
[0023] According to one example, the first mask is based on a non-metallic material, for example based on SiON, SiN, SiCN, HfO2, SiON, SiC, SiO2.
[0024] According to one example, at least one second line pattern has a critical dimension CD2, taken along an x-axis, smaller than a dimension CDi of at least one first line pattern taken along the x-axis. This minimizes the risk associated with misalignment between the first and second patterns. Since the first line pattern is typically wider than the second line pattern, the etching of the second dielectric layer, associated with the second line pattern, will effectively stop at the etching stop layer, structured according to the first line pattern. The reliability of the process is increased.
[0025] According to one example, the etching of the second dielectric layer and the etching of the first dielectric layer are carried out by one and the same etching, during one and the same step.
[0026] According to one example, the first and second dielectric layers are based on the same dielectric material.
[0027] According to one example, the first and second dielectric layers are respectively based on a first dielectric material and a second dielectric material, said first and second dielectric materials being different from each other.
[0028] According to one example, the etching of the second dielectric layer and the etching of the first dielectric layer are carried out by two different successive etchings.
[0029] According to one example, the etching stop layer is based on a material taken from: SiC, HfO2, SiN, SiCN, SiON.
[0030] According to one example, the second mask is based solely on organic materials. In particular, this second mask is not based on metallic materials such as TiN. This prevents the formation of residues during or after etching.
[0031] According to one example, the etching stop layer has at least one first line pattern and at least one metallic line is disposed, along the z direction, on said at least one first line pattern.
[0032] According to one example, at least one line has a critical dimension CDiigne, taken along an x-axis, that is less than a dimension CDb taken along the x-axis, of at least one first line pattern of the stop-burn layer. The line does not extend laterally beyond the structured stop-burn layer.
[0033] According to one example, the at least one via has a critical dimension CDvia, taken along an x-axis, substantially equal to a dimension CDopen of the at least one via opening taken along the x-axis.
[0034] According to one example, at least one via opening has a CDopen dimension, taken along an x-axis, less than a CDi dimension, taken along the x-axis, of at least one first line pattern of the burn stop layer.
[0035] According to one example, the etching stop layer is based on a material selected from: SiC, HfO2, SiN, SiCN, SiON, and the first dielectric layer is based on a dielectric material selected from: SiOCH, SiCH, SiO2 (for example, formed from a silane precursor or a tetraethyl orthosilicate precursor TEOS), SiOCH. This makes it possible to obtain an etching selectivity S2i:30 between the first dielectric layer and the etching stop layer greater than or equal to 5:1. The etching speed of the etching stop layer is at least five times lower than the etching speed of the first dielectric layer. According to one example, the etching selectivity S2i:30 between the first dielectric layer and the etching stop layer is greater than 10:1.
[0036] In one example, the first and second dielectric layers are based on the same dielectric material. In another example, the first and second dielectric layers are based on a first dielectric material and a second dielectric material, respectively, said first and second dielectric materials being different from each other. The first and second dielectric materials may, for example, advantageously have two distinct dielectric constants.
[0037] According to one example, at least one via and at least one line are based on the same metallic material, for example copper.
[0038] According to an alternative example, at least one via is based on a first metal and at least one line is based on a second metal different from the first metal.
[0039] According to one example, the substrate is Si or SiC based and includes at least one component connected to at least one connection pad. This component or these components correspond, for example, to the components of a FEOL (acronym for "Front End of Line") level.
[0040] Except in cases of incompatibility, it is understood that all the above optional features and / or the indicated variants may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.
[0041] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not do not necessarily mean "in contact with". Thus, for example, the deposit or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.
[0042] A substrate, film, or layer "based" on a material A is understood to mean a substrate, film, or layer comprising only that material A or that material A and possibly other materials, for example, dopant elements or alloying elements. Thus, a silicon nitride-based etching arrest layer (SiN) may, for example, comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even silicon oxynitride (SiON).
[0043] The term "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, the first and second dielectric layers preferably have a dielectric constant of less than 5. The first and second dielectric layers are said to be "low k" (low dielectric constant).
[0044] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, although this is generally preferred, that the steps follow each other immediately; intermediate steps may separate them.
[0045] Furthermore, the term "step" refers to the execution of a part of the process, and can designate a set of sub-steps.
[0046] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may, in particular, be followed by actions related to a different step, and other actions of the first step may be repeated subsequently. Thus, the term "step" does not necessarily imply unitary actions that are inseparable in time and in the sequence of phases of the process. The etching of the first and second dielectric layers, in particular, may be linked or considered as part of a single etching step.
[0047] Selective etching with respect to or etching exhibiting selectivity with respect to means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of the material B. It is noted SA:B. A selectivity SA:b of 10:1 means that the etching speed of material A is 10 times greater than the etching speed of material B.
[0048] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the accompanying figures.
[0049] In this patent application, the term thickness will preferably be used for a layer or film, and height for a device or structure. Thickness is measured along a direction normal to the principal plane of extension of the layer or film. Thus, a dielectric layer typically has a thickness along the z-axis. A via formed within such a dielectric layer has a height along the z-axis. The relative terms "on," "above," "above," "below," "underlying," and "below" refer to positions measured along the z-direction. A "lateral" dimension corresponds to a dimension along a direction in the xy-plane. A "lateral" or "lateral" extension is understood to be an extension along one or more directions in the xy-plane.
[0050] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically on the cross-sectional figures.
[0051] The terms "approximately", "around", "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the bounds are inclusive, unless otherwise stated.
[0052] The manufacturing steps of an interconnection level according to the invention are illustrated in figures 1 to 15.
[0053] As illustrated in [Fig. 1], the method comprises providing a substrate S typically including a silicon-based support layer 10 carrying components, for example transistors. The substrate S typically includes connecting pads 12 integrated into a first silicon oxide-based layer 11, which overlies the support layer 10. An objective of the method according to the invention is to form vias connecting the pads 12, and lines overlying and connecting these vias.
[0054] A first dielectric layer 21, typically based on a first "low k" oxide, is first formed on the substrate S. This dielectric layer 21 typically has a thickness e2i on the order of a few tens of nanometers, for example on the order of 40 nm. After deposition, the first dielectric layer 21 is typically planarized.
[0055] As illustrated in [Fig. 2], an etching stop layer 30 is then directly formed on the first dielectric layer 21. This etching stop layer 30 typically has a thickness on the order of a few nanometers, for example less than 5 nm. It is preferably based on a silicon nitride, for example SiN or SiCN. The formation of the etching stop layer 30 can in particular be carried out by one of the following techniques: physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD).
[0056] A texturing layer 31, intended to form a first etching mask, is deposited on the etching stop layer 30. This texturing layer 31 is, for example, SiON-based. It typically has a thickness e31 on the order of a few nanometers to a few tens of nanometers, for example, on the order of 5 nm to 10 nm. The texturing layer 31 is then patterned by lithography / etching to form the first etching mask. This patterning can be done by simple lithography, for example under extreme UV exposure, or by double lithography known as "double patterning".
[0057] Figures 3 to 8 illustrate a structuring of the texture layer 31 by "double patterning".
[0058] As illustrated in [Fig.3], a first lithography can be carried out so as to define line patterns 32 in a first layer of photosensitive resin, directly above the studs 12.
[0059] As illustrated in [Fig. 4], a first engraving can then be carried out so as to transfer the line patterns 32 into the texture layer 31. The texture layer is thus partially structured. This first partial structuring makes it possible to obtain line patterns 311 in the texture layer.
[0060] As illustrated in [Fig. 5], the line patterns 32 of the first resin layer are then removed, for example by oxygen-based plasma, so as to re-expose the line patterns 311 of the partially structured texturing layer. In the case of "double patterning" structuring, the line patterns 311 typically have a CDi dimension, along x, of between 70 nm and 100 nm, for example on the order of 80 nm.
[0061] As illustrated in [Fig. 6], a second lithography can be performed to define aperture patterns of via 33v in a second layer 33 of photosensitive resin, on the line patterns 311 of the partially structured texturing layer. The aperture patterns of via 33v are aligned vertically with the pads 12.
[0062] As illustrated in [Fig. 7], a second engraving can be carried out to complete the structuring of the textured layer. The opening patterns of via 33v are transferred into the texture layer. This second structuring makes it possible to obtain opening patterns of via 31v within the line patterns 311 of the texture layer.
[0063] As illustrated in [Fig.8], after removal of the second layer 33 of resin, a first etching mask 31m comprising line patterns 311 and via opening patterns 31v is formed on the etching stop layer 30.
[0064] The first etching mask is not necessarily based on a texturing layer, nor is it necessarily produced by "double patterning". When the first etching mask is produced by simple lithography, the CDi dimension of the line patterns 311 is typically between 100 nm and 200 nm, for example, on the order of 130 nm. When the first etching mask is produced by extreme UV lithography, the CDi dimension of the line patterns 311 is typically between 20 nm and 50 nm, for example, on the order of 26 nm. This first etching mask 31m is used here to directly transfer the line patterns 311 and the aperture patterns of via 31v into the etching stop layer 30.
[0065] As illustrated in [Fig. 9], an anisotropic etch of the etch stop layer 30, along z, is performed so as to form the line patterns 301 under the line patterns 311, and the via opening patterns 30v under the via opening patterns 31v. This etch may have a halogenated etch chemistry based on chlorine or fluorine, depending on the type of mask 31m and the nature of the etch stop layer 30. For a hafnium-based etch stop layer 30, the etch may be performed using a chlorinated etch chemistry, for example BC1, BC13. For a silicon-based etch stop layer 30, the etch may be performed using a fluorocarbon etch chemistry, for example CHF3, CF4.
[0066] As illustrated in Figures 10 and 11, in transverse and top views respectively, after removal of the first etching mask 31m, a structured etching stop layer, comprising line patterns 301 and via opening patterns 30v, is obtained on the first dielectric layer 21. The line patterns 301 typically have the dimension CDi along x, and the via opening patterns 30v typically have the dimension CDopen along x. When the first etching mask is produced by single lithography or by "double patterning", the CDOpen dimension of the via opening patterns 30v is typically between 30 nm and 70 nm, for example on the order of 50 nm. When the first etching mask is made by extreme UV lithography, the CDopen dimension of the aperture patterns via 30v can be between 8 nm and 20 nm, for example on the order of 10 nm.
[0067] As illustrated in [Fig. 12], after structuring of the etching stop layer, a second dielectric layer 22, typically based on a second oxide " The second low-k oxide is then formed on the first dielectric layer 21 and on the structured etching stop layer 301. This dielectric layer 22 typically has a thickness e2 on the order of a few tens of nanometers, for example, on the order of 40 nm. The thicknesses e21 and e2 are preferably chosen so that the total thickness e21 + e2 of the dielectric layers 21, 22 is between 90 nm and 110 nm. The second low-k oxide can be identical to the first low-k oxide. Alternatively, the first and second low-k oxides can be of different types. After deposition, the second dielectric layer 22 is typically planarized.
[0068] As illustrated in [Fig. 13], a second etching mask 40 comprising line patterns 401 is formed on the second dielectric layer 22. This second etching mask 40 is preferably based on organic layers, for example in the form of a stack known as "trilayer", typically comprising an organic planarization layer, an anti-reflective layer and a photosensitive resin layer.
[0069] The line patterns 401 of this second etching mask 40 are aligned with the line patterns 301 of the etching stop layer, so that the line patterns 401 are directly above the line patterns 301. The line patterns 401 typically have a CD2 dimension along x slightly smaller, for example 10% smaller, than the CDi dimension along x of the line patterns 301. This facilitates the alignment of the patterns 401 and 301 with each other. A certain tolerance on the alignment accuracy is thus obtained.
[0070] As illustrated in [Fig. 14], the first and second dielectric layers 21, 22 are then etched through their entire thickness, along z, via the line patterns 401. The second dielectric layer 22 is etched first to form the upper cavities 50sup, and then the first dielectric layer 21 is etched to form the lower cavities 50inf. The etchings of the first and second dielectric layers 21, 22 are preferably linked. According to one possibility, particularly when the first and second dielectric layers 21, 22 are of the same type, the etchings of these dielectric layers 21, 22 are carried out in a single step, using the same etching chemistry.
[0071] The etchings are chosen here so as to selectively etch the first and second "low k" oxides of the first and second dielectric layers 21, 22 with respect to the etching stop layer material. In particular, the etching selectivity S2i:30, that is, the ratio between the etching rate of the first "low k" oxide and the etching rate of the etching stop layer material, is greater or equal to 5:1, preferably greater than or equal to 10:1. The etchings may be based on a CF4 / H2 type chemistry.
[0072] After etching, upper cavities 50sup having the dimension CD2 along x are obtained above the structured etching stop layer 301 having the dimension CDi along x. Lower cavities 50inf having the dimension CDopen along x are obtained below the structured etching stop layer 301.
[0073] As illustrated in [Fig. 15], the lower cavities 50inf and the upper cavities 50sup are then filled by deposition of a metallic layer 60, typically copper-based. This deposition can typically be carried out by electrodeposition. The metallic vias 61 and the metallic lines 62 are thus formed. A diffusion barrier layer, for example based on TaN / Ta, can be depositioned before filling the cavities 50inf, 50sup, in a known manner (not illustrated).
[0074] As illustrated in [Fig. 16], a conventional chemical-mechanical polishing (CMP) planarization step is performed to finalize the formation of the interconnection level comprising the metal vias 61 and the metal lines 62. The metal lines 62 have a critical dimension CDiigne along x, equal to the dimension CD2 of the upper cavities 50sup. The metal vias 61 have a critical dimension CDvia along x, equal to the dimension CDopen of the lower cavities 50inf.
[0075] The invention is not limited to the embodiments described above. In particular, it is possible to structure the etching stop layer indirectly, by forming a first etching mask of reverse polarity and then by making a localized deposit of the etching stop layer material.
Claims
1. Demands A method for manufacturing an interconnection level comprising at least one metallic line (62) and at least one metallic via (61), said method comprising: • a supply of a substrate (S) comprising at least one connection pad (12), • the formation, on the substrate (S), of a first dielectric layer (21), • the formation, on the first dielectric layer (21), of an etching stop layer (30) exhibiting an S2i selectivity: 30 to etching with respect to the first dielectric layer (21), • a structuring of the etching stop layer (30), by means of at least one first mask (31m), such that the etching stop layer (30) has at least one first line pattern (301), said at least one first line pattern (301) comprising at least one via opening (30v), • a formation, on the etching stop layer comprising at least one via opening (30v), of a second dielectric layer (22), • the formation, on the second dielectric layer (22), of a second mask (40) defining at least one second line pattern (401) directly above at least one first line pattern (301), • an etching of the second dielectric layer (22), said etching being configured to form an upper cavity (50sup) by partially stopping on the etching stop layer (30, 301) and, • an etching of the first dielectric layer (21) through at least one via opening (30v), said etching being configured to form a lower cavity (50inf) by stopping on at least one connection pad (12) of the substrate (S), • a filling of the lower and upper cavities (50inf, 50sup) with at least one metallic material so as to form at least one metallic line (62) in the cavity upper (50sup) and at least one metallic via (61) in the lower cavity (50inf), said at least one metallic line (62) being connected to said at least one metallic via (61) through at least one via opening (30v), and said at least one metallic via (61) being connected to said at least one connection pad (12) of the substrate (S).
2. A method according to the preceding claim, wherein the structuring of the etching stop layer (30) comprises the following substeps: • a formation of the first mask (31m) on the etching stop layer (30), said first mask (31m) directly defining at least one first line pattern (301) comprising at least one via opening (30v), • a partial removal of the etching stop layer (30), only at the level of areas of the etching stop layer (30) not covered by the first mask (31m), so as to expose the first dielectric layer (21) outside the areas covered by the first mask (31m), • a removal of the first mask (31m).
3. Method according to the preceding claim, wherein the formation of the first mask (31m) is done by double lithography.
4. A method according to any one of the preceding claims, wherein the first mask (31m) is based on a non-metallic material, for example based on SiON, SiN, SiCN, HfO2, SiON, SiC, SiO2.
5. A method according to any one of the preceding claims, wherein the at least one second line pattern (401) has a critical dimension CD2, taken along an x-axis, less than a dimension CDi of the at least first line pattern (301) taken along the x-axis.
6. A method according to any one of the preceding claims, wherein the etching of the second dielectric layer (22) and the etching of the first dielectric layer (21) are carried out by a single etching, in a single step.
7. A method according to any one of the preceding claims, wherein the first and second dielectric layers (21, 22) are based on the same dielectric material.
8. A method according to any one of the preceding claims, wherein the etching stop layer (30) is based on a material taken from: SiC, HfO2, SiN, SiCN, SiON.
9. A method according to any one of the preceding claims, wherein the second mask (40) is based solely on organic materials.
10. Device comprising in stacking along a direction z: • a substrate (S) comprising at least one connection pad (12), • an interconnection level comprising • at least one metallic via (61) within a first dielectric layer (21), said at least one metallic via (61) being connected to said at least one connection pad (12), • at least one metallic line (62) within a second dielectric layer (22), said at least one metallic line (62) being connected to said at least one metallic via (61), said device being characterized in that it comprises, intercalated between the at least one via (61) and the at least one line (62), an etch stop layer (30, 301) having an etch selectivity S2i.30 vis-à-vis the first dielectric layer (21), said etching stop layer (30) comprising at least one via opening (30v) such that at least one via (61) and at least one line (62) are connected through said at least one via opening (30v).
11. Device according to the preceding claim, wherein the etching stop layer (30) has at least one first line pattern (301), and wherein at least one metallic line (62) is disposed, along the z direction, on said at least one first line pattern (301).
12. A device according to any one of claims 10 to 11, wherein at least one via (61) has a critical dimension CDvia , taken along an x-axis, substantially equal to a CDopen dimension of at least one opening via (30v) taken along the x-axis.
13. Device according to any one of claims 10 to 12, wherein the etching stop layer (30) is based on a material taken from: SiC, HfO2, SiN, SiCN, SiON and the first dielectric layer (21) is based on a dielectric material taken from: SiOCH, SiCH, SiO2, SiOCH.
14. Device according to the preceding claim, wherein the first and second dielectric layers (21, 22) are based on the same dielectric material.
15. Device according to any one of claims 10 to 14, wherein at least one via (61) and at least one line (62) are based on the same metallic material.