Circuit board with embedded electronic components

Abstract

The present invention provides an electronic component-embedded substrate in which through-holes for embedding electronic components are formed in a glass layer, and which prevents cracks or breaks from occurring in the glass during the processing of the through-holes and / or during the process of placing electronic components in the through-holes, thereby improving yield. [Solution] This disclosure relates to an electronic component embedded substrate, comprising: a glass layer; a through-hole penetrating between the upper and lower surfaces of the glass layer; a metal layer, at least a portion of which is embedded within the glass layer and at least a portion of which is exposed from the glass layer through the wall surface of the through-hole; an electronic component, at least a portion of which is disposed within the through-hole; and a sealing material, at least a portion of which is embedded within the electronic component and which fills at least a portion of the through-hole.

Description

Technical Field

[0001] The present disclosure relates to a substrate with built-in electronic components.

Background Art

[0002] In order to cope with the high-performance and miniaturization strategies of semiconductors, the levels of miniaturization and high density required for printed circuit boards are increasing. For example, in order to manufacture high-end products such as server substrates, high multi-layers and large bodies are required. However, as the number of wiring layers increases and the size of the main body increases, the substrate may become more brittle and warped. In order to solve such problems, the use of a glass core is considered. On the other hand, in order to incorporate electronic components into the glass core, a cavity can be processed and the electronic components can be arranged therein. However, cracks or cracks may occur in the glass during the cutting process when processing the cavity in the glass core. Also, cracks or cracks may occur in the glass due to collisions or the like during the process of arranging electronic components in the cavity formed in the glass core.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objects of the present disclosure is to provide a substrate with built-in electronic components in which a through-hole for incorporating an electronic component is formed in a glass layer, and to prevent cracks or cracks from occurring in the glass during the processing of the through-hole and / or during the process of arranging the electronic component in the through-hole, thereby improving the yield.

Means for Solving the Problems

[0004] One of the various solutions of the present disclosure is to pre-form a metal layer, for example, by slit processing and slit wall plating, on the cutting line of the dummy region where the through-hole of the glass layer is formed, and then form a through-hole that exposes the metal layer after laminating an insulating layer on the glass layer, and prevent cracks or cracks in the above-mentioned glass layer through the remaining metal layer.

[0005] For example, an electronic component-embedded substrate according to one example may include a glass layer, a through-hole penetrating between the upper and lower surfaces of the glass layer, a metal layer in which at least a portion is embedded within the glass layer and at least another portion is exposed from the glass layer through the wall surface of the through-hole, an electronic component in which at least a portion is disposed within the through-hole, and a sealing material that embeds at least a portion of the electronic component and fills at least a portion of the through-hole.

[0006] For example, an electronic component-embedded substrate according to one example may include a glass layer, a through-hole penetrating between the upper and lower surfaces of the glass layer, a plurality of metal layers disposed inside the glass layer and providing at least a portion of the wall surface of the through-hole, spaced apart from each other, an electronic component disposed at least a portion of within the through-hole, and an insulating body that covers at least a portion of the glass layer, the plurality of metal layers, and the electronic component, and fills at least a portion of the through-hole. [Effects of the Invention]

[0007] One of the various effects of this disclosure is that, in an electronic component-embedded substrate in which through-holes for embedding electronic components are formed in a glass layer, it is possible to prevent cracks or fractures from occurring in the glass during the processing of the through-holes and / or during the process of placing electronic components in the through-holes, thereby improving the yield. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating a schematic example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a circuit board with embedded electronic components. [Figure 3] Figure 2 is a schematic cross-sectional plan view of an electronic component-embedded circuit board along the line A-A'. [Figure 4] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of an electronic component-embedded substrate. [Figure 5] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of an electronic component-embedded substrate. [Figure 6]This is a schematic process perspective view showing an example of the step of forming slits in a glass layer. [Figure 7] This is a schematic process perspective showing an example of the step of forming a metal layer in a slit. [Figure 8] This is a schematic process perspective showing an example of the step of forming an insulating layer on a glass layer. [Figure 9] This is a schematic process perspective showing an example of the steps involved in forming a wiring layer and connection vias in an insulating layer. [Figure 10] This is a schematic process perspective view showing an example of the step of forming a penetration in the glass layer. [Figure 11] This is a schematic process perspective showing an example of the stage in which electronic components are placed in the penetration area. [Figure 12] This is a schematic process perspective showing an example of the steps involved in forming a sealing material. [Modes for carrying out the invention]

[0009] The following description of this disclosure will be made with reference to the attached drawings. The shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses a main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0012] Chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with each other. Chip-related components 1020 can also be in the form of a package containing the aforementioned chips and electronic components.

[0013] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (Long Term Evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and later. It may also include any other numerous wireless or wired standards or protocols. Furthermore, network-related component 1030 can be combined with chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic condensers). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. Furthermore, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the main board 1010, or not connected. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components used for various purposes.

[0016] The electronic device 1000 can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, automotive, a server, etc. However, it is not limited thereto, and it can also be any other electronic device that processes data.

[0017] FIG. 2 is a cross-sectional view schematically showing an example of a substrate with built-in electronic components, and FIG. 3 is a cut-away plan view along the schematic A-A' line of the substrate with built-in electronic components of FIG. 2.

[0018] Referring to the drawings, a substrate 100 with built-in electronic components according to an example includes a glass layer 110, a through-hole H penetrating between the upper and lower surfaces of the glass layer 110, a metal layer M disposed inside the glass layer 110, an electronic component 120 at least partially disposed within the through-hole H, and a sealing material 130 that at least partially embeds at least a part of the electronic component 120 and fills at least a part of the through-hole H. The metal layer M can be at least partially embedded within the glass layer 110. At least a part of the other portion of the metal layer M may be exposed from the glass layer 110 through the wall surface S of the through-hole H. At least a part of the exposed other portion of the metal layer M can provide at least a part of the wall surface S of the through-hole H. The metal layer M may be embedded within the glass layer 110 on a plane such that the number of surfaces contacting the glass layer 110 is greater than the number of surfaces contacting the sealing material 130 by being exposed from the glass layer 110 through the wall surface S of the through-hole H. The metal layer M may be disposed substantially conformally in a shape substantially corresponding to the shape of the wall surface S of the through-hole H in a cross-section. For example, the through-hole H can have a substantially hourglass shape in a cross-section, and the metal layer M can correspondingly have a form bent toward the through-hole H in a cross-section, but it is not limited thereto.

[0019] For example, as will be described later, a slit penetrating the glass layer 110 may be processed in a cutting line of a dummy region where the through-hole H of the glass layer 110 is formed, and plating may be performed on the wall surface of the processed slit to pre-form the metal layer M before processing the through-hole H. In this case, in the cutting process for forming the through-hole H, cracks or fractures in the glass layer 110 can be prevented through the pre-formed metal layer M. Further, the metal layer M can be disposed inside the glass layer 110 as described above even after the cutting process. Therefore, in the process of disposing the electronic component 120 in the through-hole H, cracks or fractures in the glass layer 11o can be prevented through the remaining metal layer M. Therefore, the yield can be improved.

[0020] On the other hand, the metal layer M may include a plurality of metal layers M1, M2. The plurality of metal layers M1, M2 can each be arranged inside the glass layer 110 and each provide at least a portion of the wall surface S of the penetration H. The plurality of metal layers M1, M2 can be separated from each other. For example, at least two of the plurality of metal layers M1, M2 may be separated from each other in at least one corner region of a plurality of corner regions C1, C2, C3, C4 of the penetration H on a plane. For example, the plurality of metal layers M1, M2 may include a first metal layer and a second metal layer M1, M2. Also, on a plane, the penetration H may have first and second wall surfaces S1, S2 facing each other in a first direction, and third and fourth wall surfaces S3, S4 facing each other in a second direction perpendicular to the first direction. Furthermore, on a plane, the penetration H may have a first corner region C1 connecting the first wall surface and the third wall surfaces S1 and S3, a second corner region C2 connecting the first wall surface and the fourth wall surfaces S1 and S4, a third corner region C3 connecting the second wall surface and the third wall surfaces S2 and S3, and a fourth corner region C4 connecting the second wall surface and the fourth wall surfaces S2 and S4. In this case, the first metal layer M1 may be arranged to surround the first corner region C1, the second metal layer M2 may be arranged to surround the fourth corner region C4, and the first metal layer and the second metal layers M1 and M2 may be separated from each other in the second corner region and the third corner regions C2 and C3.

[0021] For example, as will be described later, when processing a slit that penetrates the glass layer 110 at the cutting line of the dummy region where the penetration portion H of the glass layer 110 is formed, multiple slits spaced apart from each other can be formed. In this case, the spaced-apart spaces between the multiple slits, for example, at least one corner region of the dummy region, can function as a bridge region, thereby allowing the dummy region of the glass layer 110 to remain before the cutting process. As a result, multiple metal layers M1, M2, for example, the first metal layer and the second metal layers M1, M2, which are spaced apart from each other, can be formed through such multiple slits. Therefore, as described above, cracks and fractures in the glass layer 110 can be effectively prevented.

[0022] Referring to the drawings, an example of an electronic component-embedded substrate 100 may further include a first insulating layer and second insulating layers 141 and 142, respectively, arranged on the upper and lower surfaces of the glass layer 110. In this case, the through-hole H can penetrate the glass layer 110 and the first and second insulating layers 141 and 142 collectively, from the upper surface of the first insulating layer 141 to the lower surface of the second insulating layer 142. Therefore, at least a portion of the wall surface S of the through-hole H in the region penetrating the glass layer 110 may include at least a portion of the side surface of the metal layer M and at least a portion of the side surface of the glass layer 110, at least another portion of the wall surface S of the through-hole H in the region penetrating the first insulating layer 141 may include at least a portion of the side surface of the first insulating layer 141, and at least yet another portion of the wall surface S of the through-hole H in the region penetrating the second insulating layer 142 may include at least a portion of the side surface of the second insulating layer 142.

[0023] For example, as will be described later, a cutting process to form the penetration H can be performed after forming the first insulating layer and the second insulating layers 141 and 142 on the glass layer 110, and therefore the structural features described above can be obtained. Furthermore, the sealing material 130 can cover at least a portion of the upper surface of the first insulating layer 141 and at least a portion of the lower surface of the second insulating layer 142. In addition, the first insulating layer and the second insulating layers 141 and 142 can cover at least a portion of the upper and lower surfaces of the metal layer M, respectively, but the sides of the metal layer M do not need to be covered. This makes it possible to achieve the above-mentioned technical effects more effectively.

[0024] On the other hand, the first insulating layer and the second insulating layers 141, 142 and the sealing material 130 can provide an insulating body 145. The insulating body 145 may cover at least a portion of the glass layer 110, the metal layer M, and the electronic component 120, and can fill at least a portion of the penetration H. If necessary, the first insulating layer and the second insulating layers 141, 142 and the sealing material 130 can be integrated with each other. For example, they may not be separated by a boundary. In this case, the insulating body 145 can be composed of substantially one insulating material, and reliability can be further improved by ensuring adhesion, etc. However, it is not limited to this.

[0025] Referring to the drawings, an example of an electronic component-embedded substrate 100 may further include a metal via 115 penetrating a glass layer, a first connecting via 151 penetrating a first insulating layer 141 and directly connected to the metal via 115, a second connecting via 152 penetrating a second insulating layer 142 and directly connected to the metal via 115, a first wiring layer 161 positioned on the upper surface of the first insulating layer 141 and connected to the first connecting via 151, and a second wiring layer 162 positioned on the lower surface of the second insulating layer 142 and connected to the second connecting via 152. The sealing material 130 can cover at least a portion of each of the first wiring layer and the second wiring layers 161 and 162. For example, the first and second connection vias 151 and 152 can penetrate a portion of the insulating body 145 above and below the glass layer 110, respectively, and the first and second wiring layers 161 and 162 can be embedded within the insulating body 145 above and below the glass layer 110, respectively. In this way, wiring can be designed on the first and second insulating layers 141 and 142, respectively, and an electrical connection path can be formed inside the glass layer 110 and the first and second insulating layers 141 and 142. In this case, since wiring does not need to be designed directly on the glass layer 110, reliability can be improved. Furthermore, the electrical connection path can still be shortened, and the overall thickness of the substrate can be reduced.

[0026] On the other hand, the upper and lower surfaces of the metal via 115 may be substantially co-plane with the upper and lower surfaces of the glass layer 110, respectively, or recessed from the upper and lower surfaces of the glass layer 110, respectively. From a similar viewpoint, the upper and lower surfaces of the metal layer M may be substantially co-plane with the upper and lower surfaces of the glass layer 110, respectively, or recessed from the upper and lower surfaces of the glass layer 110, respectively. For example, the metal via 115 and the metal layer M may be formed within through holes and slits formed in the glass layer 110, and their respective upper and lower surfaces may be partially removed during the etching process of any over-plated portions as needed.

[0027] Referring to the drawings, an example of an electronic component-embedded substrate 100 may further include a third wiring layer 163 disposed on the upper surface of the encapsulant 130, a fourth wiring layer 164 disposed on the lower surface of the encapsulant 130, a first via layer 170 penetrating at least a portion of the upper side of the encapsulant 130, and a second via layer 180 penetrating at least a portion of the lower side of the encapsulant 130. For example, the third and fourth wiring layers 163 and 164 may be disposed on the upper and lower surfaces of the insulating body 145, respectively, and the first and second via layers 170 and 180 may penetrate at least a portion of the upper and lower sides of the insulating body 145, respectively. Electrodes P may be disposed above the electronic component 120. The first via layer 170 may include third and fourth connecting vias 171 and 172 that connect the third wiring layer 163 to the electrodes P of the electronic component 120 and the first wiring layer, respectively. The second via layer 180 may include a fifth connecting via 181 that connects the fourth wiring layer 164 to the second wiring layer 162. In this way, wiring can be designed on the encapsulant 130, and electrical connection paths can be formed inside the encapsulant 130. This enables a wider variety of wiring designs. Furthermore, the electronic component 150 can be electrically connected to the substrate wiring more easily via the electrode P.

[0028] On the other hand, the electronic component 120 may include an IPD (Integrated Passive Device). Therefore, parasitic inductance and parasitic capacitance can be reduced. Furthermore, high-frequency characteristics can be optimized and noise can be reduced. In addition, miniaturization and integration density can be improved. Power efficiency can be increased. Furthermore, high-speed data transmission can be optimized. However, the type of electronic component 120 is not necessarily limited to this, and other active and / or passive elements may also be included.

[0029] If necessary, the electronic component embedded substrate 100 according to one example may have a build-up layer further arranged on the upper and / or lower surface of the encapsulant 130. The build-up layer may include one or more build-up insulating layers, one or more build-up wiring layers, and one or more build-up via layers. A passivation layer may be arranged on the build-up layer. For example, the electronic component embedded substrate 100 according to one example may have a multilayer substrate structure, which allows it to be easily applied to large-area package substrates and the like.

[0030] In the following section, the components of an example electronic component embedded substrate 100 will be described in more detail with reference to the drawings.

[0031] The glass layer 110 may include glass, which is an amorphous solid. Examples of glass include pure silicon dioxide (almost 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, it is not limited to these; alternative glass materials, such as fluoroglass, phosphoric acid glass, and chalcogenide glass, can also be used. Furthermore, other additives may be included to form glass with specific physical properties. Such additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of these elements and other elements. On the other hand, the glass layer 110 can be distinguished from organic insulating materials containing glass fibers (Glass Fiber, Glass Cloth, Glass Fabric), such as CCL (Copper Clad Laminate) and PPG (Prepreg). The glass layer 110 may be in the form of, for example, a glass plate. The through-hole H can penetrate at least between the upper and lower surfaces of the glass layer 110. The through-hole H can continuously surround the perimeter of the side surface of the electronic component 120.

[0032] The metal via 115 can be placed in a through-hole that penetrates between the upper and lower surfaces of the glass layer 110. The metal via 115 can be a filled via with metal filling the through-hole. For example, the metal via 115 can contain metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the metal via 115 can contain a titanium layer and a copper layer formed by sputtering, i.e., sputtered titanium and sputtered copper, as seed layers, and based on this, it can contain electroplated copper formed by electroplating as a plating layer. If necessary, it may further contain chemical copper formed by electroless plating as a seed layer. The metal via 115 can perform various functions depending on the design. For example, the metal via 115 can include through-vias for signal transmission, through-vias for power transmission, through-vias for ground transmission, and so on. The metal via 115 may be substantially cylindrical in shape, but may also be substantially hourglass in shape. If necessary, the upper and lower surfaces of the metal via 115 may be recessed inward from the upper and lower surfaces of the glass layer 110, respectively, and thus may have a step between them and the upper and lower surfaces of the glass layer 110, respectively, but are not limited to this. There may be multiple metal vias 115.

[0033] The metal layer M may contain metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the metal layer M may include a titanium layer and a copper layer formed by sputtering, i.e., sputtered titanium and sputtered copper, as seed layers, and based on these, it may include electroplated copper formed by electroplating as a plating layer. If necessary, it may further include chemical copper formed by electroless plating as a seed layer. If necessary, the upper and lower surfaces of the metal layer M may be recessed inward from the upper and lower surfaces of the glass layer 110, respectively, and therefore may have steps between them and the upper and lower surfaces of the glass layer 110, respectively, but is not limited thereto. The metal layer M may consist of multiple layers, for example, a first metal layer and second metal layers M1 and M2 spaced apart from each other.

[0034] The electronic component 120 may include various types of active and / or passive elements. For example, the electronic component 120 may include various types of integrated circuit dies or semiconductor chips. For example, the electronic component 120 may include, but is not limited to, an IPD (Integrated Passive Device). The electronic component 120 may include electrodes P for electrical connection, and the electrodes P may be located on the top surface of the electronic component 120, for example, the front surface. The electrodes P may include conductive materials, such as metals. Metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pd), titanium (Ti), and / or alloys thereof. The electrodes P may include pads, bumps, or posts. Alternatively, the electrodes P may include pads and bumps or posts placed on the pads. There may be multiple electrodes P.

[0035] The encapsulant 130 and the first and second insulating layers 141 and 142 may each contain an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler, organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the organic insulating material may include, but is not limited to, PPG (Prepreg), ABF (Ajinomoto Build-up Film), and PID (Photo Imageable Dielectric). The encapsulant 130 may be composed of multiple layers as needed, and these multiple layers may or may not have boundaries separating them from each other. The encapsulant 130 and the first and second insulating layers 141 and 142 may each contain substantially the same insulating material. For example, the encapsulant 130 and the first and second insulating layers 141 and 142 may be integrated with each other to the extent that their boundaries are indistinct. However, the material is not limited to this, and may include different insulating materials as needed, or may be separated by boundaries. The sealing material 130 and the first insulating layer and the second insulating layers 141 and 142 can constitute the insulating body 145. The through-hole H can further penetrate between the upper and lower surfaces of the first insulating layer and the second insulating layers 141 and 142, respectively. The through-hole H can continuously surround the perimeter of the side surface of the electronic component 120.

[0036] The first and second connection vias 151 and 152 can each contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first and second connection vias 151 and 152 can each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. The first and second connection vias 151 and 152 can each perform various functions depending on the design. For example, the first and second connection vias 151 and 152 can each include signal transmission vias, power transmission vias, ground transmission vias, and so on. The first and second connecting vias 151 and 152 may each include filled vias in which at least a portion of the via hole is filled with metal, or they may include conformal vias in which metal is arranged along the wall of the via hole. The first and second connecting vias 151 and 152 may have substantially tapered forms in opposite directions to each other. The first and second connecting vias 151 and 152 may be directly connected to the upper and lower surfaces of the metal via 115, respectively. For example, they may be in direct contact with the upper and lower surfaces of the metal via 115. If there are multiple metal vias 115, there may also be multiple first and second connecting vias 151 and 152, respectively.

[0037] The first to fourth wiring layers 161, 162, 163, and 164 can each contain metals. These metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first to fourth wiring layers 161, 162, 163, and 164 can each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. The first to fourth wiring layers 161, 162, 163, and 164 can each perform various functions depending on the design. For example, the first to fourth wiring layers 161, 162, 163, and 164 can each contain signal patterns, power patterns, ground patterns, and so on. These patterns can each take various forms, such as line, trace, plane, land, and pad.

[0038] The first via layer and the second via layers 170 and 180 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first via layer and the second via layers 170 and 180 can each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this as a plating layer. The first via layer and the second via layers 170 and 180 can each perform various functions depending on the design. For example, the first via layer and the second via layers 170 and 180 can each contain a signal transmission connection via, a power transmission connection via, a ground transmission connection via, and so on. The first via layer and the second via layers 170, 180 may each include filled vias in which at least a portion of the via hole is filled with metal, but may also include conformal vias in which metal is arranged along the wall surface of the via hole. The first via layer and the second via layers 170, 180 may each include a plurality of connection vias. For example, the first via layer 170 may include third and fourth connection vias 171, 172 connecting the third wiring layer 163 to the electrode P of the electronic component 120 and the first wiring layer, respectively, and the second via layer 180 may include a fifth connection via 181 connecting the fourth wiring layer 164 to the second wiring layer 162. The connection vias included in the first via layer and the second via layers 170, 180 may have a configuration that is substantially tapered in opposite directions to each other. For example, the third and fourth connecting vias 171 and 172 may each have a configuration that is substantially tapered in the opposite direction to the fifth connecting via 181.

[0039] Figures 4 and 5 are schematic cross-sectional views illustrating an example of the manufacturing process of the electronic component-embedded substrate shown in Figure 2.

[0040] Referring to Figure 4, first, a through-hole V1 can be formed in the glass layer 110. The through-hole V1 can be formed by laser processing. Also, a slit V2 can be formed in the glass layer 110. The slit V2 can be formed by performing multiple laser processing steps, including CO2 laser processing and / or YAG laser processing. Next, a metal via 115 and a metal layer M can be formed in the through-hole V1 and the slit V2, respectively. The metal via 115 and the metal layer M can be formed by the seed layer formation step and the plating step described above. The metal layer M can be formed substantially conformally on the wall surface of the slit V2. Next, a first insulating layer and a second insulating layer 141, 142 can be formed on the glass layer 110. The first insulating layer and the second insulating layer 141, 142 can be formed by an insulating material lamination step. At least one of the first insulating layer and the second insulating layer 141, 142 can fill the space of the slit V2. Next, first and second connecting vias 151 and 152 and first and second wiring layers 161 and 162 can be formed in the first and second insulating layers 141 and 142. For example, after processing via holes in the first and second insulating layers 141 and 142 with a laser drill or the like, the first and second connecting vias 151 and 152 and first and second wiring layers 161 and 162 can be formed using the seed layer formation process and plating process described above.

[0041] Referring to Figure 5, next, through-holes H can be formed in the glass layer 110 and the first and second insulating layers 141 and 142. The through-holes H can be formed by cutting using a drilling process. In this process, the dummy area D can be removed. At this time, it is possible to prevent cracks or fractures from occurring in the glass layer 110 via the metal layer M. Next, electronic components 120 can be placed in the through-holes H. At this time, it is possible to prevent cracks or fractures from occurring in the glass layer 110 via the remaining metal layer M. Next, the electronic components 120 can be embedded using a sealing material 130. The sealing material 130 can be formed by an insulating material lamination process or the like. At this time, an insulating body 145 including the first and second insulating layers 141 and 142 and the sealing material 130 can be formed. Furthermore, via holes can be formed in the sealing material 130 by laser processing or the like, and plating can be carried out to further form a first via layer 170 including the third and fourth wiring layers 163 and 164 and the third and fourth connecting vias 171 and 172, and a second via layer 180 including the fifth connecting via 181. If necessary, a build-up process can also be further carried out on the sealing material 130.

[0042] The electronic component-embedded substrate 100 according to the example described above can be manufactured through a series of processes. Other descriptions may be substantially the same as those described above. Furthermore, the contents described in the manufacturing example may be substantially the same as those described above for the electronic component-embedded substrate 100 according to the example described above.

[0043] Figure 6 is a schematic process perspective view showing an example of the step of forming slits in a glass layer. In the drawing, the lower part shows an overall perspective view, and the upper part shows a cutaway perspective view arbitrarily cut for ease of explanation.

[0044] Referring to the drawing, a slit V2 can be machined through the glass layer 110 at the cutting line of the dummy region D of the glass layer 110. In this case, the slit V2 may include a plurality of spaced-apart slits V2-1, V2-2. The plurality of slits V2-1, V2-2 may include, for example, a first slit and second slits V2-1, V2-2. The spaced-apart interval between the first slit and the second slits V2-1, V2-2 may be a corner region of the dummy region. Such corner regions can each function as a bridge region B, thereby allowing the dummy region D of the glass layer 110 to remain before the cutting process. The space between the first slit and the second slits V2-1, V2-2 can be increased by multiple laser processing steps. Other descriptions may be substantially the same as those described above, and the contents described here may be substantially the same as those described above for the electronic component embedded substrate 100 according to the example described above.

[0045] Figure 7 is a schematic process perspective view showing an example of the steps involved in forming a metal layer in a slit. In the drawing, the lower part shows an overall perspective view, and the upper part shows a cross-sectional perspective view arbitrarily cut for ease of explanation.

[0046] Referring to the drawings, when forming metal vias 115 in the through-hole V1 by plating, a metal layer M can be formed on the wall surface of the slit V2. For example, a first metal layer and second metal layers M1 and M2 can be formed on the wall surfaces of the first slit and the second slits V2-1 and V2-2, respectively. Within the first slit V2-1, the first metal layer M1 can be formed substantially conformally, and therefore an empty space can exist within the first slit V2-1. Within the second slit V2-2, the second metal layer M2 can also be formed substantially conformally, and therefore an empty space can exist within the second slit V2-2. The first metal layer and the second metal layers M1 and M2 can be separated from each other via the bridge region B described above. Other descriptions may be substantially the same as those described above, and the contents described here may be substantially the same in application to the electronic component embedded substrate 100 according to the example described above.

[0047] Figure 8 is a schematic process perspective view showing an example of the steps involved in forming an insulating layer on a glass layer. In the drawing, the lower part shows an overall perspective view, and the upper part shows a cross-sectional perspective view arbitrarily cut for ease of explanation.

[0048] Referring to the drawings, a first insulating layer and a second insulating layer 141, 142 can be formed on the glass layer 110. For example, the first insulating layer 141 can be formed on the upper surface of the glass layer 110, and the second insulating layer 142 can be formed on the lower surface of the glass layer 110. At least one of the first insulating layer and the second insulating layers 141, 142 can fill the spaces of the first slit and the second slits V2-1, V2-2, respectively. Other descriptions may be substantially the same as those described above, and the contents described here may be substantially the same as those described above for the electronic component embedded substrate 100 according to the example described above.

[0049] Figure 9 is a schematic process perspective view showing an example of the steps involved in forming a wiring layer and connection vias in an insulating layer. In the drawing, the lower part shows an overall perspective view, and the upper part shows a cutaway perspective view arbitrarily cut for ease of explanation.

[0050] Referring to the drawings, the first and second insulating layers 141 and 142 can be formed with first and second connecting vias 151 and 152 and first and second wiring layers 161 and 162. Other descriptions may be substantially the same as those described above, and the contents described herein may be substantially the same as those described above for the electronic component embedded substrate 100 according to the example described above.

[0051] Figure 10 is a schematic process perspective view showing an example of the stage in forming a penetration in the glass layer. In the drawing, the lower part shows an overall perspective view, and the upper part shows a cutaway perspective view arbitrarily cut for ease of explanation.

[0052] Referring to the drawing, the cutting area can be processed so that the dummy area D is removed. At this time, the bridge area B described above can also be processed and removed. This separates and removes the dummy area D, and a through-hole H can be formed. At this time, it is possible to prevent cracks or fractures from occurring in the glass layer 110 through the first metal layer and the second metal layers M1 and M2. Other descriptions may be substantially the same as those described above, and the contents described here may be substantially the same in the same way as the electronic component embedded substrate 100 according to the example described above.

[0053] Figure 11 is a schematic process perspective view illustrating an example of the stage in which electronic components are placed in the penetration. In the drawing, the lower part shows an overall perspective view, and the upper part shows a cutaway perspective view arbitrarily cut for ease of explanation.

[0054] Referring to the drawing, an electronic component 120 can be placed in the through-hole H. In this case, the glass layer 110 can be protected from impacts such as collisions via the remaining first and second metal layers M1 and M2, preventing cracks and breaks from occurring. Other descriptions may be substantially the same as those described above, and the contents described here may be substantially the same for the electronic component embedded substrate 100 according to the example described above.

[0055] Figure 12 is a schematic process perspective view showing an example of the steps involved in forming a sealing material. In the drawing, the lower part shows an overall perspective view, and the upper part shows a cross-sectional perspective view arbitrarily cut for ease of explanation.

[0056] Referring to the drawings, the electronic component 120 can be fixed using the sealing material 130, and the electronic component 120 can be embedded in the substrate. At this time, an insulating body 145 can be formed, which includes the first insulating layer, the second insulating layers 141 and 142 and the sealing material 130. Other descriptions may be substantially the same as those described above, and the contents described here may be substantially the same as those described above for the electronic component embedded substrate 100 according to the example.

[0057] In this disclosure, the expression "cover" may include not only covering the entire structure but also covering at least a portion of it, and may include not only direct covering but also indirect covering. Similarly, the expression "satisfy" may include not only completely satisfying the structure but also satisfying at least a portion of it, and may include satisfying it roughly. For example, this may include cases where there are some gaps or voids. Furthermore, the expression "enclose" may include not only completely enclosing the structure but also partially enclosing or roughly enclosing it. Moreover, "expose" may include not only completely exposing the structure but also partially exposing it, and exposure may mean exposing the structure from what is embedding it.

[0058] In this disclosure, "placed within a penetration" can include not only cases where the object is completely placed within the penetration, but also cases where it partially extends upward or downward on the cross-section. For example, if it is placed within a penetration on a plane, it can be judged in a broader sense.

[0059] In this disclosure, the determination can be made including process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, having a substantially specific shape may include not only cases where it has exactly that shape, but also cases where it has roughly that shape. Also, substantially the same insulating material may mean not only cases where it is exactly the same insulating material, but also cases where it includes insulating materials of the same type. Therefore, the composition of the insulating material may be substantially the same, but the specific composition ratios may differ slightly.

[0060] In this disclosure, "on a cross-section" may mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. Furthermore, "on a plane" may mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0061] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "top," and "top surface" are used to mean the opposite direction. However, these are merely definitions of directions for explanatory purposes, and the scope of the claims is not particularly limited by such descriptions of directions, and the concepts of "up" and "down" can change at any time.

[0062] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and non-connected cases. Additionally, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of those components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0063] In this disclosure, thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness, etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the substrate containing the electronic components. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section cut along the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five locations.

[0064] The expression "example" used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and illustrate the unique and distinct features of each embodiment. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a contradictory or inconsistent description of that matter in the other example.

[0065] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of Symbols]

[0066] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 100 Electronic component embedded circuit boards 110 glass layer 115 Metal Vias 120 Electronic Components 130 Sealing material 141, 142 Insulating layer 145 Insulating body Vias 151 and 152 161, 162, 163, 164 wiring layer 170, 180 Beer Layer Vias 171 and 172 181 Connection vias H Penetration S, S1, S2, S3, S4 wall C1, C2, C3, C4 corners M, M1, M2 metal layers P electrode Dダミーfield B ブリッジ domain

Claims

1. A glass layer, A through-hole that penetrates between the upper and lower surfaces of the glass layer, A metal layer, at least a portion of which is embedded within the glass layer and at least a portion of which is exposed from the glass layer through the wall surface of the penetration, An electronic component is disposed in at least a portion of the aforementioned penetration, An electronic component embedded substrate, comprising: a sealing material that embeds at least a portion of the aforementioned electronic component and fills at least a portion of the through-hole;

2. The electronic component substrate according to claim 1, wherein the metal layer has more surfaces in contact with the glass layer on a plane than the number of surfaces in contact with the sealing material.

3. The aforementioned metal layer includes a first metal layer and a second metal layer. The electronic component substrate according to claim 1, wherein the first metal layer and the second metal layer are separated from each other in a planar plane by at least one corner region of the plurality of corner regions of the through-hole.

4. On a plane, The through portion has a first wall surface and a second wall surface facing each other in a first direction, and a third wall surface and a fourth wall surface facing each other in a second direction perpendicular to the first direction. The through-section has a first corner region connecting the first wall surface and the third wall surface, a second corner region connecting the first wall surface and the fourth wall surface, a third corner region connecting the second wall surface and the third wall surface, and a fourth corner region connecting the second wall surface and the fourth wall surface. The first metal layer is arranged to surround the first corner region, The second metal layer is arranged to surround the fourth corner region, The electronic component substrate according to claim 3, wherein the first metal layer and the second metal layer are separated from each other in the second corner region and the third corner region.

5. The aforementioned through portion has a substantially hourglass shape in cross-section. The electronic component substrate according to claim 1, wherein the metal layer is substantially conformally arranged in a cross-section to a shape substantially corresponding to the shape of the wall surface of the through-hole.

6. A first insulating layer disposed on the upper surface of the glass layer, The glass layer further includes a second insulating layer disposed on the lower surface of the glass layer, The aforementioned penetration portion penetrates the glass layer, the first insulating layer, and the second insulating layer together, from the upper surface of the first insulating layer to the lower surface of the second insulating layer. The electronic component substrate according to claim 1, wherein the sealing material covers at least a portion of the upper surface of the first insulating layer and at least a portion of the lower surface of the second insulating layer.

7. The first insulating layer, the second insulating layer, and the sealing material are integrated with each other, as described in claim 6.

8. The first insulating layer covers at least a portion of the upper surface of the metal layer, The second insulating layer covers at least a portion of the lower surface of the metal layer, The electronic component substrate according to claim 6, wherein the first insulating layer and the second insulating layer do not cover the side surface of the metal layer.

9. The electronic component substrate according to claim 6, wherein the upper and lower surfaces of the metal layer are substantially coplane with the upper and lower surfaces of the glass layer, respectively, or are recessed below the upper and lower surfaces of the glass layer, respectively.

10. At least a portion of the wall surface of the penetration in the region penetrating the glass layer includes at least a portion of the side surface of the metal layer and the side surface of the glass layer, At least another portion of the wall surface of the penetration portion in the region penetrating the first insulating layer includes at least a portion of the side surface of the first insulating layer, The electronic component substrate according to claim 6, wherein at least another portion of the wall surface of the penetration portion in the region penetrating the second insulating layer includes at least a portion of the side surface of the second insulating layer.

11. A metal via penetrating the aforementioned glass layer, A first connecting via that penetrates the first insulating layer and is directly connected to the metal via, A second connecting via that penetrates the aforementioned second insulating layer and is directly connected to the metal via, A first wiring layer disposed on the upper surface of the first insulating layer, The present invention further includes a second wiring layer disposed on the lower surface of the second insulating layer, The first connecting via and the second connecting via are connected to the first wiring layer and the second wiring layer, respectively. The electronic component substrate according to claim 6, wherein the sealing material covers at least a portion of each of the first wiring layer and the second wiring layer.

12. The electronic component substrate according to claim 11, wherein the upper and lower surfaces of the metal vias are substantially coplane with the upper and lower surfaces of the glass layer, respectively, or are recessed below the upper and lower surfaces of the glass layer, respectively.

13. A third wiring layer is placed on the upper surface of the sealing material, A fourth wiring layer is disposed on the lower surface of the sealing material, A first via layer that penetrates at least a portion of the upper side of the sealing material, The present invention further includes a second via layer that penetrates at least a portion of the lower side of the sealing material, An electrode is placed on the upper side of the aforementioned electronic component. The first via layer includes a third connecting via and a fourth connecting via that connect the third wiring layer to the electrodes of the electronic component and the first wiring layer, respectively. The electronic component substrate according to claim 11, wherein the second via layer includes a fifth connecting via that connects the fourth wiring layer to the second wiring layer.

14. The electronic component substrate according to claim 13, wherein the electronic component includes an IPD (Integrated Passive Device).

15. A glass layer, A through-hole that penetrates between the upper and lower surfaces of the glass layer, A plurality of metal layers are arranged inside the glass layer, each providing at least a portion of the wall surface of the through-hole, and are spaced apart from each other. An electronic component is disposed in at least a portion of the aforementioned penetration, An electronic component substrate comprising an insulating body that covers at least a portion of the glass layer, the plurality of metal layers, and the electronic component, and fills at least a portion of the through-hole.

16. The electronic component substrate according to claim 15, wherein at least two of the plurality of metal layers are separated from each other in at least one corner region of the plurality of corner regions of the through-hole on a plane.

17. The aforementioned through portion has a substantially hourglass shape in cross-section. The electronic component substrate according to claim 15, wherein each of the plurality of metal layers is substantially conformally arranged in a cross-section to a shape substantially corresponding to the shape of the wall surface of the through-hole.

18. A metal via penetrating the aforementioned glass layer, On the upper and lower sides of the glass layer, a first connecting via and a second connecting via penetrate a portion of the insulating body, respectively, and are directly connected to the upper and lower surfaces of the metal via, respectively. Above and below the glass layer, a first wiring layer and a second wiring layer are embedded in the insulating body, respectively, and connected to the first and second connecting vias, respectively. A third wiring layer and a fourth wiring layer are arranged on the upper and lower surfaces, respectively, of the insulating body. The present invention further includes a first via layer and a second via layer that penetrate at least a portion of the upper and lower parts of the insulating body, respectively. An electrode is placed on the upper side of the aforementioned electronic component. The first via layer includes a third connecting via and a fourth connecting via that connect the third wiring layer to the electrodes of the electronic component and the first wiring layer, respectively. The electronic component substrate according to claim 15, wherein the second via layer includes a fifth connecting via that connects the fourth wiring layer to the second wiring layer.

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