Method for fabricating a FeMFET device

Abstract

Title: Method for Manufacturing a FeMFET Device The invention relates to a method for manufacturing a FeMFET device comprising: - supplying a transistor (1) comprising a gate (10), a source (12), and a drain (13) connected to vias (14, 15), - forming a first metallic layer (21), - forming a ferroelectric layer (30a), - structuring the ferroelectric layer (30a) to form a closed pattern (31) above the gate (10) and open patterns (32a) above the vias (14, 15), - forming a second metallic layer (22), - etching the second metallic layer (22), configured to form vias (221, 222) by stopping at the ferroelectric layer (30a), and - etching the first metallic layer (21) on either side of the closed pattern (31) and the patterns open (32a), configured to form lines (211, 212). Figure for the abbreviation: Fig. 9A

Description

Title of the invention: Method for implementing a FeMFET device technical field

[0001] The present invention relates to the technical field of memory devices for microelectronics. Its particularly advantageous application is the formation of ferroelectric memory devices integrated into the end-of-line levels of a microelectronic chip. STATE OF THE ART

[0002] The ferroelectric properties of HfO2 or HfxZri XO2 (HZO) thin-film materials are particularly attractive for integrating non-volatile memories into the so-called "back end of line" (BEOL) layers of CMOS (Complementary Metal-Oxide-Semiconductor) technology for the most advanced technology nodes. Ferroelectric HfO2-based memories of the FeRAM (Ferroelectric Random Access Memory) type are currently being developed for non-volatile applications, with the aim of replacing Flash memories. Their main advantage is their very low power consumption. The basic cell of a FeRAM memory includes, in particular, a ferroelectric capacitor in which information is stored in the form of the polarization state of the electric dipoles.By connecting the ferroelectric capacitor HfO2 to the gate of a field-effect transistor, a device commonly called a FeMFET (acronym for "Ferroelectric Metal Field Effect Transistor") can also be formed. This type of FeMFET "ferroelectric transistor" advantageously exhibits a threshold voltage that varies depending on the bias state of the ferroelectric capacitor. The information density stored in such a device can be increased. Such a FeMFET device also makes it possible to perform "in-memory" calculations, thus reducing the energy consumption of electronic systems.

[0003] A known solution for integrating this type of device into the back end consists of first forming the ferroelectric capacitors on the gates of CMOS transistors using a dedicated lithography mask. The interconnecting vias are then formed in a conventional manner, for example, using a so-called "Damascene" approach. This increases the number of steps and the cost of the process. In particular, there is a need to optimize the process for manufacturing FeMFET devices that are at least partially integrated into the back end.

[0004] One object of the present invention is to meet this need, by alleviating all or part of the disadvantages mentioned above.

[0005] In particular, one object of the present invention is to provide a method for forming a FeMFET device at a reduced cost. Another object of the present invention is to provide a method for forming a FeMFET device with a limited number of steps. SUMMARY

[0006] To achieve this objective, according to one embodiment, a FeMFET device is provided comprising, stacked along a direction z: • a transistor comprising a gate surmounting a channel, a source and a drain on either side of the channel, • at least one interconnection connecting the source or drain, comprising: • at least one metallic line based on a first metal, and, • at least one metallic via based on a second metal, connected to said at least one metallic line, • a burn-stop layer interposed between at least one via and at least one line, said burn-stop layer comprising at least one via opening such that at least one via and at least one line are connected through said at least one via opening, • a ferroelectric capacitor connecting the grid, comprising: • at least one metallic line based on the first metal, and, • at least one metallic via made from the second metal, • a first portion of a ferroelectric layer interposed between at least one via and at least one line, said ferroelectric layer separating the at least one via and at least one line.

[0007] A FeMFET device, at least partially integrated into the "Back End" and connected by interconnections, is advantageously implemented. The formation of the interconnections and the ferroelectric capacitor can advantageously be carried out during the same etching steps.

[0008] The invention also provides methods for making such a FeMFET device.

[0009] The advantages described above with regard to the device apply mutatis mutandis to the methods according to the invention. BRIEF DESCRIPTION OF THE FIGURES

[0010] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0011] [Fig.lA] [Fig.2A] [Fig.3A] [Fig.4A] [Fig.5A] [Fig.6A] [Fig.7A] [Fig.8A] [Fig.9A] [Fig.1OA] [Fig. 11 A] [Fig.12A] [Fig.13A] Figures IA to 13A schematically illustrate in cross-section, in an xz plane, different stages of the manufacturing process of a FeMFET device according to a first embodiment of the present invention.

[0012] [Fig.lB] [Fig.2B] [Fig.3B] [Fig.4B] [Fig.5B] [Fig.6B] [Fig.7B] [Fig.8B] [Fig.9B] [Fig.1OB] [Fig.11B] [Fig.12B] [Fig.13B] Figures IB to IB schematically illustrate in perspective the steps of the manufacturing process of a FeMFET device illustrated respectively in Figures IA to IB, according to the first embodiment of the present invention.

[0013] [Fig.14A] [Fig.15A] [Fig.10A] [Fig.17A] [Fig.18A] [Fig.19A] [Fig.20A] [Fig.21A] [Fig.22A] [Fig.23A] [Fig.24A] Figures 14A to 24A schematically illustrate in cross-section, in an xz plane, different stages of the manufacturing process of a FeMFET device according to a second embodiment of the present invention.

[0014] [Fig. 14B] [Fig. 15B] [Fig. 10B] [Fig. 17B] [Fig. 18B] [Fig. 19B] [Fig. 20B] [Fig. 21B] [Fig. 22B] [Fig. 23B] [Fig. 24B] Figures 14B to 24B schematically illustrate, in perspective, the steps of the manufacturing process of a FeMFET device illustrated respectively in Figures 14A to 24A, according to the second embodiment of the present invention

[0015] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the thicknesses and / or dimensions of the different layers and patterns are not representative of reality. DETAILED DESCRIPTION

[0016] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0017] According to one example, the etching stop layer has, vis-à-vis the first metallic layer, an etching selectivity S2i: 30b greater than or equal to 5:1.

[0018] According to one example, the ferroelectric layer exhibits an etching selectivity S2i: si greater than or equal to 5:1 with respect to the first metal.

[0019] According to one example, the etching stop layer interposed between at least one via and at least one line of at least one interconnection is ferroelectric. The layer The etch arrest layer, inserted between at least one via and at least one line of the at least one interconnect, typically corresponds to a second part of the ferroelectric layer. The ferroelectric layer is used here both as an etch arrest layer and as a functional layer for the ferroelectric capacitor. This limits the number and type of layers in the device, thus reducing the manufacturing cost.

[0020] According to one example, the at least one interconnection comprises a first interconnection connecting the source and a second interconnection connecting the drain, and each of the first and second interconnections comprises an etch arrest layer interposed between at least one via and at least one line of said interconnection. All interconnections of the device typically have a portion of etch arrest layer interposed between two successive metallic layers of said interconnections. In this example, the etch arrest layer may be ferroelectric or non-ferroelectric.

[0021] According to one example, the vias connecting the source and drain of the transistor are obtained using a "Damascene" approach. After forming the gate and the source and drain of the transistor, a dielectric layer is deposited on the source and drain. This dielectric layer is typically planarized so as to expose one top face of the gate. Openings leading to the source and drain of the transistor are formed within the dielectric layer and then filled with a metal. Planarization is performed so as to remove the metal from the surface of the dielectric layer and the top face of the gate. Vias connecting the source and drain, and having exposed faces coplanar with the top face of the gate, are thus obtained. The top surface of the supplied transistor, including the exposed faces of the vias and the gate, is advantageously planar.This facilitates subsequent depositions, in particular the deposition of the first metallic layer and / or the deposition of the ferroelectric layer.

[0022] According to one example, the ferroelectric layer has a thickness e30 a between 2 nm and 15 nm, preferably between 7 nm and 10 nm.

[0023] According to one example, the ferroelectric layer is based on a material selected from: HfxZri XO2, HfO2. The HfO2 material may be undoped or doped. According to one example, the HfO2 material is doped with at least one of the following elements: Si, N, Gd, Y, Sc, Ge. The concentration of doping elements is typically between 0% and 10% at., preferably between 0.5% and 3% at.

[0024] According to one example, the structuring of the ferroelectric layer comprises the following sub-steps: • the formation of the first mask on the ferroelectric layer, said first mask directly defining at least one closed pattern and at least one open pattern including at least one via opening, • a partial removal of the ferroelectric layer, only in areas of the ferroelectric layer not covered by the first mask, so as to expose the first metallic layer outside the areas covered by the first mask, • the removal of the first mask.

[0025] In this example, the parts covered by the first mask correspond to the open and closed patterns. The lower electrode of the ferroelectric capacitor and the first-level lines participating in the source and drain interconnections are defined by the first mask alone.

[0026] According to one example, the partial removal of the ferroelectric layer is done by etching based on a chlorinated chemistry BC13.

[0027] According to one example, the formation of the first mask is achieved by double lithography. This well-known lithography process makes it possible to optimize, or even overcome, the resolution limitations of conventional lithography exposure equipment. Another solution is to use higher-resolution lithography equipment, for example, extreme UV or electron beam lithography. The formation of the first mask may include a first lithography followed by a second lithography, and then etching. Alternatively, the formation of the first mask may include a first lithography followed by a first etching, and then a second lithography followed by a second etching.

[0028] According to one example, the first mask is based on a non-metallic material, for example based on SiON, SiN, SiCN, HfO2, SiON, SiC.

[0029] According to one example, the second-level via(s) overlying the closed pattern(s) have a critical dimension CDvia 221, taken along an x-axis, that is smaller than a dimension CDb, also taken along the x-axis, of the closed pattern(s). This minimizes the risk associated with misalignment between the first and second masks. Since the first-level lines are typically wider than the second-level vias, the etching of the second metallic layer, associated with the formation of the second-level vias, will effectively stop at the ferroelectric layer, structured according to the closed pattern(s). The reliability of the process is thus increased.

[0030] According to one example, the second-level via(s) overlying the open pattern(s) have a critical dimension CDvia2o, taken along an x-axis, greater than or equal to a dimension CDopen of at least one via opening taken along the x-axis. This minimizes the risk of misalignment between the first and second masks. Since the second-level vias are typically wider than the via openings, aligning the second mask defining the vias with the via openings is facilitated. The etching of the second metallic layer, during The formation of the second-level vias will effectively stop at the ferroelectric layer, structured according to the open pattern(s). The etching of the second metallic layer does not extend to the via openings. The reliability of the process is increased.

[0031] According to one example, the first and second metallic layers are based on the same metallic material, for example TaN, TiN, Al, Ru, Mo.

[0032] According to one example, the etching of the second metallic layer and the etching of the first metallic layer are carried out by one and the same etching, during one and the same step.

[0033] According to one example, the first and second metallic layers are respectively based on a first metallic material and a second metallic material, said first and second metallic materials being different from each other.

[0034] According to one example, the etching of the second metallic layer and the etching of the first metallic layer are carried out by two different successive etchings.

[0035] According to an example, a method for manufacturing a FeMFET device is provided comprising: • a supply of a transistor comprising a gate surmounting a channel, a source and a drain on either side of the channel, and vias connecting the source and the drain, said vias and said gate each having a face exposed at the level of an upper surface, • the formation of a first metallic layer on the exposed faces of the upper surface, • the formation, on the first metallic layer, of a ferroelectric layer based on a ferroelectric material having, with respect to the first metallic layer, an etching selectivity S2i:3oa greater than or equal to 5:1, • a structuring of the ferroelectric layer, by means of at least one first mask, so as to expose parts of the first metallic layer and to retain parts of the ferroelectric layer in the form of at least one closed pattern overlying the transistor gate and at least one open pattern overlying at least one of the vias connecting the source or the drain, said at least one open pattern comprising at least one via opening leading to the underlying first metallic layer, • the formation of a second metallic layer on the exposed parts of the first metallic layer and on at least one closed motif and at least one open motif, • the formation, on the second metallic layer, of a second mask defining at least a second level of vias directly above at least one closed pattern and directly above at least one opening via at least one open pattern, • an etching of the second metallic layer, said etching being configured to form the vias of the second level by stopping on the ferroelectric layer and, • an engraving of the first metallic layer on either side of at least one closed pattern and at least one open pattern, said engraving being configured to form first-level lines by stopping on the upper surface.

[0036] The second-level vias above the open patterns are connected to the first-level lines through at least one via opening. These first-level lines are themselves connected to the vias connecting the transistor's source and drain. Interconnections to the transistor's source and drain are thus formed across several metal levels.

[0037] In this example, the second-level vias surmounting the closed patterns are separated from the first-level lines by the ferroelectric material. A ferroelectric capacitor is thus formed between several metallic layers. The lower electrode of the ferroelectric capacitor and the first-level lines participating in the source and drain interconnections are formed from the first metallic layer.

[0038] A FeMFET device, at least partially integrated into the "Back End" and connected by interconnections, is advantageously implemented. The formation of the interconnections and the ferroelectric capacitor is advantageously carried out during the same etching steps.

[0039] This process uses a structured ferroelectric layer embedded between the first and second metallic layers. This ferroelectric layer, which exhibits an etching selectivity S2i: 30a greater than or equal to 5:1, advantageously serves as an etching stop layer. Such an intercalated etching stop layer advantageously allows the metallic layers to be etched successively, for example in a single step or in a chained fashion. The number of process steps is thus limited.

[0040] According to another example, a method for manufacturing a FeMFET device is provided comprising: • a supply of a transistor comprising a gate surmounting a channel, a source and a drain on either side of the channel, and vias connecting the source and the drain, said vias and said gate each having a face exposed at the level of an upper surface, • the formation of a first metallic layer on the exposed faces of the upper surface, • the formation, on the first metallic layer, of an etching stop layer, • a structuring of the etching stop layer, by means of at least one first mask, so as to expose parts of the first metallic layer and to retain parts of the etching stop layer in the form of at least one open pattern overlying the grid and at least one of the vias connecting the source or the drain, said at least one open pattern comprising at least one via opening leading to the underlying first metallic layer, • the formation of a second metallic layer on the exposed parts of the first metallic layer and on at least one open motif, • the formation, on the second metallic layer, of a ferroelectric layer based on a ferroelectric material having, with respect to the second metallic layer, an S22:3o a selectivity at etching greater than or equal to 5:1, • a structuring of the ferroelectric layer, by means of at least a second mask, so as to expose parts of the second metallic layer and to retain parts of the ferroelectric layer in the form of at least one closed pattern surmounting the transistor gate, • the formation of a third metallic layer on the exposed parts of the second metallic layer and on at least one closed pattern, • the formation, on the third metallic layer, of a third mask defining vias directly above at least one closed motif and directly above at least one via opening of at least one open motif, • at least one etching of the third, second and first metallic layers, said at least one etching being configured to form vias by stopping on the ferroelectric layer and on the etching stop layer, and to form lines by stopping on the top surface.

[0041] In this example, the lower electrode of the ferroelectric capacitor is formed from the first and second metallic layers. The first-level lines participating in the source and drain interconnections are formed from the first metallic layer.

[0042] In this example, the ferroelectric capacitor is formed within the upper interconnection layers. It can be relatively far from the transistor to which it is associated. The ferroelectric layer forms only the closed pattern. The underlying etching stop layer forms an open pattern. This allows us to consider Different combinations of closed and open patterns are possible. The sizing of the capacitor's lower electrode and / or the ferroelectric separating layer of the capacitor is more precisely controlled. The etching selectivity between the different metallic layers and the dielectric layer can be adjusted, for example, reduced.

[0043] Unless otherwise required, it is understood that all optional features The above and / or the variants indicated may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0044] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposit or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0045] A substrate, film, or layer "based" on a material A is understood to mean a substrate, film, or layer comprising only that material A or that material A and possibly other materials, for example, dopant elements or alloying elements. Thus, an etching arrest layer based on silicon nitride (SiN) may, for example, comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even silicon oxynitride (SiON).

[0046] A closed motif is understood to be a motif that does not communicate with the underlying layer. Conversely, an open motif is understood to be a motif that communicates with the underlying layer through an opening, typically through a via opening.

[0047] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, although this is generally preferred, that the steps follow each other immediately; intermediate steps may separate them.

[0048] Furthermore, the term "step" refers to the execution of a part of the process, and can designate a set of sub-steps.

[0049] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may, in particular, be followed by actions related to a different step, and other actions of the first step may be repeated subsequently. Thus, The term "step" does not necessarily refer to unitary and inseparable actions in time and in the sequence of phases of the process. The etching of the first and second metallic layers, in particular, can be linked together or considered as part of a single etching step.

[0050] Selective etching with respect to or etching with selectivity with respect to means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. It is denoted SA:B. A selectivity SA:B of 10:1 means that the etching speed of material A is 10 times greater than the etching speed of material B.

[0051] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the accompanying figures.

[0052] In this patent application, the term thickness will preferably be used for a layer or film, and height for a device or structure. Thickness is measured along a direction normal to the principal plane of extension of the layer or film. Thus, a metallic layer typically has a thickness along the z-axis. A via formed from such a metallic layer has a height along the z-axis. The relative terms "on," "above," "above," "below," "underlying," and "below" refer to positions measured along the z-direction. A "lateral" dimension corresponds to a dimension along a direction in the xy-plane. A "lateral" or "lateral" extension is understood to be an extension along one or more directions in the xy-plane.

[0053] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically on the cross-sectional figures.

[0054] The terms "approximately", "around", "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the bounds are inclusive, unless otherwise stated.

[0055] Manufacturing steps for a FeMFET device according to a first embodiment of the invention are illustrated in figures IA, IB to 13A, 13B.

[0056] As illustrated in Figures IA, IB, the method comprises supplying a transistor 1, for example of the MOS (metal-oxide-semiconductor) type. This transistor 1 typically comprises a silicon-based substrate S, a gate 10 surmounting the substrate S, a source 12 and a drain 13 on either side of the gate 10, for example within the substrate S, and a channel 11 below the gate 10 and separated from the gate 10 by a or several dielectric layers 110. The grid 10 is typically flanked by spacers E.

[0057] Transistor 1 also includes vias 14 and 15 connecting the source 12 and drain 13 of the transistor, respectively. These vias 14 and 15 are preferably obtained using a "Damascene" approach. According to this approach, after the gate 10 and the source 12 and drain 13 of the transistor have been formed, a dielectric layer 401 is deposited. This dielectric layer 401 is typically planarized by chemical-mechanical polishing (CMP) to expose an upper face 100 of the gate 10. Openings leading to the source 12 and drain 13 of the transistor are formed within the dielectric layer 401 and then filled with a metal. Planarization, for example by CMP, is performed to remove the metal from the surface of the dielectric layer 401 and the upper face of the gate 10. The vias 14 and 15 are thus obtained. They respectively present exposed faces 140, 150 coplanar with the upper face 100 of the grid 10.The upper surface 200 of this transistor 1, comprising the exposed faces 140, 150, 100, is advantageously flat.

[0058] As illustrated in Figures 2A, 2B, a first metallic layer 21, typically based on a metal chosen from among TaN, TiN, Al, Ru, Mo, is first formed on the surface 200 of the transistor 1. The vias 14, 15 and the gate 10 are in direct contact with the metallic layer 21. This metallic layer 21 typically has a thickness e2i on the order of a few tens of nanometers to a few hundred nanometers, for example between 20 nm and 200 nm. The deposition of this metallic layer 21 can in particular be carried out by one of the following techniques: physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD). After deposition, the first metallic layer 21 can be planarized, for example by CMP. The first metallic layer 21 typically corresponds to a first metal layer.

[0059] As illustrated in Figures 3A and 3B, a ferroelectric layer 30a is then directly formed on the first metallic layer 21. This ferroelectric layer 30a typically has a thickness e30a on the order of a few nanometers, for example, between 2 nm and 15 nm. It is preferably based on a material chosen from: HfxZri XO2, HfO2. The deposition of this ferroelectric layer 30a is preferably carried out by ALD.

[0060] As illustrated in Figures 4A, 4B, an etching mask 301 is formed on the ferroelectric layer 30a. This etching mask 301 is, for example, SiON-based. It is typically obtained by lithography / etching, for example by means of single lithography under extreme UV exposure, or by means of double lithography, also called "double patterning".

[0061] The etching mask 301 comprises a solid pattern 311 above the gate 10 of transistor 1, and open patterns 321 above the vias 14, 15. The open patterns 321 comprise one or more openings 322 leading to the underlying ferroelectric layer 30a. The solid pattern 311 typically has a dimension Li along x of between 20 nm and 300 nm, depending on the lithography technique used. The open patterns 321 typically have a dimension L2 along x of between 8 nm and 150 nm, depending on the lithography technique used.

[0062] As illustrated in Figures 5A, 5B, the motifs 311, 321 are transferred into the ferroelectric layer 30a by anisotropic etching along the z-axis of the ferroelectric layer 30a in the presence of the mask 301. The etching of the ferroelectric layer 30a can be carried out by plasma using a chlorinated etching chemistry, for example BC1, BC13. The solid motif 311 of the mask 301 forms, after etching, the closed motif 31 in the ferroelectric layer 30a. The open motifs 321 of the mask 301 form, after etching, the open motifs 32a comprising the via openings 320 in the ferroelectric layer 30a. The motifs 31, 32a have substantially the same dimensions as the motifs 311, 321. The closed motif 31 typically has the dimension CD3i along x, and the via openings 320 of the open motifs 32a typically have the dimension CDopen along x. The mask 301 is removed after etching, for example by oxygen or hydrogen plasma.

[0063] As illustrated in Figures 6A and 6B, after structuring the ferroelectric layer 30a, a second metallic layer 22, typically based on a metal selected from TaN, TiN, Al, Ru, or Mo, is then formed on the first metallic layer 21, and on the closed motif 31 and the open motifs 32a. This metallic layer 22 typically has a thickness e22 on the order of a few tens of nanometers to a few hundred nanometers, for example, between 20 nm and 200 nm. The deposition of this metallic layer 22 can be carried out, in particular, by PVD, CVD, or ALD. After deposition, the second metallic layer 22 can be planarized, for example, by CMP. The second metallic layer 22 typically corresponds to a second metal layer.

[0064] As illustrated in Figures 7A, 7B, a second etching mask 302 comprising via patterns 323, 324 is formed on the second metallic layer 22. This second etching mask 302 is preferably based on organic layers, for example in the form of a stack known as "trilayer", typically comprising an organic planarization layer, an anti-reflective layer and a photosensitive resin layer.

[0065] The via patterns 324 of this second etching mask 302 are aligned vertically with the via openings 320 of the open patterns 32a. The via pattern 323 of this second etching mask 302 is aligned vertically with the closed pattern 31. The via patterns 324 typically have a CD32 dimension along x slightly greater, for example 10% greater, than the CDopen dimension along x of the via openings 320 of the open patterns 32a. This facilitates the alignment of the patterns 324 and 32a with each other. A certain tolerance on the alignment accuracy is thus obtained. The CD32 dimension along x of the via patterns 324 is, for example, between 10 nm and 150 nm.

[0066] As illustrated in Figures 8A, 8B, the first and second metallic layers 21, 22 are then etched through their entire thickness, along z, on either side of the via patterns 323, 324 and on either side of the open patterns 32a and the closed pattern 31. The second metallic layer 22 is first etched to form the vias 222, 221, and then the first metallic layer 21 is etched to form the lines 212, 211. The etchings of the first and second metallic layers 21, 22 are preferably linked. According to one possibility, particularly when the first and second metallic layers 21, 22 are of the same type, the etchings of these metallic layers 21, 22 are carried out in a single step, with the same etching chemistry.

[0067] The etchings are chosen here so as to selectively etch the first and second metals of the first and second metallic layers 21, 22 with respect to the ferroelectric layer material (structured in the form of motifs 31, 32a). The ferroelectric layer is advantageously used here as an etching stop layer. In particular, the etching selectivity S2i: 30 a, that is, the ratio between the etching rate of the metal of the first metallic layer 21 and the etching rate of the ferroelectric layer material, is greater than or equal to 5:1, preferably greater than or equal to 10:1. The etchings may be based on a CE| / H2 type chemistry.

[0068] As illustrated in Figures 9A, 9B, after etching, the mask 302 is removed, for example by oxygen-based plasma. Vias 222 having dimension CDvia222 along x are obtained above the open motifs 32a. The dimension CDvia222 is substantially equal to the dimension CD32 of the via motifs 324. A via 221 having dimension CDvia22i along x is obtained above the closed motif 31. A FeMFET device comprising interconnections I (212, 222) and a ferroelectric capacitor F (211, 31, 221) integrated into the interconnection levels is thus advantageously obtained. The ferroelectric capacitor F here comprises a lower electrode formed by the line 211, an upper electrode formed by the via 221, and a ferroelectric separation layer 31 between the lower and upper electrodes. The ferroelectric capacitor F is integrated here between the first and second metal layers.

[0069] As illustrated in Figures 10A, 10B, the interconnections I and the ferroelectric capacitor F are then conventionally integrated into a dielectric matrix by deposition and planarization of a dielectric layer 402, typically based on SiO2.

[0070] As illustrated in Figures 1 IA, 1 IB, a third metallic layer 23 for example based on TaN, TiN, Al, Ru, Mo, corresponding to a third metal level, can then be deposited on the layer 402 and the vias 221, 222 flush.

[0071] As illustrated in Figures 12A, 12B, a third mask 303 comprising, for example, line patterns 331 can be formed on the third metallic layer 23.

[0072] As illustrated in Figures 13A, 13B, the third metal layer 23 is then structured by etching through the mask 303. Lines 231 are thus formed in the third metal layer. These lines 231 typically connect the vias 221, 222 of the second metal layer.

[0073] Figures 14A, 14B to 24A, 24B illustrate manufacturing steps for a FeMFET device according to a second embodiment of the invention. In this second embodiment, the ferroelectric capacitor of the FeMFET device is integrated into higher interconnection levels. Only the steps and features that differ from those of the first embodiment are detailed below; the other steps and features are deemed to be identical to those of the first embodiment.

[0074] As illustrated in Figures 14A and 14B, after the formation of the first metallic layer 21, a stop layer 30b is directly formed on the first metallic layer 21. This stop layer 30b typically has a thickness e30b on the order of a few nanometers, for example, between 2 nm and 15 nm. It is preferably based on a dielectric material chosen from: SiO2, TiO2, HfO2, HfN, ZrN, SiN, or SiCN. The deposition of this stop layer 30b is preferably carried out by ALD. As before, an etch mask 301 is formed on the stop layer 30b. This etching mask 301 here includes only open patterns 321 above the vias 14, 15, and above the gate 10 of transistor 1. The open patterns 321 include one or more openings 322 leading into the underlying etching stop layer 30b.

[0075] As illustrated in Figures 15A, 15B, the patterns 321 are transferred into the etching stop layer 30b by anisotropic etching along z of the etching stop layer 30b in the presence of the mask 301. The open patterns 321 of the mask 301 form, after etching, the open patterns 32b comprising the via openings 320 in the layer 30b etching stop. Mask 301 is removed after etching, for example by oxygen-based plasma.

[0076] As illustrated in Figures 16A, 16B, after structuring the etching stop layer 30b, a second metallic layer 22, typically based on a metal taken from among TaN, TiN, Al, Ru, Mo, is then formed on the first metallic layer 21, and on the open motifs 32b. The second metallic layer 22 typically corresponds to a second metal level.

[0077] As illustrated in Figures 17A and 17B, a ferroelectric layer 30a is then directly formed on the second metallic layer 22. This ferroelectric layer 30a typically has a thickness e30a on the order of a few nanometers, for example, between 2 nm and 15 nm. It is preferably based on a material chosen from: HfxZri XO2, HfO2. The deposition of this ferroelectric layer 30a is preferably carried out by ALD.

[0078] As illustrated in Figures 18A, 18B, a second etching mask 302 comprising an intermediate motif 325 is formed on the ferroelectric layer 30a. This intermediate motif 325 is aligned vertically with the via opening 320 of the open motif 32b located above the gate 10 of the transistor. This intermediate motif 325 typically has a CD325 dimension along x greater, for example at least 20% greater, than the CDopen dimension along x of the via opening 320 of the open motif 32b. This facilitates the alignment of the motifs 325, 32b with each other. The dimensioning of the lower electrode of the capacitor and / or the ferroelectric separating layer of the capacitor is also better controlled. The CD325 dimension along x of the intermediate motif 325 is, for example, between 10 nm and 200 nm.

[0079] As illustrated in Figures 19A, 19B, the motif 325 is transferred into the ferroelectric layer 30a by anisotropic etching along the z-axis of the ferroelectric layer 30a in the presence of the mask 302. After etching, the motif 325 of the mask 302 forms the closed motif 31 in the ferroelectric layer 30a. The mask 302 is removed after etching, for example by oxygen-based plasma.

[0080] As illustrated in Figures 20A, 20B, after structuring of the ferroelectric layer 30a, a third metallic layer 23, typically based on a metal taken from TaN, TiN, Al, Ru, Mo, is then formed on the second metallic layer 22, and on the closed motif 31. The third metallic layer 23 typically corresponds to a third metal level.

[0081] As illustrated in Figures 21A, 21B, a third etching mask 303 comprising via motifs 323, 324 is formed on the third metal layer 23. The via motifs 324 of this third etching mask 303 are aligned vertically with the via openings 320 of the open motifs 32b. The via motif 323 of this The third etching mask 303 is aligned vertically with the closed pattern 31. The via patterns 324 typically have a CD32 dimension along x slightly larger, for example 10% larger, than the CDopen dimension along x of the via openings 320 of the open patterns 32b. This facilitates the alignment of the patterns 324 and 32a with each other. The CD32 dimension along x of the via patterns 324 is here, for example, between 8 nm and 150 nm.

[0082] As illustrated in figures 22A, 22B, the first, second and third metal layers 21, 22, 23 are then engraved through their entire thickness, along z, on either side of the via patterns 323, 324 and on either side of the open patterns 32b and the closed pattern 31. The third and second metal layers 23, 22 are first engraved to form the vias 222, 221 and the dot 223, then the first metal layer 21 is engraved to form the lines 212, 211. The engravings of the first, second and third metal layers 21, 22, 23 are preferably linked. According to one possibility, particularly when the first, second and third metallic layers 21, 22, 23 are of identical nature, the etching of these metallic layers 21, 22, 23 is carried out in a single step, with the same etching chemistry.

[0083] The etchings are chosen here so as to selectively etch the metals of the first, second, and third metallic layers 21, 22, 23 with respect to the material of the ferroelectric layer (structured in the form of pattern 31) and with respect to the material of the etching stop layer (structured in the form of patterns 32b). The etching stop layer and the ferroelectric layer are used as etching stop layers. In particular, the etching selectivity S22:3i, that is, the ratio between the etching rate of the metal of the second metallic layer 22 and the etching rate of the material of the ferroelectric layer, is greater than or equal to 5:1, preferably greater than or equal to 10:1. The etching selectivity S2i: 3b, that is, the ratio between the etching rate of the metal of the first metallic layer 21 and the etching rate of the material of the ferroelectric layer, is greater than or equal to 5:1, preferably greater than or equal to 10:1.The etching selectivity S2i:30b, i.e., the ratio between the etching rate of the first metal layer 21 and the etching rate of the etching stop layer material 30b, is greater than or equal to 5:1, preferably greater than or equal to 10:1. Etching may be based on chlorinated chemistry. Alternatively, the etching of the metallic material(s) may be carried out using fluorinated or fluorocarbon chemistry. In this case, it is preferable to avoid SiN and SiO2 as dielectric materials for the etching stop layer.

[0084] A FeMFET device comprising interconnections I (212, 222) and a ferroelectric capacitor F (211, 223, 31, 221) integrated within the interconnection levels is thus advantageously obtained. The ferroelectric capacitor F here comprises a lower electrode formed by line 211 and pad 223, an upper electrode formed by via 221, and a ferroelectric separation layer 31 between the lower and upper electrodes. The ferroelectric capacitor F is here integrated between the second and third metal levels.

[0085] As illustrated in figures 23A, 23B, after removal of the mask 303, the interconnections I and the ferroelectric capacitor F are then conventionally integrated into a dielectric matrix by deposition and planarization of a dielectric layer 402, typically based on SiO2.

[0086] As illustrated in Figures 24A, 24B, a fourth metallic layer 24, for example based on TaN, TiN, Al, Ru, Mo, corresponding to a fourth metal level, can then be deposited on the layer 402 and the vias 221, 222 flush with it. As before, the fourth metallic layer 24 can be structured as lines 231 connecting the vias 221, 222.

[0087] The invention is not limited to the embodiments described above. In particular, it is possible to structure the ferroelectric layer and / or the etching stop layer indirectly, by forming etching masks of opposite polarity and then carrying out a localized deposition of the materials of the ferroelectric layer and / or the etching stop layer.

Claims

1.

2. Demands FeMFET device comprising, stacked along a z-direction: • a transistor (1) comprising a gate (10) surmounting a channel (11), a source (12) and a drain (13) on either side of the channel (11), • at least one interconnection (222, 212) connecting the source (12) or the drain (13), comprising: • at least one metallic line (212) based on a first metal, and, • at least one metallic via (222) made of a second metal, connected to said at least one metallic line (212), • a burn-stop layer (32a, 32b) interposed between at least one via (222) and at least one line (212), said burn-stop layer (32a, 32b) comprising at least one via opening (320) such that at least one via (222) and at least one line (212) are connected through said at least one via opening (320), • a ferroelectric capacitor connecting the grid (10), comprising: • at least one metallic line (211) based on the first metal, and, • at least one metallic via (221) based on the second metal, a first part (31) of a ferroelectric layer (30a) intercalated between at least one via (221) and at least one line (211), said ferroelectric layer (31, 30a) separating at least one via (221) and at least one line (211). Device according to the preceding claim, wherein the etching stop layer (32a, 32b) intercalated between at least one via (222) and at least one line (212) of at least one interconnection (222, 212) is ferroelectric (30a).

3. Device according to any one of the preceding claims, wherein the at least one interconnection (222, 212) comprises a first interconnection connecting the source (12) and a second interconnection connecting the drain (13), and wherein each of the first and second interconnections comprises a burn-stop layer (32a, 32b) interposed between the at least one via (222) and the at least one line (212) of said interconnection (222, 212).

4. Device according to any one of the preceding claims, wherein at least one metallic via (222) of at least one interconnection (222, 212) connecting the source (12) or the drain (13) has a critical dimension CDvia222, taken along an x-axis, greater than or equal to a dimension CDopen of at least one via opening (320) taken along the x-axis.

5. Device according to any one of the preceding claims, wherein the at least one metallic via (221) of the ferroelectric capacitor has a critical dimension CDvia22i, taken along an x-axis, strictly less than a dimension CD3i, taken along the x-axis, of the ferroelectric layer (31) separating the at least one via (221) and the at least one line (211) of the ferroelectric capacitor.

6. Device according to any one of the preceding claims, wherein the first and second metals are based on the same metal taken from TaN, TiN, Al, Ru, Mo.

7. A method for manufacturing a FeMFET device according to any one of the preceding claims comprising: a supply of a transistor (1) comprising a gate (10) surmounting a channel (11), a source (12) and a drain (13) on either side of the channel (11), and vias (14, 15) connecting the source (12) and the drain (13), said vias (14, 15) and said gate (10) each having a face (140, 150, 100) exposed at the level of an upper surface (200), the formation of a first metallic layer (21) on the exposed faces (140, 150, 100) of the upper surface (200), a formation, on the first metallic layer (21), of a ferroelectric layer (30a) based on a ferroelectric material having, vis-à-vis the first metallic layer (21), a selectivity S2i:3o a at etching greater than or equal to 5:1, a structuring of the ferroelectric layer (30a), by means of at least one first mask (301), so as to expose parts of the first metallic layer (21) and to retain parts of the ferroelectric layer (30a) in the form of at least one closed pattern (31) surmounting the gate (10) of the transistor (1) and at least one open pattern (32a) surmounting at least one of the vias (14, 15) connecting the source (12) or the drain (13), said at least one open pattern (32a) comprising at least one via opening (320) leading to the underlying first metallic layer (21), the formation of a second metallic layer (22) on the exposed parts of the first metallic layer (21) and on at least one closed motif (31) and at least one open motif (32a), a formation, on the second metallic layer (22), of a second mask (302) defining at least a second level of vias directly above at least one closed motif (31) and directly above at least one via opening (320) of at least one open motif (32a),

8. • an etching of the second metallic layer (22), said etching being configured to form the vias (221, 222) of the second level by stopping on the ferroelectric layer (30a) and, • an engraving of the first metallic layer (21) on either side of at least one closed pattern (31) and at least one open pattern (32a), said engraving being configured to form first-level lines (211, 212) stopping on the upper surface (200). A method for manufacturing a FeMFET device according to any one of claims 1 to 6 comprising: a supply of a transistor comprising a gate above a channel, a source and a drain on either side of the channel, and vias connecting the source and the drain, said vias and said gate each having an exposed face at the level of a top surface, a formation of a first metallic layer on the exposed faces of the top surface, a formation, on the first metallic layer, of a burn-stop layer (30b), a structuring of the etching stop layer (30b), by means of at least one first mask, so as to expose parts of the first metallic layer and to retain parts of the etching stop layer (30b) in the form of at least one open pattern (32b) overlying the grid and at least one via connecting the source or the drain, said at least one open pattern (32b) comprising at least one via opening leading to the underlying first metallic layer, a formation of a second metallic layer on the exposed parts of the first metallic layer and on the at least one open pattern, a formation, on the second metallic layer, of a ferroelectric layer (30a) based on a ferroelectric material having, with respect to the second metallic layer, an S22:30a etching selectivity greater than or equal to 5:1, a structuring of the ferroelectric layer (30a), by means of at least a second mask, so as to expose parts of the second metallic layer and to retain parts of the ferroelectric layer in the form of at least one closed motif (31) surmounting the transistor gate, the formation of a third metallic layer on the exposed parts of the second metallic layer and on at least one closed pattern, a formation, on the third metallic layer, of a third mask defining vias directly above the at least one closed pattern (31) and in line with at least one via opening of at least one open pattern (32b), • at least one etching of the third, second and first metallic layers, said at least one etching being configured to form vias by stopping on the ferroelectric layer and on the etching stop layer, and to form lines by stopping on the upper surface.

9. A method according to any one of claims 7 to 8, wherein the ferroelectric layer (30a) is based on a material taken from: HfxZrl xO2, HfO2.

10. A method according to any one of claims 7 to 9, wherein the ferroelectric layer (30a) has a thickness e30a of between 2 nm and 15 nm, preferably between 7 nm and 10 nm.

11. A method according to any one of claims 7 to 10, wherein the via(s) (221) of the second level surmounting the at least one closed motif (31) have a critical dimension CDvia22i, taken along an x-axis, less than a dimension CDh taken along the x-axis, of the at least one closed motif (31).

12. A method according to any one of claims 7 to 11, wherein the via(s) (222) of the second level surmounting the at least one open motif (32a) have a critical dimension CDvia222, taken along an x-axis, greater than or equal to a dimension CDopen of the at least one via opening (320) taken along the x-axis.

13. A method according to any one of claims 7 to 12, wherein the first and second metallic layers (21, 22) are based on the same metallic material, for example TaN, TiN, Al, Ru, Mo.

14. A method according to any one of claims 7 to 13, wherein the etching of the second metallic layer (22) and the etching of the first metallic layer (21) are carried out by a single etching, in a single step.

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