Delay-optimized spad combinational logic

Abstract

A delay-optimized combinational logic circuit 120, e.g for Single Photon Avalanche Diode (SPAD) image sensors, has sixteen inputs and one output and comprises a plurality of 2-input NOR gates with del

Description

This invention relates to readout circuits for Single Photon Avalanche Diode (SPAD) image sensors, especially those designed for combining outputs from multiple SPADs into a single output. Traditional combinational logic does not optimize for delays among the outputs from the SPADs, resulting in broader histograms with increased Full Width at Half Maximum (FWHM). Our invention addresses this issue by employing customized sizes of the transistors used by the gates in the combinational logic circuits. This adjustment significantly reduces the difference between delays among the SPAD outputs, enhancing the FWHM of the resulting histogram. Embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings in which: Figure 1 illustrates a 4x4 SPADs array combined by a combinational logic to one signal output. Figure 2 shows the detailed transistor circuits corresponding to each 2-input NAND gate while the PMOS widths are adjusted to optimize the delay. Figure 3 shows the timing diagram illustrating the shortest and the longest propagation delay of the 2-input NAND gate. Figure 4 shows the detailed transistor circuits corresponding to each 2-input NOR gate while the NMOS widths are adjusted to optimize the delay. Figure 5 shows the detailed transistor circuits corresponding to each 4-input NAND gate while PMOS widths are adjusted to optimize the delay. Figure 6 shows the timing diagram illustrating the shortest and the longest propagation delay of the 2-input NOR gate. Figure 7 shows the detailed transistor circuits corresponding to each 4-input NOR gate while NMOS widths are adjusted to optimize the delay. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings in which: Figure 1 illustrates a 4x4 SPADs array combined by a combinational logic to one signal output. Figure 2 shows the detailed transistor circuits corresponding to each 2-input NAND gate while the PMOS widths are adjusted to optimize the delay. Figure 3 shows the timing diagram illustrating the shortest and the longest propagation delay of the 2-input NAND gate. Figure 4 shows the detailed transistor circuits corresponding to each 2-input NOR gate while the NMOS widths are adjusted to optimize the delay. Figure 5 shows the detailed transistor circuits corresponding to each 4-input NAND gate while PMOS widths are adjusted to optimize the delay. Figure 6 shows the timing diagram illustrating the shortest and the longest propagation delay of the 2-input NOR gate. Figure 7 shows the detailed transistor circuits corresponding to each 4-input NOR gate while NMOS widths are adjusted to optimize the delay. DETAILED DESCRIPTION OF THE EMBODIMENTS Combinational logic for SPAD pixels Figure 1 shows a 4x4 SPAD array 110 combined by a combinational logic 120 to a single output 130. A single SPAD pixel may comprise: a SPAD diode with quenching and pulse-shaping circuit 140, pixel output 150, and additional in-pixel circuits 160 including, but not limited to: SPAD-enabling circuits with a memory circuit storing enabling bit, pixel output masking circuits, and voltage level shifters. All 16 pixel outputs 170 are connected in pairs to the inputs of 8 2-input NOR gates 180. Outputs of the 8 2-input NOR gates 180 are connected to the inputs of 4 2-input NAND gates 190. The outputs of 4 2-input NAND gates 190 are connected to the inputs of 2 2-input NOR gates 180, which outputs are combined by the 2-input NAND gate 190 to the single output of the combinational logic 130. Other possible embodiments of 16-input-to-one-output combinational logic include but not limited: (a) a circuit constructed with 4 4-input NOR gates 510, which outputs are connected to a 4-input NAND gate 410, (b) a circuit constructed with 4 4-input NOR gates 510, which outputs are connected to the 4-input NOR gate 510, and (c) a circuit constructed only with the use of 2-input OR gates 150. The number of combined SPADs is purely illustrative and may be varied. Combinational logic may be used to combine signals from SPADs or other photodetectors or any other suitable electronic signals. NAND gates with delay-optimized PMOS transistors Figure 2 shows a 2-input NAND gate 210 with delay-optimized PMOS transistors 220. The propagation delay of different inputs of the 2-input NAND gate 210 and other basic logic gates is not the same for all possible input combinations. Figure 3 shows the timing diagram illustrating two different propagation delays of the 2-input NAND gate 210. All inputs of the gate change at the same time to 370. The 2-input NAND gate 210 has the longest propagation delay tdeiayjongest 3110 when the input A transitions from logic high to logic low 310 and the input B stays at logic high 320. The output 330 changes its logic state at time t2 390. The shortest propagation delay tdeiay_shortest 3100 is observed when input A transitions from logic high to logic low 340 and input B transitions from logic high to logic low 350. In this case the output 360 changes its logic state at time ti 380. The difference between the longest and the shortest propagation delay tdiff 3120 can be minimized by decreasing the resistances of the PMOS transistors 220 relative to the resistances of the NMOS transistors 230. A typical layout of the PMOS transistor 220 in a complementary metal-oxide-semiconductor (CMOS) process shown on Figure 2 comprises: an NWELL implant 240, an opening in shallow trench isolation 250, a polysilicon layer forming the gate of the transistor 260, a PPLLIS implant 270, and contacts 280. Conventionally, logic gates use equally sized PMOS and NMOS transistors, i.e. with PMOS transistor width Wp 290 equal to NMOS transistor width Wn, and PMOS transistor length Lp 2100 equal to NMOS transistor length Ln. Prior art logic gate circuits use minimum-sized PMOS and NMOS transistors, with both width and length set to the lowest values allowed by the given CMOS technology. In order to optimize the PMOS transistors 220 in the 2-input NAND gate 210 its width Wp 290 is increased while its length Lp 2100 is kept fixed, decreasing the resistance. Figure 4 shows a 4-input NAND gate 410 with delay-optimized PMOS transistors 420. The difference between the longest and the shortest propagation delay can be minimized by decreasing the resistances of the PMOS transistors 420 relative to the resistances of the NMOS transistors 430. A typical layout of the PMOS transistor 420 in a CMOS process comprises: an NWELL implant 240, an opening in shallow trench isolation 250, a polysilicon layer forming the gate of the transistor 260, a PPLUS implant 270, and contacts 280. In order to decrease the resistance of the PMOS transistor 420, its width Wp 440 is increased while its length Lp 450 is kept fixed. The choice of manufacturing layers shown in the PMOS transistor layout is purely illustrative and may vary depending on process, technology and manufacturer of the integrated circuits. The number of inputs of the NAND gate is purely illustrative and may be varied. The same PMOS resistance optimization method can be used for any number of inputs and the optimized PMOS transistor widths and lengths may vary depending on the number of inputs of the NAND gate as well as the various parameters of the CMOS technology used to manufacture the circuit. NOR gates with delay-optimized NMOS transistor Figure 5 shows a 2-input NOR gate 510 with delay-optimized NMOS transistors 530. Similarly to the 2-input NAND gate 210, the propagation delay is not the same for all possible input combinations. Figure 6 shows the timing diagram illustrating two different propagation delays of the 2-input NOR gate 510. All inputs of the gate change at the same time to 670. The 2-input NOR gate 510 has the longest propagation delay tdeiayjongest 6110 when the input A transitions from logic low to logic high 610 and the input B stays at logic low 620. The output 630 changes its logic state at time t2 690. The. In this case the output 660 changes its logic state at time h 680. The difference between the longest and the shortest propagation delay tditf 6120 can be minimized by decreasing the resistances of the NMOS transistors 530 relative to the resistances of the PMOS transistors 520. A typical layout of the NMOS transistor 530 in a CMOS process shown on Figure 5 comprises: an opening in shallow trench isolation 250, a polysilicon layer forming the gate of the transistor 260, an NPLLIS implant 540, and a contact 280. In order to decrease the resistance of the NMOS transistor 530, its width Wn 550 is increased while its length Ln 560 is kept fixed. Figure 7 shows a 4-input NOR gate 710 with delay-optimized NMOS transistors 730. The difference between the longest and the shortest propagation delay can be minimized by decreasing the resistances of the NMOS transistors 730 relative to the resistances of the NMOS transistors 720. A typical layout of the NMOS transistor 730 in a CMOS process comprises: an opening in shallow trench isolation 250, a polysilicon layer forming the gate of the transistor 260, an NPLLIS implant 540, and a contact 280. In order to decrease the resistance of the NMOS transistor 730, its width Wn 740 is increased while its length Ln 750 is kept fixed. The choice of manufacturing layers shown in the NMOS transistor layout is purely illustrative and may vary depending on process, technology and manufacturer of the integrated circuits. The number of inputs of the NOR gate is purely illustrative and may be varied. The same NMOS resistance optimization method can be used for any number of inputs and the optimized NMOS transistor widths and lengths may vary depending on the number of inputs of the NOR gate as well as the various parameters of the CMOS technology used to manufacture the circuit.

Claims

1. A delay-optimized 16-input-to-one-output combinational logic comprising:a plurality of 2-input NOR gates with delay-optimized NMOS transistor widths; anda plurality of 2-input NAND gates with delay-optimized PMOS transistor widths;wherein all circuit inputs are connected to the inputs of 8 said 2-input NOR gates, the outputs of 4 said 2-input NOR gates are connected to the inputs of 4 said 2-input NAND gates, the outputs of 4 said 2-input NAND gates are connected to the inputs of 2 said 2-input NOR gates, and the outputs of 2 said 2-input NOR gates are connected to the inputs of said 2-input NAND gate.

2. A delay-optimized 16-input-to-one-output combinational logic described in claim 1 wherein 4 4-input NOR gates with delay-optimized NMOS transistor widths and a 4-input NAND gate with delay-optimized PMOS transistor widths are used, and all circuit inputs are connected to the inputs of 4 said 4-input NOR gates, and the outputs of 4 said 4-input NOR gates are connected to the inputs of said 4-input NAND gate.

3. A delay-optimized 16-input-to-one-output combinational logic described in claim 1 wherein 15 2-input OR gates with delay optimized NMOS transistor widths are used, and all circuit inputs are connected to the inputs of 8 said 2-input OR gates, the outputs of 8 said 2-input OR gates are connected to the inputs of 4 said 2-input OR gates, the outputs of 4 said 2-input OR gates are connected to the inputs of 2 said 2-input OR gates, and the outputs of 2 said 2-input OR gates are connected to the inputs of said 2-input OR gate.

4. A delay-optimized 16-input-to-one-output combinational logic described in claim 1 wherein 5 4-input OR gates with delay-optimized NMOS transistor widths are used, and all circuit inputs are connected to the inputs of 4 said 4-input OR gates, and the outputs of said 4-input OR gates are connected to the inputs of said 4-input OR gate.

5. A delay-optimized combinational logic described in claim 1 where any number of inputs is combined to one or more outputs using any type of logic gates with delay-optimized NMOS transistor widths or delay-optimized PMOS transistor widths.

6. A delay-optimized combinational logic described in claim 1 where any number of inputs is combined to one or more outputs using any type of logic gates with any delay optimization transistor sizing method where both transistor length and width can bechosen to decrease the difference between the shortest propagation delay and the longest propagation delay.

7. A delay-optimized combinational logic described in claim 1 where any number of inputs is combined to one or more outputs using any type of logic gates with any delay optimization transistor sizing method where transistor layout is drawn using commoncentroid technique or interdigitation technique or a combination of common-centroid and inter-digitation techniques or snake-shaped transistor layout technique.