A non-linear capacitor

Abstract

The disclosed circuit charges and discharges a capacitor at differing rates. The circuit may be suitable in applications requiring different power-on and power-off delays. The different charge and dis

Description

TECHNICAL FIELD The present invention relates to the field of circuit technology, in particular, to a non-linear capacitor. BACKGROUND Power-on delay circuits usually have the following problems: when the power is turned off, for the non-linear capacitor, the discharging time is at least as long as the turned on delay time, and in most cases, the said discharging time is much longer than the said delay time. The turned on delay time can be reduced by rapidly shortening the power cycle. However, in some cases, this method is difficult to implement. In addition, depending on the specific invention of the power-on delay circuit, this method may cause a very disadvantageous impact. SUMMARY OF THE INVENTION For the above problems in the related art, the present invention proposes a non-linear capacitor with widely varying effective charging capacitance and effective discharging capacitance, thereby the charging time and the discharging time may be configured more flexibly. According to embodiments of the present invention, a non-linear capacitor is provided, comprises a capacitor, a first amplifier device, a second amplifier device, and an input and output node for providing a charging current and a discharging current, wherein the capacitor connects to the input and output node through the first and the second amplifier devices; when the capacitor is charging, one of the first and the second amplifier devices is conducted to vary the charging current, and the capacitor is charged by the changed charging current, when the capacitor is discharging, the other of the first and the second amplifier devices is conducted to vary the discharging current, and the capacitor is discharged by the varied discharging current, wherein a variation trend of the charging current is opposite to a variation trend of the discharging current. According to embodiments of the present invention, the first amplifier device is a first NPN transistor, and the second amplifier device is a second NPN transistor, an emitter of the first NPN transistor and a base of the second NPN transistor are connected to an end of the capacitor, and a base of the first NPN transistor and an emitter of the second NPN transistor are connected to the input and output node. According to embodiments of the present invention, the effective charging capacitance Ccharge and the effective discharging capacitance Cdischarge respectively are: Cdischarge — (02 +1) Cl, Ccharge — Cl / (01 +1), wherein 01 is a current gain of the first NPN transistor, and 02 is a current gain of the second NPN transistor. According to embodiments of the present invention, the first NPN transistor and the second NPN transistor are connected as a Darlington pair. According to embodiments of the present invention, the first NPN transistor and the second NPN transistor are connected as a Sziklai pair. According to embodiments of the present invention, the first amplifier device is a first PNP transistor, and the second amplifier device is a second PNP transistor, an emitter of the first PNP transistor and a base of the second PNP transistor are connected to an end of the capacitor, and a base of the first PNP transistor and an emitter of the second PNP transistor are connected to the input and output node. According to embodiments of the present invention, the effective charging capacitance Ccharge and the effective discharging capacitance Cdischarge respectively are: Ccharge = (02 +1) Cl, Cdischarge — Cl / (01 +1), wherein 01 is a current gain of the first PNP transistor, and 02 is a current gain of the second PNP transistor. According to embodiments of the present invention, the first PNP transistor and the second PNP transistor are connected as a Darlington pair. According to embodiments of the present invention, the first PNP transistor and the second PNP transistor are connected as a Sziklai pair. According to embodiments of the present invention, the non-linear capacitor further comprises a resistor connected to the input and output node. According to embodiments of the present invention, the non-linear capacitor comprises: a capacitor, a first transistor, a second transistor, and an input and output node for providing a charging current and a discharging current; an emitter of the first transistor and a base of the second transistor are connected to a first end of the capacitor, and a base of the first transistor and the second transistor are connected to the input and output node, wherein one of the first transistor and the second transistor is conducted and the other is cut off when the capacitor is charging, and the one of the first transistor and the second transistor is cutoff and the other is conducted when the capacitor is discharging. According to embodiments of the present invention, the first transistor and the second transistor are NPN transistors; wherein the first transistor is conducted when the capacitor is charging, and the second transistor is conducted when the capacitor is discharging. According to embodiments of the present invention, the first transistor and the second transistor are PNP transistors; wherein the second transistor is conducted when the capacitor is charging, and the first transistor is conducted when the capacitor is discharging. According to embodiments of the present invention, the non-linear capacitor further comprises a resistor connected to the input and output node. According to embodiments of the present invention, characterized in that, the first transistor and the second transistor are connected as a Darlington pair or a Sziklai pair. The beneficial effects of the present invention are as follows: Since a first amplifier device and a second amplifier device connect the capacitor to the input and output node in an alternate conduction manner, and the charging current and the discharging current supplied to the capacitor are inversely changed by the first amplifier device and the second amplifier device, and correspondingly the effective charging capacitance and effective discharging capacitance are inversely changed, the non-linear capacitor of the present invention may have widely varying effective charging capacitance and effective discharging capacitance. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS Some embodiments of the invention will now be described, by way of example only, with reference to the accompanying diagrammatic drawings, in which; Fig. 1 is a circuit diagram of a non-linear capacitor according to an embodiment of the present invention; Fig. 2 is a circuit diagram of an equivalent charging and discharging circuits of the circuit in Fig. 1; Fig. 3A is a diagram of simulation results of the circuit in Fig. 1; Fig. 3B is a time zoomed diagram of Fig. 3A; Fig. 4 is a circuit diagram of a non-linear capacitor using Darlington pair according to an embodiment of the present invention; Fig. 5 is a circuit diagram of a non-linear capacitor using Sziklai pair according to an embodiment of the present invention; Fig. 6 is a circuit diagram of a non-linear capacitor with fast charge time and slow discharge time according to an embodiment of the present invention; Fig. 7 is a circuit diagram of a non-linear capacitor using Darlington pair according to an embodiment of the present invention; Fig. 8 is a circuit diagram of a non-linear capacitor using Sziklai pair according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is obvious that the embodiments to be described are only a part the embodiments of the present invention rather than all of the embodiments of the present invention. All other embodiments obtained by the skilled in the art based on the embodiments of the present invention are within the protection scope of the present invention. Fig. 1 shows a circuit diagram of a non-linear capacitor according to an embodiment of the present invention. As shown in Fig. 1, the non-linear capacitor comprises a capacitor Cl, a first amplifier device 10, a second amplifier device 20, and an input and output node Nl, wherein the input and output node Nl is used to provide a charging current and a discharging current. The capacitor Cl connects to the input and output node Nl through one of the first amplifier device 10 and the second amplifier device 20. In other words, the second amplifier device 20 is cut off when the first amplifier device 10 is conducted, and the first amplifier device 10 is cut off when the second amplifier device 20 is conducted. Wherein, one of the first amplifier device 10 and the second amplifier device 20 (for example, the second amplifier device 20) may be conducted to vary the charging current when the capacitor Cl is charging. And the capacitor Cl is charged by the varied charging current. The other of the first amplifier device 10 and the second amplifier device 20 (for example, the first amplifier device 10) may be conducted to vary the discharging current when the capacitor Cl is discharging. And the capacitor Cl is discharged by the varied discharging current. For example, the charging current and the discharging current may be varied by the current gain of the amplifier devices. And a variation trend of the charging current is opposite to a variation trend of the discharging current. For example, the charging current increases as the discharging current decreases; or, the charging current decreases as the discharging current increases. Thereby, the phase difference between the effective charging capacitance and the effective discharging capacitance is increased. Through the above technical solution of the present invention, the variation trends of the effective charging capacitance and the effective discharging capacitance are opposite to each other because the variation trends of the charging current and the discharging current of capacitor Cl are opposite to each other. For example, the effective charging capacitance increases while the effective discharging capacitance decreases. Therefore, the non-linear capacitor of the present invention may have widely varying effective charging capacitance and effective discharging capacitance. Refer to Fig. 1, in an embodiment, the first amplifier device 10 is a first PNP transistor QI, and the second amplifier device 20 is a second PNP transistor Q2. In other embodiments, the first amplifier device 10 and the second amplifier device 20 may also be implemented by other suitable components or a combination of a plurality of components. An emitter of the first PNP transistor QI and a base of the second PNP transistor Q2 are connected to an end of the capacitor Cl, and a base of the first PNP transistor QI and an emitter of the second PNP transistor Q2 are connected to the input and output node Nl. A collector of the first PNP transistor QI and a collector of the second PNP transistor Q2 may be respectively connected to reference voltages. In the present embodiment, the collector of the first PNP transistor QI and the collector of the second PNP transistor Q2 are grounded respectively. In an embodiment, an asymmetric capacitor of the present invention further comprises a first resistor RI, one end of the first resistor RI is connected to a voltage source VI, and the other end is connected to the input and output node Nl. In an embodiment, the first resistor RI has a resistance of 47kQ. The resistance of the first resistor RI may be any other suitable configuration. When the capacitor Cl is charging, the first PNP transistor QI is reverse biased to be cut off. The second PNP transistor Q2 is conducted. Thus, the second PNP transistor Q2 may increase the effective capacitance of the capacitor Cl when the capacitor Cl is charging. Specifically, a charging current Icharge from the input and output node N1 provides an emitter current le2 for the second PNP transistor Q2, a base current Ib2 of the second PNP transistor Q2 charges the capacitor Cl, and a collector current lC2 of the second PNP transistor Q2 is shunted to OV. Since the operation of the second PNP transistor Q2 satisfies the following formula: Ie2 = Ib2 + Ic2 and lC2 = 02-Ib2, wherein 02 is a current gain of the second PNP transistor Q2. Therefore, the charging current Icharge from the input and output node N1 satisfies Icharge — (02 +1)■ Ib2. Thus, the current gain of the second PNP transistor Q2 decreases the base current Ib2 that is the charging current of the capacitor Cl, the resultant effective charging capacitance Charge satisfies: Ccharge = (02+1)-Cl (1). When the capacitor Cl is discharging, the second PNP transistor Q2 is reverse biased to be cut off, and the first PNP transistor QI is conducted. The first PNP transistor QI may decrease the effective capacitance of the capacitor Cl when the capacitor Cl is discharging. Specifically, a discharging current Idischarge from the input and output node N1 provides the base current Ibi for the first PNP transistor QI. The emitter current lei of the first PNP transistor QI is used as the discharging current of the capacitor Cl so as to discharge the capacitor Cl, and the collector current lei is shunted to OV. Similarly, the operation of the second PNP transistor Q2 satisfies the following formula: lei = Ibi + lei and Li =|3i-1 bi, wherein £i is a current gain of the first PNP transistor QI. Thus, the discharging current (discharge = lei / (0i +1). Since the current gain of the first PNP transistor QI increases the discharging current of the capacitor Cl, the resultant effective discharging capacitance is: Cdischarge = Cl / (Pl +1) (2). It's clear that the non-linear capacitor of the present invention provides the widely varying effective charging capacitance and effective discharging capacitance. Taking a capacitor Cl of lOOnF as an example, the non-linear capacitor proposed in the present invention has an effective charging capacitance which is about 22pF and an effective discharging capacitance which is about 620pF. Thus, the charging time and discharging time can be configured more flexibly. The asymmetric capacitor of the present invention is simulated by the circuit shown in Fig. 2. Wherein the voltage source VI and a second resistor R2 form a 50Q pulse generator, which is connected to a third resistor R3 of 50Q. A second capacitor C2 and a fourth resistor R4 are an RC network having a charging time which is equivalent to the asymmetric capacitor consisting of the first resistor RI, the capacitor Cl, the first PNP transistor QI and the second PNP transistor Q2. The third capacitor C3 and a fifth resistor R5 are an RC network having a discharging time which is equivalent to the asymmetric capacitor consisting of the first resistor RI, the capacitor Cl, the first PNP transistor QI and the second PNP transistor Q2. Diodes DI, D2 have voltages that are approximate or equal to the base-emitter voltage of the first PNP transistor QI, and diodes D3, D4 have voltages that are approximate or equal to the base-emitter voltage of the second PNP transistor Q2. The second capacitor is of llpF and the third capacitor is of 600pF. That is, the effective charging capacitance is llpF and the effective discharging capacitance is 600pF. The simulation results are shown in Fig.3A and Fig.3B, wherein SI, S2, and S3 represent the curves of simulation results of the asymmetric capacitor of the present invention, the equivalent charging RC network and the equivalent discharging RC network respectively. The asymmetric capacitor has a charging time of 517ms that is approximately as same as the 47kQ, llpF network with R4 and C2, and has a discharging time of 28.2p.s that is approximately as same as the 47kQ, 600pF network with R5 and C3. In an embodiment, a Darlington pair may be used to form the asymmetric capacitor of the present invention. As shown in Fig. 4, the first PNP transistor Qi and the second PNP transistor Q2 are connected as a Darlington pair. It should be understood that a Darlington pair represents the transistor combination of two transistors, and the gain of a Darlington pair is the product of the gains of the two transistors. Similar to the circuit shown in Fig. 1, Darlington-connected transistors Q21, Q22 charge the capacitor Cl, the effective charging time constant is about: Rl-Cl(P2rP22), and this effective charging time constant is obtained from the above formula (1). Darlington-connected transistors Qll, Q12 discharge the capacitor Cl, the effective discharging time constant is about: Rl-Cl / (Pirfhi), and this effective discharging time constant is obtained from the above formula (2). In some embodiments, Darlington pair, such as MMBTA13 and MMBTA14, may be used. In other embodiments, an on-chip Super-Beta transistor with a base-emitter voltage drop may also be used to provide an extremely high gain. In an embodiment, a Sziklai pair may be used to form the asymmetric capacitor. As shown in Fig. 5, both the first PNP transistor QI and the second PNP transistor Q2 are connected as a Sziklai pair. It should be understood that a Sziklai pair represents the transistor combination of two semiconductor types (such as NPN and PNP). The gain of the Sziklai pair is the product of the gains of the two transistors. Sziklai-connected transistors Q41, Q42 charge the capacitor Cl, the effective charging time constant is about: Rl-Cl (phr^), and this effective charging time constant is obtained from the above formula (1). Sziklai-connected transistors Q31, Q32 discharge the capacitor Cl, an effective discharging time constant is about: Rl-Cl / (¢31-332), this effective discharging time constant is obtained from the above formula (2). Fig. 6 is a circuit diagram of a non-linear capacitor according to an embodiment of the present invention. Refer to Fig. 6, the first amplifier device 10 can be a first NPN transistor QI', and the second amplifier device 20 can be a second NPN transistor Q2'. An emitter of the first NPN transistor QI' and a base of the second NPN transistor Q2' are connected to an end of the capacitor Cl, and a base of the first NPN transistor QI' and an emitter of the second NPN transistor Q2' are connected to the input and output node Nl. A collector of the first NPN transistor QI' is connected to a second reference voltage, and a collector of the second NPN transistor Q2' is connected to a third reference voltage. In the present embodiment, the second reference voltage and the third reference voltage are the voltage source V2. When the capacitor Cl is charging, the second NPN transistor Q2' is cut off. The first NPN transistor QI' is conducted. Since the operation of the first NPN transistor QI' satisfies the following formula: lei'= Ibi' + lei' and lci' =0i'-lbi', wherein Pi' is a current gain of the first NPN transistor QI'; Ibi', lei'and lci' are the base current, the emitter current, and the collector current of the first NPN transistor QI', respectively. The current gain of the first NPN transistor QI' increases the emitter current lei which is the charging current of the capacitor Cl, thus the charging time constant is about: Rl-Cl / Pi' when charging. When the capacitor Cl is discharging, the first NPN transistor QI' is cut off, and the second NPN transistor Q2' is conducted. The current gain of the second NPN transistor Q2' increases the discharging current of the capacitor Cl, thus the discharging time constant is about: Rl-Cl^' when discharging, wherein P2' is a current gain of the second NPN transistor Q2'. According to the above, a "dual circuit" (or "complementary circuit") operation with fast charging and slow discharging is achieved by using the first NPN transistor QI' and the second NPN transistor Q2'. In an embodiment, Darlington pair may be used for fast charging and slow discharging. As shown in Fig. 7, both the first NPN transistor QI' and the second NPN transistor Q2' are connected as a Darlington pair. Darlington-connected transistors Q51, Q52 charge the capacitor Cl, and the effective charging time constant is about: RrCl / (05r052). Similarly, Darlington-connected transistors Q61, Q62 discharge the capacitor Cl, and the effective discharging time constant is about: Rl-ClfPerM- In some embodiments, Darlington pair such as MMBTA13, MMBTA14 may be used. In other embodiments, an on-chip Super-Beta transistor with a base-emitter voltage drop may also be used to provide extremely high gain. In an embodiment, Sziklai pair may be used for fast charging and slow discharging. As shown in Fig. 8, both the first NPN transistor QI' and the second NPN transistor Q2' are connected as a Sziklai pair. Sziklai-connected transistors Q71, Q72 charge the capacitor Cl, and the effective charging time constant is about: Rl-Cl / fP / rfhz). Similarly, Sziklai-connected transistors Q81, Q82 discharge the capacitor Cl, and the effective discharging time constant is about: Rl'CldBsr^sz). The foregoing is only preferred embodiments of the present invention and is not intended to limit the present invention, and any modifications, equivalent substitutions, improvements and the like within the spirit and principles of the present invention are intended to be embraced by the protection scope of the present invention.

Claims

1. A non-linear capacitor, comprising:a capacitor;an input and output node for providing a charging current and a discharging current;a first amplifier device connecting the capacitor and the input and output node; anda second amplifier device connecting the capacitor and the input and output node,wherein,when the capacitor is charging, one of the first and the second amplifier devices is conducted to vary the charging current, and the capacitor is charged by the varied charging current, andwhen the capacitor is discharging, the other of the first and the second amplifier devices is conducted to vary the discharging current, and the capacitor is discharged by the varied discharging current, wherein a variation trend of the charging current is opposite to a variation trend of the discharging current.

2. The non-linear capacitor according to claim 1, wherein the first amplifier device is a first NPN transistor, the second amplifier device is a second NPN transistor, an emitter of the first NPN transistor and a base of the second NPN transistor are connected to an end of the capacitor, and a base of the first NPN transistor and an emitter of the second NPN transistor are connected to the input and output node.

3. The non-linear capacitor according to claim 2, wherein an effective charging capacitance Charge and an effective discharging capacitance Cdischarge respectively are:Cdischarge — (32 +1) Cl, and Charge = Cl / (01 +1), wherein 01 is a current gain of the first NPN transistor, and 02 is a current gain of the second NPN transistor.

4. The non-linear capacitor according to claim 2 or 3, wherein the first NPN transistor and the second NPN transistor are connected as a Darlington pair.

5. The non-linear capacitor according to claim 2 or 3, wherein the first NPN transistor and the second NPN transistor are connected as a Sziklai pair.

6. The non-linear capacitor according to claim 1, wherein the first amplifier device is a first PNP transistor, the second amplifier device is a second PNP transistor, an emitter of the first PNP transistor and a base of the second PNP transistor are connected to an end of the capacitor, and a base of the first PNP transistor and an emitter of the second PNP transistor are connected to the input and output node.

7. The non-linear capacitor according to claim 6, wherein an effective charging capacitance Charge and an effective discharging capacitance Cdischarge respectively are:Ccharge = (02 +1) Cl, and Cdischarge = Cl / (01 +1),wherein 01 is a current gain of the first PNP transistor, and 02 is a current gain of the second PNP transistor.

8. The non-linear capacitor according to claim 6 or 7, wherein the first PNP transistor and the second PNP transistor are connected as a Darlington pair.

9. The non-linear capacitor according to claim 6 or 7, wherein the first PNP transistor and the second PNP transistor are connected as a Sziklai pair.

10. The non-linear capacitor according to any preceding claim, wherein the non-linear capacitor further comprises a resistor connected to the input and output node.

11. A non-linear capacitor, comprising:a capacitor having a first end;a first transistor having an emitter and a base;a second transistor having an emitter and a base; andan input and output node for providing a charging current and a discharging current, wherein the emitter of the first transistor and the base of the second transistor are connected to the first end of the capacitor, and the base of the first transistor and the emitter of the second transistor are connected to the input and output node,wherein one of the first transistor and the second transistor is conducted and the other is cut off when the capacitor is charging, and the one of the first transistor and the second transistor is cut off and the other is conducted when the capacitor is discharging.

12. The non-linear capacitor according to claim 11,wherein the first transistor and the second transistor are NPN transistors, wherein the first transistor is conducted when the capacitor is charging, and the second transistor is conducted when the capacitor is discharging.

13. The non-linear capacitor according to claim 11, wherein the first transistor and the second transistor are PNP transistors, wherein the second transistor is conducted when the capacitor is charging, and the first transistor is conducted when the capacitor is discharging.

14. The non-linear capacitor according to any of claims 11 to 13, wherein the non-linear capacitor further comprises a resistor connected to the input and output node.5 15. The non-linear capacitor according to claim any preceding claim,wherein the first transistor and the second transistor are connected as a Darlington pair or a Sziklai pair.AMENDMENTS TO THE CLAIMS HAVE BEEN FILED AS FOLLOWSClaims1. A timing circuit that charges and discharges a capacitor at different rates of charge and discharge, comprising:a capacitor;an input and output node for providing a charging current and a discharging current;a first amplifier device connecting the capacitor and the input and output node; anda second amplifier device connecting the capacitor and the input and output node,wherein,when the capacitor is charging, one of the first and the second amplifier devices operates to vary the charging current, and the capacitor is charged by the varied charging current, andwhen the capacitor is discharging, the other of the first and the second amplifier devices operates to vary the discharging current, and the capacitor is discharged by the varied discharging current,wherein the charging current increases, as the discharging current decreases, or the charging current decreases as the discharging current increases , such that the effective charging capacitance increases while the effective discharging capacitance decreases.

2. The timing circuit according to claim 1, wherein the first amplifier device is a first NPN transistor, the second amplifier device is a second NPN transistor, an emitter of the first NPN transistor and a base of the second NPN transistor are connected to an end of the capacitor, and a07 10 24base of the first NPN transistor and an emitter of the second NPN transistor are connected to the input and output node.

3. The timing circuit according to claim 2, wherein an effective charging capacitance Ccharge and an effective discharging capacitance Cdischarge respectively are:Cdischarge = (P2 +1) C1 , and Ccharge = C1 / (p1 +1),wherein p1 is a current gain of the first NPN transistor, and p2 is a current gain of the second NPN transistor.

4. The timing circuit according to claim 2 or 3, wherein each one of the first NPN transistor and the second NPN transistor is a Darlington pair.

5. The timing circuit according to claim 2 or 3, wherein each one of the first NPN transistor and the second NPN transistor is a Sziklai pair.

6. The timing circuit according to claim 1, wherein the first amplifier device is a first PNP transistor, the second amplifier device is a second PNP transistor, an emitter of the first PNP transistor and a base of the second PNP transistor are connected to an end of the capacitor, and a base of the first PNP transistor and an emitter of the second PNP transistor are connected to the input and output node.

7. The non-linear capacitor according to claim 6, wherein an effective charging capacitance Ccharge and an effective discharging capacitance Cdischarge respectively are:Ccharge = (p2+1)C1,andCdischarge —C1 / (P1 +1),wherein pi is a current gain of the first PNP transistor, and P2 is a current gain of the second PNP transistor.

8. The timing circuit according to claim 6 or 7, wherein the first PNP transistor and the second PNP transistor are connected as a Darlington pair.

9. The timing circuit according to claim 6 or 7, wherein the first PNP transistor and the second PNP transistor are connected as a Sziklai pair.

10. The timing circuit according to any preceding claim, wherein the non-linear capacitor further comprises a resistor connected to the input and output node.07 10 2421

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