Semiconductor structures

Abstract

A semiconductor device which may be a photonic device, a laser such as a VCSEL, an LED or a sensing device comprises a semiconductor multilayer structure over a substrate which may be a GaAs or Ge substrate 110. The multilayer structure may comprise a first III-V semiconductor layer 202 which may be a buffer layer comprising a first set of III-V elements; and a strain compensation layer 204 comprising a second set of III-V elements and N, which may be a dilute nitride material; wherein the first and second sets of III-V elements respectively comprise one of: GaAs and AlAs; GaP and AlP; GaSb and AlSb. Lattice mismatch between epitaxial layers is mitigated. A VCSEL semiconductor laser (Fig. 1: 100) may comprise first and second multilayer mirrors (Fig. 1: 120, 140) with an active region (Fig. 1: 30) between them, where one or both multilayer mirrors may comprise repeated alternating layers of a first III-V layer and a strain compensation layer comprising a dilute nitride semiconductor material, or repeated units where alternate pairs of layers do not comprise a dilute nitride material. A first III-V semiconductor layer may comprise the same set of group III and group V elements as a second III_V semiconductor layer.

Description

Technical field The present application relates to semiconductor structures. The present application also relates to a semiconductor device, a sensing device, an electronic device and a vehicle. Background It is becoming increasingly desirable to form semiconductor devices from compound semiconductor materials. Compound semiconductor materials comprising elements from group III and group V of the periodic table exhibit many desirable photonic and electronic properties, which make them attractive for forming photonic semiconductor devices. Photonic semiconductor devices include optoelectronic semiconductor devices, such as a laser, light emitting diode (LED) or photodetector. Compound semiconductor materials including group III and group V elements are commonly referred to as lll-V semiconductor materials. Ill-V semiconductor materials are typically formed using epitaxial growth techniques. Such techniques can include molecular beam epitaxy (MBE) and metal organic chemical vapour deposition (MOCVD). In such techniques, group III elements and group V elements are deposited on to a substrate. Under the appropriate growth conditions, the elements combine to form a layer of Ill-V semiconductor material on the substrate. Typically, a plurality of Ill-V semiconductor layers are grown on the substrate. The resulting semiconductor structure is commonly termed an epitaxial wafer. The epitaxial wafer is subsequently processed to a plurality of semiconductor devices. 100s or 1000s of semiconductor devices can be formed from one epitaxial wafer. A common problem in the formation of an epitaxial wafer is bow and warp. Ill-V semiconductor layers are commonly grown on a substrate where there is at least some lattice mismatch between the crystal structure of the Ill-V semiconductor layer and the substrate. Furthermore, when a plurality of different Ill-V semiconductor layers are grown on top of one another, there can be lattice mismatches between several of the layers. Lattice mismatches result in strain occurring throughout the layer stack, which can lead to wafer bow or warp where the wafer begins to curve in a concave or convex manner. Bow and warp is undesirable, because semiconductor device fabrication processes are designed for flat wafers. Curvature can result in areas of the wafer being unsuitable for semiconductor device fabrication, which reduces yield. Strain engineering can minimise the presence of bow and warp in a wafer. However, some semiconductor devices, such as vertical cavity surface emitting lasers (VCSELs) commonly comprise structures with over 100 layers of 11 l-V semiconductor material. Over these many layers, there can be significant bow and warp in the resulting wafer due to lattice mismatches between the layers. It is also desirable to form epitaxial wafers on larger diameter substrates, as a greater number of semiconductor devices can be fabricated from wafers with a larger diameter. However, the effects of bow and warp due to lattice mismatches are amplified for wafers with a larger diameter. Summary It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a semiconductor structure comprising: a substrate; a semiconductor multilayer structure over the substrate. The semiconductor multilayer structure comprises: a first Ill-V semiconductor layer comprising a first set of 11 l-V elements; and a strain compensation layer comprising a second set of 11 l-V elements and N; wherein the first set of 11 l-V elements and the second set of 11 l-V elements respectively comprise one of: GaAs and AlAs; GaP and AIP; GaSb and AlSb. According to a second aspect there is provided a semiconductor structure comprising: a substrate; a first multilayer mirror comprising semiconductor material; a second multilayer mirror; and an active region between the first multilayer mirror and the second multilayer mirror. The first multilayer mirror comprises: a first IIl-V semiconductor layer; and a strain compensation layer comprising a first dilute nitride semiconductor material. According to a third aspect there is provided a semiconductor structure comprising: a substrate; and a multilayer structure over the substrate. The multilayer structure comprises: a first Ill-V semiconductor layer comprising a first set of group III elements and group V elements; and a second lll-V semiconductor layer comprising the first set of group III elements and group V elements, and further comprising N. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a VCSEL; Figure 2 is an example of a semiconductor structure; Figure 3 is another example of a semiconductor structure; Figure 4 is another example of a semiconductor structure; Figure 5 is another example of a semiconductor structure; Figures 6a and 6b are examples of wafer bow / warp and flatness results; Figures 7a and 7b are examples of reflectivity results. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25GaAs means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb). A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100> crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. Lattice matched means that two crystalline layers have the same, or similar, lattice spacing and so the second layer will tend to grow isomorphically on the first layer. Lattice constant is the unstrained lattice spacing of the crystalline unit cell. Lattice coincident means that a crystalline layer has a lattice constant which is, or is close to, an integer multiple of the previous layer so that the atoms can be in registry with the previous layer. Lattice mismatch is where the lattice constants of two adjacent layers are neither lattice matched nor lattice coincident. Such mismatch introduces elastic strain into the structure, particularly the second layer, as the second layer adopts the in-plane lattice spacing of the first layer. The strain is compressive where the second layer has a larger lattice constant and tensile where the second layer has a smaller lattice constant. Where the strain is too great the structure relaxes to minimise energy through defect generation, typically dislocations, known as slip, or additional interstitial bonds, each of which allows the layer to revert towards its lattice constant. The strain may be too great due to a large lattice mismatch or due to an accumulation of small mismatches over many layers. A relaxed layer is known as metamorphic, incoherent, incommensurate or relaxed, which terms are also commonly interchangeable. A pseudomorphic system is one in which a single-crystal thin layer overlies a singlecrystal substrate and where the layer and substrate have similar crystal structures and nearly identical lattice constants. In a pseudomorphic structure the in-plane lattice spacing of the thin layer adopts the in-plane lattice constant of the substrate and is therefore elastically strained, either compressively where the layer has a larger lattice spacing than the substrate or tensilely where the layer has a smaller lattice spacing than the substrate. A pseudomorphic structure is not constrained in the out-of-plane direction and so the lattice spacing of the thin layer in this direction may change to accommodate the strain generated by the mismatch between lattice spacing. The thin layer may alternatively be described as “coherent”, “commensurate”, “strained” or “unrelaxed”, which terms are often used interchangeably. In a pseudomorphic structure all the layers adopt the lattice spacing of the substrate in their respective in-plane lattice spacing. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function. Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. Examples according to the present disclosure provide a semiconductor structure that comprises a substrate and a semiconductor multilayer structure over the substrate. The semiconductor multilayer structure comprises a first 11 l-V semiconductor layer comprising a first set of IIl-V elements; and a strain compensation layer comprising a second set of 11 l-V elements and N. In some examples, the strain compensation layer comprises dilute amounts of N and is a dilute nitride material. Dilute nitrides are a class of 11 l-V semiconductor material, which contain a small concentration of N atoms. The nitrogen atoms are typically present in the 11 l-V semiconductor material with a concentration of less than 5% of the group V materials. Dilute nitrides have been widely used in the active regions of photonic semiconductor devices, such as VCSELs, edge emitting lasers (EEL) and PhotoDetectors. Incorporating small amounts of N into a lll-V semiconductor active region results in a reduction of the bandgap and this shifts the operational wavelength of the semiconductor device to longer wavelengths. This is desirable in many applications involving long wavelength (>900nm) semiconductor emitters and detectors. Such semiconductor devices are useful in many applications, such as facial recognition systems. The use of dilute nitride semiconductor materials, has, however been primarily applied for use in the active region of semiconductor devices. Examples, according to the present disclosure provide a dilute nitride semiconductor material layer, which is outside of the active region and is present in a semiconductor multilayer structure, which in some examples may be incorporated into a DBR for a VCSEL. The incorporation of dilute nitride material in a 11 l-V semiconductor material also acts to decrease the lattice constant of the material. Incorporating dilute nitride into a semiconductor material can thus act to reduce lattice mismatches between some semiconductor materials, reducing accumulated strain in a layer stack and reduce the effect of bow and warp. The reduction of strain in a 11 l-V epitaxial stack can also allow the formation of thicker structures, enabling more 11 l-V material to be grown on a substrate, which may have not previously been achievable due to accumulated strain. In one example, the dilute nitride based strain compensation may allow the formation of multijunction VCSEL structures, without significant bow and warp in the final wafer. For example, a semiconductor multilayer structure may comprise a first lll-V semiconductor layer and a second lll-V semiconductor layer. The material of the second lll-V semiconductor layer may comprise a larger lattice constant than the material of the first lll-V semiconductor layer, resulting in lattice mismatch between the first lll-V semiconductor layer and a second lll-V semiconductor layer. For example the first lll-V semiconductor layer and a second lll-V semiconductor layer may respectively comprise one of: GaAs and AlAs; GaP and AIP; and GaSb and AlSb. In examples according to the present disclosure, N is added to the second lll-V semiconductor layer in dilute amounts, which reduces the lattice constant of the material. This affect can reduce the lattice mismatch between the first and second lll-V semiconductor layers and thereby reduce the affects of total strain in a semiconductor multilayer structure. In examples according to the present disclosure, the layer comprising the dilute nitride material may thus be referred to as a ‘strain compensation layer’, where the addition of the dilute nitride material acts to compensate or eliminate strain in a semiconductor multilayer structure. In some examples, the semiconductor multilayer structure according to examples of the present disclosure may be incorporated into a layer stack comprising many semiconductor layers. For example, the semiconductor multilayer structure may be incorporated into a semiconductor mirror for a VCSEL. In such examples, the bow and warp, which is a result of accumulated strain of the mismatched layers stack for the VCSEL can be reduced. Examples according to the present disclosure may thus enable the formation of epitaxial wafers with reduced bow and warp, which increases yield and allows the incorporation of 11 l-V semiconductor material on to large diameter substrates. Figure 1 is an example of a vertical cavity surface emitting laser (VCSEL) 100. VCSEL 100 comprises a substrate 110. In one example, the substrate may comprise GaAs or Ge. VCSEL 100 further comprises a lower mirror in the form of a lower distributed Bragg reflector (DBR) 120. Lower DBR 120 is formed of a stack of 11 l-V semiconductor layers 122. The DBR is formed of a repeating period of a combination of lll-V semiconductor layers with differing refractive indices. The differences in refractive indices results in the lower DBR 120 having reflective properties to light over a region of the electromagnetic spectrum. In one example, lower DBR comprises a period of GaAs and AI(Ga)As layers, which are repeated a plurality of times to form the lower DBR 120. VCSEL 100 further comprises active region 130. Active region 130 comprises a region of the VCSEL where electrons and holes recombine to result in the emission of light 170. In some examples, active region 130 may comprise a quantum structure, such as a quantum well, a quantum dot or a combination thereof. In some examples, the active region 130 may comprise a dilute nitride semiconductor material. In some examples, the active region may output light at long wavelengths greater than 900 nm. In some examples, the active region 130 may output light greater than 1300 nm, for example, 1380 nm. VCSEL 100 further comprises an upper mirror in the form of upper DBR 140. In a similar manner to that described above, upper DBR comprises a stack of lll-V semiconductor materials for reflecting light. In one example, upper DBR 140 may thus similarly comprise alternating layers of GaAs and AI(Ga)As. The reflectivity of the upper DBR may be less than the reflectivity of the lower DBR 120. For example, the upper DBR 140 may be thinner than the lower DBR 120. As such, a portion of the light reflected from within the cavity formed between the lower and upper DBR 120, 140 passes out of the upper DBR 140. VCSEL 100 further comprises p contacts 152, 154 and n contact 160 for the application of a current to VCSEL 100. When a current is applied to the contacts 152, 154, 160, charge carriers are injected into the VCSEL 100 and recombine in the active region 130. The recombination results in the emission of light 170 from VCSEL 100. VCSEL 100 is fabricated from an epitaxial wafer. As such all of the semiconductor layers used to form the VCSEL are grown on substrate 110. The epitaxial wafer used to form the VCSEL 100 comprises 100s of layers of lll-V semiconductor material. This is primarily due to the lower and upper DBRs 120,140. For example, the lower DBR can comprise 60 repeats of a GaAs / AI(Ga)As period and the upper DBR can comprise 40 repeats of a GaAs / AI(Ga)As period. The alternating layers of GaAs and AI(Ga)As have a small lattice mismatch, which over many layers can build up and result in the epitaxial wafer exhibiting significant bow and warp. This effect is amplified when the epitaxial layers are grown on larger diameter substrates of 8 or 12 inches. Figure 2 illustrates a semiconductor structure 200. In one example, lower DBR 120 and / or upper DBR 140 of VCSEL 100 may comprise the semiconductor structure 200. In such examples, semiconductor structure 200 can significantly reduce the bow and warp of an epitaxial wafer for forming VCSEL 100. Semiconductor structure 200 comprises substrate 110, which in the illustrated example of Figure 2 comprises GaAs. In other examples, substrate 110 may comprise Ge. Semiconductor structure 200 further comprises a buffer layer 202 comprising GaAs. In some examples, structural defects may be present on substrate 110. Buffer layer 202 may be epitaxially grown on the surface of substrate 110 to smooth out and reduce the impact of such defects of the grown epitaxial wafer. Semiconductor structure 200 further comprises a first period 220 on the buffer layer 202. The period 220 may be repeated N times to, for example, form a DBR for a VCSEL. Period 220 comprises a strain compensation layer 204 comprising AI(Ga)As with a dilute concentration of N atoms to form AI(Ga)AsN. In one example, the AI(Ga)AsN layer may comprise a N concentration of less than 5% of the group V material. Strain compensation layer 204 thus comprises a dilute nitride semiconductor material. Period 220 further comprises a second lll-V semiconductor material 206 comprising GaAs. As described above, the DBR structure for a VCSEL can result in an epitaxial wafer exhibiting bow or warp because of small lattice mismatches that exist between the layers forming the DBR. For example, pairs of GaAs and AI(Ga)As are commonly stacked on top of one another to form a DBR. AI(Ga)As can have a slightly larger lattice constant than GaAs. As such, the small lattice mismatch present between these materials can result in strain, and bow or warp being exhibited in the resulting epitaxially grown wafer. In particular, DBRs used in long wavelength (>900nm) emitters can comprise over 100 layers and are typically thick structures ranging from 9 pm to 15 pm. Over this thickness range significant strain and thus bow and warp can be exhibited in the resulting epitaxially grown structure. In such emitters, the strain problem is further exacerbated by the incorporation of relatively high concentrations of Al into the AI(Ga)As layers to provide high refractive index contrast with the GaAs material to achieve good reflectivity performance. The higher the Al content, the larger the lattice mismatch with the GaAs layers of the DBR and the commonly used GaAs substrate for forming a VCSEL. The Al content for the AI(Ga)As layers commonly exceeds 85% to provide the suitable refractive index contrast with GaAs. The AI(Ga)As material comprises a lower refractive index than the GaAs material. Examples according to the present disclosure thus provide a strain compensation layer where N is incorporated into the AI(Ga)As material in dilute amounts to reduce the lattice constant of the material and thereby reduce the lattice mismatch with GaAs. This reduces the strain in the structure and thereby reduces the effect of bow and warp. Examples according to the present disclosure may thus incorporate N in dilute amounts into the lower refractive index material for a period for forming a DBR. The composition of the layers forming a DBR are carefully designed such that the DBR reflects light at the desired wavelength for the VCSEL. As described above, the refractive indices of the layers forming a DBR are selected to reflect light at the desired wavelength. In other examples, it has been observed that the incorporation of N in dilute amounts reduces the bandgap of a material, which in turn increases the refractive index of the material. In examples according to the present disclosure, however, it has been observed that the incorporation of dilute nitride material in a DBR does not have a significant effect on the reflectivity of a DBR, compared to a corresponding structure without the dilute nitride material, as will be described in more detail below with respect to Figures 7a-b. As such, dilute nitride material can be conveniently incorporated into a DBR for a VCSEL to reduce strain and maintain good reflectivity characteristics for a desired wavelength range. Figure 3 illustrates a semiconductor structure 300. In one example, lower DBR 120 and / or upper DBR 140 of VCSEL 100 may comprise the semiconductor structure 300. Semiconductor structure 300 comprises elements in common with semiconductor structure 200. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor structure 300 comprises a period 320 comprising strain compensation layer 204 and first GaAs layer 206. Period 320 further comprises second GaAs layer 208 and AI(Ga)As layer 210. As described above, commonly DBR structures for a VCSEL are formed by layering pairs of GaAs and AI(Ga)As layers to form a reflector or mirror. Referring briefly to Figure 2, when a DBR is formed by repeating the period 220 N times, all of the AI(Ga)As content of the DBR comprises dilute nitride material, such that the DBR is formed of GaAs and AI(Ga)AsN. However, referring again to Figure 3, in some examples, a DBR may be formed by repeating period 320 N times, where only half of the AI(Ga)As content of the DBR comprises dilute nitride material. Period 320 comprises strain compensation layer 204 comprising AI(Ga)AsN and AI(Ga)As layer 210. Period 320 further comprises first and second GaAs layers 206,208. Thus, within period 320, only half the AI(Ga)As content of the period comprises dilute nitride material. As such, in a DBR formed from repeating period 320 N times, only half of the AI(Ga)As content may comprise dilute nitride material. In such examples, bow and warp of an epitaxial wafer comprising the period 320 repeated N times may be reduced where only half of the AI(Ga)As content comprises dilute nitride material. As illustrated in Figure 3, the thickness of the strain compensation layer 204 and the AI(Ga)As layer 210 may be substantially the same, such that about half of the AI(Ga)As content of period 320 comprises dilute nitride material. However, in other examples, the thickness of the strain compensation layer 204 and / or the AI(Ga)As layer 210 may be varied to vary the content of the AI(Ga)As in the period 320 that comprises dilute nitride material. In other words, a semiconductor mirror formed of period 320 may comprise a quantity of AI(Ga)AsN material that is less than or equal to a quantity of AI(Ga)As material. In some examples a semiconductor mirror may comprise period 320 repeated N times, where one or more of the N repeats are interspersed with one or more semiconductor layers that do not comprise dilute nitride material. For example, a two layer structure comprising GaAs and AI(Ga)As may be inserted between two of the periods 320. In such examples, the semiconductor mirror may still comprise reduced bow and / or warp. Thus in a similar manner to that described above, a semiconductor mirror according to examples of the present disclosure may comprise a quantity of AI(Ga)AsN material that is less than or equal to a quantity of AI(Ga)As material. Furthermore, in some examples, a semiconductor mirror may comprise more layers of AI(Ga)As than layers of AI(Ga)AsN. Figure 4 illustrates a semiconductor structure 400. In one example, lower DBR 120 and / or upper DBR 140 of VCSEL 100 may comprise the semiconductor structure 400. Semiconductor structure 400 comprises elements in common with semiconductor structures 200, 300. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor structure 400 comprises a period 420 comprising strain compensation layer 204 comprising AI(Ga)AsN. Period 420 further comprises first AI(Ga)As layer 410 and second AI(Ga)As layer 404. In a similar manner to that described above for semiconductor structure 300, in some examples, a portion of the total AI(Ga)As content of the period 420 comprises dilute nitride material. Furthermore, period 420 may thus comprise more AI(Ga)As layers than AI(Ga)AsN layers. In the illustrated example of Figure 4, period 420 comprises three layers that comprise AI(Ga)As, where only strain compensation layer 204 comprises dilute nitride material. As such, in some examples, only a fraction of the AI(Ga)As content of period 420 comprises dilute nitride material. Thus, in some examples, where period 420 is repeated N times to form a DBR for a VCSEL, about a third of the AI(Ga)As content of said DBR may comprise dilute nitride material. As illustrated in Figure 4, the first and second AIGaAs layers 410, 404 are disposed either side of the strain compensation layer 204. During fabrication, first AI(Ga)As layer 410 may be grown on buffer layer 202 by activating suitable sources to epitaxially grown AI(Ga)As layer 410. To grow strain compensation layer 204, the sources to grow the AI(Ga)As layer 410 may remain active and a N source may be activated to incorporate a dilute amount of N into the AI(Ga)As material. To grow the second AI(Ga)As layer 404, the sources to grow the AI(Ga)As material may remain active and the N source may be deactivated and suspended from outputting N. In this way, first AIGaAs layer 410, strain compensation layer 204 and second AIGaAs layer 404 may be grown in a continual manner to maintain the speed and efficiency for the formation of semiconductor structure 400. As illustrated in Figure 4, the thickness of the strain compensation layer 204 and the AI(Ga)As layers 404, 410 may be substantially the same, such that about a third of the AI(Ga)As content of period 420 comprises dilute nitride material. In other words, a mirror formed of period 420 may comprise a quantity of AI(Ga)AsN material that is less than or equal to half a quantity of AI(Ga)As material. However, in other examples, the thickness of the strain compensation layer 204 and / or the AI(Ga)As layers 404, 410 may be varied to vary the content of the AI(Ga)AsN in the period 420 that comprises dilute nitride material. Examples according to the present disclosure thus further provide a semiconductor structure comprising a substrate and a multilayer structure over the substrate. The multilayer structure comprises a first lll-V semiconductor layer comprising a first set of group III elements and group V elements; and a second lll-V semiconductor layer comprising the first set of group III elements and group V elements, and further comprising N. The N may be included in the second lll-V semiconductor layer in dilute amounts, which for example, is incorporated with a concentration of less than 5% of the group V material. The dilute nitride material may thus be included in a mirror where a portion of the total content of a material for forming the mirror comprises N in dilute amounts. For example, GaAs and AI(Ga)As may be selected for forming a mirror that can provide appropriate reflective properties for a desired wavelength. Incorporating dilute concentrations of N into a proportion less than the total sum of the AI(Ga)As material may provide appropriate strain compensation effects and thus reduce the effect of bow and warp. For example, half or a third of the AI(Ga)As material may comprise dilute nitride material. The mirror may thus comprise a first period comprising AIGaAs and a second period comprising AIGaAsN. Although examples of the present disclosure have been described with reference to incorporating dilute amounts of N into a As material system, incorporating dilute amounts of N into other lll-V semiconductor material systems may also provide strain compensation effects. For example, N may be incorporated into Sb or P material systems to provide similarly described strain compensation effects. For example, the incorporation of N in dilute amounts for strain compensation may be applied to any suitable material comprising a binary, ternary, quaternary etc. alloy comprising group III elements selected from Al, Ga or In and group V elements selected from N, P or As. Furthermore, a mirror formed in these material systems may further comprise a lll-V semiconductor material where less than a total sum of the lll-V semiconductor material comprises dilute nitride material in a similar manner to that described above. In some examples, N may be incorporated into a material comprising a larger lattice constant than another semiconductor material, where the difference in lattice constants is less than about 0.5 A. The incorporation of N in dilute amounts into the material with the larger lattice constant may act to reduce the lattice mismatch between the two materials and not substantially affect the optical properties of the material, such as refractive index. In some examples, incorporating N into a material where a difference with another material is greater than 0.5 A may reduce the lattice mismatch, but result in N being incorporated in such a way that the optical properties, such as refractive index are substantially affected. In some examples, this may be undesirable, as this may involve significant redesign of the properties and composition of a DBR. However, in other examples, incorporating N into a multilayer structure for a DBR in such a way that the optical properties of the layer are adjusted may be desirable to, for example, provide a way of adjusting the reflectivity properties of a DBR. In some examples, N may be incorporated into a material comprising a larger lattice constant than another semiconductor material, where the difference in lattice constants is less than about 0.25 A. In some examples, N may be incorporated into a material comprising a larger lattice constant than another semiconductor material, where the difference in lattice constants is less than about 0.1 A. Figure 5 illustrates a semiconductor structure 500. Semiconductor structure 500 is an example of an epitaxial wafer layer stack for forming a VCSEL. Semiconductor structure 500 comprises elements in common with VCSEL 100 and semiconductor structures 200, 300, 400. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality to that described above. Semiconductor structure 500 comprises a lower DBR 120 over GaAs substrate 110. Lower DBR 120 is formed of up to 40 repeats of period 420. Period 420 comprises corresponding layers to period 420 described above with respect to Figure 4, where the order of the layers has been reversed. Lower DBR 120 thus comprises strain compensation layer 204. In some examples, about one third of the AI(Ga)As content of the lower DBR 120 may thus comprise dilute nitride material. Semiconductor structure 500 further comprises active region 130 positioned over the lower DBR 120. As described above, active region 130 may comprise one or more layers comprising quantum structures, such as quantum wells or quantum dots. Said layers may be separated by suitable barrier layers. Semiconductor structure 500 further comprises an upper DBR 140 over the active region 130. Upper DBR 140 is formed of up to 30 repeats of period 520. Period 520 comprises a first upper DBR AI(Ga)As layer 506, an upper strain compensation layer 508, a second upper DBR AI(Ga)As layer 510 and an upper DBR GaAs layer 512. Period 520 may thus comprise corresponding layers to period 420. The dilute nitride material incorporated into upper DBR 140 may further reduce strain and bow and warp in semiconductor structure 500. In other examples, only one of upper DBR 140 or lower DBR 120 may comprise dilute nitride material. For example, only one of upper DBR 140 or lower DBR 120 may comprise one of the periods 220, 320 or 420 described above. In other examples, both upper DBR 140 and lower DBR 120 may comprise dilute material, but in different configurations, such as in different quantities, thicknesses, layer order etc. For example, upper DBR 140 and lower DBR 120 may comprise any combination of periods 220, 320 or 420 described above. Semiconductor structure 500 is thus an example of a layer stack of an epitaxial wafer for forming a VCSEL. One or more VCSELs may thus be fabricated from the semiconductor structure 500. Figures 6a and 6b are flatness results of DBR structures. Figure 6a illustrates a flatness result 600a obtained for a DBR structure formed of a period comprising a GaAs layer and an AlAs layer. The DBR was formed by repeating the period 60 times. Result 600a illustrates that the DBR structure comprises a bow of 143 pm and a total warp of 275 pm. These values represent a significant bow and warp and are undesirable. Figure 6b illustrates a flatness result obtained for a DBR structure formed of a period corresponding to period 420 described above with respect to Figure 4. A DBR structure was formed by repeating the period 60 times. Thus, about one third of the AlAs content of the DBR structure comprised dilute nitride material. Result 600b illustrates that the DBR structure comprises a bow of 11 pm and a total warp of 30 pm. The inclusion of dilute nitride material into a DBR structure can thus significantly reduce the bow and warp of an epitaxial wafer for forming a DBR, which increases wafer yield. Figures 7a-b illustrate reflectivity results. Figure 7a illustrates reflectivity result 700a obtained from a DBR formed from periods comprising GaAs and AlAs. Figure 7b illustrates reflectivity result 700b obtained from a DBR from periods comprising GaAs and AlAsN. The reflectivity result 700b was obtained with a DBR structure formed of a period corresponding to period 220 described above with respect to Figure 2. As illustrated, the stop band width (SB Width) of result 700a from the GaAs / AIAs DBR is 125.2 nm and the SB Width of the result 700b from the GaAs / AIAsN DBR is 125.4 nm. There is thus only a 0.157% change between the SB Width of the two results, which is an indication that the refraction of index contrast between the layers of the two DBRs is substantially the same. As further illustrated, result 700a comprises a peak reflectivity wavelength of 1309 nm and result 700b comprises a peak reflectivity wavelength of 1299 nm. This difference in peak reflectivity wavelength is ~10 nm and is not considered significant. Small changes in the peak reflectivity can be attributed to run-run variations in the epitaxial growth process. It is hypothesized that the effect of the dilute incorporation of N into a lll-V semiconductor material such as AlAs to result in a reduced lattice constant, but substantially no change in the optical properties, such as the refractive index of the material is due to the fabrication method for incorporating the N into the semiconductor material in dilute amounts. Typically, As-based DBRs are grown at relatively high temperatures of greater than 600 °C, whereas the active region of a VCSEL structure is grown at colder temperatures of less than 500 °C. The incorporation of dilute nitride material in active regions structures at such temperatures typically results in a change in the optical properties of the structures, such as, by reducing the bandgap of the structure. However, it is hypothesized that incorporating N into a 11 l-V semiconductor material at a higher growth temperature, such as a temperature typically associated with fabrication of a As-based VCSEL, results in the lattice constant of the Ill-V semiconductor material being reduced, but does not result in the refractive index of the semiconductor material being substantially affected, or being affected to the extent that the change in lattice constant would typically result in. Examples according to the present disclosure have described the effect of dilute nitride material to relieve strain in a GaAs material system. However, in other examples, N may be incorporated in dilute amounts into other 11 l-V material systems to also result in strain compensation, as described above. For example, strain compensation may occur in a similar manner in a GaP material system or a GaSb material system. For example, there is lattice mismatch between GaP and AIP. N may thus be incorporated into AIP in dilute amounts to reduce the lattice mismatch between GaP and AIP. Similarly, there is lattice mismatch between GaSb and AlSb. N may thus be incorporated into AlSb in dilute amounts to reduce the lattice mismatch between GaSb and AlSb. The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a photonic semiconductor device. In some examples the photonic semiconductor device may comprise one of: a laser, a laser diode, a vertical cavity surface emitting laser (VCSEL), a multi-junction VCSEL, an edge emitting laser (EEL), a photodetector, a photodiode and a PIN diode. The present disclosure further provides a sensing device comprising a semiconductor device according to examples of the present disclosure. In some examples the sensing device may comprise a 3D sensing device, such as for use in a facial recognition system or for use in a light detection and ranging (LiDAR) system. In some examples the sensing device may comprise a proximity sensor. In some examples the sensing device may comprise a sensing device for use in a health monitoring device or system, such as a spectrometer. In some examples the sensing device may comprise a camera. The present disclosure further provides an electronic device comprising a sensing device according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console, or similar. In some examples the electronic device may comprise a comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar. The present disclosure further provides a vehicle comprising a sensing device according to examples of the present disclosure. In some examples the vehicle may comprise an automotive vehicle such as a car, a van, a heavy goods vehicle (HGV), a bus, a motorbike, or similar. In some examples the vehicle may comprise an aviation vehicle, such as an aeroplane, helicopter, or similar. In some examples the vehicle may comprise an aeronautical vehicle, such as, a boat, ship or similar. It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A semiconductor structure comprising:a substrate;a semiconductor multilayer structure over the substrate comprising:a first lll-V semiconductor layer comprising a first set of lll-V elements; anda strain compensation layer comprising a second set of lll-V elements and N;wherein the first set of lll-V elements and the second set of lll-V elements respectively comprise one of:GaAs and AlAs;GaP and AIP;GaSb and AlSb.

2. The semiconductor structure according to claim 1 wherein the semiconductor multilayer structure further comprises a third lll-V semiconductor layer; and wherein the third lll-V semiconductor layer does not comprise N.

3. The semiconductor structure according to claim 2, wherein the third lll-V semiconductor layer comprises the first set of lll-V elements.

4. The semiconductor structure according to claim 2 or 3 wherein the first lll-V semiconductor layer comprises GaAs, the strain compensation layer comprises AlAsN and the third lll-V semiconductor layer comprises GaAs.

5. The semiconductor structure according to claim 2 wherein the first lll-V semiconductor material comprises GaAs, the strain compensation layer comprises AlAsN and the third lll-V semiconductor layer comprises AlAs.

6. The semiconductor structure according to any of claims 2-5 wherein the semiconductor multilayer structure further comprises a fourth lll-V semiconductor layer; and wherein the fourth lll-V semiconductor layer does not comprise N.

7. The semiconductor structure according to claim 6, when dependent on claim 4 or 5, wherein the fourth lll-V semiconductor layer comprises AlAs.

8. The semiconductor structure according to any preceding claim wherein the semiconductor multilayer structure comprises a period of semiconductor layers repeated a plurality of times; and wherein the period comprises the first lll-V semiconductor layer and the strain compensation layer.

9. The semiconductor structure according to claim 8, when dependent on claim 2, wherein the period further comprises the third lll-V semiconductor layer.

10. The semiconductor structure according to claim 9, when dependent on claim 6, wherein the period further comprises the fourth lll-V semiconductor layer.

11. The semiconductor structure according to any preceding claim wherein the multilayer structure comprises a semiconductor material comprising the second set of lll-V elements and a dilute nitride semiconductor material comprising the second set of lll-V elements and N and wherein a quantity of the dilute nitride semiconductor material is less than or equal to a quantity of the semiconductor material.

12. The semiconductor structure according to claim 11 wherein the quantity of the dilute nitride semiconductor material is less than half the quantity of the second lll-V semiconductor material.

13. The semiconductor structure according to any of preceding claim further comprising a mirror comprising the semiconductor multilayer structure.

14. The semiconductor structure according to claim 13 wherein the mirror comprises a distributed Bragg reflector, DBR.

15. A semiconductor structure comprising:a substrate;a first multilayer mirror comprising semiconductor material;a second multilayer mirror; andan active region between the first multilayer mirror and the second multilayer mirror; andwherein the first multilayer mirror comprises:a first lll-V semiconductor layer; anda strain compensation layer comprising a first dilute nitride semiconductor material.

16. The semiconductor structure according to claim 15 wherein the first multilayer mirror is below the active region.

17. The semiconductor structure according to claim 15 or 16 wherein the second multilayer mirror comprises a second dilute nitride semiconductor material.

18. The semiconductor structure according to any preceding claim wherein the substrate comprises GaAs or Ge.

19. A semiconductor structure comprising:a substrate; anda multilayer structure over the substrate, the multilayer structure comprising:a first 11 l-V semiconductor layer comprising a first set of group III elements and group V elements; anda second 11 l-V semiconductor layer comprising the first set of group III elements and group V elements, and further comprising N.

20. A semiconductor structure according to claim 19 wherein the multilayer structure comprises a semiconductor mirror.

21. A semiconductor device comprising the semiconductor structure according to any of claims 1-20.

22. A sensing device comprising semiconductor device according to claim 21.

23. An electronic device comprising the semiconductor device according to claim 21 or the sensing device according to claim 22.

24. A vehicle comprising the semiconductor device according to claim 21 or the sensing device according to claim 22.

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