High electron mobility transistors

Abstract

A high electron mobility transistor (HEMT) 100 comprises a III-N channel layer 110 which may comprise GaN; a gate contact 140 on a first side 112 of the channel layer; and at least one of a source con

Description

Technical field The present application relates to a high electron mobility transistor (HEMT), a semiconductor structure, a method of forming a HEMT and a method of forming a semiconductor structure. Background There is increasing interest to form semiconductor devices such as transistors from III-N semiconductor materials. Ill-N semiconductor materials, such as GaN, possess desirable electronic properties, such as a high breakdown voltage and high critical electric field. A popular semiconductor device formed from lll-N semiconductor materials, such as GaN, is the high electron mobility transistor (HEMT). A HEMT comprises a two-dimensional electron gas (2DEG) for carrier flow between the source and the drain, which is attractive due to the high electron mobility of the 2DEG. The GaN HEMT has found use in RF and power applications. Summary. In particular, the GaN HEMT is an attractive semiconductor device for RF applications. 5G and 6G communications protocols involve the use of higher frequency signals. In some applications, a GaN HEMT is better suited to the higher frequency signals compared to other devices, such as, Si MOSFETs. For an RF semiconductor device, parasitic capacitances are a common problem. Parasitic capacitances can result in signal loss, voltage handling reduction and nonlinearities. Gate to source capacitance (Cgs), gate to drain capacitance (Cgd), and source to drain capacitances (Csd) all contribute to the parasitic capacitance problems. RF semiconductor devices and RF modules are therefore carefully designed to limit parasitic capacitance effects. However, as RF communications protocols move to higher frequency signals, the determinantal impact of parasitic capacitances becomes harder to combat using conventional techniques. In particular, parasitic capacitances due to routing proximity, parasitic resistances due to long routing and reduced device width, and parasitic inductances due to long routing, can all be difficult to combat in high frequency applications. Furthermore, whilst the formation of the 2DEG is desirable, it commonly results in a HEMT exhibiting depletion mode (D-mode) behaviour where a negative bias voltage is applied to the HEMT in order to turn the HEMT to the non-conducting ‘off’ state. The D-mode behaviour of a HEMT is typically not as desirable as an enhancement mode (E-mode) operation, where a transistor is normally in the ‘off’ state and a positive bias voltage is applied to turn the transistor to the conducting ‘on’ state. One way to form an E-mode HEMT is to form p-type lll-N material between the gate contact and barrier layer. However, forming p-type lll-N material commonly involves the use of a Mg dopant. It is challenging to introduce Mg into lll-N material in a consistent and controllable manner due to Mg diffusion and the high activation energy of Mg. As such, an E-mode HEMT has not found widespread use in many applications due to the challenges associated with working with Mg. It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques. According to a first aspect there is provided a high electron mobility transistor (HEMT) comprising: a channel layer; a gate contact on a first side of the channel layer; and at least one of a source contact and a drain contact on a second side of the channel layer, opposite the first side. The channel layer is between the gate contact and the at least one of the source contact and the drain contact. The channel layer comprises a channel for lateral carrier flow across the channel layer between the source contact and the drain contact. According to a second aspect there is provided a semiconductor structure comprising the HEMT according to the first aspect and a handle wafer bonded to the HEMT. According to a third aspect there is provided a radio frequency, RF, module comprising the HEMT according to the first aspect or the semiconductor structure according to the second aspect. According to a fourth aspect there is provided a electronic device comprising the HEMT according to the first aspect, the semiconductor structure according to the second aspect or the RF module according to the third aspect. According to a fifth aspect there is provided a method of forming a HEMT comprising: forming a channel layer; forming a gate contact on a first side of the channel layer; and forming at least one of a source contact and a drain contact on a second side of the channel layer, opposite the first side. The channel layer is between the gate contact and the at least one of the source contact and the drain contact. The channel layer comprises a channel for lateral carrier flow across the channel layer between the source contact and the drain contact. According to a sixth aspect there is provided a method of forming a semiconductor structure comprising the method according to the fifth aspect and further comprising: bonding the HEMT to a handle wafer. According to a seventh aspect there is provided a HEMT comprising: a channel layer configured to laterally conduct a current across the channel layer; a first contact on a first side of the channel layer; and a second contact on a second side of the channel layer, opposite the first side. The channel layer is between the first contact and the second contact. Brief description of the drawings For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a HEMT; Figure 2 is an example of a semiconductor structure; Figures 3a-g are examples of process steps in a method of manufacturing a semiconductor structure; Figure 4 is an example of a HEMT; Figure 5 is an example of a HEMT; Figure 6 is an example of a HEMT; Figure 7 is an example of a HEMT; Figure 8 is an example of a semiconductor structure; Figures 9a-g are examples of process steps in a method of manufacturing a semiconductor structure; Figure 10 is an example of a HEMT; Figure 11 is an example of a HEMT; Figure 12 is an example of a HEMT; Figure 13 is a flow chart illustrating process steps in a method of manufacturing a HEMT. Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition. A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus AlojsGaAs means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As. Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type. A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided. A fully depleted porous layer means a layer in which there are no charge carriers. Where a device is described it should be understood that it will typically be formed on a circular substrate waferof 4” (100mm), 6” (150mm), 8” (200mm), 12” (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer. Throughout the present disclosure corresponding elements in the Figures are labelled with corresponding reference numerals. Examples according to the present disclosure provide a HEMT that comprises a channel layer, a first contact on a first side of the channel layer, a second contact on a second side of the channel layer, opposite the first side, such that the channel layer is between the first contact and the second contact. Examples according to the present disclosure thus provide a HEMT where each side of the channel layer of the HEMT may be accessed in order to form electrical contacts, such as a source, drain or gate on either side of the channel layer. In one example, forming the electrical contacts on each side of the channel layer may reduce the parasitic capacitance issue described above. For example, the parasitic issues described above can arise, in conventional solutions, due to the gate, source and drain contacts being located on the same side of a HEMT. This restricts contact and routing design, which can result in the development of parasitics. Examples according to the present disclosure present a HEMT where the gate, source and drain contacts can be located on either side of the HEMT. In this way, the contacts and routing can thus be configured accordingly to help reduce parasitic capacitances that can arise between the contacts of the HEMT and from the routing to and from the HEMT. Examples according to the present disclosure further provide a HEMT comprising a first gate contact; a second gate contact and a channel layer between the first gate contact and the second gate contact. The ability to access either side of the channel layer enables two gate contacts to be formed on either side of the channel layer. One gate contact may be used to set the threshold voltage of the HEMT and the other may be used to control current conduction through the HEMT. For example, a first gate contact may be negatively biased such that the formation of the 2DEG is interrupted to prevent current flow between the source contact and the drain contact of the HEMT. A second gate contact may then be used to alter the electric field in the channel layer and enable the formation of the 2DEG in the channel layer, thus effectively counteracting the negative bias applied to the first gate contact. In this way, the HEMT according to examples of the present disclosure may exhibit E-mode behaviour. In other examples, however, the voltage applied to the first gate contact may be adjusted accordingly to operate the HEMT as an E-mode or D-mode HEMT, where the voltage applied to the first gate contact can set the threshold voltage of the HEMT. In this way, an E-mode HEMT can be formed without the issues associated with doping GaN p-type with Mg. Examples according to the present disclosure further provide a method of manufacturing a HEMT where each side of the channel layer can be accessed for fabrication of contacts thereon. Figure 1 is an example of a HEMT 100 according to examples of the present disclosure. HEMT 100 comprises a channel layer 110 and a barrier layer 120. The barrier layer 120 may comprise a material configured to induce the formation of a two-dimensional electron gas (2DEG) 130 in the channel layer 110, as one skilled in the art will readily understand. For example, the channel layer and barrier layer may comprise lll-N semiconductor material, which results in the formation of the 2DEG 130 in the channel layer 110. In one example, the channel layer comprises GaN and the barrier layer comprises AIGaN. Current conduction between the drain contact 150 and source contact 160 may thus occur through the 2DEG 130. As illustrated in Figure 1, the 2DEG 130 may be formed under the gate contact 140. The 2DEG 130 thus forms a channel in the channel layer 110, which is configured to permit lateral carrier flow between the source contact 160 and drain contact 150. HEMT 100 may thus comprise a lateral HEMT or lateral semiconductor device where carrier flow occurs laterally via the 2DEG 130 across the channel layer 110. HEMT 100 further comprises a gate contact 140 on a first side 112 of the channel layer 110. HEMT 100 further comprises a drain contact 150 and a source contact 160 located on a second side 114 of the channel layer 110. Although gate contact 140, source contact 160 and drain contact 150 are illustrated as being directly in contact with the channel layer 110, in some examples, one or more intermediary layers or material may be present between anyone of the gate contact 140, source contact 160 and drain contact 150, and the channel layer 110. For example, at least a portion of barrier layer 120 may be present between the channel layer 110 and the source contact 160 and drain contact 150, and the source contact 160 and drain contact 150 may be considered to be on the second side 114 of the channel layer 110. In another example, one or more semiconductor buffer layers, such as a one or more lll-N buffer layers, may be present between the gate contact 140 and the first side 112 of the channel layer 110, and the gate contact may still be considered to be on the first side 112 of the channel layer 110. Gate contact 140, drain contact 150 and source contact 160 may comprise any suitable material for forming electrical contacts for a HEMT. The HEMT 100 thus comprises a channel layer 110 situated between a gate contact 140 and the drain contact 150 and source contact 160. The HEMT 100 further comprises a gate contact 140 located on the opposite side of the channel layer 110 to the drain contact 150 and source contact 160. In other words, opposing sides 112, 114, which may also be referred to as opposing surfaces, of the channel layer 110 are between the gate contact 140, and the drain contact 150 and source contact 160. In such examples, the opposing surfaces may thus comprise the major surfaces of the channel layer 110 and the edges 116, 118 of the channel layer 110 may not comprise the major surfaces and instead comprise the minor surfaces. In other words, the channel layer 110 may comprise a thickness midpoint, where the gate contact 140 is on a first side of the channel layer 110 relative to the thickness midpoint, and the drain contact 150 and source contact 160 are on a second side of the channel layer 110 relative to the thickness midpoint. Additionally, in the illustrated example, the gate contact 140, source contact 150 and source contact 160 are positioned between a distance defined by edges 116, 118 of the channel layer 110. In one example, the arrangement of the gate contact 140, drain contact 150 and source contact 160 as described above may help reduce parasitic capacitances between the gate contact 140, drain contact 150 and source contact 160. In some examples, the first side 112 may comprise an N-polar side of the channel layer 110. As described above, in some examples the channel layer 110 may comprise GaN. The formation of the GaN channel layer 110 may comprise the epitaxial growth of the GaN channel layer 110. GaN typically grows Ga-polar with Ga atoms at the upper surfaces of the grown GaN layer. In conventional solutions, this typically means that the gate contact is formed on the Ga-polar side. Examples according to the present disclosure enable each side of the channel layer 110 to be accessed for fabrication. As such, the gate contact 140 may be fabricated on the N-polar side of the channel layer. In other words, the gate contact 140 is closer to the N-polar side of the channel layer 110 than the Ga-polar side of the channel layer 110. Forming the gate contact 140 on the N-polar side of the channel layer 110 can improve the gate control of the gate contact 140 and provide greater design freedom for adjusting the threshold voltage of the HEMT 100, compared to forming the gate contact 140 on the Ga-polar side. In other examples, however, the first side 112 may comprise the Ga-polar side of the channel layer 110. Alternatively, gate contact 140 may be formed on the barrier layer 120 on the second side 114 of the channel layer 110, and the drain contact 150 and source contact 160 may be formed on the first side 112 of the channel layer 110. In such examples, the gate contact may be formed on the Ga-polar side of the channel layer 110. Figure 2 is an example of a semiconductor structure 101. Semiconductor structure 101 comprises a first semiconductor wafer 190 bonded to a handle wafer 200. First semiconductor wafer 190 comprises the HEMT 100, which comprises corresponding elements to that described above. First semiconductor wafer 190 further comprises a first interconnect layer 170. First interconnect layer 170 comprises a first interconnect 172 connected to gate contact 140 and a first contact pad 174 connected to the first interconnect 172. The first contact pad 174 may be connected to other circuitry to control gate contact 140. First interconnect layer 170 further comprises first dielectric material 176. In one example, one or more layers of first dielectric material 176 may be deposited over gate contact 140 and channel layer 110, and the first interconnect 172 and first contact pad 174 may be formed in the one or more layers of first dielectric material 176. In some examples, first interconnect layer 170 may thus be formed using back end of line (BEOL) fabrication techniques, as will be described in more detail below. First semiconductor wafer 190 further comprises a second interconnect layer 180. Second interconnect layer 180 comprises a second interconnect 182 configured to connect drain contact 150 to second contact pad 184. The second contact pad 184 connects the drain contact 150 to the second semiconductor wafer 200. Second interconnect layer 180 further comprises a third interconnect 186 configured to connect source contact 160 to third contact pad 188. The third contact pad 188 connects the source contact 160 to the second semiconductor wafer 200. Second interconnect layer 180 further comprises second dielectric material 189. In one example, one or more layers of second dielectric material 189 may be deposited over barrier layer 120, and the second interconnect 182, second contact pad 184, third interconnect 186 and third contact pad 188 may be formed in the one or more layers of second dielectric material 189. In some examples, second interconnect layer 180 may thus be formed using BEOL fabrication techniques, as will be described in more detail below. Semiconductor structure 101 further comprises a handle wafer 200. Handle wafer 200 comprises a substrate 210. In some examples, the substrate 210 may comprise a epitaxial growth substrate to permit the epitaxial growth of semiconductor material thereon. In some examples, the substrate 210 may thus comprise a semiconductor material. For example, the substrate 210 may comprise a group IV semiconductor material such as Si, Ge or SiC. In another example, the substrate 210 may comprise a group 11 l-V semiconductor material such as GaN. In other examples, the substrate 210 may not comprise a epitaxial growth substrate and may comprise a material bonded to form the handle wafer 200. For example, substrate 210 may comprise glass, diamond, a polycrystalline substrate, such as Poly-AIN or Poly-SiC or any suitable material for integrated circuit manufacture. Handle wafer 200 further comprises a first semiconductor device 220 and a second semiconductor device 230. In one example, the first semiconductor device 220 and the second semiconductor device 230 may be formed on substrate 210. In another example, first semiconductor device 220 and the second semiconductor device 230 may be formed on an alternative substrate and bonded to the substrate 210. First semiconductor device 220 and a second semiconductor device 230 may comprise any suitable semiconductor device. In one example, the first semiconductor device 220 and / or a second semiconductor device 230 may comprise an electronic semiconductor device, such as a transistor e.g. HEMT, MOSFET, MISFET etc. In another example, the first semiconductor device 220 and / or a second semiconductor device 230 may comprise an optoelectronic device such as a photoemitter or a photodetector. Although first semiconductor device 220 and second semiconductor device 230 are illustrated as being fabricated on the substrate 210, it will be appreciated that these are illustrative examples and one or more elements of first semiconductor device 220 and second semiconductor device 230 may be formed in the substrate 210. In such examples, substrate 210 may thus comprise a semiconductor wafer comprising semiconductor layers for forming one or more semiconductor devices. In some examples, first semiconductor device 220 and second semiconductor device 230 may comprise group IV semiconductor material, such as Si. In some examples, first semiconductor device 220 and second semiconductor device 230 may comprise group I ll-V semiconductor material such as GaN, GaAs, InP etc. In some examples, the first semiconductor device 220 and second semiconductor device 230 may be formed using complementary metal-oxide semiconductor (CMOS) fabrication techniques. Handle wafer 200 further comprises third interconnect layer 240. Third interconnect layer 240 comprises a fourth interconnect 241 connecting the first semiconductor device 220 to the fourth contact pad 242. The third interconnect layer further comprises a first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245. First interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 form a fifth interconnect connecting the second semiconductor device 230 to a fifth contact pad 246. Third interconnect layer 240 further comprises third dielectric material 247. In one example, one or more layers of third dielectric material 247 may be deposited over substrate 210, and the fourth interconnect 241, fourth contact pad 242, first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 and fifth contact pad 246 may be formed in the one or more layers of third dielectric material 247. In some examples, third interconnect layer 240 may thus be formed using BEOL fabrication techniques. In some examples, the first interconnect 172, first contact pad 174, second interconnect 182 second contact pad 184, third interconnect 186, third contact pad 188, fourth interconnect 241, fourth contact pad 242, first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 and fifth contact pad 246 may be formed from any suitable metal used for integrated circuit metallization and routing. First semiconductor wafer 190 and handle wafer 200 are bonded together in such a way that the second contact pad 184 is bonded to the fifth contact pad 246 and the third contact pad 188 is bonded to the fourth contact pad 242. In this manner the drain contact 150 is connected to the third semiconductor device 230 and the source contact 160 is connected to the second semiconductor device 220. The bonding of the first semiconductor wafer 190 to the handle wafer 200 may thus enable the formation of a 3D integrated circuit (3DIC). It will be appreciated that first semiconductor wafer 190 and handle wafer 200 are illustrative examples, and in other examples, first semiconductor wafer 190 and handle wafer 200 may comprise many more semiconductor devices and interconnects that may be connected to form a 3DIC. In some examples, due to the formation of gate contact 140, and the source contact 150 and drain contact 160 on the opposite sides of the HEMT 100, the parasitic capacitances between the contacts 140,150,160 and the interconnects connected to the contacts can be reduced. Furthermore, the ability to form the gate contact 140, and the source contact 150 and drain contact 160 on the opposite sides of the HEMT 100 can enable greater design freedom for the formation of a 3DIC compared to forming the gate contact 140, the source contact 150 and drain contact 160 on the same side of the HEMT 100. Figure 3a-g illustrate process steps in a method for manufacturing the HEMT 100 and the semiconductor structure 100 described above. Figure 3a illustrate a first process step 300a, in which a buffer layer 320, the channel layer 110 and the barrier layer 120 are formed on a substrate 310. In one example, the buffer layer 320, the channel layer 110 and the barrier layer 120 are epitaxially grown on the substrate 310. For example, the buffer layer 320, the channel layer 110 and the barrier layer 120 may be formed by metal organic-chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In such examples, the buffer layer 320, the channel layer 110 and the barrier layer 120 may comprise semiconductor material, such as Ill-N semiconductor material as described above. In some examples, the substrate 310 may thus comprise a material configured to permit the epitaxial growth of semiconductor material thereon. For example, the substrate 310 may comprise Si, Sic, GaN or AIN. As illustrated in Figure 3a, the 2DEG 130 is again formed in the channel layer 110. The barrier layer thus comprises a material configured to induce the formation of the 2DEG 130 in the channel layer 110. Figure 3b illustrates a second process step 300b in which drain contact 150 and source contact 160 are formed on the second side 114 of the channel layer 110. For example, drain contact 150 and source contact 160 may be formed using any suitable fabrication technique, such as, etching and lithography techniques. As illustrated in Figure 3b, drain contact 150 and source contact 160 are formed directly contacting the second side 114 of the channel layer 110. However, in other examples, at least a portion of the barrier layer 120 may be between the second side 114, and the drain contact 150 and source contact 160. Figure 3c illustrates a third step 300c in which the second interconnect layer 180 is formed. In one example, forming the second interconnect layer 180 may comprise depositing one or more layers of the second dielectric material 189 and forming the second interconnect 182 and third interconnect 186 in the one or more layers of the second dielectric material 189. For example, one or more vias may be formed in the one or more layers of the second dielectric material 189 and metal may be formed in the vias to form the second interconnect 182 and third interconnect 186. In a similar manner, in a final layer of the second dielectric material 189, the contact pads 184, 188 may be formed by etching the final layer of the second dielectric material 189 to provide space to deposit metal to form the contact pads 184, 188. In such examples, second interconnect 182, third interconnect 186 and contact pads 184, 188 may thus be formed using BEOL fabrication processes. Figure 3d illustrates a fourth step 300d in which handle wafer 200 is bonded to the second interconnect layer 180. Handle wafer 200 again comprises first semiconductor device 220 and second semiconductor device 230 on substrate 210. Handle wafer 200 further comprises the third interconnect layer 240 comprising corresponding elements and functionality to that described above. Handle wafer 200 may thus be fabricated in a separate process, prior to step 300d. As illustrated in Figure 3d, the handle wafer 200 is bonded to the second interconnect layer 180 in such a way that the second contact pad 184 contacts the fifth contact pad 246 and the third contact pad 188 contacts the fourth contact pad 242. As such, the drain contact 150 is connected to the first semiconductor device 220 and source contact 160 is connected to the third semiconductor device 230. The bonding of handle wafer 200 to the second interconnect layer 180 may thus involve a hybrid bonding process. Figure 3e illustrates a fifth step 300e in which substrate 310 and buffer layer 320 are removed from the channel layer 110. The removal of buffer layer 320 and substrate 310 is performed to expose the first side 112 of the channel layer 110 for further fabrication steps, as will be described in more detail below. In one example, the substrate 310 and the buffer layer 320 may be removed in a grinding process. In another example, the substrate 310 and the buffer layer 320 may be removed using a release layer. For example, a release layer may be formed between the buffer layer 320 and the channel layer 110, which can release the buffer layer 320 and substrate 310 from the channel layer 110. In another example, the buffer layer 320 may act as the release layer. In some examples, the release layer may comprise a porous layer. For example, lll-N semiconductor materials can be porosified by heavily doping the lll-N semiconductor material n-type (N+) and subjecting the N+ lll-N semiconductor material to an electrochemical etch process. The electrochemical etch process is further selective to the N+ lll-N semiconductor material meaning that other material in a lll-N layer stack can be substantially unaffected by the electrochemical etch process. After the porous layer has been formed, the porous layer can then be removed using an annealing process where the pores expand to remove the porous layer. As such, in some examples, a porous layer can be formed between the channel layer 110 and buffer layer 320. In another example, the buffer layer 320 may be porosified and comprise a porous layer. For example, during the epitaxial growth of the layers in step 300b, the buffer layer 320 may be doped N+ or an additional N+ layer may be formed between the channel layer 110 and the buffer layer 320. The N+ layer or N+ buffer layer 320 can then be porosified using an electrochemical etch process. The porosifcation process is elective to the N+ material, as described above. In one example, the porosifcitaion process may take place after the growth of the channel layer 110 and barrier layer 120. In another example, the porosifctaion may take place before the growth of the channel layer 110 and barrier layer 120, and the channel layer 110 and barrier layer 120 may be formed on the porous layer. The porous layer may remain intact during the fabrication processes described above at steps 300b-d and the porous layer may be subsequently removed at step 300e, for example using an anneal process. Figure 3f illustrates a sixth process step 300f in which the semiconductor structure is flipped and the gate contact 140 is formed on the first side 112 of the channel layer 110. Gate contact 140 may be formed using any suitable fabrication technique, such as, etching and lithography techniques. As described above, in some examples, the first side 112 may comprise the N-polar side of the GaN channel layer 100. When formed on the N-polar side, the gate contact 140 may have improved control of the 2DEG 130 compared to forming the gate contact 140 on the Ga-polar side of the channel layer 110. Figure 3g illustrates a seventh process step 300g in which first interconnect layer 170 is formed. In one example, forming the first interconnect layer 170 may comprise depositing one or more layers of the first dielectric material 176 and forming the first interconnect 172 in the one or more layers of the first dielectric material 176. For example, one or more vias may be formed in the one or more layers of the first dielectric material 176 and metal may be formed in the vias to form the first interconnect 172. In a similar manner, in a final layer of the first dielectric material 176 the first contact pad 174 may be formed by etching the final layer of the first dielectric material 176 to provide space to deposit metal to form the first contact pads 176. In such examples, the first interconnect 172 and the first contact pad 174 may thus be formed using BEOL fabrication processes. Steps 300a-300g thus illustrates process steps forming a 3DIC semiconductor structure including a HEMT according to examples of the present disclosure. Figure 4 illustrates another example of a HEMT 400 according to examples of the present disclosure. HEMT 400 comprises gate contact 140 and drain contact 450 on the first side 112 of the channel layer 110. HEMT 400 further comprises source contact 160 on the second side 114 of the channel layer 110. The gate contact 140 and the drain contact 450 are thus formed on the same side of the channel layer 110 and the source contact 160 is formed on the opposite side of the channel layer 110. In other words, opposing sides 112, 114, which may also be referred to as opposing surfaces, of the channel layer 110 are between the gate contact 140 and the drain contact 450, and source contact 160. In other words, the channel layer 110 may comprise a thickness midpoint, where the gate contact 140 and drain contact 450 are on a first side of the channel layer 110 relative to the thickness midpoint, and the source contact 160 is on a second side of the channel layer 110 relative to the thickness midpoint. In some examples, forming the drain contact 450 and gate contact 140 on the opposite side of the channel layer 110 to the source contact 160 may reduce parasitic capacitances between the contacts 140, 450, 160 compared to locating the drain contact 450 and source contact 160 on the same side of the channel layer 110. In some examples, the drain contact 450 may thus be formed during substantially the same fabrication process as the gate contact 140. For example, step 300f described above may be modified such that drain contact 450 is formed during step 300f. In a similar manner, step 300b described above may be modified such that drain contact 450 is not formed during step 300b. Appropriate interconnects and contact pads can thus be fabricated to connect to drain contact 450, in a similar manner to the BEOL process described above. HEMT 400 is a lateral semiconductor device where carrier flow between the source contact 160 and drain contact 450 is again provided by the 2DEG 130. The 2DEG 130 thus forms a channel in the channel layer 110, which is configured to permit lateral carrier flow between the source contact 160 and drain contact 450. HEMT 400 may thus comprise a lateral HEMT or lateral semiconductor device where carrier flow occurs laterally via the 2DEG 130 across the channel layer 110. Thus, at least a majority of the carrier flow between the source contact 160 and drain contact 450 may occur in a lateral direction across the channel layer 110. Figure 5 illustrates another example of a HEMT 500 according to examples of the present disclosure. HEMT 500 comprises gate contact 140 and source contact 560 on the first side 112 of the channel layer 110. HEMT 500 further comprises drain contact 150 on the second side 114 of the channel layer 110. The gate contact 140 and the source contact 560 are thus formed on the same side of the channel layer 110 and the drain contact 150 is formed on the opposite side of the channel layer 110. In other words, opposing surfaces of the channel layer 110 are between the gate contact 140 and the source contact 460, and drain contact 150. In other words, the channel layer 110 may comprise a thickness midpoint, where the gate contact 140 and source contact 460 are on a first side of the channel layer 110 relative to the thickness midpoint, and the drain contact 150 is on a second side of the channel layer 110 relative to the thickness midpoint. In some examples, forming the source contact 560 and gate contact 140 on the opposite side of the channel layer 110 to the drain contact 150 may reduce parasitic capacitances between the contacts 140, 150, 560 compared to locating the source contact 560 and drain contact 150 on the same side of the channel layer 110. In some examples, the source contact 560 may thus be formed during substantially the same fabrication process as the gate contact 140. For example, step 300f described above may be modified such that source contact 560 is formed during step 300f. In a similar manner, step 300b described above may be modified such that source contact 560 is not formed during step 300b. Appropriate interconnects and contact pads can thus be fabricated to connect to source contact 560, in a similar manner to the BEOL process described above. HEMT 500 is a lateral semiconductor device where carrier flow between the source contact 560 and drain contact 150 is again provided by the 2DEG 130. The 2DEG 130 thus forms a channel in the channel layer 110, which is configured to permit lateral carrier flow between the source contact 560 and drain contact 150. HEMT 500 may thus comprise a lateral HEMT or lateral semiconductor device where carrier flow occurs laterally via the 2DEG 130 across the channel layer 110. Thus, at least a majority of the carrier flow between the source contact 560 and drain contact 150 may occur in a lateral direction across the channel layer 110. Figure 6 illustrates another example of a HEMT 600 according to examples of the present disclosure. HEMT 600 comprises a gate field plate 642 connected to the gate 140 and a source field plate 662 connected to the source contact. As one skilled in the art will be familiar with, a source field plate and gate field plate can grade the drain electric field between the drain contact 150 and the source contact 160. This improves the breakdown voltage of the HEMT and further provides hot carrier injection protection. However, in conventional HEMT architectures where the gate, source and drain are located on the same side of the channel layer, a source field plate and gate field plate can create non-linear capacitances, particularly in applications involving higher drain biases. In conventional solutions, the source field plate and gate field plate can result in a high gate to source capacitance (Cgs) and a voltage dependent drain capacitance (Cdd)- HEMT 600, however, comprises the gate field plate 642 and the source field plate 662 on opposite sides of the channel layer 110. In this architecture, the effect of the gate field plate 642 and the source field plate 662 on Cgs and Cdd can be reduced compared to when the gate field plate 642 and the source field plate 662 are located on the same side of the HEMT. In some examples, the gate field plate 642 is formed following the formation of gate contact 140. For example, the gate field plate 642 may be formed as part of the first interconnect layer 170 in step 300g described above. In such examples, suitable interconnects may thus be formed between the gate field plate 642 and contact pads, in a similar manner to that described above. In some examples, the source field plate 662 is formed following the formation of source contact 160. For example, the source field plate 662 may be formed as part of the second interconnect layer 180 in step 300c described above. In such examples, suitable interconnects may thus be formed between the source field plate 642 and contact pads, in a similar manner to that described above. In some examples, drain contact 150 may be located on the first side 112 in a similar manner to that described above. In such examples, the drain contact may thus be on the same side as the gate contact 140 and the gate field plate 642. In other examples, one of the gate field plate 642 or the source field plate 662 may be omitted such that the HEMT 600 comprises one of the gate field plate 642 or the source field plate 662. One of the gate field plate 642 or the source field plate 662 can again help grade the drain electric field. Examples according to the present disclosure have thus far have described a HEMT where the gate, source and drain contacts can be formed on either side of a channel layer of the HEMT to reduce parasitic capacitance issues. However, as described above, examples according to the present disclosure further provide a HEMT where a first and second gate contact can be formed on either side of the channel layer of a HEMT, which, in some examples, can result in the HEMT exhibiting E-mode behaviour. Examples according to the present disclosure may thus provide a HEMT comprising: a first gate contact; a second gate contact; and a channel layer between the first gate contact and the second gate contact. Examples according to the present disclosure may thus additionally provide a semiconductor structure comprising a HEMT. The HEMT may comprise a channel layer a first gate contact on a first side of the channel layer; and a second gate contact on a second side of the channel layer. The semiconductor structure may further comprise a biasing element configured to apply a bias voltage to the first gate contact, wherein the biasing element is operable to adjust the bias voltage to operate the HEMT in depletion mode or enhancement mode. Figure 7 is an example of a HEMT 700 according to examples of the present disclosure. HEMT 700 comprises a channel layer 110 and a barrier layer 120. The barrier layer 120 may comprise a material configured to induce the formation of a two-dimensional electron gas (2DEG) in the channel layer 110, as one skilled in the art will readily understand. For example, the channel layer 110 and barrier layer 120 may comprise III-N semiconductor material, which induces the formation of a 2DEG in the channel layer 110. In one example, the channel layer comprises GaN and the barrier layer comprises AIGaN. As will be described in more detail below, formation of the 2DEG may be interrupted due a negative voltage applied to one of the gate contacts 140, 142. The formation of the 2DEG may thus be prevented in a region beneath one of the first gate contact 140 and the second gate contact 142. As such, HEMT 700 comprises a first 2DEG portion 130a and a second 2DEG portion 130b. In the illustrated example, a continuous 2DEG is thus not formed across the channel layer 110 resulting in the HEMT 700 exhibiting E-mode behaviour. HEMT 100 thus again illustrates a lateral HEMT or lateral semiconductor device where carrier flow occurs laterally via a 2DEG across the channel layer 110 between the source contact 160 and drain contact 150. Once the 2DEG is formed, the 2DEG provides a channel in the channel layer 110, which is configured to permit lateral carrier flow between the source contact 160 and drain contact 150. HEMT 700 further comprises a first gate contact 140 on a first side 112 of the channel layer 110. HEMT 700 further comprises a drain contact 150, a source contact 160 and a second gate contact 142 located on a second side 114 of the channel layer 110. Although the barrier layer 120 is between the second gate contact 142 and the second side 114 of the channel layer, it will be appreciated that the second gate contact is ‘on’ the second side 114 of the channel layer 110. Furthermore, although first gate contact 140, source contact 160 and drain contact 150 are illustrated as being directly in contact with the channel layer 110, in some examples, one or more intermediary layers or material may be present between anyone of the first gate contact 140, source contact 160 and drain contact 150, and the channel layer 110. For example, at least a portion of barrier layer 120 may be present between the channel layer 110 and the source contact 160 and drain contact 150, and the source contact 160 and drain contact 150 may be considered to be on the second side 114 of the channel layer 110. In another example, one or more semiconductor buffer layers, such as a one or more 11 l-N buffer layers, may be present between the first gate contact 140 and the first side 112 of the channel layer 110, and the first gate contact 140 may still be considered to be on the first side 112 of the channel layer 110. First gate contact 140, second gate contact 142, drain contact 150 and source contact 160 may comprise any suitable material for forming electrical contacts for a HEMT. The HEMT 700 thus comprises a channel layer 110 situated between a first gate contact 140 and a second gate contact 142. In other words, opposing sides 112,114, which may also be referred to as opposing surfaces, of the channel layer 110 are between the first gate contact 140 and the second gate contact 142. In some examples, ‘between’ shall be taken to mean the space between overlapping portions of the first gate contact 140 and the second gate contact 142. In such examples, the opposing surfaces may thus comprise the major surfaces of the channel layer 110 and the edges 118, 116 of the channel layer 110 may not comprise the major surfaces and instead comprise the minor surfaces. In some examples, the channel layer 110 may comprise a thickness midpoint, where the first gate contact 140 is on a first side of the channel layer 110 relative to the thickness midpoint, and the second gate contact 142 is on a second side of the channel layer 110 relative to the thickness midpoint. Additionally, in the illustrated example, the first gate contact 140 and second gate contact 142 are positioned between a distance defined by edges 116, 118 of the channel layer 110. As illustrated in Figure 7, the first gate contact 140 comprises a first edge 140a and a second edge 140b. The second gate contact 142 comprises a first edge 142a and a second edge 142b. The channel layer 110 comprises a first edge 118 and second edge 116. The first edge 118 and second edge 116 of channel layer 110 thus extends outside a distance defined between the first edge 140a and a second edge 140b of first gate contact 140, and the first edge 142a and second edge 142b of the second gate contact 142. The channel layer 110 is between the first edge 140a of first gate contact 140 and the first edge 142a of the second gate contact 142. The first edge 140a of first gate contact 140 and the first edge 142a of the second gate contact 142 may thus be substantially aligned. Similarly, the channel layer 110 is between the second edge 140b of first gate contact 140 and the second edge 142b of the second gate contact 142. The second edge 140b of first gate contact 140 and the second edge 142b of the second gate contact 142 may thus be substantially aligned. As described above, a negative bias voltage may be applied to one of the first gate contact 140 or second gate contact 142, which interrupts the formation of the 2DEG. In one example, the negative bias voltage is applied to the first gate contact 140. As such, the formation of the 2DEG is interrupted in the region of the channel layer 110 beneath the first gate contact 140. The second gate contact 142 may thus be used to control current flow between the source contact 160 and the drain contact 150. However, in other examples, the negative bias voltage may be applied to the second gate contact 142 and the first gate contact 140 may be used to control current flow between the source contact 160 and the drain contact 150. In some examples, the first side 112 may comprise an N-polar side of the channel layer 110. As described above, in some examples the channel layer 110 may comprise GaN. The formation of the GaN channel layer 110 may comprise the epitaxial growth of the GaN channel layer 110. GaN typically grows Ga-polar with Ga atoms at the upper surfaces of the grown GaN layer. In conventional solutions, this typically means that the gate contact is formed on the Ga-polar side. Examples according to the present disclosure enable each side of the channel layer 110 to be accessed for fabrication. As such, the first gate contact 140 may be fabricated on the N-polar side of the channel layer. In other words, the first gate contact 140 is closer to the N-polar side of the channel layer 110 than the Ga-polar side of the channel layer 110. In examples, where the first gate contact 140 is negatively biased, forming the first gate contact 140 on the N-polar side of the channel layer 110 can improve the setting of the threshold voltage of the HEMT 700. In other examples, where the first gate contact 140 controls current flow between the drain contact 150 and source contact 160, forming the first gate contact on the N-polar side of the channel layer 110 can improve the gate control for the HEMT 700. Figure 8 is an example of a semiconductor structure 801. Semiconductor structure 801 comprises a first semiconductor wafer 190 bonded to a handle wafer 200. First semiconductor wafer 190 comprises the HEMT 700, which comprises corresponding elements to that described above. First semiconductor wafer 190 further comprises a first interconnect layer 170. First interconnect layer 170 comprises a first interconnect 172 connected to first gate contact 140 and a first contact pad 174 connected to the first interconnect 172. The first contact pad 174 may be connected to other circuitry to control first gate contact 140. First interconnect layer 170 further comprises first dielectric material 176. In one example, one or more layers of first dielectric material 176 may be deposited over first gate contact 140 and channel layer 110, and the first interconnect 172 and first contact pad 174 may be formed in the one or more layers of first dielectric material 176. In some examples, first interconnect layer 170 may thus be formed using back end of line (BEOL) fabrication techniques, as will be described in more detail below. First semiconductor wafer 190 comprises a biasing element 191 configured to apply a bias voltage Vbias to the first gate contact 140 via first interconnect 172. The bias voltage Vbias may comprise a negative voltage configured to interrupt formation of the 2DEG in the channel layer 110. Although biasing element 191 is illustrated as being in the first interconnect layer 170, it will be appreciated that the biasing element 191 may be located at any suitable position on the first semiconductor wafer 190 to apply the bias voltage Vbias to the first gate contact 140. In some examples, the biasing element 191 may comprise a resistive element. In some examples, the resistive element may help prevent the bias voltage Vbias from oscillating. In some examples, the biasing element 191 may be configured to adjust the bias voltage Vbias in situ or ‘on-the-fly’. In this way, the threshold voltage of the HEMT 700 may be adjusted for a particular application, after the fabrication of the HEMT 700 and semiconductor structure 801. For example, HEMT 700 may form part of field programmable gate array (FPGA), where the function of the HEMT 700 may be set by programming the FPGA. In such examples, the biasing element 191 may thus be configured to adjust the bias voltage Vbias and therefore the appropriate threshold voltage to configure the HEMT 700 for a given application. In a similar manner, the biasing element 191 may be configured to adjust the bias voltage Vbias to operate the HEMT 700 in either D-mode or E-mode. In this way, HEMT 700 may be configured as part of a circuit to perform logic operations. First semiconductor wafer 190 further comprises a second interconnect layer 180. Second interconnect layer 180 comprises a second interconnect 182 configured to connect drain contact 150 to second contact pad 184. The second contact pad 184 connects the drain contact 150 to the second semiconductor wafer 200. Second interconnect layer 180 further comprises a third interconnect 186 configured to connect source contact 160 to third contact pad 188. The third contact pad 188 connects the source contact 160 to the second semiconductor wafer 200. Although, not illustrated in Figure 8, in some examples, second interconnect layer 180 may comprise an interconnect to connect the second gate contact 142 to another device or component, for example, to apply a voltage to the gate contact 142 to control current conduction between the source contact 160 and drain contact 150. Second interconnect layer 180 further comprises second dielectric material 189. In one example, one or more layers of second dielectric material 189 may be deposited over barrier layer 120, and the second interconnect 182, second contact pad 184, third interconnect 186 and third contact pad 188 may be formed in the one or more layers of second dielectric material 189. In some examples, second interconnect layer 180 may thus be formed using BEOL fabrication techniques, as will be described in more detail below. Semiconductor structure 801 further comprises a handle wafer 200. Handle wafer 200 comprises a substrate 210. In some examples, the substrate 210 may comprise a epitaxial growth substrate to permit the epitaxial growth of semiconductor material thereon. In some examples, the substrate 210 may thus comprise a semiconductor material. For example, the substrate 210 may comprise a group IV semiconductor material such as Si, Ge or SiC. In another example, the substrate 210 may comprise a group 11 l-V semiconductor material such as GaN. In some examples, the substrate 210 may comprise sapphire. In other examples, the substrate 210 may comprise a material bonded to form the handle wafer 200. For example, substrate 210 may comprise glass, trap-rich Si, porous Si, diamond, a polycrystalline substrate, such as Poly-AIN or Poly-SiC or any suitable material for integrated circuit manufacture. Handle wafer 200 further comprises a first semiconductor device 220 and a second semiconductor device 230. In one example, the first semiconductor device 220 and the second semiconductor device 230 may be formed on substrate 210. In another example, first semiconductor device 220 and the second semiconductor device 230 may be formed on an alternative substrate and bonded to the substrate 210. First semiconductor device 220 and a second semiconductor device 230 may comprise any suitable semiconductor device. In one example, the first semiconductor device 220 and / or a second semiconductor device 230 may comprise an electronic semiconductor device, such as a transistor e.g. HEMT, MOSFET, MISFET etc. In another example, the first semiconductor device 220 and / or a second semiconductor device 230 may comprise an optoelectronic device such as a photoemitter or a photodetector. Although first semiconductor device 220 and second semiconductor device 230 are illustrated as being fabricated on the substrate 210, it will be appreciated that these are illustrative examples and one or more elements of first semiconductor device 220 and second semiconductor device 230 may be formed in the substrate 210. In such examples, substrate 210 may thus comprise a semiconductor wafer comprising semiconductor layers for forming one or more semiconductor devices. In some examples, first semiconductor device 220 and second semiconductor device 230 may comprise group IV semiconductor material, such as Si. In some examples, first semiconductor device 220 and second semiconductor device 230 may comprise group 11 l-V semiconductor material such as GaN, GaAs, InP etc. In some examples, the first semiconductor device 220 and second semiconductor device 230 may be formed using complementary metal-oxide semiconductor (CMOS) fabrication techniques. Handle wafer 200 further comprises third interconnect layer 240. Third interconnect layer 240 comprises a fourth interconnect 241 connecting the first semiconductor device 220 to the fourth contact pad 242. The third interconnect layer further comprises a first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245. First interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 form a fifth interconnect connecting the second semiconductor device 230 to a fifth contact pad 246. Third interconnect layer 240 further comprises third dielectric material 247. In one example, one or more layers of third dielectric material 247 may be deposited over substrate 210, and the fourth interconnect 241, fourth contact pad 242, first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 and fifth contact pad 246 may be formed in the one or more layers of third dielectric material 247. In some examples, third interconnect layer 240 may thus be formed using BEOL fabrication techniques. In some examples, the first interconnect 172, first contact pad 174, second interconnect 182 second contact pad 184, third interconnect 186, third contact pad 188, fourth interconnect 241, fourth contact pad 242, first interconnect portion 243, second interconnect portion 244 and third interconnect portion 245 and fifth contact pad 246 may be formed from any suitable metal used for integrated circuit metallization and routing. First semiconductor wafer 190 and handle wafer 200 are bonded together in such a way that the second contact pad 184 is bonded to the fifth contact pad 246 and the third contact pad 188 is bonded to the fourth contact pad 242. In this manner the drain contact 150 is connected to the third semiconductor device 230 and the source contact 160 is connected to the second semiconductor device 220. The bonding of the first semiconductor wafer 190 to the handle wafer 200 may thus enable the formation of a 3D integrated circuit (3DIC). It will be appreciated that first semiconductor wafer 190 and handle wafer 200 are illustrative examples, and in other examples, first semiconductor wafer 190 and handle wafer 200 may comprise many more semiconductor devices and interconnects that may be connected to form a 3DIC. Similarly, in other examples, one or more semiconductor devices on first semiconductor wafer 190 or second semiconductor wafer 200 may be connected to the first and second gate contacts 140, 142. Figure 9a-g illustrate process steps in a method for manufacturing the HEMT 700 and the semiconductor structure 700 described above. Figure 9a illustrate a first process step 900a, in which a buffer layer 320, the channel layer 110 and the barrier layer 120 are formed a substrate 310. In one example, the buffer layer 320, the channel layer 110 and the barrier layer 120 are epitaxially grown on the substrate 310. For example, the buffer layer 320, the channel layer 110 and the barrier layer 120 may be formed by metal organic-chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In such examples, the buffer layer 320, the channel layer 110 and the barrier layer 120 may comprise semiconductor material, such as Ill-N semiconductor material as described above. In some examples, the substrate 310 may thus comprise a material configured to permit the epitaxial growth of semiconductor material thereon. For example, the substrate 310 may comprise Si, Sic, GaN or AIN. As illustrated in Figure 9a, a 2DEG 130 is formed in the channel layer 110. The barrier layer thus comprises a material configured to induce the formation of the 2DEG in the channel layer 110. Figure 9b illustrates a second process step 900b in which drain contact 150 and source contact 160 are formed on the second side 114 of the channel layer 110. Process step 900b further illustrates that the second gate contact 142 is formed on the barrier layer 120. Although the second gate contact 142 is formed on the barrier layer 120, the second gate contact is additionally formed ‘on’ the first side of the channel layer 110. In some examples, second gate contact 142, drain contact 150 and source contact 160 may be formed using any suitable fabrication technique, such as, etching and lithography techniques. As illustrated in Figure 9b, drain contact 150 and source contact 160 are formed directly contacting the second side 114 of the channel layer 110. However, in other examples, at least a portion of the barrier layer 120 may be between the second side 114, and the drain contact 150 and source contact 160. Figure 9c illustrates a third step 900c in which the second interconnect layer 180 is formed. In one example, forming the second interconnect layer 180 may comprise depositing one or more layers of the second dielectric material 189 and forming the second interconnect 182 and third interconnect 186 in the one or more layers of the second dielectric material 189. For example, one or more vias may be formed in the one or more layers of the second dielectric material 189 and metal may be formed in the vias to form the second interconnect 182 and third interconnect 186. In a similar manner, in a final layer of the second dielectric material 189, the contact pads 184, 188 may be formed by etching the final layer of the second dielectric material 189 to provide space to deposit metal to form the contact pads 184, 188. In such examples, second interconnect 182, third interconnect 186 and contact pads 184, 188 may thus be formed using BEOL fabrication processes. Figure 9d illustrates a fourth step 900d in which handle wafer 200 is bonded to the second interconnect layer 180. Handle wafer 200 again comprises first semiconductor device 220 and second semiconductor device 230 on substrate 210. Handle wafer 200 further comprises the third interconnect layer 240 comprising corresponding elements and functionality to that described above. Handle wafer 200 may thus be fabricated in a separate process, prior to step 900d. As illustrated in Figure 9d, the handle wafer 200 is bonded to the second interconnect layer 180 in such a way that the second contact pad 184 contacts the fifth contact pad 246 and the third contact pad 188 contacts the fourth contact pad 242. As such, the drain contact 150 is connected to the first semiconductor device 220 and source contact 160 is connected to the third semiconductor device 230. The bonding of handle wafer 200 to the second interconnect layer 180 may thus involve a hybrid bonding process. Elements of the HEMT 700, such as second gate contact 142, are thus bonded to the handle wafer via second interconnect layer 180. Figure 9e illustrates a fifth step 900e in which substrate 310 and buffer layer 320 are removed from the channel layer 110. The removal of buffer layer 320 and substrate 310 is performed to expose the first side 112 of the channel layer 110 for further fabrication steps, as will be described in more detail below. In one example, the substrate 310 and the buffer layer 320 may be removed in a grinding process. In another example, the substrate 310 and the buffer layer 320 may be removed using a release layer. For example, a release layer may be formed between the buffer layer 320 and the channel layer 110, which can release the buffer layer 320 and substrate 310 from the channel layer 110. In another example, the buffer layer 320 may act as the release layer. In some examples, the release layer may comprise a porous layer. For example, Ill-N semiconductor materials can be porosified by heavily doping the Ill-N semiconductor material n-type (N+) and subjecting the N+ lll-N semiconductor material to an electrochemical etch process. The electrochemical etch process is further selective to the N+ lll-N semiconductor material meaning that other material in a lll-N layer stack can be substantially unaffected by the electrochemical etch process. After the porous layer has been formed, the porous layer can then be removed using an annealing process where the pores expand to remove the porous layer. As such, in some examples, a porous layer can be formed between the channel layer 110 and buffer layer 320. In another example, the buffer layer 320 may be porosified and comprise a porous layer. For example, during the epitaxial growth of the layers in step 900b, the buffer layer 320 may be doped N+ or an additional N+ layer may be formed between the channel layer 110 and the buffer layer 320. The N+ layer or N+ buffer layer 320 can then be porosified using an electrochemical etch process. The porosifcation process is elective to the N+ material, as described above. In one example, the porosifcitaion process may take place after the growth of the channel layer 110 and barrier layer 120. In another example, the porosifctaion may take place before the growth of the channel layer 110 and barrier layer 120, and the channel layer 110 and barrier layer 120 may be formed on the porous layer. The porous layer may remain intact during the fabrication processes described above at steps 900b-d and the porous layer may be subsequently removed at step 900e, for example using an anneal process. Figure 9f illustrates a sixth process step 900f in which first gate contact 140 is formed on the first side 112 of the channel layer 110. First gate contact 140 may be formed using any suitable fabrication technique, such as, etching and lithography techniques. As described above, in some examples, the first side 112 may comprise the N-polar side of the GaN channel layer 700. Figure 9g illustrates a seventh process step 900g in which first interconnect layer 170 is formed. In one example, forming the first interconnect layer 170 may comprise depositing one or more layers of the first dielectric material 176 and forming the first interconnect 172 in the one or more layers of the first dielectric material 176. For example, one or more vias may be formed in the one or more layers of the first dielectric material 176 and metal may be formed in the vias to form the first interconnect 172. In a similar manner, in a final layer of the first dielectric material 176 the first contact pad 174 may be formed by etching the final layer of the first dielectric material 176 to provide space to deposit metal to form the first contact pads 176. In such examples, the first interconnect 172 and the first contact pad 174 may thus be formed using BEOL fabrication processes. Process step 900g further illustrates that basing element 191 is formed to apply the bias voltage Vbias to the first gate contact 140. As described above, the bias voltage Vbias may comprise a negative bias voltage to interrupt the formation of the 2DEG in the channel layer 110. In some examples, forming the biasing element may comprise forming a resistive element. In some examples, the biasing element 191 may be formed before process step 900g, and process step 900g may comprise forming an interconnect to connect the first interconnect 172 to the biasing element 191. Steps 900a-900g thus illustrates process steps form forming a 3DIC semiconductor structure including a HEMT according to examples of the present disclosure. Figure 10 illustrates another example of a HEMT 1000 according to examples of the present disclosure. HEMT 1000 comprises first gate contact 140 and drain contact 1050 on the first side 112 of the channel layer 110. HEMT 1000 further comprises second gate contact 142 and source contact 160 on the second side 114 of the channel layer 110. The first gate contact 140 and the drain contact 1050 are thus formed on the same side of the channel layer 110, and second gate contact 142 and the source contact 160 is formed on the opposite side of the channel layer 110. In other words, opposing sides 112, 114, which may also be referred to as opposing surfaces of the channel layer 110 are between the first gate contact 140 and the drain contact 1050, and the second gate contact 142 and source contact 160. In other words, the channel layer 110 may comprise a thickness midpoint, where the first gate contact 140 and drain contact 1050 are on a first side 112 of the channel layer 110 relative to the thickness midpoint, and the source contact 160 and second gate contact 142 are on a second side 114 of the channel layer 110 relative to the thickness midpoint. In some examples, forming the drain contact 1050 and first gate contact 140 on the opposite side of the channel layer 110 to the second gate contact 142 and source contact 160 may reduce parasitic capacitances between the contacts 140, 1050, 160 compared to locating the drain contact 1050 and source contact 160 on the same side of the channel layer 110. In some examples, parasitic capacitances can develop between the contacts 140,1050, 142, 160. Configuring the contacts 140, 1050, 142, 160 as shown in Figure 10 may help reduce said parasitic capacitances. In some examples, the drain contact 1050 may thus be formed during substantially the same fabrication process as the first gate contact 140. For example, step 900f described above may be modified such that drain contact 1050 is formed during step 900f. In a similar manner, step 900b described above may be modified such that drain contact 1050 is not formed during step 900b. Appropriate interconnects and contact pads can thus be fabricated to connect to drain contact 1050, in a similar manner to the BEOL process described above. HEMT 1000 is a lateral semiconductor device where carrier flow between the source contact 160 and drain contact 1050 is again provided by a 2DEG, when formed. The 2DEG forms a channel in the channel layer 110, which is configured to permit lateral carrier flow between the source contact 160 and drain contact 1050. HEMT 1000 may thus comprise a lateral HEMT or lateral semiconductor device where carrier flow occurs laterally via the 2DEG across the channel layer 110. Thus, at least a majority of the carrier flow between the source contact 160 and drain contact 1050 may occur in a lateral direction across the channel layer 110. Figure 11 illustrates another example of a HEMT 1100 according to examples of the present disclosure. HEMT 1100 comprises first gate contact 140 and source contact 1160 on the first side 112 of the channel layer 110. HEMT 1100 further comprises second gate contact 142 and drain contact 150 on the second side 114 of the channel layer 110. The first gate contact 140 and the source contact 1160 are thus formed on the same side of the channel layer 110 and the second gate contact 142 and drain contact 150 is formed on the opposite side of the channel layer 110. In other words, opposing sides 112, 114, which may also be referred to as opposing surfaces of the channel layer 110 are between the first gate contact 140 and the source contact 460, and the second gate contact 142 and drain contact 150. In other words, the channel layer 110 may comprise a thickness midpoint, where the first gate contact 140 and source contact 1160 are on a first side 112 of the channel layer 110 relative to the thickness midpoint, and the drain contact 150 and second gate contact 142 are on a second side 114 of the channel layer 110 relative to the thickness midpoint. In some examples, forming the source contact 1160 and first gate contact 140 on the opposite side of the channel layer 110 to the second gate contact 142 and drain contact 150 may reduce parasitic capacitances between the contacts 140, 150, 1160 compared to locating the source contact 1160 and drain contact 150 on the same side of the channel layer 110. In some examples, parasitic capacitances can develop between the contacts 140, 450, 142, 1160. Configuring the contacts 140, 450, 142, 1160 as shown in Figure 10 may help reduce said parasitic capacitances. In some examples, the source contact 1160 may thus be formed during substantially the same fabrication process as the first gate contact 140. For example, step 900f described above may be modified such that source contact 1160 is formed during step 900f. In a similar manner, step 900b described above may be modified such that source contact 1160 is not formed during step 900b. Appropriate interconnects and contact pads can thus be fabricated to connect to source contact 1160, in a similar manner to the BEOL process described above. HEMT 1100 is a lateral semiconductor device where carrier flow between the source contact 1160 and drain contact 150 is again provided by a 2DEG, when formed. The 2DEG forms a channel in the channel layer 110, which is configured to permit lateral carrier flow between the source contact 1160 and drain contact 150. HEMT 1000 may thus comprise a lateral HEMT or lateral semiconductor device where carrier flow occurs laterally via the 2DEG across the channel layer 110. Thus, at least a majority of the carrier flow between the source contact 160 and drain contact 1050 may occur in a lateral direction across the channel layer 110. Figure 12 illustrates another example of a HEMT 1200 according to examples of the present disclosure. HEMT 1200 comprises a gate field plate 1242 connected to the first gate contact 140 and a source field plate 1262 connected to the source contact 160. As one skilled in the art will be familiar with, a source field plate and gate field plate can grade the drain electric field between the drain contact 150 and the source contact 160. This improves the breakdown voltage of the HEMT and further provides hot carrier injection protection. However, in conventional HEMT architectures where the gate, source and drain are located on the same side of the channel layer, a source field plate and gate field plate can create non-linear capacitances, particularly in applications involving higher drain biases. In conventional solutions, the source field plate and gate field plate can result in a high gate to source capacitance (Cgs) and a voltage dependent drain capacitance (Cdd)- HEMT 1200, however, comprises the gate field plate 1242 and the source field plate 1262 on opposite sides of the channel layer 110. In this architecture, the effect of the gate field plate 1242 and the source field plate 1262 on Cgs and Cdd can be reduced compared to when the gate field plate 1242 and the source field plate 1262 are located on the same side of the HEMT. In some examples, the gate field plate 1242 is formed following the formation of first gate contact 140. For example, the gate field plate 1242 may be formed as part of the first interconnect layer 170 in step 900g described above. In such examples, suitable interconnects may thus be formed between the gate field plate 1242 and contact pads, in a similar manner to that described above. In some examples, the source field plate 1262 is formed following the formation of source contact 160. For example, the source field plate 1262 may be formed as part of the second interconnect layer 180 in 900c described above. In such examples, suitable interconnects may thus be formed between the source field plate 1242 and contact pads, in a similar manner to that described above. In some examples, drain contact 150 may be located on the first side 112 in a similar manner to that described above. In such examples, the drain contact may thus be on the same side as the first gate contact 140 and the gate field plate 1242. In other examples, one of the gate field plate 1242 or the source field plate 1262 may be omitted such that the HEMT 1200 comprises one of the gate field plate 1242 or the source field plate 1262. One of the gate field plate 1242 or the source field plate 1262 can again help grade the drain electric field. Figure 13 is a flowchart illustrating process steps in a method 1300 for forming a HEMT. The method 1300 comprises, in a first step 1310, forming a channel layer. The method 1300 further comprises, in a second step 1320, forming a gate contact on a first side of the channel layer. The method 1300 further comprises, in a third step 1330, forming at least one of a source contact and a drain contact on a second side of the channel layer, opposite the first side, wherein the channel layer is between the gate contact and the at least one of the source contact and the drain contact and wherein the channel layer comprises a channel for lateral carrier flow across the channel layer between the source contact and the drain contact. The present disclosure further provides an RF module comprising a HEMT according to examples of the present disclosure ora semiconductor structure according to examples of the present disclosure. In some examples the RF module may comprise one of: a switch module, a power amplifier module, a transmitter module, a receiver module and a transceiver module. The present disclosure further provides an electronic device comprising a HEMT according to examples of the present disclosure, a semiconductor structure according to examples of the present disclosure an RF module according to examples of the present disclosure. In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar. 5 It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the 10 functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. A high electron mobility transistor, HEMT, comprising: a channel layer;5 a gate contact on a first side of the channel layer; andat least one of a source contact and a drain contact on a second side of the channel layer, opposite the first side;wherein the channel layer is between the gate contact and the at least one of the source contact and the drain contact;10 wherein the channel layer comprises a channel for lateral carrier flow across thechannel layer between the source contact and the drain contact.

2. The HEMT according to claim 1 wherein the source contact and the drain contact are on the second side.

153. The HEMT according to claim 1 wherein the other of the source contact and the drain contact is on the first side.

4. The HEMT according to any preceding claim further comprising a source field 20 plate connected to the source contact.

5. The HEMT according to claim 4 wherein the source field plate is on the second side.25 6. The HEMT according to any preceding claim further comprising a gate field plateconnected to the gate contact.

7. The HEMT according to any preceding claim wherein the first side comprises a N-polar side of the channel layer.

308. The HEMT according to any preceding claim further comprising a second gate contact on the second side.

9. A semiconductor structure comprising the HEMT according to any preceding35 claim and a handle wafer bonded to the HEMT.

10. The semiconductor structure according to claim 9 wherein the handle wafer comprises one or more semiconductor devices connected to the HEMT.

11. The semiconductor structure according to any of claims 9-10, when dependent on claim 8, further comprising a biasing element configured to apply a bias voltage to the first gate contact or the second gate contact to set a threshold5 voltage of the HEMT.

12. The semiconductor structure according to claim 11 wherein the biasing element comprises a resistive element.10 13. The semiconductor structure according to claim 11 or 12 wherein the thresholdvoltage is greater than 0 V.

14. A radio frequency, RF, module comprising the HEMT according to any of claims 1-8 or the semiconductor structure according to any of claims 9-13.1515. An electronic device comprising the HEMT according to any of claims 1-8, the semiconductor structure according to any of claims 9-13 or the radio frequency module according to claim 14.20 16. A method of forming a HEMT comprising:forming a channel layer;forming a gate contact on a first side of the channel layer; andforming at least one of a source contact and a drain contact on a second side of the channel layer, opposite the first side;25 wherein the channel layer is between the gate contact and the at least one of thesource contact and the drain contact;wherein the channel layer comprises a channel for lateral carrier flow across the channel layer between the source contact and the drain contact.30 17. The method according to claim 16 further comprising forming the source contactand the drain contact on the second side.

18. The method according to claim 16 further comprising forming the other of the source contact and the drain contact on the first side.3519. The method according to any of claims 16-18 further comprising forming a second gate contact on the second side.

20. A method of forming a semiconductor structure comprising the method according to any of claims 16-19 and further comprising:bonding the HEMT to a handle wafer.5 21. The method according to claim 20 further comprising:forming the channel layer on a substrate;bonding the channel layer to the handle wafer; and removing the substrate from the channel layer.101522. The method according to claim 21 further comprising:forming a release layer on the substrate; andforming the channel layer on the release layer;wherein removing the channel layer from the substrate comprises removing the release layer.

23. The method according to claim 22 wherein the release layer comprises a buffer layer.

24. The method according to claim 22 or 23 wherein the release layer comprises a20porous layer.

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