Power converter arrangement

Abstract

A power converter arrangement that comprises a ceramic substrate (1) having an upper side (11) and a lower side (12), a plurality of first metallisations (2) arranged on the upper side (11), wherein the first metallisations (2) are configured to be connected to a first DC voltage, a plurality of second metallisations (3) arranged on the upper side (11), wherein the second metallisations (3) are configured to be connected to a second DC voltage, a third metallisation (4) arranged on the upper side (11), wherein the third metallisation (4) is configured to provide an AC output voltage, and a plurality of discrete packaged semiconductor packages (5) arranged on the upper side (11) of the ceramic substrate (1), wherein each semiconductor package (5) is connected to one of the first and second metallisations (2, 3) and to the third metallisation (4), wherein the semiconductor packages (5) are configured to form a power converter circuit (15) or a part (150) thereof with an output AC voltage on the third metallisation (4).

Description

Field of the disclosure The present disclosure relates to a power converter arrangement. Background It is known to implement power converters by connecting a plurality of power electronics modules to a printed circuit board, wherein each power electronics module comprises a power semiconductor arranged on a ceramic substrate. Such power electronics modules are specifically designed components. There is an interest to alternatively provide for power converters which are built on the basis of off-the-shelf components. There is a need to provide for a power converter arrangement that allows the use of off-the-shelf components. Summary of the disclosure According to an aspect of the disclosure, a power converter arrangement is provided. The power converter arrangement comprises a ceramic substrate having an upper side and a lower side, a plurality of first metallizations arranged on the upper side, wherein the first metallizations are configured to be connected to a first (positive or negative) DC voltage, a plurality of second metallizations arranged on the upper side, wherein the second metallizations are configured to be connected to a second (negative or positive) DC voltage, and a third metallization arranged on the upper side, wherein the third metallization is configured to provide an AC output voltage. There is further provided a plurality of discrete packaged semiconductor packages arranged on the upper side of the ceramic substrate, wherein each semiconductor package is connected to one of the first and second metallizations and to the third metallization. The semiconductor packages are configured to form a power converter circuit or a part thereof with an output AC voltage on the third metallization. Aspects of the disclosure are thus based on the idea of building a power converter circuit or a part thereof on a ceramic substrate based on discrete packaged semiconductor packages which may be off the shelf semiconductor packages. Accordingly, a power converter circuit is provided for by readily available components, thereby avoiding the necessity to build specific proprietary prepackaged modules that include power semiconductors. For example, the discrete packaged semiconductor packages may be of the D2PAK-7 family which is a package type for power semiconductor devices including MOSFETs having a specific package outline. The MOSFETs may be SiC MOSFETs. The present disclosure is based on the realization that discrete packaged semiconductor packages are suitable to form a power converter when arranged on a ceramic substrate having three metallizations as claimed. As mentioned, the semiconductor packages form a power converter or a part of a power converter on the ceramic substrate. The power converter may be an inverter converting a DC input to an AC output. In other embodiments, the power converter may be a rectifier or a DC / DC converter. In some embodiments, the semiconductor packages form a part of a power converter, namely two switches of a power converter which are arranged in series between a positive DC voltage and a negative DC voltage, wherein each of the two switches comprises a plurality of power semiconductors arranged in parallel as is customary when high currents are to be switched. The feature that the semiconductor packages are discrete packaged is to be understood such that each semiconductor package contains one power semiconductor, arranged in an individual package with defined dimensions. The semiconductor packages may be off-the-shelf packages. It should be noted that, for the purposes of the present disclosure, the side of the ceramic substrate on which the semiconductor packages are arranged are always referred to as the upper side of the ceramic substrate, regardless of the actual spatial orientation. In some embodiments, the arrangement further comprises capacitors, in particular DC link capacitors arranged on the upper side of the ceramic substrate, wherein each capacitor connects one of the first metallizations and one of the second metallizations (and is thus connected between the positive DC voltage and the negative DC voltage). DC link capacitors are part of a power converter circuit. To include them on the upper side of the ceramic substrate increases efficiency and compactness of the arrangement. In some embodiments, the first and second metallizations are formed as patches, wherein two adjacent patches of the first and second metallizations are each connected through a DC link capacitor. In some embodiments, the lower side of the ceramic substrate comprises a large area fourth metallization configured to thermally couple the ceramic substrate to a heatsink. In this respect, it may be provided that the fourth metallization is relatively thin such as having a thickness of no more than 0.5 millimeters (such as 0.3 millimeters), to reduce material costs and weight. A relatively thin fourth metallization made may in particular be provided if the semiconductor packages themselves include a heat spreader, as is the case in embodiments, as will be discussed further below In some embodiments, each semiconductor package comprises a power semiconductor with a gate connection, a source connection and a drain connection, wherein the drain connection is a bottom side metallization of the semiconductor package, and wherein the drain connection I bottom side metallization is connected to the first metallization or the third metallization. Accordingly, a bottom side metallization of the semiconductor packages is connected to one of the metallizations on the ceramic substrate. In some embodiments, the bottom side metallization is configured to act as a heat spreader for the semiconductor package. For example, if the semiconductor packages is from the D2PAK-7 family, a bottom copper terminal of the package is automatically provided for which acts as heat buffer and heat spreader. Since copper has a very high thermal conductivity compared to the ceramic insulator, spreading of the heat can counteract the thermal resistance of the copper. The advantage is provided that the copper bottom metallization acting as heat buffer reduces temperature swing because of its thermal capacity, thereby increasing reliability of the component. In some embodiments, the source connection and the gate connection are pin connections, wherein the pin connections are connected to separate small metallizations on the ceramic substrate (which are separately connected through a printed circuit board by contacting means such as vertical pins). In some embodiments, the top side of the ceramic substrate including the semiconductor packages and the DC-link capacitors is coated or potted, the coating or potting providing for a cuboid module having a flat top surface configured to be attached to a printed circuit board, wherein electrical contacts that connect the metallizations and gate / source contact pins with a printed circuit board may stick out the module top surface. Accordingly, by the coating / potting a module is provided for that may be preassembled and that may be connected as one part to a printed circuit board. This allows to efficiently build the power converter circuit. The printed circuit board to which such module is connected may be a main printed circuit board, wherein all relevant contacts for the module are provided for by respective contacts of the main printed circuit board. In particular, the main printed circuit board may comprise drivers for the semiconductor packages. The printed circuit board is attached to the top surface of the module, wherein the contacts of the module are connected to respective contacts of the printed circuit board. Alternatively, the printed circuit board is an interposer printed circuit board configured to provide gate signals and source signals to the gate connections and the source connections of the semiconductor packages, wherein the interposer printed circuit board is connected to a main (power) printed circuit board, and wherein the main printed circuit board provides to the interposer printed circuit board a high side (positive) source signal, a high side (positive) gate signal, a low side (negative) source signal and a low side (negative) gate signal. By using an interposer printed circuit board which distributes the high side signals and the low side signals, the number of connections necessary at the main printed circuit board is reduced to four, thereby also reducing the number of required through-hole connections in the main printed circuit board, and thereby increasing the power handling capability of the main printed circuit board. As mentioned, the semiconductor package is of the kind that comprises one bottom contact and several pins such as in the D2PAK-7 family. In some embodiments, the first, second and third metallizations are provided by copper layers. However, in principle, other metals or metal alloys may be used as well such as silver or aluminum. In some embodiments, the first, second and third metallizations are connected to the ceramic substrate by direct copper bonding (DBC) or active metal brazing. Direct copper bonding (also referred to as “direct bonded copper”) is the direct mating of two dissimilar electronic materials (copper and ceramic). The interface between the pure copper and the ceramic is very reliable. The DBC process takes advantage of the copper - oxygen eutectic where the melting point is lower than that of pure copper or oxide ceramic. At the melting temperature the eutectic is the only liquid present, wherein it wets and bonds to both surfaces. Active metal brazing is also a known process which involves using a molten filler metal that contains reactive elements to create a bond materials. This process relies on the formation of compounds between the filler metal and the surfaces being joined. In some embodiments, the ceramic substrate has a high thermal conductivity and a similar thermal expansion coefficient as the material of the semiconductor (such as silicon carbide in the case of SiC MOSFETs) for high reliability. Examples of such ceramics are aluminium nitride (AIN) and silicon nitride (SisN^. The use of such ceramics is further associated with the advantage of excellent isolation properties (free of partial discharge). A “similar” thermal expansion coefficient of the ceramic substrate and the semiconductor material is assumed to be present if the difference between the thermal expansion coefficients divided by the larger thermal expansion coefficient is less than 40 percent. In some embodiments, the connections of the semiconductor packages are connected to the respective metallizations by soldering or silver sintering. Silver sintering represents an alternative to soldering for high quality electrical connections. In some embodiments, the first and second metallizations are arranged along a first line and a second line, wherein along each of the first and second lines the first and the second metallizations are formed as patches and are arranged alternately, and wherein the third metallization is arranged along a third line, wherein the third line is arranged between the first and second lines, thereby forming a middle line. Using such geometric configuration, it is easily possible to place the semiconductor packages on the respective metallizations. In some embodiments, the semiconductor packages are configured to form two switches of a power converter circuit arranged in series between the positive DC voltage and the negative DC voltage, wherein each of the two switches comprises a plurality of power semiconductors arranged in parallel. It is pointed out that the present disclosure is not limited to a particular number of the discrete packaged semiconductor packages. In some embodiments, there may be arranged six or alternatively four semiconductor packages in parallel. It is also possible to connect several modules in parallel, with a configuration of, e.g., 4+4 or 4+6 semiconductor packages. The skilled person will appreciate that except where mutually exclusive, a feature or parameter described in relation to any one of the above aspects may be applied to any other aspect. Furthermore, except where mutually exclusive, any feature or parameter described herein may be applied to any aspect and / or combined with any other feature or parameter described herein. Brief Description of the Drawings The disclosure will be explained in more detail on the basis of exemplary embodiments with reference to the accompanying drawings in which: FIG. 1 is a top view on the upper side of a ceramic substrate that comprises first, second and third metallizations and a plurality of discrete packaged semiconductor packages connected to the metallizations, FIG. 2 is a top view on the bottom side of the ceramic substrate of FIG. 1, wherein the bottom side comprises a large area metallization; FIG. 3 is a perspective view on the upper side of the ceramic substrate of FIG. 1; FIG. 4 is a sectional view of an example semiconductor package; FIG. 5 is a sectional view of a power module that comprises the ceramic substrate and the semiconductor packages of FIG. 1, wherein the top side of the ceramic substrate including the semiconductor packages are embedded in a potting material that defines the outer dimensions of the power module; FIG. 6 is a ceramic substrate with semiconductor packages similar to the substrate of FIG. 1, wherein additionally high current connections and driving inputs are identified; FIG. 7 is an electric circuit that is implemented by the ceramic substrate with semiconductor packages of FIG. 1; FIG. 8 is a sectional view of an arrangement that comprises the power module of FIG. 5 thermally coupled at its lower side to a heat sink and electrically connected at its upper side to a printed circuit board; FIG. 9 is an electric circuit of an optional interposing printed circuit board providing gate signals and source signals to power semiconductors of the semiconductor packages of FIG. 1; FIG. 10 is a sectional view of an arrangement that comprises the power module of FIG. 5 thermally coupled at its lower side to a heat sink and electrically connected at its upper side to an interposing printed circuit board which implements the electric circuit of FIG. 9, wherein the interposing printed circuit board is connected to a main printed circuit board; and FIG. 11 is a standard electric circuit of a power converter. Detailed description Before discussing embodiments of the present disclosure with respect to FIGS. 1 to 10, the background of the disclosure is discussed with respect to FIG. 11. FIG. 11 shows a standard three-phase inverter circuit for motor drive applications. The inverter circuit is an example of a power converter circuit. The inverter circuit comprises a DC power supply 16 (such as a DC battery or alternatively a DC / DC or AC / DC converter) that has a positive terminal 161 and a negative terminal 162. Between the positive terminal 161 and the negative terminal 162 a DC voltage is present. A positive voltage rail 153 is connected to the DC positive terminal 161 and a negative voltage rail 154 is connected to the DC negative terminal 162. The positive voltage rail 153 and the negative voltage rail 154 form a high-voltage bus. The inverter circuit further comprises a filtering capacitor 6 and an inverter circuitry 15 both arranged between the positive voltage rail 153 and the negative voltage rail 154. The inverter circuitry 6 comprises six semiconductor power switches S1 to S6 which provide for a three-phase alternating current ia, ib, ic for a load 152 (such as a motor or a generator). Before the load 152 a filter 151 may be arranged. The semiconductor power switches S1 to S6 each comprise at least one transistor and a bypass diode. The switches S1 to S6 may be MOSFET (Metal-oxide semiconductor fieldeffect transistors) such as Si (Silicon) MOSFET, GaN (Gallium Nitride) MOSFET or SiC (Silicon Carbide) MOSFET, or IGBT (Insulated Gate Bipolar Transistor) switches. The switches S1 to S6 are controlled by a controller 155 which provides switching signals to the gates of the switches. In the inverter circuitry 15, switches S1, S2 form a module 150 and are arranged in series between the positive voltage rail 153 and the negative voltage rail 154 and provide for alternating current ia. While the switches S1, S2 are indicated in FIG. 11 to comprise one transistor only, the switches S1, S2 may actually each be formed by a plurality of transistors (such as MOSFET, IGBT) arranged in parallel to reduce the current that is controlled by a single transistor. Similarly, switches S3, S4 form another module 150 and are arranged in sequence between the positive voltage rail 153 and the negative voltage rail 154 to provide for alternating current ib and switches S5, S6 form a further module 150 and are arranged in sequence between the positive voltage rail 153 and the negative voltage rail 154 to provide for alternating current ic. The other switches S3 to S6 may also each be formed by a plurality of parallel transistors. The positive voltage rail 153 and the negative voltage rail 154 with mounted filtering capacitors 6 and connected to the energy supply 16 are termed as DC link and the filtering capacitors 6 mounted on these busbars are termed as DC link capacitors which are meant to filter any AC noise present in the DC line when operating at higher voltage levels. They are necessary for filtering switching noise and current ripple to reduce voltage ripple below acceptable levels. It is known to implement the switches S1 to S6 as modules connected to a printed circuit board, wherein each power semiconductor is arranged in an individual module referred to as prepackage module, wherein in the prepackage module the power semiconductor is arranged on a ceramic substrate. While such prepackage modules provide for good results, their disadvantage lies in that they are specifically designed modules and not off-the-shelf products. In the following, embodiments of a power converter arrangement are discussed that allow to implement a power converter based on off-the-shelf power semiconductors. More particularly, arrangements are discussed which comprise a ceramic substrate with several metallizations and a plurality of discrete packaged semiconductor packages, wherein the semiconductor packages are configured to form part of a power converter, namely, two switches arranged in series such as switches S1, S2 or S3, S4 or S5, S6 in modules 150 of FIG. 11, wherein each of the two switches comprises a plurality (such as six) parallel semiconductor packages (with a MOSFET or IGBT power semiconductor). In other embodiments, another number of switches may be implemented. Also, it may be provided that all switches S1 to S6 and thus the complete power converter circuit is formed by the semiconductor packages. FIG. 1 shows a power converter arrangement which comprises a ceramic substrate 1 with an upper side 11. A plurality of first metallizations 2 and a plurality of second metallizations 3 are formed on the upper side 11. Each metallization 2, 3 is in the form of a rectangular patch 20, 30, but the patches 20, 30 may have other forms as well. The first metallization 2 is connected to a DC positive voltage, such as the positive voltage of the positive voltage rail 153 of FIG. 11. The second metallizations 3 is connected to a DC negative voltage such as the negative voltage of the negative voltage rail 154 of FIG. 11. The respective electrical connection is through a printed circuit board (not shown in FIG. 1), wherein, e.g., vertical pins or spring terminals provide for the respective electrical connection. The first metallization 2 and a second metallization 3 are arranged in an alternate manner along a first line 17 and a second line 18 which are parallel. In between and parallel to the first and second lines 17, 18, a third metallization 4 is arranged along a line 19. The third metallization 4 is configured to provide an output AC voltage. A plurality of discrete packaged semiconductor packages 5 are arranged on the upper side 11 of the chronic substrate 1. The semiconductor packages 5 may be of the D2PAK-7 family, having a bottom side metallization 50 and several pin connections 5i, such seven pin connections. A sectional view of such semiconductor package 5 is shown in FIG. 4. The semiconductor package 5 comprises a power semiconductor chip 55. Electrical contacts to / from the chip 55 are provided through a bottom side metallization 50 and several pin connections 5i. The package 5 comprises a potting material 56 in which the semiconductor chip 55 is embedded. Such package 5 that comprises a bottom side metallization 50 is associated with the advantage that the bottom metallization 50 serves as a heat buffer and heat spreader. By providing such heat buffer and heat spreader, the necessity to transfer heat to a heat sink is reduced such that reduced interfaces to a heat sink may be provided for. The semiconductor packages 5 are arranged such on the upper side 11 of the ceramic substrate 1 that each semiconductor package 5 is connected to one of the first and second metallizations 2, 3 and is further connected to the third metallization 4. For example, the semiconductor package 5a at the left top of FIG. 1 is connected with its bottom metallization 50 to the first metallization 2 and with several of its pin connections 5i to the third metallization 4. In another example, the semiconductor package 5b at the left bottom of FIG. 1 is connected with several of its pin connections 5i to the second metallization 3 and connected with its bottom metallization 50 the third metallization 4. That a semiconductor package 5 is connected with several of its pin connections 5i to the second or third metallization 3, 4 means that all of the pins except two are connected to the respective metallization 3, 4. However, as will be discussed further below, two pins, namely, an input pin for a gate signal and an input pin for a source signal are separate and connected separately to a separate small metallization patches on the upper side 11 of the ceramic substrate 1. Further, along the first and second lines 17, 18, the orientation of the semiconductor packages 5 alternates, i.e., if a semiconductor package contacts with its bottom metallization 50 the first metallization 2, the neighboring semiconductor package contacts with its bottom metallization 50 the third metallization 4. There are further arranged DC link capacitors 6 on the upper side 11 of the ceramic substrate 1, wherein each DC link capacitors 6 connects one of the first metallization patches 20 and one of the second metallization patches 30. The DC link capacitors 6 are also arranged along lines 17 and 18. The ceramic substrate 1 may be formed by SisN4, AL2O3 or AIN in some embodiments, without limiting the disclosure to such ceramics. The first, second and third metallizations 2, 3, 4 may be copper layers and may be attached to the ceramic substrate 1, e.g., by active metal brazing. In some embodiments, the metallizations 2, 3, 4 are attached to the ceramic substrate by direct copper bonding. Further, it may be provided that the semiconductor packages 5 are electrically connected to the respective metallization 2, 3, 4 by soldering or, alternatively, by silver sintering. The lower side 12 of ceramic substrate 1 is shown in FIG. 2. It comprises a large size metallization 7 only, wherein the metallization 7 serves to thermally connect the arrangement to a heat sink, as will be discussed with respect to in FIGS. 8 and 10. The thickness of the metallization 7 may be rather low (such as 0.3 or 0.5 millimeters) as heat spreading is also provided by the bottom metallization 50 as shown in FIG. 4. FIG. 3 is a perspective view of the arrangement of FIG. 1. What can be well seen in FIG. 3 is that each semiconductor package 5 comprises a gate connection 51 for providing a signal to the gate of the power semiconductor and a source connection 52 providing a signal to the source of the power semiconductor. The drain connection of the power semiconductor is provided by the bottom metallization 50. The gate connection 51 and the source connection 52 of each power semiconductor 5 are not connected to any of the first, second and third metallizations 2, 3, 4, but are connected separately to separate small metallization patches 3a, 3b on the upper side 11 of the ceramic substrate 1, which are separately contacted through a printed circuit board. In this respect, it is pointed out that the source connection 52 to the power semiconductor 5 provides an input signal serving as an internal reference for the semiconductor chip, wherein the source is also connected by pins 5i to the second metallization 3 or the third metallization 4. The bottom metallization 50 is connected to either the first metallization 2 or the third metallization 4, wherein the orientation of the power semiconductors 5 alternates. As shown in the sectional view of FIG. 5, the top side 11 of the ceramic substrate 1 including the semiconductor packages 5 is potted with a potting material 8 which provides for a cuboid outline with a flat top surface 110. The ceramic substrate 1, the semiconductor packages 5 and the potting material form a power module 10. Before potting, plastic 115 may be glued around the edges of the ceramic substrate 1 to increase a creeping distance between the upper side 110 and a heat sink attached to the bottom side. FIG. 6 is similar to FIG. 1, wherein additionally the current connections and signals (DC inputs and AC output, G as the gate voltage, and S as the source voltage) are indicated. FIG. 7 depicts the electric circuit implemented by the configuration of FIG. 6. In the depicted embodiment, there are provided six transistors forming switches S11 to S16 between the positive voltage applied to the first metallization 2 and the AC output voltage provided on the third metallization 4. The six switches, e.g., form the first switch S1 of the power module 150 of the power converter of FIG. 11. There are further provided six transistors forming switches S21 to S26 between the negative voltage applied to the second metallization 3 and the AC output voltage provided on the third metallization 4. The six switches, e.g., form the second switch S2 of the power module 150 of the power converter of FIG. 11. The number of six switches is to be understood as an example only. There may be implemented another number of switches such as four switches instead. Accordingly, the electric circuit forms two switches of a power converter arranged in series between the positive DC voltage and the negative DC voltage, wherein each of the two switches comprises a plurality of power semiconductors arranged in parallel. In other embodiments, a different numbers of switches may be implemented. It is noted that each switch / transistor S11-S16, S21-S26 comprises individual inputs for the gate G and for the source S, which makes a total of 24 signals in the depicted embodiment. FIG. 8 depicts an arrangement in which the power module 10 of FIG. 5 is thermally coupled on its lower side to a heat sink 9 depicted schematically. Further, the power module 10 is electrically connected at its upper side to a printed circuit board 30. The printed circuit board provides connections to the first, second and third metallizations 2, 3, 4 as well as the input signals for the gates G and the sources S of the semiconductor packages 5. The manner in which the power module 10 is electrically connected to the printed circuit board 30 may be chosen from well-known techniques. For example, the respective metallizations and semiconductor package pins are contacted through pins or spring terminals that extend vertically from the upper surface 110 of the power module 10 with a respective contact area of the printed circuit board 30. Such vertical pins 95 are shown schematically in FIG. 8. It is pointed out that FIG. 8 is a schematic depiction only. For example, the lower side of the power module 10 may be thermally coupled to the heat think 9 through a thermal interface material. The upper side of the power module 10 may be connected to the printed circuit board 30 through a plastic material. Also, the pins 95 connecting the printed circuit board 30 and the ceramic are depicted in a schematic manner only. For example, they may have an S-like bend in them to account for thermal expansion. As mentioned before, in the depicted embodiment, a total of 24 signals need to be provided for the gates G and sources S of the 12 switch / transistors S11-S16, S21-S26. Accordingly, such high number of through-hole connections etc. needs to be implemented in the printed circuit board 30. To avoid this, an interposer printed circuit board may be provided for the gate driver signals and the source signals. The circuit implemented by such interposer printed circuit board is depicted in FIG. 9. The interposer printed circuit board receives 4 signals from the main circuit board only, namely, a high side common source signal, a high side common gate signal, a low side common source signal and a low side common gate signal (“high side” meaning the positive side and “low side” meaning the negative side). These four input signals are distributed through the interposer printed circuit board to the total of 24 output signal divided as high side gate signals, high side source signals, low side gate signals and low side source signals to the respective switches / transistors S11-S16, S21-S26. As the number of through-hole connections necessary in the main printed circuit board is reduced, the power handling capability of the main printed circuit board is increased. FIG. 10 shows a corresponding arrangement, wherein compared to FIG. 8 an interposer printed circuit board 35 is arranged between the power module 10 and the main (power) printed circuit board 30. As mentioned, the semiconductor packages 5 may be of the D2PAK-7 package type, which are off-the-shelf available. The capacitors 6 may be formed by ceramic capacitors which are also available off-the-shelf. The ceramic substrate 1 may be a Si3N4 or AIN substrate on which the metallizations 2, 3, 4 are connected by direct copper bonding (DBG) or active metal brazing (AMB). It should be understood that the above description is intended for illustrative purposes only, and is not intended to limit the scope of the present disclosure in any way. Also, those skilled in the art will appreciate that other aspects of the disclosure can be obtained from a study of the drawings, the disclosure and the appended claims. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. Various features of the various embodiments disclosed herein can be combined in different combinations to create new embodiments within the scope of the present disclosure. In particular, the disclosure extends to and includes all combinations and sub-combinations of one or more features described herein. Any ranges given herein include any and all specific values within the range and any and all sub-ranges within the given range.

Claims

1. A power converter arrangement comprising:a ceramic substrate (1) having an upper side (11) and a lower side (12);a plurality of first metallizations (2) arranged on the upper side (1), wherein the first metallizations (2) are configured to be connected to a first DC voltage;a plurality of second metallizations (3) arranged on the upper side (11), wherein the second metallizations (3) are configured to be connected to a second DC voltage;a third metallization (4) arranged on the upper side (11), wherein the third metallization (4) is configured to provide an AC output voltage; anda plurality of discrete packaged semiconductor packages (5) arranged on the upper side (11) of the ceramic substrate (1), wherein each semiconductor package (5) is connected to one of the first and second metallizations (2, 3) and to the third metallization (4);wherein the semiconductor packages (5) are configured to form a power converter circuit (15) ora part (150) thereof with an output AC voltage on the third metallization (4).

2. The power converter arrangement of claim 1, further comprising capacitors (6) arranged on the upper side (11) of the ceramic substrate (1), each capacitor (6) connecting one of the first metallizations (2) and one of the second metallizations (3).

3. The power converter arrangement of claim 2, wherein the first and second metallizations (2, 3) are formed as patches (20, 30), wherein two neighboring patches (20, 30) of the first and second metallizations (2, 3) are each connected through a capacitor (6).

4. The power converter arrangement of any preceding claim, wherein the lower side (12) of the ceramic substrate (1) comprises a large area fourth metallization (7) configured to thermally couple the ceramic substrate (1) to a heat sink (9).

5. The power converter arrangement of any preceding claim, wherein each semiconductor package (5) comprises a power semiconductor (S11-S16, S21-S26) with a gate connection (51), a source connection (52) and a drain connection (50), wherein the drain connection (50) is a bottom side metallization of the semiconductor package (5), and wherein the drain connection (50) is connected to the first metallization (2) or the third metallization (4).

6. The power converter arrangement of claim 5, wherein the bottom side metallization (50) is configured to act as a heat spreader for the semiconductor package (5).

7. The power converter arrangement of claim 5 or 6, wherein the source connection (52) and the gate connection (51) are pin connections, wherein the pin connections are connected by separate contacting means.

8. The power converter arrangement of any preceding claim, wherein the top side (11) of the ceramic substrate (1) including the semiconductor packages (5) is coated or potted, the coating or potting (8) providing for a cuboid module (10) having a flat top surface (110) configured to be attached to a printed circuit board (20).

9. The power converter arrangement of claim 8, further comprising a printed circuit board (30, 35) attached to the top surface (110) of the module (10).

10. The power converter arrangement of claim 9, wherein the printed circuit board is a main printed circuit board (35) that comprises a gate driver for the semiconductor packages (5).

11. The power converter arrangement of claim 9, when dependent on claim 5, wherein the printed circuit board is an interposer printed circuit board (35) configured to provide gate signals and source signals to the gate connections (51) and the source connections (52) of the semiconductor packages (5), wherein the interposer printed circuit board (35) is connected to a main printed circuit board (30), wherein the main printed circuit board (30) provides to the interposer printed circuit board (35) a high side source signal, a high side gate signal, a low side source signal, and a low side gate signal.

12. The power converter arrangement of any preceding claim, wherein the semiconductor packages (5) are of the kind that comprises one bottom contact and several pins.

13. The power converter arrangement of any preceding claim, wherein the first, second and third metallizations (2, 3, 4) are provided by copper layers.

14. The power converter arrangement of any preceding claim, wherein the first, second and third metallizations (2, 3, 4) are connected to the ceramic substrate (1) by direct copper bonding or active metal brazing.

15. The power converter arrangement of any preceding claim, wherein the ceramic substrate (1) is made of aluminum nitride or silicone nitride.

16. The power converter arrangement of any preceding claim, wherein the first and second metallizations (2, 3) are arranged along a first line (17) and a second line(18), wherein along each of the first and second lines (17, 18) the first and the second metallizations (2, 3) are formed as patches (20, 30) and are arranged alternately, and wherein the third metallization (4) is arranged along a third line (19), wherein the third line (19) is arranged between the first and second lines (17, 18).5 17. The power converter arrangement of any preceding claim, wherein thesemiconductor packages (5) are configured to form two switches (S1, S2; S3, S4; S5, S6) of a power converter circuit (15) arranged in series between the positive DC voltage and the negative DC voltage, wherein each of the two switches (S1, S2; S3, S4; S5, S6) comprises a plurality of power semiconductors (S11 -S16, S21-S26)10 arranged in parallel.

Images