Reliability enhancement for monolithically integrated transistors

Abstract

Integrated circuit 200 includes substrate 202 comprising first sub-region 202a enclosed by junction structure 224 and second sub-region 202b outside the junction structure. The integrated circuit includes first compound transistor 204a over the first sub-region and comprising first metal interconnect structure 216a electrically contacted to the first sub-region and junction structure and second compound transistor 204b over the second sub-region and comprising second metal interconnect structure 216b electrically contacted to the second sub-region. The first metal interconnect structure may comprise a source contact 214a and a body contact 216a. The first sub-region and second sub-region each may comprise one of a P-type doped region and N-type doped region. The junction structure may be the other of a P-type doped region and N-type doped region (e.g., a P-well ring or an N-well ring). The second sub-region may be enclosed by a second junction structure.

Description

Semiconductor device fabrication is a process used to create integrated circuits that are present in many electrical and electronic devices. It is a multiple-step sequence of photolithographic, mechanical, and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconducting material. For example, during semiconductor device fabrication, numerous discrete circuit components, including transistors, resistors, capacitors, inductors, and diodes may be formed on a single semiconductor die. A transistor is a semiconductor device with many uses. Generally speaking, a transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is composed of semiconductor material usually with at least three terminals for connection to an external circuit. Typically, a voltage or current applied to one pair of the transistor’s terminals controls the current through another pair of terminals. One common type of transistor is a field-effect transistor (FET). A typical FET comprises an insulated gate, whose voltage determines the conductivity of the device as seen between two other non-gate terminals of the device, known as a drain terminal and a source terminal. The FET’s ability to change conductivity with the amount of applied voltage allows it to be used for amplifying or switching electronic signals. FETs may be formed from numerous semiconductor materials, including without limitation, silicon (Si) and gallium nitride (GaN). For example, in some instances, GaN FETs may be formed upon an Si substrate. For example, as shown in FIGURES 1A and IB, multiple GaN FETs may be monolithically integrated on a common Si substrate. FIGURE 1A illustrates a cross-sectional side elevation view of a portion of an example circuit die 100A comprising a Si substrate 102 with two monolithically integrated GaN FETs 104 (e.g., high-side FET 104a and low-side FET 104b) formed thereon and an equivalent circuit diagram, as is known in the art. As shown in FIGURE 1 A, a buffer layer 106 of aluminum gallium nitride (AlGaN) and / or aluminum nitride (AIN) may be formed over substrate 102 and a channel layer 108 of unintentional-doped GaN may be formed over buffer layer 106. A barrier layer 110 of AlGaN may be formed over channel layer 108. Drain terminals 112 and source terminals 114 may be formed upon barrier layer 110, and gate layer 116 may be formed upon barrier layer 110, with gate metals 118 formed over gate layer 116. Dielectric material 120 (e.g., oxide or silicone nitride) may be formed on circuit die 100A and appropriately patterned in order to electrically isolate the various terminals from one another, as well as electrically isolate high-side FET 104a from low-side FET 104b. Metallization layer 122 may be added and appropriately patterned to allow electrical coupling of the various terminals to voltage rails (e.g., a source voltage VDD and a ground voltage GND) and / or other circuits integrated within circuit die 100A or external to circuit die 100A. As shown in FIGURE 1A, source terminal 114b of low-side FET 104b may be formed through buffer layer 106, channel layer 108, and barrier layer 110, thus tying source terminal 114b to substrate 102. One disadvantage of this approach is that a high electric field may exist between substrate 102 and the terminals of high-side FET 104a, which may degrade the reliability of high-side FET 104a. FIGURE IB illustrates a cross-sectional side elevation view of a portion of an example circuit die 100B comprising a Si substrate 102 with two monolithically integrated GaN FETs 104 (e.g., high-side FET 104a and low-side FET 104b) formed thereon and an equivalent circuit diagram, as is known in the art. Example circuit die 100B shown in FIGURE IB may be similar in many respects to example circuit die 100A of FIGURE 1A, except that rather than source terminal 114b of low-side FET 104b being electrically tied to substrate 102, source terminal 114a of high-side FET 104a may be electrically tied to substrate 102. One disadvantage of this approach is that a high electric field may exist between substrate 102 and the terminals of low-side FET 104b, which may degrade the reliability of low-side FET 104b. Accordingly, fabrication techniques that reduce or eliminate these disadvantages may be desired. SUMMARY In accordance with the teachings of the present disclosure, certain disadvantages and problems associated with existing approaches to manufacturing FETs may be reduced or eliminated. In accordance with embodiments of the present disclosure, an integrated circuit may include a substrate comprising a first sub-region enclosed by a junction structure and a second sub-region outside the junction structure. The integrated circuit may also include a first compound transistor formed over the first sub-region and comprising a first metal interconnect structure electrically contacted to the first sub-region and the junction structure and a second compound transistor formed over the second sub-region and comprising a second metal interconnect structure electrically contacted to the second sub-region. In accordance with these and other embodiments of the present disclosure, an integrated circuit may include a substrate comprising a sub-region surrounded by a junction structure, wherein the sub-region and the junction structure comprise a surface of the substrate. The integrated circuit may also include a compound transistor formed over the surface and comprising a metal interconnect structure contacted to the sub-region. In accordance with these and other embodiments of the present disclosure, a method may include forming, in a substrate, a first sub-region enclosed by a junction structure and a second sub-region outside the junction structure, forming a first compound transistor over the first sub-region, the first compound transistor comprising a first metal interconnect structure, electrically contacting the first metal interconnect structure to the first sub-region and the junction structure, forming a second compound transistor over the second subregion, the second compound transistor comprising a second metal interconnect structure, and electrically contacting the second metal interconnect structure to the second sub-region. In accordance with these and other embodiments of the present disclosure, a method may include forming a sub-region surrounded by a junction structure in a substrate, wherein the sub-region and the junction structure comprise a surface of the substrate. The method may also include forming a compound transistor over the surface, wherein the compound transistor comprises a metal interconnect structure. The method may further include contacting the compound transistor to the sub-region. Technical advantages of the present disclosure may be readily apparent to one having ordinary skill in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are explanatory examples and are not restrictive of the claims set forth 5 in this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein: FIGURE 1A illustrates a cross-sectional side elevation view of a portion of an example circuit die comprising a Si substrate with two monolithically integrated GaN FETs formed thereon and an equivalent circuit diagram, as is known in the art; FIGURE IB illustrates a cross-sectional side elevation view of a portion of another example circuit die comprising a Si substrate with two monolithically integrated GaN FETs formed thereon and an equivalent circuit diagram, as is known in the art; FIGURE 2A illustrates a cross-sectional side elevation view of a portion of an example circuit die comprising a lightly P-type doped Si substrate with two monolithically integrated GaN FETs formed thereon, in accordance with embodiments of the present disclosure; FIGURE 2B illustrates a top-down plan view of a high-side FET formed in the example circuit die of FIGURE 2A, in accordance with embodiments of the present disclosure; FIGURE 2C illustrates a top-down plan view of a low-side FET formed in the example circuit die of FIGURE 2A, in accordance with embodiments of the present disclosure; FIGURE 3 illustrates an equivalent circuit diagram for the two monolithically integrated GaN FETs in the example circuit die of FIGURE 2A, in accordance with embodiments of the present disclosure; FIGURE 4 illustrates a cross-sectional side elevation view of a portion of another example circuit die comprising a lightly P-type doped Si substrate with two monolithically integrated GaN FETs formed thereon, in accordance with embodiments of the present disclosure; FIGURE 5 illustrates a cross-sectional side elevation view of a portion of yet another example circuit die comprising a lightly P-type doped Si substrate with two monolithically integrated GaN FETs formed thereon, in accordance with embodiments of the present disclosure; FIGURE 6 illustrates a cross-sectional side elevation view of a portion of yet another example circuit die comprising a lightly P-type doped Si substrate with two monolithically integrated GaN FETs formed thereon, in accordance with embodiments of the present disclosure; FIGURE 7 illustrates a cross-sectional side elevation view of a portion of yet another example circuit die comprising a lightly P-type doped Si substrate with two monolithically integrated GaN FETs formed thereon, in accordance with embodiments of the present disclosure; FIGURE 8 illustrates a cross-sectional side elevation view of a portion of yet another example circuit die comprising a lightly P-type doped Si substrate with two monolithically integrated GaN FETs formed thereon, in accordance with embodiments of the present disclosure; FIGURE 9A illustrates a cross-sectional side elevation view of a portion of yet another example circuit die comprising a lightly P-type doped Si substrate with two monolithically integrated GaN FETs formed thereon, in accordance with embodiments of the present disclosure; FIGURE 9B illustrates a top-down plan view of a high-side FET formed in the example circuit die of FIGURE 9A, in accordance with embodiments of the present disclosure; FIGURE 9C illustrates a top-down plan view of a low-side FET formed in the example circuit die of FIGURE 9A, in accordance with embodiments of the present disclosure; FIGURE 10 illustrates an equivalent circuit diagram for the two monolithically integrated GaN FETs in the example circuit die of FIGURE 9A, in accordance with embodiments of the present disclosure; FIGURE 11A illustrates a cross-sectional side elevation view of the circuit die of FIGURES 2A-2C after a first step of a fabrication process, in accordance with embodiments of the present disclosure; FIGURES 11B and 11C respectively illustrate a top-down plan view of the high-side FET of FIGURE 2B and a top-down plan view of the low-side FET of FIGURE 2C after the first step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURE 12A illustrates a cross-sectional side elevation view of the circuit die of FIGURES 2A-2C after a second step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURES 12B and 12C respectively illustrate a top-down plan view of the high-side FET of FIGURE 2B and a top-down plan view of the low-side FET of FIGURE 2C after the second step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURE 13 A illustrates a cross-sectional side elevation view of the circuit die of FIGURES 2A-2C after a third step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURES 13B and 13C respectively illustrate a top-down plan view of the high-side FET of FIGURE 2B and a top-down plan view of the low-side FET of FIGURE 2C after the third step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURE 14A illustrates a cross-sectional side elevation view of the circuit die of FIGURES 2A-2C after a fourth step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURES 14B and 14C respectively illustrate a top-down plan view of the high-side FET of FIGURE 2B and a top-down plan view of the low-side FET of FIGURE 2C after the fourth step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURE 15A illustrates a cross-sectional side elevation view of the circuit die of FIGURES 2A-2C after a fifth step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURES 15B and 15C respectively illustrate a top-down plan view of the high-side FET of FIGURE 2B and a top-down plan view of the low-side FET of FIGURE 2C after the fifth step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURE 16A illustrates a cross-sectional side elevation view of the circuit die of FIGURES 2A-2C after a sixth step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURES 16B and 16C respectively illustrate a top-down plan view of the high-side FET of FIGURE 2B and a top-down plan view of the low-side FET of FIGURE 2C after the sixth step of the fabrication process, in accordance with embodiments of the present disclosure; FIGURE 17A illustrates a cross-sectional side elevation view of the circuit die of FIGURES 2A-2C after a seventh step of the fabrication process, in accordance with 5 embodiments of the present disclosure; and FIGURES 17B and 17C respectively illustrate a top-down plan view of the high-side FET of FIGURE 2B and a top-down plan view of the low-side FET of FIGURE 2C after the seventh step of the fabrication process, in accordance with embodiments of the present disclosure. 10 DETAILED DESCRIPTION FIGURE 2A illustrates a cross-sectional side elevation view of a portion of an example circuit die 200 comprising a lightly P-type doped Si substrate 202 with two monolithically integrated GaN FETs 204 (e.g., high-side FET 204a and low-side FET 204b) formed thereon, in accordance with embodiments of the present disclosure. FIGURE 2B illustrates a top-down plan view of high-side FET 204a (with dielectric material removed, for purposes of clarity and exposition), in accordance with embodiments of the present disclosure. FIGURE 2C illustrates a top-down plan view of low-side FET 204b (with dielectric material removed, for purposes of clarity and exposition), in accordance with embodiments of the present disclosure. FIGURE 3 illustrates an equivalent circuit diagram for monolithically integrated GaN FETs 204, in accordance with embodiments of the present disclosure. As shown in FIGURES 2A-2C, circuit die 200 may include lightly P-type doped Si substrate 202. During fabrication, as described in greater detail below, substrate 202 may be effectively separated into two sub-regions, a first sub-region 202a and a second subregion 202b. First sub-region 202a and second sub-region 202b may be formed and separated by an N-well 224 that is formed below high-side FET 204a and encloses subregion 202a. As shown in FIGURES 2A-2C, N-well 224 may be formed by a predominantly horizontal N-type doped region 226 implanted into substrate 202 at a depth d (e.g., d = 50nm), and a predominantly vertical highly N-type doped N-well ring 228 implanted into substrate 202 between the depth d and a surface of substrate 202. Thus, N-type doped region 226 may serve as the bottom of N-well 224 and N-well ring 228 may serve as the side walls of N-well 224. The fabrication of N-type doped region 226 may leave a floating N-well 230 below low-side FET 202b. Further, a predominantly horizontal highly P-type doped region 232 may be implanted into first subregion 202a and N-type doped region 226 and just below the surface of substrate 202. In the same process step or another process step as the implantation of highly P-type doped region 232, a highly P-type doped region 234 may be implanted just below the surface of substrate 202. As also shown in FIGURES 2A-2C, a buffer layer 206 may be formed over substrate 202 and a channel layer 208 of GaN may be formed over buffer layer 206. A barrier layer 210 of AlGaN may be formed over channel layer 208. Buffer layer 206, channel layer 208, and barrier layer 210 may be patterned to electrically isolate high-side FET 204a from low-side FET 204b. Drain terminals 212 and source terminals 214 may be formed through layer 210 to contact channel layer 208, and a gate layer (not explicitly shown) may be formed upon channel layer 208, with gate terminals 218 formed over the gate layer. Further, body terminals 216 may be formed such that body terminal 216a is in electrical contact with N-well 224, and body terminal 216b is in electrical contact with highly P-type doped region 234. Further, body terminal 216a may be electrically isolated from second sub-region 202b. Drain terminals 212, source terminals 214, body terminals 216, and gate terminals 218 may be formed with a metallization layer deposited upon circuit die 200 and appropriately patterned to create such terminals and to allow electrical coupling of the various terminals to voltage rails (e.g., an input voltage Vin and a ground voltage GND) and / or other circuits integrated within circuit die 200 or external to circuit die 200. Further, as shown in FIGURES 2A-2C, such metallization layer may be patterned to electrically short source terminal 214a to body terminal 216a and electrically short source terminal 214b to body terminal 216b. Dielectric material 220 (e.g., oxide or silicon nitride) may be formed on circuit die 200 and appropriately patterned in order to electrically isolate the various terminals from one another, as well as electrically isolate high-side FET 204a from low-side FET 204b. To ensure sufficient electrical isolation between first sub-region 202a and second sub-region 202b, the doping of N-well 224 may be greater than the doping of substrate 202. For example, substrate 202 may comprise a lightly-doped P-type substrate with a doping concentration of approximately 1014 / cm3 to approximately 1015 / cm3, while N-well 224 may have at least 100 times greater doping concentration than substrate 202, such as highly-doped N-type substrate with a doping concentration of approximately 1016 / cm3 to approximately 1020 / cm3, to ensure that a high electric field will not penetrate into the GaN stack of high-side FET 204a. Further, depth d must be sufficiently deep (e.g., at least 50nm) to prevent full depletion of first sub-region 202a during operation, which may cause high-side FET 204a to lose its back-gate control. In addition, to prevent full depletion of first sub-region 202a during operation, the doping concentration of highly P-type doped region 232 may be significantly greater (e.g., 100 times or more greater) than the doping concentration of N-well 224. FIGURE 4 illustrates a cross-sectional side elevation view of a portion of an example circuit die 400 comprising a lightly P-type doped Si substrate 202 with two monolithically integrated GaN FETs 204 (e.g., high-side FET 204a and low-side FET 204b) formed thereon, in accordance with embodiments of the present disclosure. Circuit die 400 of FIGURE 4 may be similar in many respects to circuit die 200 of FIGURES 2A-2C. Accordingly, only certain differences between circuit die 400 and circuit die 200 are described herein. Notably, one difference between circuit die 200 and circuit die 400 is that in circuit die 400, the metallization may be formed and patterned such that N-well 224 is electrically tied to drain terminal 212a of high-side FET 204a, which may receive input voltage Vin, which may be the highest voltage within the circuit including FETs 204. By tying drain terminal 212a to N-well 224, N-well 224 may provide electrical isolation between first sub-region 202a and second subregion 202b. FIGURE 5 illustrates a cross-sectional side elevation view of a portion of an example circuit die 500 comprising a lightly P-type doped Si substrate 202 with two monolithically integrated GaN FETs 204 (e.g., high-side FET 204a and low-side FET 204b) formed thereon, in accordance with embodiments of the present disclosure. Circuit die 500 of FIGURE 5 may be similar in many respects to circuit die 200 of FIGURES 2A-2C. Accordingly, only certain differences between circuit die 500 and circuit die 200 are described herein. Notably, one difference between circuit die 200 and circuit die 500 is that in circuit die 500, highly P-type doped region 234 may be extended horizontally in the x-y plane to underlie the terminals of low-side FET 204b. As a result of fabrication process, floating N-well 230 may also extend horizontally in the x-y plane to underlie the extended highly P-type doped region 234. Such increased dimensions of highly P-type doped region 234 of circuit die 500, as compared to highly P-type doped region 234 of circuit die 200, may be an improvement of a back-bias control of low-side FET 204b and increased voltage uniformity under low-side FET 204b. FIGURE 6 illustrates a cross-sectional side elevation view of a portion of an example circuit die 600 comprising a lightly P-type doped Si substrate 202 with two monolithically integrated GaN FETs 204 (e.g., high-side FET 204a and low-side FET 204b) formed thereon, in accordance with embodiments of the present disclosure. Circuit die 600 of FIGURE 6 may be similar in many respects to circuit die 200 of FIGURES 2A-2C. Accordingly, only certain differences between circuit die 600 and circuit die 200 are described herein. Notably, one difference between circuit die 200 and circuit die 600 is that in circuit die 600, an additional lithography and implantation process step may be used to separately define highly P-type doped region 232 and highly P-type doped region 234 from N-type doped region 226. In other words, while circuit die 200 may use a common lithography step to concurrently define highly P-type doped regions 232 / 234 and N-type doped region 226, circuit die 200 may use independent steps. As a result, the artifact of floating N-well 230 may not be present in circuit die 600. FIGURE 7 illustrates a cross-sectional side elevation view of a portion of an example circuit die 700 comprising a lightly P-type doped Si substrate 202 with two monolithically integrated GaN FETs 204 (e.g., high-side FET 204a and low-side FET 204b) formed thereon, in accordance with embodiments of the present disclosure. Circuit die 700 of FIGURE 7 may be similar in many respects to circuit die 200 of FIGURES 2A-2C. Accordingly, only certain differences between circuit die 700 and circuit die 200 are described herein. Notably, one difference between circuit die 200 and circuit die 700 is that in circuit die 700, each of the body terminals 216 are in contact with the buffer layer 206, channel layer 208, and layer 210 of their respective FET stacks. In some embodiments, body terminals 216 may be in contact with implanted portions 206a, 208a, and 210a of buffer layer 206, channel layer 208, and layer 210, respectively. In some embodiments, implanted portions 206a, 208a, and 210a may be formed using a nitrogen implantation process, thus becoming semi-insulating layers. Compared to circuit die 200, circuit die 700 may be smaller in size. FIGURE 8 illustrates a cross-sectional side elevation view of a portion of an example circuit die 800 comprising a lightly P-type doped Si substrate 202 with two monolithically integrated GaN FETs 204 (e.g., high-side FET 204a and low-side FET 204b) formed thereon, in accordance with embodiments of the present disclosure. Circuit die 800 of FIGURE 8 may be similar in many respects to circuit die 200 of FIGURES 2A-2C. Accordingly, only certain differences between circuit die 800 and circuit die 200 are described herein. Notably, one difference between circuit die 200 and circuit die 800 is that in circuit die 800, body terminals 216 may be absent, and source terminals 214 may be formed vertically through buffer layer 206, channel layer 208, and barrier layer 210. Further, source terminal 214a may be in electrical contact with first sub-region 202a while source terminal 214b may be in electrical contact with second sub-region 202b. Compared to circuit die 200, circuit die 800 may be smaller in size. FIGURE 9A illustrates a cross-sectional side elevation view of a portion of an example circuit die 900 comprising a lightly P-type doped Si substrate 202 with two monolithically integrated GaN FETs 204 (e.g., high-side FET 204a and low-side FET 204b) formed thereon, in accordance with embodiments of the present disclosure. FIGURE 9B illustrates a top-down plan view of high-side FET 204a (with dielectric material removed, for purposes of clarity and exposition), in accordance with embodiments of the present disclosure. FIGURE 9C illustrates a top-down plan view of low-side FET 204b (with dielectric material removed, for purposes of clarity and exposition), in accordance with embodiments of the present disclosure. FIGURE 10 illustrates an equivalent circuit diagram for monolithically integrated GaN FETs 204, in accordance with embodiments of the present disclosure. Circuit die 900 of FIGURES 9A-9C may be similar in many respects to circuit die 200 of FIGURES 2A-2C. Accordingly, only certain differences between circuit die 900 and circuit die 200 are described herein. Notably, one difference between circuit die 200 and circuit die 900 is that in circuit die 900, a second N-well 924, similar to N-well 224, may be embedded in substrate 202 formed below low-side FET 204b, such that second subregion 202b is fully enclosed by N-well 924. Compared to circuit die 200, circuit die 900 may enable all FETs 204 to be free from high-electric field, thus improving reliability. Further, by adding additional N-wells, circuit die 900 may be able to accommodate additional voltage domains. One or more additional N-wells, similar or identical to N-well 924, may also be added to any of circuit dies 200, 400, 500, 600, 700, or 800. In each of circuit dies 200, 400, 500, 600, 700, 800, and 900, all doping polarities (e.g., P-type and N-type) within substrate 202 may have the opposite polarities than those discussed above. For example, P-type Si substrates may be changed to N-type Si substrates, with N-wells being changed to P-wells, and highly-doped P+ regions changed to highly-doped N+ regions. An example fabrication process for fabricating circuit die 200 is described below with reference to FIGURES 11A-17C. However, a fabrication process similar to that described below may also be used to fabricate any of circuit dies 400, 500, 600, 700, 800, and / or 900. FIGURE 11A illustrates a cross-sectional side elevation view of circuit die 200 after a first step of a fabrication process, in accordance with embodiments of the present disclosure. FIGURES 1 IB and 1 IC respectively illustrate a top-down plan view of high-side FET 204a and a top-down plan view of low-side FET 204b after the first step of the fabrication process, in accordance with embodiments of the present disclosure. In this first step, lightly P-type doped substrate 202 may be provided. Substrate 202 may be an Si substrate with a (111) plane, and may be doped at a concentration of approximately 1014 / cm3. FIGURE 12A illustrates a cross-sectional side elevation view of circuit die 200 after a second step of the fabrication process, in accordance with embodiments of the present disclosure. FIGURES 12B and 12C respectively illustrate a top-down plan view of high-side FET 204a and a top-down plan view of low-side FET 204b after the second step of the fabrication process, in accordance with embodiments of the present disclosure. In this second step, multiple ion-implantation processes may be used to form N-well 226, highly P-type doped region 234, floating N-well 230, and highly P-type doped region 232. In some embodiments, these ion-implantation processes may share the same lithography step. For purposes of clarity and exposition, highly P-type doped region 234 is not shown in FIGURE 12B and floating N-well 230 is not shown in FIGURE 12C. FIGURE 13 A illustrates a cross-sectional side elevation view of circuit die 200 after a third step of the fabrication process, in accordance with embodiments of the present disclosure. FIGURES 13B and 13C respectively illustrate a top-down plan view of high-side FET 204a and a top-down plan view of low-side FET 204b after the third step of the fabrication process, in accordance with embodiments of the present disclosure. In this third step, an ion-implantation process may be used to form N-well ring 228, thus forming and defining first sub-region 202a and second sub-region 202b of substrate 202. The doping concentration of N-well ring 228 may be higher than that of highly P-type doped region 234. FIGURE 14A illustrates a cross-sectional side elevation view of circuit die 200 after a fourth step of the fabrication process, in accordance with embodiments of the present disclosure. FIGURES 14B and 14C respectively illustrate a top-down plan view of high-side FET 204a and a top-down plan view of low-side FET 204b after the fourth step of the fabrication process, in accordance with embodiments of the present disclosure. In this fourth step, buffer layer 206, channel layer 208, and barrier layer 210 may be epitaxially grown upon the surface of substrate 202. Buffer layer 206 may comprise AIN, thick AlGaN, or a super-lattice of AlGaN and GaN. For purposes of clarity and exposition, FIGURE 14B depicts N-well 226 and N-well ring 228, although layer 210 would obscure N-well 226 and N-well ring 228 after this fourth step. Further, also for purposes of clarity and exposition, FIGURE 14C depicts highly P-type doped region 234, although layer 210 would obscure highly P-type doped region 234 after this fourth step. FIGURE 15A illustrates a cross-sectional side elevation view of circuit die 200 after a fifth step of the fabrication process, in accordance with embodiments of the present disclosure. FIGURES 15B and 15C respectively illustrate a top-down plan view of high-side FET 204a and a top-down plan view of low-side FET 204b after the fifth step of the fabrication process, in accordance with embodiments of the present disclosure. In this fifth step, a patterning step (e.g., lithography and etch) may be applied to buffer layer 206, channel layer 208, and barrier layer 210 to define high-side FET 204a and low-side FET 204b. FIGURE 16A illustrates a cross-sectional side elevation view of circuit die 200 after a sixth step of the fabrication process, in accordance with embodiments of the present disclosure. FIGURES 16B and 16C respectively illustrate a top-down plan view of high-side FET 204a and a top-down plan view of low-side FET 204b after the sixth step of the fabrication process, in accordance with embodiments of the present disclosure. In this sixth step, dielectric layer 220 may be added (e.g., using lithography, deposition, etching, and polishing) to cover high-side FET 204a and low-side FET 204b. For purposes of clarity and exposition, dielectric layer 220 is not shown in FIGURES 16A and 16B. FIGURE 17A illustrates a cross-sectional side elevation view of circuit die 200 after a seventh step of the fabrication process, in accordance with embodiments of the present disclosure. FIGURES 17B and 17C respectively illustrate a top-down plan view of high-side FET 204a and a top-down plan view of low-side FET 204b after the seventh step of the fabrication process, in accordance with embodiments of the present disclosure. In this seventh step, lithography and metallization may be used to form drain terminals 212, source terminals 214, body terminals 216, and gate terminals 218. Drain terminals 212 and source terminals 214 may be formed to be in electrical contact with channel layer 208. Body terminal 216a may be formed to be in electrical contact with first sub-region 202a and N-well ring 228 while body terminal 216b may be formed to be in electrical contact with second sub-region 202b. Each of gate terminals 218 may protrude into barrier layer 210 a desired amount in order to define a threshold voltage for high-side FET 204a and low-side FET 204b. For purposes of clarity and exposition, dielectric layer 220 is not shown in FIGURES 17Aand 17B. Although FIGURES 11A-17C show specific steps in fabrication of circuit die 200, steps other than those depicted may be used in fabrication of circuit dies 200, 400, 500, 600, 700, 800, and 900. Although the foregoing contemplates reliability enhancements in gallium nitride FETs, identical or similar approaches may be used for FETs or other compound transistors fabricated using other semiconductor materials. The systems and methods described herein may define an integrated circuit (e.g., circuit die 200, 400, 500, 600, 700, 800, 900) comprising a substrate (e.g., substrate 202), a first compound transistor (e.g., high-side FET 204a), and a second compound transistor (e.g., low-side FET 204b). The substrate (e.g., substrate 202) may comprise a first subregion (e.g., first sub-region 202a) and a second sub-region (e.g., second sub-region 202b). The first sub-region (e.g., first-sub-region 202a) may be enclosed by a junction structure (e.g., N-well 224). The second sub-region (e.g., second sub-region 202b) may be outside of a well-region (e.g., N-well 224). The first compound transistor (e.g., high-side FET 204a) may be formed over the first sub-region (e.g., first sub-region 202a), and the first compound transistor (e.g., high-side FET 204a) may comprise a first metal interconnect structure (e.g., body terminal 216a and / or source terminal 214a) electrically contacted to the first sub-region (e.g., first sub-region 202a) and the junction structure (e.g., N-well 224). The second compound transistor (e.g., low-side FET 204b) may be formed over the second sub-region (e.g., second sub-region 202b), and the second compound transistor (e.g., low-side FET 204b) may comprise a second metal interconnect structure (e.g., body terminal 216b and / or source terminal 214b) electrically contacted to the second sub-region (e.g., second sub-region 204b). In some embodiments, the first compound transistor and the second compound transistor may be made of GaN, AIN, boron nitride (BN), silicon carbide (SiC), Gallium Arsenide (GaAs), indium Gallium arsenide (InGaAs), or indium phosphide (InP). The first sub-region (e.g., first sub-region 202a) and the second sub-region (e.g., second sub-region 202b) may comprise a P-type layer, and the junction structure (e.g., N-well 224) may comprise an N-type layer. In such embodiments, the junction structure (e.g., N-well 224) may comprise an N-well ring (e.g., N-well ring 228). Alternately, the first sub-region (e.g., first sub-region 202a) and the second subregion (e.g., second sub-region 202b) may comprise an N-type layer, and the junction structure may comprise a P-type layer. In such embodiments, the junction structure may comprise a P-well ring. Furthermore, the second sub-region (e.g., second sub-region 202b) may be enclosed by another junction structure (e.g., N-well 924) in the substrate (e.g., substrate 202). In addition, the first metal interconnect structure may comprise a source contact (e.g., source terminal 214a) in electrical contact with a channel layer (e.g., channel layer 208) of the first compound transistor (e.g., high-side FET 204a), and the first metal interconnect structure may further comprise a body contact (e.g., body terminal 216a) in electrical contact with the first sub-region (e.g., first sub-region 202a) and the junction structure (e.g., N-well 224). The systems and methods described herein may also define an integrated circuit (e.g., circuit die 200, 400, 500, 600, 700, 800, 900) comprising a substrate (e.g., substrate 202) and a compound transistor (e.g., high-side FET 204a). The substrate (e.g., substrate 200) may comprise a sub-region (e.g., first sub-region 202a) and a junction structure (e.g., N-well 224) surrounding the sub-region (e.g., first sub-region 202a). The sub-region (e.g., first sub-region 202a) and the junction structure (e.g., N-well 224) may include a top surface (e.g., surface of substrate 202). The compound transistor (e.g., high-side FET 204a) may be formed over the top surface (e.g., surface of substrate 202), and the compound transistor (e.g., high-side FET 204a) may comprise a metal interconnect structure (e.g., body terminal 216a and / or source terminal 214a) electrically contacted to the sub-region (e.g., first sub-region 202a). The substrate (e.g., substrate 202) may further comprise a second sub-region (e.g., second sub-region 202b) outside the sub-region (e.g., first subregion 202a), wherein the second sub-region (e.g., second sub-region 202b) comprises the top surface (e.g., surface of substrate 202). The metal interconnect structure (e.g., body terminal 216a and / or source terminal 214a) may electrically contact the junction structure (e.g., N-well 224). The junction structure (e.g., N-well 224) may comprise an N-type layer (e.g., N-well 226 and N-well ring 228), and the sub-region (e.g., first sub-region 202a) may comprise a P-type layer. Alternately, the junction structure may comprise a P-type layer, and the sub-region may comprise an N-type layer. The compound transistor (e.g., high-side FET 204a) may comprise a channel layer (e.g., channel layer 208) electrically contacted to the metal interconnect structure (e.g., body terminal 216a and / or source terminal 214a). The compound semiconductor (e.g., high-side FET 204a) may comprise a source terminal (e.g., source terminal 214a) connecting the metal interconnect structure. As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements. This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set. Although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above. Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale. All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by 5 the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure. 10 Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description. To aid the Patent Office and any readers of any patent issued on this application in 15 interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.

Claims

25WHAT IS CLAIMED IS:

1. An integrated circuit comprising:a substrate comprising:5 a first sub-region enclosed by a junction structure; anda second sub-region outside the junction structure;a first compound transistor formed over the first sub-region and comprising a first metal interconnect structure electrically contacted to the first sub-region and the junction structure; and10 a second compound transistor formed over the second sub-region and comprising asecond metal interconnect structure electrically contacted to the second sub-region.

2. The integrated circuit of Claim 1, wherein:the first sub-region and the second sub-region each comprises a P-type doped 15 region; andthe junction structure comprises an N-type doped region.

3. The integrated circuit of Claim 2, wherein the junction structure is an N-well ring formed in the substrate.

204. The integrated circuit of Claim 1, wherein:the first sub-region and the second sub-region each comprises an N-type doped region; andthe junction structure comprises a P-type doped region.

255. The integrated circuit of Claim 4, wherein the junction structure is a P-well ring formed in the substrate.

6. The integrated circuit of any of Claims 1-5, wherein the second sub-region 30 is enclosed by a second junction structure.

7. The integrated circuit of any of Claims 1-6, wherein the first metal interconnect structure comprises:a source contact in electrical contact with a channel layer of the first compound transistor; and5 a body contact in electrical contact with the first sub-region and the junctionstructure.

8. The integrated circuit of any of Claims 1-7, wherein: the substrate comprises a first semiconductor material; and10 the first compound transistor and the second compound transistor are formed witha second semiconductor material formed over the substrate.

159. The integrated circuit of Claim 8, wherein: the first semiconductor material is silicon; and the second semiconductor material is gallium nitride.15 04 2510. An integrated circuit comprising:a substrate comprising a sub-region surrounded by ajunction structure, wherein the sub-region and the junction structure comprise a surface of the substrate; anda compound transistor formed over the surface and comprising a metal interconnect 5 structure contacted to the sub-region.

11. The integrated circuit of Claim 10, wherein:the substrate further comprises a second sub-region outside the junction structure; and10 the second sub-region comprises the top surface.

12. The integrated circuit of Claim 10 or 11, wherein the metal interconnect structure contacts the junction structure.15 13. The integrated circuit of any of Claims 10-12, wherein:the sub-region comprises a P-type doped region; andthe junction structure comprises an N-type doped region.

14. The integrated circuit any of Claims 10-12, wherein:2 0 the sub-region comprises a N-type doped region; andthe junction structure comprises a P-type doped region.

15. The integrated circuit of any of Claims 10-14, wherein the compound transistor comprises a channel layer vertically over the sub-region and laterally surrounded 2 5 by the j uncti on structure.

16. The integrated circuit of any of Claims 10-15, wherein the metal interconnect structure comprises a source terminal of the compound transistor.

17. The integrated circuit of any of Claims 10-16, wherein:the substrate comprises a first semiconductor material; andthe compound transistor is formed with a second semiconductor material formed over the substrate.

18. The integrated circuit of Claim 17, wherein:the first semiconductor material is silicon; andthe second semiconductor material is gallium nitride.LDCM15 04 2519. A method comprising:forming, in a substrate, a first sub-region enclosed by a junction structure and a second sub-region outside the junction structure;5 forming a first compound transistor over the first sub-region, the first compoundtransistor comprising a first metal interconnect structure;electrically contacting the first metal interconnect structure to the first sub-region and the junction structure;forming a second compound transistor over the second sub-region, the second10 compound transistor comprising a second metal interconnect structure; andelectrically contacting the second metal interconnect structure to the second subregion.

20. The method of Claim 19, wherein:15 the first sub-region and the second sub-region each comprises a P-type dopedregion; andthe junction structure comprises an N-type doped region.

21. The method of Claim 20, wherein the junction structure is an N-well ring 2 0 formed in the substrate.

22. The method of Claim 19, wherein:the first sub-region and the second sub-region each comprises an N-type doped region; and2 5 the junction structure comprises a P-type doped region.

23. The method of Claim 22, wherein the junction structure is a P-well ring formed in the substrate.30 24. The method of any of Claims 19-23, further comprising enclosing thesecond sub-region by a second junction structure.

25. The method of any of Claims 19-24, further comprising:electrical contacting a source contact of the first metal interconnect structure with a channel layer of the first compound transistor; andelectrical contacting a body contact of the first metal interconnect structure with the5 first sub-region and the junction structure.

26. The method of any of Claims 19-25, wherein:the substrate comprises a first semiconductor material; andthe first compound transistor and the second compound transistor are formed with10 a second semiconductor material formed over the substrate.

27. The method of Claim 26, wherein:15the first semiconductor material is silicon; andthe second semiconductor material is gallium nitride.15 04 2528. A method comprising:forming a sub-region surrounded by a junction structure in a substrate, wherein the sub-region and the junction structure comprise a surface of the substrate;forming a compound transistor over the surface, wherein the compound transistor 5 comprises a metal interconnect structure; andcontacting the compound transistor to the sub-region.

29. The method of Claim 28, further comprising forming a second sub-region in the substrate and outside the junction structure, wherein the second sub-region comprises 10 the top surface.

30. The method of Claim 28 or 29, further comprising contacting the metal interconnect structure to the junction structure.15 31. The method of any of Claims 28-30, wherein:the sub-region comprises a P-type doped region; andthe junction structure comprises an N-type doped region.

32. The method of any of Claims 28-30, wherein:2 0 the sub-region comprises a N-type doped region; andthe junction structure comprises a P-type doped region.

33. The method of any of Claims 28-32, wherein the compound transistor comprises a channel layer vertically over the sub-region and laterally surrounded by the 2 5 junction structure.

34. The method of any of Claims 28-33, wherein the metal interconnect structure comprises a source terminal of the compound transistor.

35. The method of any of Claims 28-34, wherein:the substrate comprises a first semiconductor material; andthe compound transistor is formed with a second semiconductor material formed over the substrate.

536. The method of Claim 35, wherein:the first semiconductor material is silicon; andthe second semiconductor material is gallium nitride.10LDCM37

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