UV optoelectronic devices

Abstract

A UV optoelectronic device (e.g., a UVC LED, laser, or photodetector) comprising a group III-V (e.g., n-AlGaN) semiconductor substrate with a patterned surface having nanostructure cores with pyramidal or conical tips. A III-V layer is on the nanostructure cores, which may comprise an n-AlGaN layer, a multiple quantum well layer, a p-AlGaN layer, a p-GaN layer, and a metallic p-contact, with part of the III-V layer being pyramidal or conical. The nanostructure cores and III-V layer, or only the group III-V layer, form a p-n or p-i-n junction. A process of preparing the UV optoelectronic device may comprise etching the III-V semiconductor layer to form the substrate. The III-V semiconductor layer, and any doped or undoped sub-layers, may be on a support comprising an oxide layer. The III-V layer may be grown on the nanostructure core and the support layer may be removed using chemical etching or laser lift-off.

Description

Field of the Invention This invention concerns UV optoelectronic devices comprising nanostructure cores patterned on a substrate. The devices comprise at least one group IIl-V layer positioned on top of said nanostructure cores, wherein at least part of said group 11 l-V layer is either pyramidal or conical in shape. Background UV optoelectronic devices, such as deep UV light-emitting diodes (DUV LEDs) with light emission in the 200-300 nm wavelength range, are in high demand, not only to replace traditional large and toxic mercury lamps, but to serve the fastgrowing market of applications in the biomedical sector, such as sterilisation and water disinfection. Besides the obvious benefit of being non-toxic, group Ill-V-based semiconductor optoelectronic devices also have the advantages of being much smaller and cost-efficient requiring only low voltages and are thus highly integrable. Over recent years, the interest in devices based on semiconductor nanostructures has intensified as nanotechnology becomes an important engineering discipline in light emission and light absorption devices. Electronic devices such as DUV LEDs are commonly based on group-Ill nitride p-n or p-i-n junctions, mostly in thin film heterostructures. Their overall efficiency (wall-plug efficiency, WPE) describes the ability of the device to convert electrical input power to optical output power. Among the factors playing into the WPE are the internal quantum efficiency (IQE), light extraction efficiency (LEE) and electric efficiency (EE). A type of previously-demonstrated nanostructured UV optoelectronic device is one in which nanostructures are grown on a substrate. Such ‘bottom-up’ growth typically involves growing nanostructure cores on a planar substrate by depositing material using epitaxial methods such as MOCVD / MOVPE. However, devices with ‘bottom-up’ grown nanostructures can suffer from a number of problems. Typically, such devices require mask layers, buffer layers, nucleation holes, nucleation nanoislands etc. to either aid in the nucleation of the nanostructures or to aid in their positioning. There is also an interface or boundary between the substrate and the nanostructure core, since these are often made of compositionally different materials. The introduction of these features can reduce the efficiency of the device, either by the introduction of impurities from the processes required or by the very nature of the introduced feature. For example, a GaN buffer layer is absorbent to UVC and therefore can reduce the efficiency of a UV device. The process of selectively growing a less absorbent or even UVC transparent AIGaN buffer layer with high crystal quality on the other hand is very challenging. Furthermore, a mask layer formed from the often-used material SiO2 is reflective and therefore also reduces the efficiency of the device. The present inventors sought to address one or more of the above problems and have surprisingly found that UV optoelectronic devices with beneficial light extraction efficiency (LEE) can be obtained when such devices comprise group lll-V substrates which are patterned with nanostructure cores, and which have lll-V layers positioned thereon. The cores and lll-V layers are substantially pyramidal or conical in shape. The nanostructure cores protrude from the substrate as a result of ‘top-down’ etching of a substrate precursor layer, and are different to ‘bottom-up’ grown nanostructure cores which have been formed via deposition methods. The fact that nanostructure cores are formed from the same material as the rest of the substrate is beneficial since it results in a compositionally purer substrate / nanostructure feature which does not suffer from the aforementioned issues with ‘bottom-up’ grown nanostructures. The process is also considerably simplified. Moreover, the smaller dimensions of pyramidal or conical cores and lll-V layers, compared to thin film alternatives, allow better strain management and provide a larger emitting area per chip area. In contrast to other types of interfaces (e.g., polar or non-polar) the semipolar interfaces present in pyramidal or conical nanostructures provide special physical properties in terms of charge carrier distribution and light-matter-interaction. In the case of UV LEDs, highly TM-polarized light can result from the semipolar interfaces. In addition, polar surfaces induce an effect called the quantum confined Stark effect, which is an undesired effect in LEDs. The semipolar plane will, due to the reduced polarity, also have a reduced quantum confined Stark effect. These physical properties can be exploited to improve radiative recombination efficiency, leading to increased internal quantum efficiency (IQE) and light extraction efficiency (LEE) in LEDs in particular. As a result, the wall plug efficiency (WPE) of the structures is improved compared to standard thin film LEDs. Summary of the Invention Viewed from a first aspect, the invention provides a UV optoelectronic device comprising: a group 11 l-V semiconductor substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips; at least one group 11 l-V layer positioned on top of said nanostructure cores, wherein at least part of said at least one group 11 l-V layer is pyramidal or conical; wherein said nanostructure cores and the at least one group 11 l-V layer form a p-n or a p-i-n junction, or wherein the at least one group 11 l-V layer forms a p-n or p-i-n junction. Viewed from another aspect, the invention provides a process for preparing a UV optoelectronic device as defined herein, comprising: (I) etching a group 11l-V semiconductor layer to form a substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips; (II) growing said at least one 11 l-V layer on top of said nanostructure cores. Viewed from another aspect, the invention provides a process for preparing a UV optoelectronic device as defined herein, comprising: (I) etching a group 11l-V semiconductor layer to form a substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips, wherein said Ill-V semiconductor layer, and optionally any doped or undoped sub-layer(s), are positioned on top of a support comprising an oxide layer; (II) growing said at least one 11 l-V layer on top of said nanostructure core; (III) removing the support layer through a lift-off technique such as chemical etching or laser lift-off. The features of the aspects and / or embodiments indicated herein are useable individually and in combination in all aspects and embodiments of the invention where technically viable, unless otherwise indicated. Brief Description of the Figures Figure 1 shows the top-down etching of 11 l-V semiconductor layer to form a substrate (i.e. patterned substrate) as defined herein. The substrate can be seen as comprising a base region (alternatively called a non-protruding region or nonpatterned region) and a patterned region (alternatively called a protruding region or nano-patterned surface structure). Both regions are formed of the same material. The Figure shows a cone rod or pyramid rod as the nanostructure core, but the invention is not so limited. Figure 2a illustrates a device in which the substrate comprises a patterned AIGaN substrate with pyramid rods or cone rods as nanostructure cores. The device comprises multiple 11 l-V layers disposed on the nanostructure cores. Between the nanostructure cores, there are interstitial voids with a width F and a height G, wherein F and G are both independently in the range of 0 to 2 pm. The internal pyramidal angle of the nanostructure core and the at least one 11 l-V layer is typically in the range of 30 to 120°. Herein, the plurality of 11 l-V layers continuously covers at least a portion of the nanostructure cores. Figure 2b illustrates a similar UV optoelectronic device to Figure 1a, but wherein the patterned substrate comprises only u-AIN (i.e. undoped or intrinsic AIN). Figure 3 illustrates a UV optoelectronic device which is free from interstitial voids between the nanostructure cores. The substrate comprises a patterned AIGaN template (i.e. substrate) with cones or pyramids as nanostructure cores. Herein, the plurality of 11 l-V layers continuously covers at least a portion of the nanostructure cores. Figure 4 illustrates a UV optoelectronic device in which the regions between the nanostructure cores comprise an insulating material. The substrate comprises a patterned AIGaN template (i.e. substrate) with pyramid rods or cone rods as nanostructure cores. Figure 5 illustrates a UV optoelectronic device similar to that depicted in Figure 2, but in which the support comprises layers of silica (SiOz) and silicon, which can be subsequently removed via chemical etching. Figure 6a is a reference structure, which is a simplification of the structure shown in Figure 3 and shows the calculation parameters for determining the dependence of light extraction efficiency on the angle of the pyramidal or conical portions of the at least one 11 l-V layer. The calculation results are shown in Figures 6b, 6c, 7a, 7b. Figure 6b shows the relationship between internal pyramidal or conical angle (a) of the at least one 11 l-V layer and the average light extraction efficiency (LEE). Figure 6c is the same as Figure 6b, but the angle is shown as angle 9 (i.e. the angle between the pyramidal or conical sidewalls of the at least one 11 l-V layer and the horizontal plane). The calculation for Figure 6b and 6c was carried out with a 25 nm p-GaN layer. Figure 7a shows the relationship between internal pyramidal or conical angle (a) of the at least one 11 l-V layer and the average light extraction efficiency (LEE). Figure 7b is the same as Figure 7a, but the angle is shown as angle 9 (i.e. the angle between the pyramidal or conical sidewalls of the at least one 11 l-V layer and the horizontal plane). Figures 7a and 7b show the results for a structure with a 215 nm p-GaN layer, instead of a 25nm p-GaN layer as shown in Figures 6b and 6c. Figures 8a-8c illustrate the relationship between angle (9) (i.e. the angle between the pyramidal or conical sidewalls of the 11 l-V layer and the horizontal plane) or internal pyramidal / conical angle (a) and the area scale factor for various compositions which differ in the ratio between the nanostructure core width (C) and the width of the interstitial spaces (D) which separate each nanostructure core. Figure 8a shows the calculation parameters for the reference structure, which is a simplification of the structure shown in Figure 3. Figure 8b shows the relationship between nanostructure area factor and internal pyramidal / conical angle (a) for the reference structure in Figure 8a. Figure 8c is the same as Figure 8b, but the angle is shown as angle 9 (i.e. the angle between the pyramidal or conical sidewalls of the at least one 11 l-V layer and the horizontal plane). In Figures 8a-8c, the sequence of layers is the same as in Figures 6 / 7, i.e. from bottom to top: n-AIGaN substrate with n-AIGaN nanostructure cores, MQW layer, p-AIGaN layer, p-GaN layer (with Au contact assumed). Detailed Description of the Invention Optoelectronic Device The term “UV optoelectronic device” refers to devices and systems which emit, find, detect and control light in the ultraviolet (UV) range of the electromagnetic spectrum. The UV range of the electromagnetic spectrum refers to light with a wavelength of 10 to 400 nm. The term “device” as referred herein corresponds to a UV optoelectronic device. Preferably, the UV optoelectronic device will be selected from an ultraviolet A (UVA), an ultraviolet B (UVB) or an ultraviolet C (UVC) optoelectronic device, preferably a UVC optoelectronic device. As described herein, UVA typically refers to UV light with a wavelength of 315 to 400 nm, UVB typically refers to UV light with a wavelength of 280 to 315 nm and UVC typically refers to light with a wavelength of 100 to 280 nm. An ideal embodiment for the UV optoelectronic device includes, but is not limited to, any of the following: a light emitting diode (LED), a laser or a photodetector. A preferable embodiment for the UV optoelectronic device is an LED, especially a UV LED. A UVC LED is particularly preferred. The device may act as a flip chip device. For optoelectronic devices which may act as a flip chip device, a reflective (typically metallic) layer would typically be present on top of the at least one 11 l-V layers. This directs light back towards (and through) the substrate. In some cases, therefore, the optoelectronic device may act as a flip chip and comprise a reflective layer at the top of the device (i.e. located on top of the at least one 11 l-V layer), and / or a transparent or substantially transparent substrate at the bottom of the device. Unless otherwise stated, the term ‘bottom’ refers to the substrate side of the nanostructure cores, and the term ‘top’ refers to the side of the nanostructure cores that is opposite to the substrate. The terms are meant as relative terms only and may not reflect final positioning in the device. Substrate The substrate as described herein is a group Ill-V semiconductor substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips. The nanostructure cores protrude from the substrate. The patterned surface of the substrate may therefore be seen as comprising a plurality of protruding nanostructure cores having pyramidal or conical tips. Alternatively put, the substrate has a plurality of protruding nanostructure cores at its surface. The substrate can be viewed as a patterned (or nano-patterned) substrate, therefore. The nanostructure cores are nano-patterned (e.g. etched) into the substrate. This is different from many prior art structures, which may have nanostructure cores which are grown (i.e. bottom-up) on the surface of a substrate. The substrate can be seen as comprising a base region (alternatively called a non-protruding region or non-patterned region) and a patterned region (alternatively called a protruding region or nano-patterned surface structure). This is shown in Figure 1. Essentially, the former designates the bulk region of the substrate, and the latter describes the protrusions (i.e. nanostructure cores) on the base region. The base region is typically planar. The terms “substrate”, “patterned substrate” or “nano-patterned substrate” can be used interchangeably herein. Similarly, the wording “substrate” and “template” may be used interchangeably herein. The patterned region (and thus the nanostructure cores) and the base region have the same composition, i.e. are formed of the same material e.g. both in terms of atomic ratios and carrier concentration. The base region and the patterned region (i.e. nanostructure cores) form a compositionally uniform structure, therefore. Preferably the only patterning on the substrate is the patterned region as defined herein on. The substrate typically does not comprise a mask layer positioned thereon, a buffer layer positioned thereon, nucleation holes positioned thereon and / or nucleation nanoislands (i.e. nanoislands grown by bottom-up epitaxial methods). This is because the nanostructure cores are formed by patterning of the substrate, i.e. by etching a group lll-V semiconductor layer to form a substrate comprising a patterned surface (i.e. horizontal plane as defined by the base region). As a result, there is no grain boundary between the nanostructure cores and the base region of the substrate. Having a ‘top-down’ etched patterned substrate is beneficial as it does not require mask layers, buffer layers, nucleation holes, nucleation nanoislands etc. which are traditionally seen with ‘bottom-up’ grown nanostructures and which can have a negative impact on the efficiency of the device. Moreover, the top-down etching results in a one-step process to form a template for the subsequent Ill-V layer(s). As mentioned above and below, the structure of those layers results in beneficial emission (or absorption) characteristics. The patterned region comprises a patterned surface. The patterned region as referred to herein comprises a plurality of nanostructure cores. The patterned region, and thus the patterned substrate, is typically achieved through etching a semiconducting group Ill-V layer to form a patterned surface. As the patterned substrate comprises nanostructure cores in the form of the patterned region, the substrate may be referred to as a patterned substrate, i.e. ‘patterned substrate’ = ‘base region’ + ‘patterned region’. The substrate is typically a crystalline substrate. The substrate is typically semiconducting. The substrate may have a crystal orientation of

[111] ,

[110] ,

[0001] or

[100] perpendicular to the surface.

[0001] is preferred. Preferably, the substrate is a

[0001] lll-N substrate. The following discussion, relating to group 11 l-V materials for the substrate, applies to both the patterned surface / region and base region of the substrate, and thus also the nanostructure cores. The following discussion may also apply to group IIl-V layers, where technically appropriate. For the group lll-V (preferably lll-N) substrate, group III options are B, Al, Ga, In or Tl, preferably Al, Ga or In. Group V options are N, P, As, Sb, preferably N. It is of course possible to use more than one element from group III and / or more than one element from group V for the group lll-V semiconducting substrate. Typically, the lll-V material of the substrate comprises at least Al as a group III element. Compounds based on Al, Ga and In in combination with N are preferred (along with any doping atoms as herein described). Compounds based on Al and optionally Ga in combination with N are preferred. The use of AIGaN, AllnGaN and / or AIN is highly preferred for the substrate, especially AIGaN and AIN. The substrate may comprise or consist of a ternary compound (allowing for doping atoms). The ternary compound may be of formula XYZ wherein X is a group III element, Y is a group III element which is different to X, and Z is a group V element. The X to Y molar ratio is preferably 0.01-0.99, e.g. 0.1 to 0.9, i.e. the formula is preferably XxYi.xZ wherein subscript x is 0.01 to 0.99. In certain cases, the substrate comprises or is AlxGai-xN, wherein x is in the range of 0.4 to 1, such as 0.40 to 0.70, or 0.50 to 0.70. Preferably, for UV applications in particular, the nanostructures do not comprise InGaN, since InGaN is poorly suitable for UV / UVC applications. Similarly, it is preferable if the substrate does not comprise GaN, since it is poorly suitable for UVC applications given its opacity to UVC light. The substrate may also comprise or consist of a quaternary group lll-V semiconductor (allowing for doping atoms). The quaternary compound may be of formula AxBi.xCyDi.y where A and B are group III elements and C and D are group V elements or AxByCi-x-yD where A, B and C are group III elements and D is a group V element. Again, subscripts x and y are typically 0.01-0.99, e.g. 0.1 to 0.9. Other options will be clear to the skilled person. The substrate may be doped, i.e. n-doped or p-doped, preferably n-doped. The doped substrate typically acts as, or is part of, an n-current spreader. It typically participates in the functioning of the device. The doped substrate can be an injector of electrons (i.e. if n-doped) or an injector of holes (i.e. if p-doped). For applications such as UVC LED, the substrate is preferably n-type doped. Doping of the substrate typically involves the introduction of impurity ions. The doping level can be controlled from ~ 1015 / cm3to 1022 / cm3, preferably 1016 / cm3 to 1021 / cm3, preferably 1017 / cm3to 102° / cm3, preferably 1018 / cm3to 1019 / cm3, (these numbers refer to the number of doping / impurity ions per cm3). Suitable acceptors for the substrate can be Be, Mg and Zn, when the substrate is p-type doped. The substrate may therefore be doped with at least one of Be, Mg and Zn. For n-type substrates, suitable donors can be Te, Sn, Si, Ge and C. The substrate may therefore be doped with at least one of Te, Sn, Si, Ge and C. Si can be amphoteric and act as either a donor or acceptor depending on the site where the Si goes to, depending on the orientation of the growing surface and the growth conditions. Dopants can be introduced during the growth process or by ion implantation after formation of the substrate. The advantages of having a doped substrate are the following. The doped substrate facilitates the electrical functionality of a device, i.e., transport of charge carriers and injection / extraction at the functional components, e.g., metal contacts or active region. Preferably, doped substrates have a low sheet resistance as well as low contact resistance which enables efficient devices, in particular in terms of low voltages, low heat generation, and high wall-plug efficiency. In case of a multi-layer doped substrate, layers with different properties can be stacked to improve different aspects, e.g., two layers with different doping levels optimized to improve sheet resistance and contact resistance, respectively. In such a way, key properties can be decoupled to independently improve multiple aspects of efficiency. In addition, thermal conductivity will be affected by doping. So, a doped substrate will most likely improve heat conductivity and extraction. The substrate preferably comprises or is n-AIGaN or i-AIN (e.g. with the ratios of Al and Ga as defined above). The substrate may be positioned on one or more additional sub-layers of group lll-V semiconducting compounds, typically ternary Ill-V compounds. Any additional sub-layers are typically positioned on the opposite side of the base region of the substrate to the patterned region. Any sub-layer(s) is therefore on the opposite side of the substrate to the nanostructure cores. It is generally preferred for any sub-layer to be planar. An n-AIGaN substrate layer, for example, may be positioned on an n-AIGaN sub-layer having a different composition. The device may therefore comprise an n-doped substrate on a different n-doped layer (preferably both n-AIGaN layers with different atomic ratios or carrier concentration). The n-substrate layer and any additional n-doped sub-layer(s) typically form an n-current spreading layer (see Figures 2 to 5). For example, the substrate may be AlxGai-xN, wherein x is in the range of 0.45 to 0.65 (such as Alo.55Gao.45N), and the sub-layer may be AlxGai-xN, wherein x is in the range of 0.66 to 0.9 (such as Alo.7Gao.3N). Preferably the sub-layer has a higher Al content than the substrate. The presence of one or more sub-layers, in particular one or more planar sub-layers, may be beneficial, as said sub-layer can allow strain moderation and ensure compositional uniformity of the substrate. The ‘top’ layer when referring to the substrate herein typically refers to the base region of the substrate. It is further preferred if the substrate consists of a group lll-V (preferably III-N) semiconducting compound (whilst allowing for doping elements). The thickness of the substrate is not particularly limited, but typically will be in the range of 0.1 to 2 pm, such as 0.2 to 1 pm. The thickness of the base region of the substrate is not particularly limited, but typically will be in the range of 0.1 to 2 pm, such as 0.2 to 1 pm. The thickness of the n-current spreading layer (i.e. combination of the n-doped base region of the substrate and any n-doped sublayers) is typically in the range 0.1 to 2 pm, such as 0.2 to 1 pm. The substrate (and any doped sub-layers) may be positioned on one or more undoped group lll-V layers. Again, these undoped layers are on the opposite side of the substrate to the nanostructure cores. The undoped layers may comprise undoped AIGaN and / or AIN. The undoped region may comprise a plurality of layers, such as 10 to 50 (e.g. 30) pairs of alternating undoped AIGaN / AIN layers of 5 nm or less (e.g. 1 nm to 4 nm) in thickness. The undoped layer region may comprise at least one AIN layer with a thickness in the range of 1 to 10 pm, preferably 2 to 5 pm. It is also preferable for the AIN layer to be planar. The undoped layers, similar to the sub-layers, may allow strain moderation and compositional uniformity for the device through “epi-moderation” and lattice matching between the substrate and the support. The AIGaN in the undoped region is preferably AlxGai.xN wherein the x is in the range 0.3-0.9, preferably at least 0.5-0.7, preferably 0.6. It is preferred if the substrate and any (doped or undoped) sub-layers positioned on the opposite side of the base region of the substrate to the patterned region, do not comprise GaN. Support The substrate may be positioned on a support layer, optionally wherein doped or undoped sub-layers are present between the substrate and the support layer. The substrate may be removed from the support by a number of methods, including chemical etching, laser lift-off, or other methods of delamination. There may be a sacrificial layer of GaN between the substrate and support, since GaN can be used for laser lift off. The support layer may be sacrificial (i.e. used in the preparation of the device but then removed) or it may be part of the UV optoelectronic device. The support layer is not particularly limited, and may comprise at least one of the following: silica (SiO2), quartz, alumina (AI2O3), sapphire, Si, SiC, GaAs, or AIN. Preferably, the support layer comprises or consists of sapphire. In an alternative embodiment, the support layer comprises or consists of SiO2 and / or Si. The support layer may comprise at least one SiO2 layer. Using a support comprising, for example, SiO2 has the benefit that the support may be chemically etched away, e.g. for deposition onto different substrates. If the support comprises a UVC absorbent material (e.g. Si, SiC, GaAs, GaN), it is preferred if the support is chemically etched away or removed by other processes such as laser lift-off in the processing of the final device, for UVC optoelectronic devices. It is thus preferred if the support layer is free from GaN, SiC, Si, GaAs for UVC optoelectronic devices. The thickness of the support is not particularly limited, but preferably is in the range of 10 to 2000 pm, such as 250 to 750 pm. The support is the 400 pm sapphire layer in Figs 2-4, for example, but the invention is not limited thereto. In a specific embodiment, the substrate and / or the support layer may be transparent or substantially transparent. Transparent as defined herein covers transparency across all UV wavelengths, in particular UVC wavelengths. Nanostructure cores / nanostructures Patterning of the substrate results in the substrate having a patterned surface. The patterned surface as defined herein comprises a plurality of nanostructure cores, wherein the nanostructure cores have pyramidal or conical tips. Discussion of nanostructures also can refer to the nanostructure cores, or the cores in combination with the additional layers positioned thereon. Typically, the term “nanostructure” refers to the nanostructure cores in combination with additional layers positioned on top of the cores. As mentioned above, the nanostructure cores are part of the substrate and protrude at the surface thereof. “Nanostructure” as defined herein may refer to a nanowire (also termed nanorod, nanopillar, nanocolumn or nanowhisker) with a pyramidal or conical tip, a nanocone, or a nanopyramid. The ‘tip’ is on the end of the nanostructure core which is at the furthest position in the vertical direction from the base region of the substrate. The base of the nanostructure core is the part of the nanostructure core which is adjacent or in closest proximity to the base region of the substrate. The term ‘vertical’ typically herein refers to the direction in which the base of the nanostructures extends to the tip, or an axis along the longest dimensions of the nanostructure (i.e. perpendicular to substrate plane). Preferably the tips are not horizontal planes. The term ‘horizontal’ refers herein to the plane of the substrate (i.e. of the base region of the substrate). A nanowire refers to a solid, wire-like structure of nanometer dimensions. Nanowires preferably have an even diameter throughout the majority of the nanowire, e.g. at least 75% of its length or along the part of the nanowire which is not pyramidal or conical. Ideally, the diameter at the base of the nanowire and at the top of the nanowire should remain about the same (e.g. within 20% of each other), excluding the tapered portion. The nanowire cores have tapered end structures which are pyramidal or conical. The nanowires can be said to be in essentially one-dimensional form with nanometer dimensions in their width or diameter and their length typically in the range of 100 nm to a few (e.g. 5) pm. The non-tapered body of the nanowire preferably has a length of 2 pm or less. Where a plurality of nanowires is patterned, it is preferred if at least 90%, preferably all, meet these dimension requirements. Ideally the nanowire diameter / width (C) is not greater than 1000 nm. It may be up to 2 pm, however. Ideally the nanowire diameter / width is between 10 and 1000 nm, e.g. 50 and 500 nm. The term nanopyramid refers to a solid pyramidal type structure. The term pyramidal is used herein to define a structure with a base whose sides taper to a single point generally above the centre of the base. Typically, the single vertex point is not chamfered, e.g. such that the pyramid does not have a flat top. The nanopyramids may have multiple faces, such as 3 to 8 faces, or 4 to 7 faces. Thus, the base of the nanopyramids might be a triangle, square, pentagonal, hexagonal, heptagonal, octagonal and so on. The pyramid is formed as the faces taper from the base to a central point (forming therefore triangular faces). The triangular faces are normally terminated with {1-101} or {1-102} planes. The triangular side surfaces with {1-101} facets could either converge to a single point at the tip or could form a new facet ({1-102} planes) before converging at the tip. These 4-digit indices are typically most appropriate for hexagonal crystals. The base itself may comprise a portion of even cross-section before tapering to form a pyramidal structure begins. The nanostructure core is formed by top-down etching, e.g. from a pregrown layer structure. This pre-grown layer structure (i.e. before being etched) could also be seen as a substrate precursor layer (see Figure 1). The pre-grown layer structure is a group 11 l-V semiconductor layer, which will form the patterned substrate. The substrate is thus etched to form a patterned region on a base region, wherein the patterned region comprises nanostructure cores. The base (C) of the nanopyramids may typically be between 50 and 1000 nm across its widest point. It may be up to 2 pm, however. The height of the nanopyramids may be 100 nm to a few (e.g. 5) micrometers, such as 400 nm to 1 micrometer in height. Similar considerations apply to nanocones. As illustrated in Figures 2 to 5, length (B) denotes the sum of the height of the nanostructure core and any additional 11 l-V layers thereon. Length (B) thus denotes the height of the nanostructure. Length (A) refers to the n-current spreading layer. The n-current spreading layer refers to all n-type semiconducting layers which are present under the base region of the substrate, including the base region of the substrate. The nanostructure core is herein defined as the (innermost) part of any nanostructure which is formed as the patterned region / surface of the substrate. As mentioned above, the nanostructure cores thus have the same composition as the base region substrate (i.e. both the patterned region and the base region) e.g. both in terms of atomic ratios and carrier concentration. The nanostructure cores may be viewed as the patterned region or surface of the substrate. Typically, when the nanostructure cores have conical or pyramidal tips as defined herein, the overall structure (i.e. the nanostructure core and any additional layers) will also have conical or pyramidal tips. Preferably the tips are hexagonal pyramidal. The UV optoelectronic device typically comprises nanostructure cores with conical or pyramidal tips, wherein the nanostructure cores have width (C). The nanostructure cores may have a conical rod or pyramidal rod shape (as in Figures 2, 4, 5), or a conical or pyramidal shape (as in Figures 3, 6a, 8a). ‘Cone rods’ or ‘pyramid rods’ refer to nanowires with conical or pyramidal tips. ‘Cones’ or ‘pyramids’ refer to nanopyramids or nanocones (without vertical side walls). In either case, the cores comprise sides which taper to a single point generally above the centre of the base. Without being bound by theory, having a nanostructure core shaped into conical or pyramidal rods (i.e. with a pyramidal or conical tip) can increase light extraction efficiency and internal quantum efficiency through an increase in the light emitting area. The width (C) of the nanostructure core (e.g. conical rod, pyramidal rod, cone or pyramid), is not particularly limited. In some cases, the width (C) may be 50 nm to 2 pm. As further illustrated in Figures 2 to 5, each nanostructure core in the device is separated by interstitial spaces of width (D), i.e. by an interstitial distance (D). Alternatively viewed, the patterned surface / region of the patterned substrate comprises interstitial spaces in addition to nanostructure cores, wherein the interstitial spaces separate each nanostructure core. The nanostructure cores are typically patterned in a regular array on the substrate. Width / distance D can be seen as the distance between nearest neighbouring nanostructure cores in an array of nanostructure cores. Typically, the width of the interstitial spaces (D) is equal to or less than the width (C) of the nanostructure core. In some cases, width (D) may be zero. It is generally preferred for the average total width per nanostructure core and interstitial space, i.e. (C)+(D), to be 2 pm or less, such as in the range 50 nm to 1 pm. Often, this coincides with the pitch of the device which is defined as the distance centre to centre of nearest neighbours in the array, i.e. the distance between the pyramidal or conical tips of adjacent nanostructures / nanostructure cores. As referred to above, the thickness of the n-current spreading layer (e.g. n-doped base region of the substrate and any n-doped sublayer positioned underneath the substrate) is labelled as (A). Typically, (B) + (A) is larger than or equal to (C) + (D). The values of (A) to (D) refer to average (e.g. mean) values for the specific parameter. Moreover, it will be preferred if the nanostructure cores have the same dimensions, e.g. to within 10% of each other. Thus, at least 90% (preferably substantially all) of the nanostructure cores on a substrate will preferably be of the same diameter / width and / or the same length (i.e. to within 10% of the diameter / length of each other). Essentially, therefore the skilled person is looking for homogeneity and nanostructure cores that are substantially the same in terms of dimensions. The size, shape and location of the nanostructure cores are controlled by the etching of the group II l-V semiconductor substrate precursor layer to form the patterned surface / region of the substrate. It is ideal if the nanostructure cores are perpendicular to the base region of the substrate and ideally therefore e.g. in the [111 ]-direction for cubic crystal structure or e.g. in the

[0001] -direction for hexagonal crystal structure. The nanostructure cores and substrate base region are crystallographically uniform. The nanostructure cores are preferably doped. The nanostructure cores are part of the substrate. They form a nano-patterned surface thereof. As a result, they have the same chemical composition as the base region of the substrate. In other words, the patterned substrate (which includes the nanostructure cores) is formed from a single and / or compositionally-uniform material. Therefore, any discussion on the composition of the substrate, as referred to herein, is also applicable to the nanostructure cores. This also applies to doping type. Group lll-V layer(s) The UV optoelectronic device of the present invention further comprises at least one group lll-V (preferably lll-N) layer on top of the nanostructure cores. The at least one group lll-V layer may be referred herein to the at least one lll-V layer. Alternatively viewed, the at least one lll-V layer may be formed on the patterned surface of the substrate. Similar to the substrate / nanostructure cores, the at least one lll-V layer is semiconducting. The at least one group lll-V layer is preferably semipolar, or at least part of said at least one group lll-V layer is semipolar. Semipolar as defined herein refers to semipolar crystallinity which concerns planes which are neither vertical (nonpolar) nor horizontal (polar). At least part of said at least one group lll-V layer is conical or pyramidal. At least part as referred to herein refers to any region of the layer. It is preferable for the region of the lll-V which is directly on top of the nanostructure core to be semipolar, and thus pyramidal or conical. Without being bound by theory, having semipolar / pyramidal MQW- and p-layers is beneficial compared to fully core-shell nanostructures, since undesired absorption of light by one or more of the lll-V layers is minimised. For example, if the composition or device comprises a top GaN (e.g. p-GaN) layer, which absorbs UV light, then having semipolar group lll-V layers, especially a semipolar GaN layer ensures that UV absorption is minimized, since there are no wrap-around shell layer(s), for example, which may absorb UV light and reduce the efficiency of the device. In a fully core-shell structure, undesirably high levels of absorption can occur. This is especially the case in devices where light is emitted / absorbed via the bottom of the device. Minimizing absorption by a UV-opaque top layer is important. The top layer as referred herein refers to the Ill-V layer which is the furthest lll-V layer from the base of the nanostructure core in the vertical direction. A polar structure can be seen as a structure without space inversion symmetry, and of the 31 crystal classes 21 of them have this property. All polar crystal structures, such as Wurtzite, have a specific polar axis, along where the space inversion symmetry is broken. Semipolar planes are planes that have a normal vector at an angle which is non-0°, non-90° and non-180° with respect to the polar axis of the crystal structure. Semipolar planes / layers are therefore planes / layers which are not perpendicular to, nor parallel to, the polar axis of the crystal structure. The at least one lll-V layer is therefore typically formed of a compound with a semipolar crystal structure, and the lll-V layer is neither perpendicular nor parallel to the polar axis of said polar crystal structure. Preferably the at least one lll-V layer does not comprise vertical or non-polar portions. Preferably, the only lll-V layer which can comprise vertical or non-polar portions is a lll-V layer directly on top of the nanostructure cores, i.e. the lll-V layer closest to the substrate. Preferably, the at least one lll-V layer(s) comprises one or more layers which do not comprise vertical or non-polar portions. The at least one lll-V layer is therefore typically formed of a compound with a semipolar crystal structure. The lll-V layer is typically neither perpendicular nor parallel to the growth axis of the nanostructure. The lll-V layer is typically neither perpendicular nor parallel to the substrate plane. In the case of substrates without a horizontal c-plane surface or polar axis the at least one lll-V layer has an orientation which is not perpendicular to, nor parallel to, a low index (e.g.

[001] ,

[010] ,

[100] ) axis of that substrate. The nanostructure core’s upper surface is typically composed of six equivalent surface parts arranged in a pyramidical shape merging at a common tip. Considering the polarity properties of the I ll-N wurtzite crystal structure, for example, each of the six equivalent surface parts forms a semipolar plane, characterized by a specific angle and an equivalent set of Miller’s indices, e.g., 62° with respect to the horizontal plane and {10-11}. By stacking additional lll-V (preferably 11 l-N) layer(s) on top, the angle and indices of the pyramidal or conical planes are reproduced. In this way, multiple pyramidal or conical interfaces can be created. In contrast to other types of interfaces (e.g., polar or non-polar) such pyramidal or conical (semipolar) interfaces provide special physical properties in terms of charge carrier distribution and light-matter-interaction. In case of UV LEDs, highly TM-polarized light can result from the pyramidal or conical interfaces. In addition, polar surfaces induce an effect called the quantum confined stark effect, which is an undesired effect in LEDs. The pyramidal or conical plane will, due to the reduced polarity, also have a reduced quantum confined Stark effect. These physical properties can be exploited to improve radiative recombination efficiency and light extraction efficiency in LEDs in particular. The at least one 11 l-V layer is typically a pyramidal layer (or comprises a plurality of pyramidal portions), preferably a hexagonal pyramidal layer (since Ill-N nanostructure cores are preferred and these typically have hexagonal symmetry). Alternatively put, the at least one lll-V layer comprises tilted sidewalls extending from a pyramid peak, wherein the sidewalls are semipolar. The tips of the semipolar (i.e. pyramidal) layers can be seen as the meeting point of 6 semipolar planes (for hexagonal symmetry). As mentioned above, the at least one lll-V layer typically has six equivalent planes / surface parts arranged in a pyramidical shape merging at a common tip. Each surface part preferably is a {IQ-11} facet, but a range of similar planes can be considered herein. Generally speaking, therefore, the at least one lll-V layer typically has {10-11} facets, but higher index facets are also possible. It is preferred if the at least one lll-V layer matches the crystal facets of the pyramidal or conical tips of the nanostructure core. Therefore, it is preferable if the at least one lll-V layer is formed on the same plane as the nanostructure core, and thus has an epitaxial relationship with the nanostructure core, and thus with the patterned substrate. The internal pyramid angle (or internal conical angle) refers to the angle at the tip where the planes of the lll-V layer merge. This is denoted by a in the Figures. The discussion of internal pyramidal angles herein applies also to internal conical angles. Internal pyramidal (or conical) angle a = (90° - 9) x 2 (wherein 0 is the angle between the pyramidal or conical sidewalls of the at least one lll-V layer and the horizontal plane) The present inventors have investigated the effect of the internal pyramidal / conical angle of the lll-V layer and the active area on the average LEE of the device (see Figures 6b, 7a and 8b). The present inventors have surprisingly found an increase in LEE in UV optoelectronic devices at certain angles. The internal pyramidal angle may be 70° or less, preferably 65° or less, preferably 62° or less. The internal pyramidal angle may also be 60° or less. The internal pyramidal angle of said at least one 11 l-V layer may be 49° or less, such as 45° or less, or 40° or less. The internal pyramidal angle may be 20° or more, preferably 30° or more. The internal pyramidal / conical angle of said at least one III-V layer is preferably in the range of 20° to 70°, preferably 30° to 60°, preferably 30° to 56°. Other suitable ranges include 50° to 70°, or 35° to 45°. The exact value will depend on the c / a ratio of the crystal structure (and hence the strain and the Al content, if present). In some cases, the sidewalls of the 11 l-V layer may have an angle (0) of 30° or less with the horizontal plane, such as 5° to 30° with the horizontal plane. Consequently, in certain embodiments, the internal pyramidal angle of said at least one 11 l-V layer may be in the range of 120° to 170°. The sidewalls of the 11 l-V layer may have an angle (9) of 5° to 30° with the horizontal plane and / or the group IIl-V layer has an internal pyramidal angle in the range of 120° to 170° when the thickness of the at least one group lll-V layer is 50 nm or less, such as in the range of 10 to 40 nm. Without being bound by theory, typically when the internal pyramidal angle of said at least one lll-V layer decreases (i.e. the angle (0) between the sidewalls of the lll-V layer and the horizontal plane increases), the light extraction (or absorption) efficiency increases. However, the present inventors have also surprisingly found that a high LEE may be observed when the internal pyramidal angle is high, such as higher than 100°, such as 120° to 170°. Alternatively viewed, a high LEE may be observed when the angle (0) between the sidewalls of the lll-V layer and the horizontal plane is in the range of 5° to 30°, in addition to typical values of 50° to 70°, for example. Moreover, the active area typically increases when the angle (0) between the sidewalls of the lll-V layer and the horizontal plane increases, increasing the potential power output by the same factor. The active area, as referred herein, corresponds to the surface area of the active region. As the active region lies within or above the at least one lll-V layer, the active region typically has the same surface area as the patterned surface of the substrate (i.e. the nanostructure core). Therefore, the active area typically reflects the total surface area of the nanostructure. The relative increase in active area is larger when the width of the interstitial spaces (D) between the nanostructure cores is decreased, as demonstrated in Figure 8. In the particular case where the width of the interstitial spaces is zero (D=0), the area factor is found to increase by a factor of 1 / cos(0), wherein angle (9) is the angle between the sidewalls of the lll-V layer and the horizontal plane. Therefore, the larger the value of 9, the sharper the increase in the active area, which also positively influences the LEE of the optoelectronic device. The width (D) of the interstitial spaces between the nanostructure cores of width (C) is also found to be influential on the rate of increase of the area factor, wherein a sharper increase is found for larger values of (D) / (C). In a particular embodiment, the D / C ratio is of 1 / 2 or less, preferably 1 / 3 or less, preferably 1 / 4 or less, preferably 1 / 5 or less, preferably 0. For a set value of angle (9) or (a), lower D / C ratios have increased area factors (see Figures 8b / 8c). The angles (a) and (9) may refer to the angle between the sidewalls of the nanostructure core and the horizontal plane and thus the internal pyramidal angle may also refer to the internal angle of the pyramidal or conical tip(s) of the nanostructure core(s). Any discussion of preferred angles or ranges of angles above for the lll-V layer are therefore applicable to the internal pyramidal / conical angle of the nanostructure cores or the angle between the sidewalls of the nanostructure core and the horizontal plane. The at least one lll-V layer preferably comprises a group 11 l-N semiconducting compound. It is especially preferred if the at least one lll-V layer comprises or consists of GaN, AIN, AIGaN or AllnGaN, especially GaN or AIGaN. In other words, the device preferably comprises one or more lll-V layers each independently selected from GaN, AIN, AIGaN or AllnGaN, especially GaN or AIGaN. The thickness of the at least one lll-V layer is not particular limited. Typically, the thickness of each lll-V layer is 500 nm or less, such as 1 to 400 nm. In some cases, the thickness of the at least one lll-V layer may be 200 nm or more, such as 200 to 400 nm. In other cases, the thickness of the at least one lll-V layer may be 50 nm or less, such as 10 to 40 nm. In certain cases, the at least one layer is 1 nm or more in thickness, such as 1 to 20 nm or 1 to 10 nm. In certain cases, the UV optoelectronic device as defined herein comprises a plurality of lll-V layers on top of the nanostructure core. If there is more than one lll-V layer on top of the core, then the layers are preferably stacked vertically, i.e. on top of each other along the vertical axis (i.e. growth axis or longest dimension of the nanostructures or microstructures). The stacking could be considered to be vertical stacking, or pyramidical / conical stacking, therefore. These terms are considered to be equivalent. The nanostructures are preferably axially heterostructured, or comprise at least one axially heterostructured 11 l-V layer. It is generally preferred if the nanostructures are not purely radially heterostructured. As used herein, “purely radially heterostructured” refers to nanostructures which are only radially heterostructured, e.g. core-shell nanostructures. In the present invention, the nanostructures may include both axial and radial structuring. In cases where there is both axial and radial structuring, it is typically preferred if radial structuring is only observed for the Ill-V layer which is directly in contact with the nanostructure core, e.g. in electrical contact with the nanostructure core. Preferably, any p-doped 11 l-V layers are axially heterostructured only. Preferably, any p-doped layers are fully semipolar. It is generally preferred if the nanostructure cores and the at least one group 11 l-V layer form a p-n or p-i-n junction. Consequently, the nanostructure (i.e. a nanostructure core in combination with the at least one Ill-V layer disposed thereon) contains a p-n or p-i-n junction. If the nanostructure core is undoped (e.g. u-AIN), then the p-n or p-i-n junction is formed in the at least one group 11 l-V layer. The p-i-n or p-n junction can be in the form of additional layers on the cores. Devices of the invention are therefore optionally provided with an active region (i.e. light emitting region in the case of light emitting devices or a light absorbing region in the case of absorbers such as photodetectors). In some cases, the active region comprises an undoped intrinsic 11 l-V semiconductor region, wherein the active region is between a p-type semiconductor region and an n-type semiconductor region. The active region is typically a Ill-V layer or a plurality of IIl-V layers. The n-type semiconductor region comprises the substrate if the substrate is n-doped. The active (e.g. intrinsic) region may consist of a single layer of material or a heterostructure consisting of multiple quantum wells and barriers. Typically, the active region is a multiple quantum well. In certain cases, a multiple quantum well may be present between a p-type semiconductor and an n-type semiconductor region. The multiple quantum well typically comprises quantum well layers and barrier layers which are alternatively stacked. The barrier layers may be doped (e.g. n-doped). The multiple quantum layer may comprise alternating layers of i-AlxGai- XN as the quantum well layers, wherein x is in the range of 0.35 to 0.45, and n-AlxGai-xN as the barrier layers, wherein x is in the range of 0.55 to 0.65. The multiple quantum well will typically comprise 3 to 10 repetitions of well and barrier layers. The active region (i.e. the region comprising the intrinsic layer) may be positioned directly on the core, or there may be an intermediate layer between the nanostructure core and the active region. The active region is typically positioned between n-region (e.g. the nanostructure core) and the p-region (e.g. a p-doped III-V layer). Typically, the active region refers to an intrinsic region and / or any multiple quantum well. The active region layer typically acts as the light emitting layer, in the case of light emitters (such as LEDs), or as the light absorbing layer, in the case of absorbers (e.g. photodetectors). If the nanostructure core is n-type doped, the at least one 11 l-V layer positioned on the nanostructure core will typically comprise at least a p-type doped layer (preferably p-AIGaN and p-GaN) to form the p-i-n or p-n junction, and vice versa. Therefore, in a preferable embodiment, the devices comprise additional n, i-n, p, i-p, n-i-p or p-i-n layers e.g. positioned on top of the cores. The type and concentration of dopants refers to any described herein (e.g. for the substrate / nanostructure core) to any aspect of the present invention. If the nanostructure core is undoped, the device will typically comprise a III-V layer which is n-doped. In cases where the nanostructure core is doped (e.g. n-doped) it would typically comprise a lll-V layer which is also n-doped. The n-doped 11 l-V layer may have the same composition as the nanostructure core (e.g. nAlo.55Gao.45N in Figs 2-5). Typically, the first lll-V layer positioned directly on the nanostructure core will be n-doped and may reduce any surface defects which are present on the nanostructure core. The at least one lll-V layer typically comprises a doped layer, preferably p-doped as herein described. It is especially preferred if the at least one lll-V layer comprises p-GaN or p-AIGaN. The use of GaN in UV optoelectronic devices, e.g. p-GaN, for at least one lll-V layer is surprising, as GaN is known to be an absorbent of UVC light. However, the present invention may comprise a GaN layer and still emit light efficiently. The p-GaN is preferably in contact with the electrode, e.g. the ohmic metal of the electrode. Preferably, the p-GaN is the uppermost lll-V layer (i.e. furthest away from the substrate) and this uppermost p-GaN layer is the only GaN layer in the p-n or p-i-n-junction structure. In a preferable embodiment the device comprises an active region (e.g. i-layer) directly positioned on the core, and one or more (e.g. 2 to 4) p-layers on top of the active region / i-layer (i.e. if the core is n-doped) or one or more (e.g. 2 to 4) n-layers on top of the active region / i-layer (i.e. if the core is p-doped). In an alternative embodiment, the nanostructure comprises an additional n-layer (i.e. if the core is n-doped) or p-layer (i.e. if the core is p-doped) between the nanostructure core and any active region (e.g. i-layer). The nanostructures may additionally comprise p-AIGaN, i-AIGaN, and / or n-AIGaN layers for example. AI(ln)GaN is also suitable. The ‘(In)’ indicates that small amounts of In may optionally be present. Such nomenclature is well known in the art. Preferably, therefore, the nanostructures comprise or consist of an AIGaN (e.g. n-AIGaN) nanostructure core, and additionally have at least n-AIGaN, i-AIGaN, and / or p-AIGaN layers thereon, and optionally a GaN (e.g. p-GaN) layer, preferably in that order. The composition may comprise at least one i-AIGaN layer, at least one p-AIGaN layer (optionally two p-AIGaN layers, optionally differentiated by different doping, different Al percentage, and / or different thickness), and preferably at least one p-GaN layer, preferably in that order. AIGa(ln)BN systems are also suitable herein (i.e. AIGa(ln)BN core and one or more AIGa(ln)BN layers). Preferably, therefore, the devices comprise at least n-AIGaN, i-AIGaN, and / or p-AIGaN layers on an AIGaN (e.g. n-AIGaN) nanostructure core, and optionally a GaN (e.g. p-GaN) layer, preferably in the order AIGaN (e.g. n-AIGaN) nanostructure core - n-AIGaN - MQW (i-AIGaN) - p-AIGaN layers and optionally GaN (e.g. p-GaN). The device may comprise at least one i-AIGaN layer, at least one p-AIGaN layer (optionally two p-AIGaN layers, optionally differentiated by different doping, different Al percentage, and / or different thickness), and preferably at least one p-GaN layer, preferably in that order. AIGa(ln)BN systems are also suitable herein (i.e. AIGa(ln)BN core and one or more AIGa(ln)BN layers). It is generally preferred if the UV optoelectronic device comprises at least one 11 l-V layer which is transparent or substantially transparent to UV light. Generally, any II l-V compound as defined herein may be suitable for the substrate (e.g. patterned substrate comprising nanostructure cores) and / or at least one II l-V layer. The definitions of the group I ll-V materials for the patterned substrate equally apply to the Ill-V materials, therefore. Structure As mentioned herein, it is particularly preferred if the nanostructure cores have pyramidal or conical tips, and any additional 11 l-V layers (whether p, i or n layers) mirror the topography (i.e. shape) of the underlying cores. The at least one 11 l-V layers are typically conformally formed on the nanostructure core, therefore. The at least one 11 l-V layers are typically conformal with each other. Unless otherwise indicated, the term ‘on’ (as in ‘group 11 l-V layer positioned on top of said nanostructure cores’) typically means ‘directly on’, i.e. without intermediate layers. The term also typically means ‘in electrical contact with’. The nanostructure cores are considered to be part of the substrate. The nanostructure cores protrude from the substrate as a result of top-down etching of a substrate precursor layer. The substrate is thus considered to comprise the nanostructure cores. The at least one 11 l-V layer, can either be limited to the width of the nanostructure core (in which case the combination of the at least one II l-V layer and the nanostructure cores may be referred to as a ‘nanostructure’), and / or they may be in the form of a layer continuously covering at least a portion of the plurality of nanostructure cores. Any discussion of various Ill-V layers as defined above or below in the case of nanostructures also applies to cases where the 11 l-V layer(s) continuously covers at least a portion of the plurality of nanostructure cores. Any layer continuously covering at least a portion of the plurality of nanostructure cores are layers which are ridged / corrugated, i.e. comprising a plurality of protrusions, wherein the protrusions (e.g. pyramidal protrusions) are positioned above the tips of the nanostructure cores. The at least one 11 l-V layer preferably continuously covers at least a portion of the nanostructure cores, preferably at least 50% of the nanostructure cores, e.g. at least 75%, at least 90%, or at least 99% of the nanostructure cores. The layer(s) that continuously cover at least a portion of the nanostructure cores may be continuous in its upper region, but may have voids in its lower region (e.g. Figures 2a, 2b, 5). Interstitial voids may be present between at least a portion of the nanostructures or nanostructure cores of the present invention, as shown in Figures 2 and 5. Such voids may reduce dislocations. As herein defined, at least a portion refers to at least 50 %, such as at least 75 % or at least 99 % of the nanostructures. From Figures 2a-b and 5, the interstitial voids, when present, have a width (F) and a height (G). Preferably, the width (F) and / or the height (G) are 0 to 2 pm, e.g. 0.5 to 1.5 pm. In some cases, the interstitial voids are enclosed voids formed within the first 11 l-V layer extending over the region between the nanostructure cores. The top layer (e.g. the top AIGaN or GaN layer) may be continuous, e.g. it may cover at least 50% of the nanostructures, e.g. at least 75%, at least 90%, or at least 99% of the nanostructures. Layers beneath the top layer (e.g. the i-layer and below) may be continuous or they may be non-continuous (i.e. limited to the width of the nanostructures). In a preferable embodiment, the UV optoelectronic device comprises at least one electrical contact layer (i.e. metallic contact layer). The at least one electrical contact layer may continuously extend over the at least one II l-V layer and thus act as a top layer. This is typically a p-contact. The at least one 11 l-V layer (and the electrical contact layer in contact with the top lll-V layer) will typically be ridged / corrugated, i.e. comprising a plurality of protrusions, wherein the protrusions (e.g. pyramidal or conical protrusions) are positioned on top of the nanostructure tips. The electrical contact layer (which is typically metallic) will preferably continuously cover at least a portion of the plurality of nanostructures, such as at least 50 %, at least 75 %, at least 90 % or at least 99 % of the nanostructure. Alternatively, the electrical contact layer will continuously cover at least a portion of the uppermost lll-V layer, such as at least 50 %, at least 75 %, at least 90 % or at least 99 % of the area of the uppermost lll-V layer. The electrical contact positioned on top of the at least one lll-V layer may be in the form of a reflective layer, which is typically metallic. Typically, a plurality of nanostructures may be present, which are formed from the at least one group lll-V layer on the nanostructure cores. In certain cases, the plurality of nanostructures may coalesce at a certain distance (e.g. in the vertical direction) from the base of the nanostructure core. It can be beneficial to form large area structures through coalescence of positioned nanostructures, or through coalescence of one of the top lll-V layers (e.g. p-AIGaN, p-GaN etc.). The nanostructures may be coalesced, therefore. The coalescence of nanostructures may appear almost film like (e.g. like a corrugated film if the nanostructures have pyramidal tips). Coalescence refers to the side-on joining of two or more nanostructures during growth. This results in a 2D or 3D structure. For coalescence, the nanostructures must preferably have their crystal lattices in the same orientation, such that the formation of gaps and dislocations can largely be eliminated, i.e. the lll-V layers of the coalescing nanostructures must preferably have nearly identical epitaxial relationship with respect to the substrate and thus nanostructure cores. However, the nanostructures may be coalesced with amorphous, polycrystalline or a different crystalline material in between them. The region between the nanostructures or nanostructure cores may be amorphous lll-V material or consist of multiple lll-V grains that are not epitaxially related to the nanostructures. The regions between the nanostructures or nanostructure cores may be III-V material (e.g. the same as used for nanostructure growth), air, vacuum, a dielectric material or an insulating material. The insulating material may be AI2O3, SiOz, a metal fluoride (e.g. MgF2), and / or a fluoropolymer (e.g. PTFE). In the case of insulating materials, it is especially preferred if there are regions of AI2O3 between the nanostructures. There may be a grain boundary between the structures. Any lll-V material between the nanostructures may be amorphous, polycrystalline or crystalline. The coalescence may occur via the nanostructure cores, the at least one lll-V layer, or both. In order for the UV optoelectronic device to be complete, an electrical contact layer (typically an n-contact) will also typically be positioned on part of the substrate which is free of nanostructure cores. It is typical for the n-contact to position on the base region of the substrate and not the patterned region. It is generally preferred for the UV optoelectronic device to comprise a p-contact on an outermost lll-V layer of the nanostructure, and a n-contact on the substrate (e.g. base region of substrate). In summary, the device typically has a first electrode electrically connected to the p-side of the p-n or p-i-n junction, called a p-contact, and a second electrode electrically connected to the n-side of the p-n or p-i-n junction, called an n-contact. The p-contact is typically in direct contact with an uppermost p-GaN layer, and the n-contact is typically in direct contact with the substrate (e.g. n-AIGaN), or in direct contact with an n-doped sub-layer (e.g. n-AIGaN) positioned on the opposite side of the base region of the substrate to the patterned region comprising the nanostructure cores. The metallic p-contact, in addition to the n-contact, will be appropriately connected to a power supply to enable the UV optoelectronic device to function. Process Viewed from an alternative aspect, the present invention provides a process for preparing a device as defined herein, comprising: (I) etching a group 11l-V semiconductor layer to form a substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips; (II) growing the at least one 11 l-V layer on top of said plurality of nanostructure cores. The group 11 l-V semiconducting layer which is etched in step (I) thus forms the substrate (i.e. patterned substrate), once the etching process is complete. The 11 l-V material around and in between the nanostructure cores is removed by etching, leaving the nanostructure cores protruding at the surface of the substrate. The patterned surface is fabricated by a process of patterning, followed by etching. The patterning process may be performed by a number of methods familiar to the skilled practitioner, including mask photolithography, direct-write photolithography, interference lithography, Talbot displacement lithography, scanning laser photolithography, electron beam lithography (EBL), or nano-imprint lithography (NIL). The patterning process is preferably performed by NIL. The pattern generated by the patterning process is then transferred to the mask precursor layer by a process of etching. The etch process may include reactive ion etching (RIE), ion beam etching (IBE), or chemical etching by a number of aqueous or vaporous reactive materials. The etch process may also include a sequence of multiple types of etch types. In some cases, a secondary layer of sacrificial material ("hard mask") may be introduced on the top side of the substrate precursor. In such cases, the hard mask is patterned first by one method to transfer the pattern to the hard mask, then used to mask the etch performed on the substrate material. After etching is completed, all temporarily applied materials are removed from the patterned substrate by a number of standard processes, including chemical and plasma removal. The substrate (e.g. patterned substrate), patterned region, nanostructure cores and / or 11 l-V layer referred to in any process herein may refer to any substrate (e.g. patterned substrate), patterned region, nanostructure cores and / or IIl-V layer as described herein, across all aspects of the invention. For step (II) of the above-mentioned process, typically the at least one IIl-V layer is grown on the surface of the nanostructure core (e.g. plurality of nanostructure cores) by metalorganic chemical vapour deposition (MOCVD), which may alternatively be referred to as metalorganic vapour phase epitaxy (MOVPE). In the case of MOCVD / MOVPE, the deposition material is supplied in the form of metalorganic precursors, which on reaching the high temperature patterned surface / nanostructure core decompose leaving atoms on the patterned / surface nanostructure core. In addition, this method requires a carrier gas (typically H2 or N2) to transport deposition materials (atoms / molecules) across the surface of the nanostructure core. These atoms reacting with other atoms form an epitaxial layer on the nanostructure core surface. Choosing the deposition parameters carefully results in the formation of group 11 l-V layer(s) on the surface of the nanostructure core. Viewed from a yet alternative aspect, the present invention provides a process for preparing a device as defined herein, comprising: (I) etching a group 11 l-V semiconductor layer to form a substrate comprising patterned surface, wherein said patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips, and wherein said group III-V semiconductor layer, and optionally any doped or undoped sub-layer(s), are positioned on top of a support comprising an oxide layer; (II) growing said at least one 11 l-V layer on top of said nanostructure core; (III) removing the support layer with a lift-off technique such as chemical etching or laser lift-off. The support and sub-layer(s) may refer to any support and sub-layer(s) as defined herein. Preferably the support comprises Si and S1O2. As used herein, the term “about”, “around” “substantially” or “approximately” in relation to a number or a range of numbers will generally indicate that the number or range specified is preferred but that such a number may be varied to a certain extent without materially affecting the properties of the relevant material, composition, method or product. The skilled worker will typically be able to readily establish the extent by which such numbers may be varied without prejudicing the key advantages of the present invention. As a general guide, such numbers or the ends of such ranges referred to with such terms may be varied by ± 20% or ± 10%, preferably ± 5% and more preferably ±1%. A corresponding meaning may be attributed to compositions “consisting essentially of” certain components, which may include up to 20% or up to 10%, preferably up to 5% and most preferably up to 1% of other components in addition to those specified. Compositions described as comprising or consisting essentially of certain components include the compositions consisting solely of those components. However, ‘consisting of’ does not typically exclude the presence of doping compounds / atoms. A layer ‘consisting of’ AIGaN, for example, would not exclude a doped AIGaN layer (e.g. n-doped or p-doped) which includes doping species. Examples Shown in Figures 6b, 6c, 7a, and 7b are the results of wave optics simulation of light extraction efficiency (LEE) for a reference structure shown in Figure 6a. In these computations, a test optical emission source is placed within the simulated quantum well layer, and the resultant optical flux emitted from the underlying substrate is computed by frequency domain finite element analysis (FEA) of the electromagnetic wave equations. The fraction of optical power transmitted from the source to the exterior, compared with the defined input optical power, is given as the LEE. The results are averaged amongst a multitude of different test emission locations within the quantum well structure, and amongst all optical polarizations. Figures 6b and 6c show the LEE simulation results for devices with a relatively thin p-GaN layer (25 nm), while Figures 7a and 7b show the corresponding results for a thicker p-GaN layer (215 nm). In the results for thinner p-GaN, the simulated LEE is higher, due to a fraction of light penetrating the absorbing GaN and reflecting from the metal contact. Both cases show a variation in the LEE at differing pyramid angles, which can inform the structural optimization of the claimed nanostructures. In particular, it has surprisingly been found that beneficial light extraction efficiencies are obtained at an internal pyramidal angle a of 70 ° or less. The LEE simulation results do not include any LEE changes due to layers beneath the substrate, nor emission from the transparent support material. Such changes can be considered to be an independent factor that can be readily computed by a skilled worker. These preliminary calculations demonstrate that the UV optoelectronic devices described herein have the potential to include significantly larger amounts of active light-generating junction material in a device without increasing the outer dimensions. Further, the light extraction properties of the nanostructured device are expected to be similar to a planar device, and in some cases improved over planar devices. The graphs in Figures 8b and 8c show the (nanostructure) area factor for the reference structure shown in Figure 8a. The area factor is defined as the ratio of the surface area of the nanostructured quantum well layer bounded by a given perimeter to the area of a flat plane with the same perimeter. This value does not depend on the absolute value of the structure dimensions, but only on the internal pyramidal or conical angle (a); and the ratio of interstitial spaces of width (D) and nanostructure cores of width (C), i.e. (D) / (C). Note that a value of 0=0° (or a=180°) corresponds to a planar surface, and the computation diverges as 0 approaches 90°; also note that this computation assumes the nanostructures are not truncated at their tops. In general, for increasingly sharp nanostructures (smaller a, larger 0), the area factor will be increased. For nanostructures with no gaps between them (D / C=0), the area factor is 1 / cos(0), and reaches a value of 2 for 0=a=6O°. The area factor is reduced for nanostructures with larger flat spaces between them. This shows that the UV optoelectronic devices provide means to include a larger amount of optically active quantum well layer within a chip, compared to a device made from planar thin films.

Claims

1. A UV optoelectronic device comprising:a group 11 l-V semiconductor substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips;at least one group 11 l-V layer positioned on top of said nanostructure cores, wherein at least part of said at least one group 11 l-V layer is pyramidal or conical;wherein said nanostructure cores and the at least one group 11 l-V layer form a p-n or a p-i-n junction, or wherein the at least one group 11 l-V layer forms a p-n or p-i-n junction.

2. A UV optoelectronic device as claimed in claim 1, wherein the at least one II l-V layer has an internal pyramidal or conical angle of 70° or less, preferably 65° or less, especially 60° or less.

3. A UV optoelectronic device as claimed in claim 1 or 2, wherein the pyramidal or conical tips of the nanostructure cores have a pyramidal or conical angle of 70° or less, preferably 65° or less, especially 60° or less.

4. A UV optoelectronic device as claimed in any preceding claim wherein a plurality of interstitial voids is located between the nanostructure cores, optionally wherein the interstitial voids are enclosed voids formed within a first 11 l-V layer extending over the region between the nanostructure cores.

5. A UV optoelectronic device as claimed in any preceding claim wherein the at least one 11 l-V layer comprises a p-GaN layer having a thickness of 10 to 400 nm, preferably wherein said p-GaN layer is the uppermost of the group 11 l-V layers (i.e. on the side opposite to the substrate).

6. A UV optoelectronic device as claimed in any preceding claim, wherein the group lll-V semiconductor substrate is an AIGaN, AIN or AllnGaN substrate, more preferably an n-AIGaN or AIN substrate.

7. A UV optoelectronic device as claimed in any preceding claim, wherein the group lll-V semiconductor substrate is an n-AIGaN substrate, and wherein said substrate is positioned on an n-AIGaN sub-layer having a different atomic ratio.

8. The UV optoelectronic device as claimed in any preceding claim, comprising an n-current spreading layer, wherein the n-current spreading layer is formed of the base region of the substrate which is n-doped, optionally positioned on one or more n-doped sublayers.

9. A UV optoelectronic device as claimed in any preceding claim wherein the group lll-V semiconductor substrate is an AlxGai.xN substrate wherein x is in the range of 0.4 to 1, preferably 0.45 to 0.8.

10. A UV optoelectronic device as claimed in any preceding wherein regions of insulating material are located between the nanostructure cores.

11. A UV optoelectronic device as claimed in any preceding claim wherein the at least one lll-V layer matches the crystal facets of the pyramidal or conical tips.

12. A UV optoelectronic device as claimed in any preceding claim wherein the nanostructure cores comprise or consist of AIGaN, preferably p-AIGaN or n-AIGaN, preferably n-AIGaN.

13. A UV optoelectronic device as claimed in any preceding claim, wherein the nanostructure cores comprise or consist of AIN or AIGaN, preferably n-AIGaN.

14. A UV optoelectronic device as claimed in any preceding claim wherein the at least one lll-V layer comprises i-AIGaN and p-AIGaN or i-AIGaN and n-AIGaN, preferably i-AIGaN and p-AIGaN.

15. A UV optoelectronic device as claimed in claim 1 or 2 wherein the at least one lll-V layer comprises i-AIGaN, p-AIGaN and p-GaN.

16. A UV optoelectronic device as claimed in any preceding claim, wherein one or more of the at least one 11 l-V layer(s) continuously cover(s) at least a portion of the plurality of nanostructure cores.

17. A UV optoelectronic device as claimed in any preceding claim comprising: a) an n-AIGaN substrate with a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips;b) an n-AIGaN layer disposed on top of said nanostructure cores;c) a multiple quantum well layer disposed on top of said n-AIGaN layer;d) a p-AIGaN layer disposed on top of said multiple quantum layer;e) a p-GaN layer disposed on top of said p-AIGaN layer;f) a metallic p-contact disposed on said p-GaN layer.

18. A UV optoelectronic device as claimed in any preceding claim, wherein at least one 11 l-V layer comprises sidewalls extending from a pyramid or conical peak, and wherein said sidewalls are semipolar.

19. A UV optoelectronic device as claimed in any preceding claim, wherein the substrate comprises a base region and a patterned region / surface, and wherein both regions are formed of the same material.

20. A UV optoelectronic device as claimed in any preceding claim, wherein the width of the interstitial spaces between the nanostructure cores is D andthe width of the nanostructure cores is C; and whereinthe D / C ratio is of 1 / 2 or less, preferably 1 / 3 or less, preferably 1 / 4 or less, preferably 1 / 5 or less, preferably 0.

21. A UV optoelectronic device as claimed in any preceding claim which is a LED, laser, or photodetector, preferably a LED, especially a UVC LED.

22. A process for preparing a UV optoelectronic device as claimed in any preceding claim, comprising:(I) etching a group 11l-V semiconductor layer to form a substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips;(II) growing said at least one 11 l-V layer on top of said nanostructure cores.

23. A process for preparing a UV optoelectronic device as claimed in any of claims 1-21, comprising:(I) etching a group 11 l-V semiconductor layer to form a substrate having a patterned surface, wherein the patterned surface comprises a plurality of nanostructure cores having pyramidal or conical tips, wherein said Ill-V semiconductor layer, and optionally any doped or undoped sub-layer(s), are positioned on top of a support comprising an oxide layer;(II) growing said at least one 11 l-V layer on top of said nanostructure core;(III) removing the support layer through a lift-off technique such as chemical etching or laser lift-off.Application No: GB2402615.5Claims searched: 1-23Examiner: Contract Unit ExaminerDate of search: 21 October 2024Patents Act 1977: Search Report under Section 17Documents considered to be relevant:Category Relevant to claims Identity of document and passage or figure of particular relevance X 1-5, 8, 10, 11, 18-23 CN105810784 A (WANG XINGHE) paragraphs [0002] - [0018]; figures 1-3, 5 X 1,4, 6, 7, 9, 12-17, 21 KR20150030288 A (LG INNOTEK CO LTD) paragraphs [0032] - [0037]; figures 2-5 A - CN107863428 B (BEIJING ZHONGKE YOUWEILL HITECH CO LTD) the whole document A - NANOTECHNOLOGY, vol 28, 2017, KEUN MAN SONG ET AL, "White light emission of monolithic InGaN / GaN grown on morphology-controlled, nanostructured GaN templates", page 225703 the whole documentCategories:X Document indicating lack of novelty or inventive step A Document indicating technological background and / or state of the art. Y Document indicating lack of inventive step if combined with one or more other documents of same category. P Document published on or after the declared priority date but before the filing date of this invention. & Member of the same patent family E Patent document published on or after, but with priority date earlier than, the filing date of this application.Field of Search:Search of GB, EP, WO &US patent documents classified in the following areas of the UKCX :Worldwide search of patent documents classified in the following areas of the IPC_____________HO IL_______________________________________________________The following online and other databases have been used in the preparation of this search reportInternational Classification:Subclass Subgroup Valid From HO IL 0033 / 32 01 / 01 / 2010 HO IL 0033 / 06 01 / 01 / 2010 HO IL 0033 / 08 01 / 01 / 2010 HO IL 0033 / 24 01 / 01 / 2010

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