A semiconductor wafer and method of testing the same

Abstract

A semiconductor wafer 100 including a plurality of integrated circuits (IC) 111, 112 – 11N arranged in a plurality of sets of groups 110, 110’. Each set contains more than one IC and each IC is conne

Description

Technical Field

[0001] The present disclosure relates to a semiconductor wafer and corresponding method of testing a plurality of integrated chips on the semiconductor wafer. The disclosure also relates to a testing device for use with the semiconductor wafer. Background

[0002] For most types of integrated circuit (IC) it is necessary to perform one or more functional tests to check that the IC fulfils its specification. These tests typically require electrical connections to be made with some or all of the IC’s contact pads, then signals to be applied to one or more pads and then other signals to be measured from one or more pads. This has the effect of powering some of the IC’s circuits and checking that their response is as expected. Such functional testing is conventionally performed by a probe station, which connects to, and tests, each IC in turn. The serial nature of such a process leads to a relatively low throughput. Multiple probe stations may be required to enable a sufficient throughput of ICs, adding to costs of manufacture. Whilst low volume, high cost ICs may withstand this cost burden, it becomes significant for high volume, low cost ICs, for instance those used in Radio frequency identification (RFID) devices or RFID tags. To maximise efficiency, such functional testing must be performed before the ICs are singulated. This is referred to as on-wafer functional testing.

[0003] US7312622 describes a wafer having several regions referred to as reticles. The ICs are linked to each other and to one or more test sites in a reticle by signal tracks running along scribe lines. By arranging test sites in all four corners of each reticle, four reticles may be tested simultaneously in a single position of a four-point probe contact, e.g. over test sites 202, 203, 204 and 206 identified in figure 2 of US7312622. The test methodology requires each IC to be addressed in turn by cycling through ID sequences in the test input signals until all of the ICs in the connected reticles have been tested. This is only applicable to ‘reader talks first’ RFID architectures. Multiple signal lines in the scribe lanes carry inputs such as Vdd, a demodulated RFID signal, and various other I / Os, to and from each IC.

[0004] This on-wafer functional testing method can only address a limited number of ICs from each test site (i.e. the ICs in four adjoining reticle fields), and still requires serial IC testing using a probe station, along with the associated throughput and cost disadvantages. The present disclosure seeks to mitigate the above-mentioned limitations. Summary

[0005] According to a first aspect of the disclosure, there is provided a semiconductor wafer comprising a plurality of integrated circuits arranged in a plurality of sets that include at least one test set; wherein for each test set the semiconductor wafer comprises one or more test contact areas; and wherein at least one integrated circuit in the test set is coupled to the one or more test contact areas.

[0006] Optionally, the test contact areas are distributed along a path extending between two virtual points of the semiconductor wafer. The path may be a linear path or a semicircular path or a curved path or a non-geometric path. For instance, the path may extend between two virtual points on the edge of the semiconductor wafer that are diametrically opposed.

[0007] Optionally, the one or more test contact areas are provided on a peripheral region of the semiconductor wafer; or wherein the one or more test contact areas are provided along an axis of the semiconductor wafer.

[0008] For instance, a plurality of test contact areas may be provided along a central axis or a symmetry axis of the semiconductor wafer.

[0009] Optionally, the at least one integrated circuit in the test set comprises a first contact pad connected to the one or more test contact areas.

[0010] Optionally, each integrated circuit in the test set comprises a first contact pad and a second contact pad; wherein the first contact pad is connected to a first test contact area and the second contact pad is connected to a second test contact area.

[0011] Optionally, the semiconductor wafer has a first half portion and a second half portion and the one or more test contact areas are provided on the same half portion.

[0012] Optionally, a plurality of contact pads of adjacent integrated circuits in a test set are connected together to form an extended contact pad; or wherein a plurality of contact pads of adjacent integrated circuits in a test set are connected via a connecting channel.

[0013] Optionally, each integrated circuit in the test set comprises two power contact pads and one or more communication contact pad.

[0014] Optionally, a plurality of contact pads extends between several test sets.

[0015] Optionally, the one or more test contact areas comprise an area of a conductor layer on a surface of the wafer. For instance the conductor layer may be a redistribution layer (RDL).

[0016] Optionally, each test set is arranged as a linear array of integrated circuits. For instance, the linear array may extend across the semiconductor wafer. The linear array may extend from one edge of the semiconductor wafer to another edge.

[0017] Optionally, the plurality of integrated circuits comprises radio frequency identification (RFID) integrated circuits.

[0018] According to a second aspect of the disclosure, there is provided a testing device for use with a semiconductor wafer according to the first aspect, the testing device comprising a wafer connector having one or more terminals adapted to couple to the one or more test contact areas; a signal generator configured to generate a test signal; and a signal analyser adapted to receive and analyse one or more response signals from the semiconductor wafer.

[0019] Optionally, the signal analyser is configured to identify from which integrated circuit a response signal is arising from.

[0020] Optionally, the signal analyser is configured to decode the response signal to recover data from the integrated circuit.

[0021] For instance, the data may comprise an integrated circuit identifier. The signal analyser may be configured to demodulate the response signal to obtain the data.

[0022] Optionally, the signal analyser is configured to separate individual response signals in time or frequency.

[0023] Optionally, the signal analyser is configured to output a test result for each integrated circuit in the test set, wherein a positive test result indicates that the integrated circuit is functional, and a negative test result indicates that the integrated circuit is non-functional.

[0024] For instance, when the response received is within the specification of the IC the signal analyser may return a positive response; and when the response received is outside of the specification of the IC, or when no response is received, the signal analyser may return a negative response.

[0025] Optionally, the signal analyser is configured to output a negative test result when no response signal is received from the integrated circuit within a predefined duration.

[0026] Optionally, the wafer connector comprises a cavity adapted to receive the semiconductor wafer.

[0027] Optionally, the wafer connector has a first wall and a second wall forming the cavity, and wherein the one or more terminals are provided on the first wall.

[0028] Optionally, the wafer connector has a first wall provided with a recess forming the cavity, and wherein the one or more terminals are provided on the recess.

[0029] Optionally, the wafer connector comprises a clamp configured to engage with the peripheral region of the semiconductor wafer.

[0030] Optionally, the test signal is configured to deliver power or both power and an interrogation signal to the integrated circuits in the one or more test sets.

[0031] Optionally, the one or more terminals are adapted to form a contactless capacitive coupling to the one or more test contact areas; or wherein the one or more terminals are adapted to form a physical contact to the one or more test contact areas.

[0032] According to a third aspect of the disclosure there is provided a method of testing a plurality integrated chips on a semiconductor wafer according to the first aspect, the method comprising applying a test signal to one or more test sets of integrated circuits via at least one test contact area per test set; receiving one or more response signals from the one or more test sets; and analysing the one or more response signals.

[0033] For instance, the one or more response signals may be analysed to verify the functionality of the integrated circuits present in each test set. This may be achieved by checking a list of unique identifiers transmitted by each test set against a reference list of expected unique identifiers for that test set.

[0034] Optionally, upon receipt of the test signal each integrated circuit in the test set modulates an impedance between two contact pads of the integrated circuit. Description of the Drawings

[0035] The disclosure is described in further detail below by way of example and with reference to the accompanying drawings, in which: figure 1 is a diagram of a semiconductor wafer according to the disclosure; figure 2 is a diagram of a semiconductor wafer according to the disclosure; figure 3 is a top view of a portion of a semiconductor wafer showing a test set of integrated circuits; figure 4 is a perspective view of a testing device for testing a semiconductor wafer as shown in figures 1 or 2; figure 5 is a flow chart of a method for testing a plurality integrated chips on a semiconductor wafer; figure 6 is a diagram showing the semiconductor of figure 1 coupled to the testing device of figure 4; figure 7A is a top view of a selected portion of a wafer provided with a plurality of flexible integrated circuits; figure 7B is a cross sectional view of the wafer of figure 7A along the x axis; figure 8A is a top view of a selected portion of another wafer provided with a plurality of flexible integrated circuits; figure 8B is a cross sectional view of the wafer of figure 8A along the y axis; figure 9A is a top view of a selected portion of another wafer provided with a plurality of flexible integrated circuits; figure 9B is a cross sectional view of the wafer of figure 9A along the y axis. Detailed Description

[0036] Figure 1 is a schematic diagram of a semiconductor wafer according to the disclosure. The semiconductor wafer 100 includes a plurality of integrated circuits arranged in a plurality of sets. In this example only three sets are represented and labelled 101, HOand 110’.The set 101 is a conventional set of integrated circuits that may be arranged in any desired fashion. The sets 110 and 110’ are referred to as test sets, for which one or more test contact areas are provided. For each test set at least one IC is coupled to the one or more test contact areas. The contact pads of each individual IC may be connected together directly to form an extended contact pad. Alternatively, different contact pads may be coupled via an additional connecting channel or layer. Each test set may be arranged as a linear array of integrated circuits. For instance, the linear array may extend across the semiconductor wafer. The linear array may extend from one edge of the semiconductor wafer to another edge. The test set 110 has a series of N integrated circuits (ICs) 111-11N connected to two test contact areas labelled 130a and 130b. For example, the IC 111 has a first contact pad 121a connected to the test contact area 130a via channel 140a, and a second contact pad 121b connected to the test contact area 130b via channel 140b. In this example all of the ICs in the test set 110 are connected in the same fashion, however it will be appreciated that some ICs may not be connected to the test contact areas 130a and 130b, or may be connected to only one of them. IC contact pads 121a, 121b may be electrical contact pads for interfacing the IC to a system into which it becomes assembled, in use. For instance, for RFID ICs, the contact pads may be connected to an antenna when assembled for use.

[0037] The test set 110’ has a series of N integrated circuits (ICs) 11T-11N’ connected to two test contact areas labelled 130’a and 130’b. In this test set the first contact pads of each IC are merged together to form a single extended contact pad 140’a, the end of which forms the test contact area 130’a. Similarly, the second contact pads of each IC are merged together to form a single extended contact pad 140’b, the end of which forms the test contact area 130’b. For example, the IC 11T has a first contact pad 121’a connected to the test contact area 130’a via channel 140’a, and a second contact pad 121 ’b connected to the test contact area 130’b via channel 140’b. The contact pads of each IC, once the ICs have been singulated, may be electrical contact pads for interfacing the IC to a system into which it becomes assembled, in use.

[0038] It will be appreciated that the electrical connection between individual contact pads of ICs may be achieved in different fashion. In one variation, the contact pads of adjacent sets of ICs (for instance set 110 and 110’) are connected together, as well as the contact pads of adjacent ICs in each set.

[0039] In figure 1, the test contact areas 130a, 130b, 130’a, 130’b are located on a peripheral region of the wafer. The peripheral region of the semiconductor wafer may extend from the edge of the wafer towards the centre of the wafer to define a finite width of the peripheral region. More generally, the test contact areas of the various test sets present on the wafer may be distributed along a virtual path extending between two virtual points of the semiconductor wafer, for example a top point and a bottom point. For instance, such a path may be a linear path or a semicircular path or a curved path, or a non-geometric path. The path may extend between two virtual points on the edge of the semiconductor wafer that are diametrically opposed, such as virtual points A and B shown in figure 1. The path may extend along the edge of the semiconductor wafer or may go through a half portion of the semiconductor wafer, or may even be a straight line between the two opposite virtual points.

[0040] It will be appreciated that by using the arrangements described above, all of the ICs in a test set can be tested using a single placement of one or more testing device terminals. An example testing device is described later with reference to Figure 4. The test contact areas 130a, 130b or 130’a and 130’b may be provided for all rows on the wafer so, by extension, all of the ICs in multiple test sets on the wafer may be tested using a single placement of the required number of testing device terminals on the test contact areas. The testing device terminals may be simpler and less delicate than conventional high precision probe contacts. Test contact areas may be similar in structure to any other conducting features on the upper surface of the wafer. For example a test contact area may comprise an area of a conductor layer on the upper surface of the wafer, such as a redistribution layer (RDL). A test contact area may comprise further layers or structures beneath a conductor on the upper surface of the wafer. In some examples, test contact areas may comprise structural features similar to those of IC contact pads.

[0041] It will be appreciated that the proposed approach may be used with different types of ICs, and could be extended to ICs having more or fewer than two contact pads. Some ICs may only require a single contact pad to be tested, while other ICs may require 2 or more contact pads. For example the ICs may be provided with two pads for powering the IC (including a ground pad), and one or more command pads, also referred to as communication pads or signal pads. When the IC is for use in an ID tag, only two contact pads may be required.

[0042] The test sets 110 and 110’ are arranged in a linearfashion, however they could be arranged as columns or in two dimensional arrays. The number of test sets may also vary. For instance all of the ICs present on the wafer could be arranged in one or more test sets.

[0043] The wafer 100 could be implemented on different types of substrates, such as a polyimide substrate among others.

[0044] Figure 2 is a schematic diagram of another semiconductor wafer according to the disclosure. In this example the wafer 200 includes three test sets 210’ each being implemented as the test set 110’ of Figure 1. The same reference numerals are used to represent the same features. In this case for each set 210’ the test contact areas 130’a and 130’b are located at or near the midpoint of the extended contact pad 140’a and 140’b, respectively. In this example the test contact areas are located along the symmetry axis z of the wafer.

[0045] Figure 3 is a top view of a portion of a semiconductor wafer showing a test set of integrated circuits. The wafer 300 is only shown partially to focus on the test set 310 provided between two other sets 301 and 302. In this example the sets 301 and 302 are of standard design (i.e. with their contact pads isolated from those of neighbouring ICs in the same row). The test set 310 includes several ICs of which only 6 are shown labelled 311 to 316. The ICs in a row are aligned and have their equivalent contact pads electrically connected. The top contact pads 321a-326a of each IC are connected together. Similarly, the bottom contact pads 321b-326b are also connected together. The rows of contact pads extend continuously to the edge of the wafer, from where they can be conveniently contacted to a testing device at test contact areas.

[0046] Figure 4 is a perspective view of a testing device for testing a semiconductor wafer as shown in Figures 1 or 2. The testing device 400 includes a wafer connector 410, a signal generator 420 for generating a test signal, and a signal analyser 430 adapted to receive and analyse one or more response signals from the semiconductor wafer. In this example the wafer connector 410 forms a cavity configured to receive the semiconductor wafer. The housing 405 has a slot 412 at the entrance of the cavity 410. A terminal 414 is provided on a wall of the cavity 410 to form a coupling to the one or more test contact areas of the wafer. The terminal 414 may be a single terminal extending along an area that is sufficient to couple with a plurality of test contact areas. Alternatively, multiple smaller terminals may be provided and arranged so that each terminal couples to one or more test contact area. The coupling between terminal and test contact area may be achieved by a physical coupling (direct connection) or a contactless capacitive coupling. Therefore the terminal 414 may be designed in various ways to accommodate a particular arrangement of test areas as illustrated for example in the wafer topologies of Figures 1 or 2. In an exemplary implementation, the terminal or terminals are adapted to couple with all of the test contact areas present on the wafer. In this case neither the testing device terminal(s) nor the wafer need to move in order to test all of the ICs on the wafer. The wafer connector 410 may be implemented as a zero insertion force (ZIF) connector in which a wafer is placed and left until the testing device has tested the whole wafer’s ICs. Depending on implementation, the testing device may be operated in different ways. For instance the testing device may be operated to test a group formed of multiple sets simultaneously, and then the relative position of the terminal(s) with respect to the wafer may be changed to test another group formed of multiple sets. The number of test sets in a group may vary for example one or two, four, eight... set(s)). In another example the testing device may be operated to test all ICs on the wafer simultaneously.

[0047] The testing device 400 could also be modified to include multiple slots and cavities arranged in a cassette-like stack fashion, so that many wafers may be loaded I unloaded in parallel. The signal generator 420 and the signal analyser 430 may also be configured to perform parallel testing of the wafers. Other arrangements could also be considered. For instance, the wafer connector 410 may be provided on a platform implemented having a recess forming a cavity, and one or more terminal may be provided in the recess. In another example the wafer connector may be implemented as a clamp configured to engage with the peripheral region of the semiconductor wafer. The clamp may be located in a wafer carrier, cassette or other structure in the IC production line. Alternatively, non-contact testing may be enabled by features in the wafer connector 410 that couple capacitively with test contact areas 130a, 130b, 130’a, 130’b or with channels 140a, 140b, or with extended contact pads 140’a, 140’b on the wafer. Such features in the wafer connector may comprise conductive features that are positioned proximally to, and in alignment with, the afore-mentioned features on the wafer.

[0048] Figure 5 is a flow chart of a method for testing a plurality integrated chips on a semiconductor wafer according to the disclosure. For instance the method may be applied to a semiconductor wafer as shown in Figure 1 or 2. At step 510 a test signal is applied to one or more test sets of integrated circuits via at least one test contact area per test set. For instance, the at least one test contact area may be provided on a peripheral region of the semiconductor wafer as shown in Figure 1, or along an axis of the wafer as shown in Figure 2. At step 520 one or more response signals are received from the one or more test sets of integrated circuits. At step 530 the one or more response signals are analysed. It will be appreciated that this method enables, in combination with the semiconductor wafers and testing devices described herein, many types of ICs to be tested efficiently whilst on wafer, in a scalable manner. The ICs may be either individually addressable or they may respond uniquely to a common stimulus. Therefore the test signal applied to a test set may be used to address all the ICs present in the test set, or to address a specific IC in the test set. In many examples a test set requires two test contact areas to provide two power connections and at least one test contact area for a signal connection or communication that could be the same test contact area as one of the power connections. Some specific and non-limiting examples of the method are described below.

[0049] In a first example a test set of passive, tag-talks-only (TTO) RFID ICs may be activated by applying power to them, for example by establishing a voltage difference between two test contact areas from a testing device. An appropriate anti-collision scheme allows the response signals of the ICs to be separated in time, and measured from a modulation of the impedance between either the same two test contact areas or between two other test contact areas. The response signals can be analysed to verify the functionality of the ICs, for example by checking their transmitted unique identifiers against a reference list of expected unique identifiers for that test set. In a second example a test set of uniquely addressable ICs, for example reader-addressable RFID ICs or ICs that are addressable over a common serial or parallel communications bus, such as I2C or USB, may be activated by applying power and interrogation signals to the appropriate test contact areas from a testing device. Analysis of the received signals provides the desired data to identify functional ICs in the test set.

[0050] Functional ICs will return a response that is either positive (IC within the specification) or negative (IC outside of the specification). Non-functional ICs may not return any response at all, which would also lead to a negative test result. Based on the analysis of the signal received from the ICs, a test result may be generated for each integrated circuit in the test set. A positive test result indicates that the integrated circuit is functional, hence operating as expected. A negative test result indicates that the integrated circuit is non-functional, hence departing from its expected mode of operation.

[0051] The proposed method can be used to test a whole row or column of ICs, or the whole wafer in a convenient fashion. For instance there is no need for high precision stepping via a probe station. This increases functional testing efficiency, and in turn reduces cost.

[0052] Figure 6 is a diagram showing the semiconductor wafer of Figure 1, coupled to the testing device of Figure 4. In operation, the wafer 100 is inserted into the cavity 410 so that the terminal 414 is in contact with the test contact areas 130a, 130b and 130’a and 130’b. The signal generator 420 (not shown in Figure 6) generates a test signal that is applied to the ICs via the test contact areas. The signal analyser 430 (not shown in Figure 6) then receives a response signal from each IC present in the test sets. The signal analyser then identifies from which IC the response signal is arising. This may be achieved in different ways. The response signals may contain information that provides the identity of the IC; alternatively the response signals may be separated in time or in frequency.

[0053] A timeout duration may also be used. For instance any IC not responding within a predefined period (timeout duration) may be deemed to be non-functional. The timeout duration may be chosen to maintain a high throughput, without unduly increasing the likelihood of false negatives. Depending on the application only a predefined percentage of ICs may need to be tested on each wafer. For instance, if 99 % of responses are obtained within a specified time, then overall the wafer may be regarded as having a sufficiently high yield.

[0054] Using this approach it is possible to power up and test an entire set of ICs (for instance a row or a column of ICs) on the wafer in a single operation from just two test contact areas.

[0055] The nature of the test signal may depend on the type of ICs present on the wafer. When the ICs are RFID ICs, the test signal may be a signal that provides either power only or both power and an interrogation signal to the RFID IC. A set of ‘tag talks only’ ICs receives power from a test signal at a carrier frequency applied between the two test contact areas for that set, for instance 130’a and 130’b of set 110’. The test signal may be a radio frequency (RF) signal. Each RFID IC then modulates the impedance between its two contact pads, according to the data and logic functions of that IC. The signal analyser 430 then demodulates the response signal to recover the data.

[0056] Various protocols may be used to address many ICs. For instance an addressing / anti-collision protocol can handle 10,000s of die simultaneously, then the test setup could have common wiring for all sets (for instance all rows of ICs), and test the entire wafer simultaneously with a single testing device (rather than needing a separate testing device per row). The ICs may perform their impedance modulation sequence in a time-separated fashion. This may be achieved using a so-called anticollision scheme. Such schemes can be used to enable RFID applications in which multiple RFID ICs are located within the sensitive range of a single reader. Examples include the use of random delays by each IC, and the ‘tag only talks after listening’ protocol. Such schemes also serve to enable the modulation sequence of each IC in a set to be isolated, and therefore each IC to be functionally tested, in the presence of the others in its set. When the signal analyser 430 has detected all of the modulation sequences in the set, for example when the number of distinct sequences is equal to the number of ICs in that set, the test is complete. In a separate step, dicing or singulation may then be used to disconnect all ICs from each other.

[0057] When the contact pads and / or test contact areas of adjacent sets of ICs are connected together, as well as the contact pads of adjacent ICs in each set, the testing device 400 applies the power-up signals (and the modulation sequence detection) to alternate rows of ICs, instead of to every row of ICs.

[0058] The approach of the disclosure is applicable to different types of RFID ICs including ‘tag talks only’, ‘tag only talks after listening’ and ‘tag talks first’ RFID ICs, as well as ‘reader talks first’ types. In the latter case, each individual IC could be addressed in signals sent along the shared conductor (‘bus’) from the tester. Similarly, it could be used for any non-RFID circuit where I / O is via a bus architecture (e.g. could have >2 parallel tracks going across the wafer).

[0059] Figure 7A is a top view of a selected portion of a wafer provided with a plurality of flexible integrated circuits. The wafer 700 has an array of flexible ICs (“FlexICs”). In Figure 7A the array only shows three columns and three rows for nine ICs. Each flexible IC has a communication contact pad 710 connected to a communication addressing rail (also referred to as communication bus 720) that extends in the direction of a first axis (X axis). First and second power addressing rails 730 and 740 are also provided. The first and second power addressing rails are parallel to each other and extend in the direction of a second axis (Y axis) substantially perpendicular to the first axis.

[0060] Figure 7B is a cross sectional view of the wafer of Figure 7A along the X axis. The communication bus 720 along the X axis is provided between two upper dielectric layers of the IC. The communication contact pad 710 is provided on top of the upper dielectric layer and is connected to the communication bus by a connecting via. The first and second power addressing rails 730, 740 are also provided on top of the upper dielectric layer. They are part of a redistribution layer (RDL), which may be implemented as a metallic layer or as a printed conductive ink layer, for example.

[0061] In this example a single “column” of ICs is powered up using the power rails along the Y-direction, for contacts supplying Vdd / Gnd references, while communication is restricted to one “row” of ICs, via the communication rail along the X-direction. This permits individual ICs to be isolated (tested) while still only connecting from the wafer edge. This wafer topology reduces or eliminates the requirement for the ICs to have an anti-collision scheme or to be otherwise individually addressable, hence broadening the applicability of the technique to a wider range of ICs. Whilst not useful for two-pad RF chips, this wafer topology may be used with ICs having more than two pads, or for other externally powered ICs (e.g. active RFID ICs, non-RFID ICs). Row and column addressing may be realised in several other ways.

[0062] Figure 8A is a top view of a selected portion of another wafer provided with a plurality of flexible integrated circuits. Figure 8B is a cross sectional view of the wafer of Figure 8A along the Y axis. In Figure 8A the array only shows three columns and three rows for nine ICs. Each flexible IC has a power and communication contact pad 810 connected to a power and communication addressing rail (also referred to communication bus 820) that extends in the direction of a first axis (X axis). A power pad 830 is connected to a power rail 840 that extends in the direction of a second axis (Y axis) substantially perpendicular to the first axis.

[0063] In this topology the power and communication contacts pads 810 and the power contact pads 830 cross the dice lanes between flexible ICs. This provides a relatively large contact area that facilitates testing. For two terminal ICs the power and communication addressing rail 820 may be connected to the ICs’ Vdd / signal potential, and the power rail 840 may be connected to the ICs’ Gnd potential. The row and column arrangement of these rails and contact pads may make use of vias between the RDL and one or more lower metal layers for one or both rails (as shown). This example also shows contact pads that do not extend across the full width of the FlexIC, hence reducing the floorplan area taken up by those contacts (if circuitry cannot be placed beneath them).

[0064] Figure 9A is a top view of a selected portion of another wafer provided with a plurality of flexible integrated circuits. Figure 9B is a cross sectional view of the wafer of Figure 9A along the Y axis. The topology of the wafer 900 is similar to the topology of the wafer 800, however in this case each of the contact pads is confined within the area of one flexible ICs. In other words, the contact pads do not extend into or across the dice lanes between ICs. Of course it will be appreciated that although the topologies of the wafers of figures 7, 8 and 9 have been shown for flexible ICs, they would also apply for non-flexible ICs.

[0065] A skilled person will therefore appreciate that variations of the disclosed arrangements are possible without departing from the disclosure. Accordingly, the 5 above description of the specific embodiments is made by way of example only and not for the purposes of limitation. It will be clear to the skilled person that minor modifications may be made without significant changes to the operation described. 10

Claims

1. A semiconductor wafer comprisinga plurality of integrated circuits arranged in a plurality of sets that include at least one test set;wherein for each test set the semiconductor wafer comprises one or more test contact areas; and wherein at least one integrated circuit in the test set is coupled to the one or more test contact areas.

2. The semiconductor wafer as claimed in claim 1, wherein the test contact areas are distributed along a path extending between two virtual points of the semiconductor wafer.

3. The semiconductor wafer as claimed in claim 1 or 2, wherein the one or more test contact areas are provided on a peripheral region of the semiconductor wafer; or wherein the one or more test contact areas are provided along an axis of the semiconductor wafer.

4. The semiconductor wafer as claimed in any one of the preceding claims, wherein the at least one integrated circuit in the test set comprises a first contact pad connected to the one or more test contact areas.

5. The semiconductor wafer as claimed in claim 4, wherein each integrated circuit in the test set comprises a first contact pad and a second contact pad; wherein the first contact pad is connected to a first test contact area and the second contact pad is connected to a second test contact area.

6. The semiconductor wafer as claimed in any one of the preceding claims, wherein the semiconductor wafer has a first half portion and a second half portion and wherein the one or more test contact areas are provided on the same half portion.

7. The semiconductor wafer as claimed in any one of the preceding claims, wherein a plurality of contact pads of adjacent integrated circuits in a test set are connected together to form an extended contact pad; or wherein a plurality of contact pads of adjacent integrated circuits in a test set are connected via a connecting channel.

8. The semiconductor wafer as claimed in any one of the preceding claims, wherein each integrated circuit in the test set comprises two power contact pads and one or more communication contact pad.

9. The semiconductor wafer as claimed in any one of the preceding claims, wherein a plurality of contact pads extends between several test sets.

10. The semiconductor wafer as claimed in any one of the preceding claims, wherein the one or more test contact areas comprise an area of a conductor layer on a surface of the wafer.

11. The semiconductor wafer as claimed in any one of the preceding claims, wherein each test set is arranged as a linear array of integrated circuits.

12. A testing device for use with a semiconductor wafer as claimed in any one of the preceding claims, the testing device comprisinga wafer connector having one or more terminals adapted to couple to the one or more test contact areas;a signal generator configured to generate a test signal; and a signal analyser adapted to receive and analyse one or more response signals from the semiconductor wafer.

13. The testing device as claimed in claim 12, wherein the signal analyser is configured to identify from which integrated circuit a response signal is arising from.

14. The testing device as claimed in claim 12 or 13, wherein the signal analyser is configured to decode the response signal to recover data from the integrated circuit.

15. The testing device as claimed in any one of the claims 12 to 14, wherein the signal analyser is configured to separate individual response signals in time or frequency.

16. The testing device as claimed in any one of the claims 12 to 15, wherein the signal analyser is configured to output a test result for each integrated circuit in the test set, wherein a positive test result indicates that the integrated circuit is functional, and a negative test result indicates that the integrated circuit is non-functional.

17. The testing device as claimed in any one of the claims 12 to 16, wherein the signal analyser is configured to output a negative test result when no response signal is received from the integrated circuit within a predefined duration.

18. The testing device as claimed in any one of the claims 12 to 17, wherein the wafer connector comprises a cavity adapted to receive the semiconductor wafer.

19. The testing device as claimed in claim 18, wherein the wafer connector has a first wall and a second wall forming the cavity, and wherein the one or more terminals are provided on the first wall.

20. The testing device as claimed in claim 18, wherein the wafer connector has a first wall provided with a recess forming the cavity, and wherein the one or more terminals are provided on the recess.

21. The testing device as claimed in any one of the claims 12 to 20, wherein the wafer connector comprises a clamp configured to engage with the peripheral region of the semiconductor wafer.

22. The testing device as claimed in any one of the claims 12 to 21, wherein the test signal is configured to deliver power or both power and an interrogation signal to the integrated circuits in the one or more test sets.

23. The testing device as claimed in any one of the claims 12 to 22, wherein the one or more terminals are adapted to form a contactless capacitive coupling to the one or more test contact areas; or wherein the one or more terminals are adapted to form a physical contact to the one or more test contact areas.

24. A method of testing a plurality integrated chips on a semiconductor wafer as claimed in any one of the claims 1 to 11, the method comprisingapplying a test signal to one or more test sets of integrated circuits via at least one test contact area per test set;receiving one or more response signals from the one or more test sets; andanalysing the one or more response signals.

25. The method as claimed in claim 24, wherein upon receipt of the test signal each integrated circuit in the test set modulates an impedance between two contact pads of the integrated circuit.

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