Integrated circuit chip

Abstract

An integrated circuit chip IC 100 comprises a substrate 102, active / circuit layer(s) 104, and an electrical connection region (figure 2 shows assembly) preferably comprising a metallisation layer 106

Description

[0001] The present invention relates to an integrated circuit (IC) chip, an electronic device comprising application circuitry and at least one IC chip, and to methods and / or apparatus for fabricating an IC chip and / or for assembling at least one IC chip with application circuitry to form an electronic device. The invention has particular, but not exclusive, relevance to the provision of a flexible IC chip having a layer for protecting and / or for supporting the IC chip, during assembly with corresponding application circuitry to form an electronic device such as, but not limited to, a radio-frequency identification (RFID) tag.

[0002] Historically, during the manufacture of IC chips, a wafer consisting of a thin layer of semiconductor material such as crystalline Silicon (c-Si) is provided which serves as a substrate for supporting microelectronics that form the IC chips. Such wafers typically have an extreme level of purity and are formed in a single crystal structure.

[0003] During the manufacturing process the IC chips may be built up on the wafer. For example, devices such as diodes, transistors, capacitors, and resistors, can be built up by forming p-type and n-type regions, at appropriate locations, in the semiconductor substrate (or other semiconducting layers) using appropriate doping, and by building up and patterning one or more layers of insulating and / or conducting material using appropriate fabrication processes. Layers of insulating, semiconducting and / or conducting material are typically formed using appropriate deposition, growth and / or crystallisation processes. The location of the n-type and p-type regions, the pattern of insulating, semiconducting and / or conducting material in each layer, and the interconnectivity between them, is typically defined using appropriate photolithographic processes.

[0004] Whilst fabrication on crystalline semiconductor substrates is widespread, fabrication of IC chips may be carried out on other substrate materials including flexible insulating substrates. For example, it is known to use a flexible substrate formed of, for example, a thin, heat-resistant material such as polymers to manufacture flexible IC chips. Where the substrate is flexible, a rigid carrier is typically used to support the flexible substrate during the subsequent manufacture of electronic devices on that flexible substrate to form the flexible IC chip, for example using manufacturing processes similar to those described above for a crystalline semiconductor wafer, albeit adapted to be suitable to the flexible substrate being used (e.g., using lower temperatures suitable for polymer substrates or the like).

[0005] Over the past decade there has been a large increase in the demand for flexible IC chip based electronic devices, especially for electronic devices such as RFID devices / tags that typically incorporate simple two terminal flexible IC chips. This increase in demand has been driven, in particular, by the increasing and varied applications of RFID tags in fields as diverse as medical devices, product packaging, asset tracking, security, logistics, etc.

[0006] IC chips, whether crystalline semiconductor-based IC chips or flexible IC chips, once fabricated, are typically separated / singulated (or diced) into individual dies for subsequent removal and integration with external application circuitry to form an end product in the form of an electronic device such as an RFID tag, or the like.

[0007] One method of assembly that is widely used includes the use of an anisotropic conductive medium such as an anisotropic conductive adhesive (ACA) I anisotropic conductive paste (ACP) / anisotropic conductive film (ACF) that is deposited as a blanket layer onto a surface of a substrate carrying the application circuitry with exposed connection regions (referred to as ‘bond pads’ or ‘contact pads’) formed from a layer of metal (or other conductive material) for allowing electrical connection to the application circuitry. The ACA typically comprises a spatial distribution of conductive particles, in a non-conductive polymer matrix (for example formed of an epoxy resin or acrylic), that is intrinsically random. A surface of the IC chip, carrying complementary connection regions, is then appropriately aligned for required electrical connectivity with the application circuitry and then pressed into the ACA on the substrate with sufficient pressure to press the conductive particles into the connection regions of the IC chip and the application circuitry. Heat is also applied to the assembly to cure the polymer matrix and secure the IC chip in place with the required electrical connectivity to the application circuitry.

[0008] The concentration and size of the conductive particles in the ACA, and the thickness of the ACA, is such that the adhesive will allow electrical conduction generally orthogonal to the bonded surfaces of the application circuitry substrate and IC chip substrate, through the thickness of the adhesive, without allowing transverse flow generally parallel to those opposing surfaces. Accordingly, when the IC chips are bonded to the application circuitry an orthogonal electrical connection is formed between the complementary connection regions of the application circuitry and the IC chip without any transverse electrical connection being formed (parallel to the surfaces of the IC chip substrate I application circuitry substrate) between different laterally spaced connection regions.

[0009] It can be seen, therefore, that the use of ACA beneficially allows the assembly of IC chips and external application circuitry, without the need for localised placement of a conductive adhesive onto the relatively small complementary connection regions on the bonded surfaces of the application circuitry substrate and / or IC chip substrate. This helps to reduce the complexity of assembly processes, and hence the cost. Whilst this is particularly important in the context of flexible IC chips, it also provides benefits in the context of crystalline semiconductor-based IC chips.

[0010] It will be appreciated that, the pressure that needs to be applied to the IC chip during assembly is relatively high, to ensure that the ACA layer is squeezed to form a sufficiently thin film (i.e., slightly thinner than the average size of the conductive particles), and to ensure that the particles are sufficiently pressed into the respective electrical connection regions of both the IC chip and the application circuitry to form good electrical connections with those regions. However, as the ACA is deposited as a blanket layer, the ACA will extend laterally beyond the connection regions and in-between the active circuitry of the IC chip and the application circuitry. Moreover, whilst the active circuitry is typically protected by an insulating / passivating layer such as an oxide, a nitride, or the like, the insulating layer can be relatively thin (typically <1pm) and / or soft (especially in the case of flexible IC chips). Accordingly, when pressure is applied during assembly the conductive particles in the ACA (which may have a size that is several times the thickness of the protective insulating / passivating layer) can damage (or ‘punch through’) the insulating / passivating layer, and potentially the underlying active circuitry, causing unpredictable parasitic effects and even short / open circuits that result in the IC chip becoming unusable.

[0011] Moreover, as the electrical connection regions are typically formed from a relatively thick layer of a metal (or other conductive material), when the connection regions of the IC chip and the connection regions of the application circuitry are bonded together, a relatively large gap may arise between the surface of the IC chip substrate and the surface of the application circuitry substrate in areas where a connection region is not present. Whilst this gap may be at least partially filled with ACA, the pressures and temperatures used in the assembly process can result in stress induced distortion of, and or damage to, the IC, as the forces applied to the IC chip during assembly tend to urge the IC chip substrate into the gap in areas located laterally between the connection regions.

[0012] Due to the nature of the flexible substrate used these issues are of particular concern in the context of flexible IC chips. Specifically, by their nature, the flexible substrates tend to be thin, flexible, pieces of plastic or the like, which deform easily under pressure and are particularly prone to damage from high point / indentation forces. Accordingly, flexible IC chips are particularly susceptible both to distortion such as ‘sagging’ between adjacent connection regions or tracks of the application circuitry and to conductive particle induced damage. Nevertheless it will be appreciated that, during assembly, other forms of IC chip, including IC chips with rigid substrates, may also experience distortion, pressure induced stress related damage, and / or conductive particle induced damage.

[0013] To protect against these issues, a number of proposals have been made including to introduce additional stand-off features (e.g., pillars of dielectric or the like) to provide improved IC chip support, and / or to use a redistribution layer (RDL) formed of a blanket layer of metal (or other conductive material) as a shield that protects against damage such as ‘punch through’ caused by the hard metal particles in the ACA.

[0014] It will be appreciated that the use of a blanket layer RDL shield helps to provide a consistent flat structure as well and is thus beneficial for providing improved IC chip support and mitigating issues such as distortion or ‘sagging’ between adjacent connection regions or tracks of the application circuitry (even where stand-off features are not present).

[0015] However, the formation of stand-off features adds to process complexity as it requires additional deposition and patterning steps. Moreover, the use of a blanket RDL based shield introduces constraints on the design of the application circuitry (e.g., RFID antenna) to which the IC chip is ultimately bonded where the IC chip crosses that application circuitry, and hence reduces the flexibility available to designers of electronic devices that incorporate the IC chip. This lack of flexibility would also be present if an alternative flip-chip type assembly approach were used if some form of RDL shield is desirable.

[0016] The invention aims to provide an IC chip, an electronic device comprising application circuitry and at least one IC chip, and / or associated methods and / or apparatus that at least partially contributes to mitigating one or more of the above issues.

[0017] In one example described herein there is provided an integrated circuit chip comprising: a substrate on which is formed an integrated circuit; at least one connection region for forming an external electrical connection to the integrated circuit; and a plurality of shielding elements for providing protection of the integrated circuit and / or supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device; wherein the shielding elements are arranged in a tessellating pattern with gaps between adjacent shielding elements within the tessellating pattern.

[0018] The shielding elements may have a maximum dimension that is smaller than a minimum gap size defined for spacing of elements of the external circuitry. The gaps may have a width that is greater than an expected maximum dimension of a conducting particle forming part of an anisotropic conducting medium to be used for securing the integrated circuit chip to the external circuitry to form the electronic device.

[0019] Each of the shielding elements respectively forming the tessellating pattern may be a polygon shaped shielding element. At least a subset of the shielding elements may be regular polygon shaped shielding elements. The tessellating pattern may comprise a regular tessellation comprising the regular polygon shaped shielding elements. At least a subset of the regular polygon shaped shielding elements may be hexagon shaped shielding elements. A subset of the shielding elements may each have a respective shape that corresponds to part of the regular polygon shaped shielding elements. At least one connection region may have a polygonal shape having at least one edge that extends at a first angle, relative to an edge of the integrated circuit chip, that matches a second angle at which a side of an adjacent regular polygon shaped shielding element extends relative to that edge of the integrated circuit chip.

[0020] The at least one connection region may be trapezoidal in shape. The at least one connection region may have a polygonal shape that tessellates with a plurality of the regular polygon shaped shielding elements adjacent the boundary of the at least one connection region.

[0021] The tessellating pattern may extend substantially to opposing edges of the integrated circuit chip in at least one of a transverse and / or a longitudinal direction relative to the integrated circuit chip. The tessellating pattern may extend substantially to and around at least part of the boundary of the at least one connection region. The tessellating pattern and at least one connection region may be mutually configured to extend substantially an entire surface of the integrated circuit chip. The substrate may be a flexible substrate, and the integrated circuit chip is a flexible integrated circuit chip.

[0022] In one example described herein there is provided a method of fabricating an integrated circuit chip, the method comprising: providing a substrate; forming, on the substrate, an integrated circuit; forming at least one connection region for forming an external electrical connection to the integrated circuit; and forming a plurality of shielding elements for providing protection of the integrated circuit and / or supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device; wherein the shielding elements are arranged in a tessellating pattern with gaps between adjacent shielding elements within the tessellating pattern.

[0023] The at least one connection region and tessellating pattern of shielding elements may be formed from a common layer of conductive material. The conductive material of the common layer may be deposited in a deposition step forming part of the method. The at least one connection region and tessellating pattern of shielding elements may be patterned as part a common patterning step forming part of the method.

[0024] In one example described herein there is provided an electronic device comprising: electronic circuitry formed on an electronic device substrate; and an integrated circuit chip, as introduced above, electrically connected to the electronic circuitry to form the electronic device.

[0025] At least one supporting element may be provided on the electronic substrate for providing mechanical support to the integrated circuit chip. The at least one supporting element may comprise at least one structure comprising: an active structure; an inactive structure; a functional part of the electronic circuitry; a non-functional part of the electronic circuitry; at least part of a conductive routing trace; an extension of a contact region or pad; and / or at least part of a dummy circuit.

[0026] The electronic circuitry may comprise at least one antenna. The electronic device may be a radio frequency identification (RFID) device. The electronic device substrate may be a flexible electronic device substrate.

[0027] In one example described herein there is provided a method of assembling an electronic device, the method comprising: providing an electronic device substrate on which electronic circuitry of the electronic device is formed; providing integrated circuit chip as introduced above; and electrically connecting the integrated circuit chip to the electronic circuitry to form the electronic device.

[0028] The electrically connecting may comprise: depositing a layer of an anisotropic conducting medium on the electronic device substrate; positioning the integrated circuit chip relative to the electronic circuitry to align at least one connection region of the integrated circuit chip with at least one corresponding electrical connection region of the electronic circuitry; and / or pressing the integrated circuit chip, when in the aligned position, into the anisotropic conducting medium to form an electrical connection between the at least one connection region of the integrated circuit chip and the at least one corresponding electrical connection region of the electronic circuitry.

[0029] The electrically connecting may further comprise curing the anisotropic conducting medium to secure the integrated circuit chip in position.

[0030] Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a simplified three-dimensional view of an integrated circuit (IC) chip; Figure 2 is a is a simplified illustration showing a generalised procedure that may be used for fabricating the IC chip of Figure 1; Figure 3 is an illustration showing simplified illustrative cross-sections respectively through the IC chip of Figure 1 and through a corresponding circuit component with which that IC chip is to be assembled; Figure 4 is an illustration showing simplified illustrative cross-sections respectively through the IC chip of Figure 1 and through the corresponding circuit component with which that IC chip is to be assembled following the first stage of an assembly procedure; Figure 5 is an illustration showing simplified illustrative cross-sections respectively through the IC chip of Figure 1 and through the corresponding circuit component with which that IC chip is being assembled during a second stage of an assembly procedure; and Figure 6 is a simplified illustration of an alternative contact region design that may be used in the IC chip of Figure 1. Overview

[0031] Figure 1 is a simplified three-dimensional view of an integrated circuit (IC) chip 100. In the illustrated example, the IC chip 100 is generally rectangular having two substantially parallel short edges and two substantially parallel long edges.

[0032] The IC chip 100 comprises a substrate 102 having a surface on which an integrated circuit (IC) layer (or active layer) 104 is formed. An IC (not visible in Figure 1) is formed in the IC layer. The substrate 102 in this example is a flexible substrate. Nevertheless, it will be appreciated that the substrate 102 may be formed of any suitable rigid or flexible material depending on the application for which the IC is to be used.

[0033] A metallisation layer 106, which may be referred to as a redistribution (or redistributive) layer (RDL), extends over the IC layer 104 for substantially the whole area of the IC chip 100. The metallisation layer 106 is patterned to form a plurality of connection regions 106a (which may be referred to as ‘bond pads’ or ‘contact pads’) and a tessellating pattern 106b of isolated shielding elements 106b-1, 106b-2 separated by narrow isolating gaps / regions between adjacent shielding elements 106b-1,106b-2.

[0034] As will be described in more detail later the connection regions 106a are interconnected internally to the IC, whereas the shielding elements 106b-1, 106b-2, are not interconnected internally to the IC.

[0035] As seen in Figure 1, in this example, the tessellating pattern 106b comprises (primarily) a regular tessellation of substantially congruent regular polygon shaped (in this example hexagonal) shielding elements 106b-1 . Nevertheless, at the edges of the IC chip 100, and where the tessellating pattern 106b borders the connection regions 106a, the tessellating pattern 106b comprises a number of irregular polygon shaped (or ‘partial’) shielding elements 106b-2. In the illustrated example each partial shielding element 106b-2 has a respective shape that corresponds to part of the shape of the regular polygon shaped shielding elements 106b-1 (although it will be appreciated that this need not be the case).

[0036] The tessellating pattern 106b and the connection regions 106a are mutually configured together to extend substantially the entire surface of the IC chip 100 (other than the narrow gaps / regions between the shielding elements 106b-1, 106b-2, and between the shielding elements 106b-1, 106b-2, and the connection regions 106a). In this example, the tessellating pattern 106b is configured to extend substantially continuously to the transverse and longitudinal edges of the IC chip 100, other than where the tessellating pattern 106b interfaces with the connection regions 106a. Where the tessellating pattern 106b reaches the connection regions 106a, the tessellating pattern 106b extends to, and around the boundary of the connection regions 106a (with narrow isolating gaps / regions between the shielding elements 106b-1, 106b-2, and the connection regions 106a).

[0037] As seen in Figure 1, in the illustrated example the tessellating pattern 106b is oriented such that a pair of opposing sides of each regular polygon shaped shielding element 106b-1 respectively extend parallel to the short edges of the IC chip 100 (and hence perpendicular to the long edges of the IC chip 100). Nevertheless, it will be appreciated that the tessellating pattern 106b may be arranged in any suitable orientation (e.g., with a pair of opposing sides of each regular polygon shaped shielding element 106b-1 extending parallel to the long edges of the IC chip 100).

[0038] Beneficially, the maximum dimension of the shielding elements 106b-1, 106b-2 is configured to be less than a minimum gap size between elements (e.g., conductive elements such as conductive traces, bond pads, antenna tracks, and / or the like) of an application circuit with which the IC chip 100 is ultimately to be assembled (e.g., according to design rules associated with that application circuit). Moreover, the isolating gaps / regions between the shielding elements 106b-1, 106b-2 are beneficially configured to be wider than a maximum dimension of the conductive particles of an anisotropic conductive medium such as an anisotropic conductive adhesive (ACA) or the like that is to be used during the assembly of the IC chip 100 with the application circuit to form an associated electronic device.

[0039] In the illustrated example there are two connection regions 106a that are respectively located at the short edges of the IC chip 100. This arrangement may, for example, be appropriate for bridging correspondingly spaced parallel conductive traces I connection regions of the application circuit when the IC chip 100 is assembled with that application circuit to form the associated electronic device. Nevertheless, it will be appreciated that there may be any suitable number of connection regions 106a, located anywhere on the IC chip 100 (e.g., depending on the connectivity requirements imposed by the IC and / or application circuitry to which the IC is to be connected).

[0040] Each connection region 106a has a location, a size, and a shape that are configured to fit within the tessellating pattern 106b harmoniously, whilst also meeting the connectivity requirements imposed by the IC and / or application circuitry to which the IC is to be connected. Specifically, the location, the size, and the shape of each connection region 106a in this example are configured in a manner that minimises the number of partial shielding elements 106b-2 that need to be formed adjacent to that connection region 106a to form the tessellating pattern 106b (whilst maintaining a relatively simple quadrilateral shaped connection region).

[0041] For example, in the illustrated example, each connection region 106a has a generally isosceles trapezoidal shape having parallel longer and shorter bases with lateral edges (referred to as ‘legs’) extending from the longer base, at a common internal acute angle, a, to the shorter base. As seen in Figure 1, the longer base of each trapezoidal connection region 106a (in this example) extends along a different respective short edge of the IC chip 100. The lateral edges of at least one connection region are configured to extend at an angle, relative to an edge of the IC chip 100, that matches the angle at which one side of an adjacent regular polygon shaped shielding element extends relative to the same edge.

[0042] Specifically, the internal angle, a, at which each lateral edge of a corresponding trapezoidal connection region 106a extends (relative to its longer base) is configured to complement the internal angle, 0, at which a side of a respective adjacent regular polygon shaped shielding element 106b-1 extends (i.e., a = 180° - 0). In this example, therefore, as each regular polygon shaped shielding element 106b-1 is hexagonal, adjacent sides of the polygon shaped shielding elements 106b-1 extend at an internal angle, p, of 120° relative to one another. Thus, each lateral edge of a corresponding trapezoidal connection region 106a is configured to extend at an internal angle of 60° relative to the longer base of that trapezoidal connection region 106a.

[0043] Similarly, as seen in Figure 1, the length of each base of a corresponding trapezoidal connection region 106a is configured to correspond to the distance occupied by a respective whole number of adjacent regular polygon shaped shielding elements 106b-1 (including isolation gaps), as arranged in the regular tessellation along a line parallel to that base (i.e., taking account of the lateral offset between the adjacent regular polygon shaped shielding elements 106b-1 when arranged along that line).

[0044] Beneficially, the tessellating pattern 106b effectively forms a protective layer (or ‘RDL Shield’) across the surface of the IC chip 100 that does not impose significant restrictions on the configuration of any application circuitry that will lie directly between the IC chip 100, and a substrate (e.g., a flexible or rigid printed circuit board (PCB) or the like) on which that application circuitry is provided, following assembly. Specifically, restricting the maximum dimension of each shielding element 106b-1, 106b-2 to being smaller than a minimum gap size associated with the application circuitry to which the IC chip 100 will be attached, ensures that no shielding element 106b-1, 106b-2 will bridge (and hence short circuit) the conductive elements of any application circuitry designed according to the design rules of the system in which the IC chip 100 will be used.

[0045] Similarly, making the isolating gaps / regions between the shielding elements 106b-1, 106b-2 wider than a maximum dimension of the conductive particles of the anisotropic conductive medium ensures that adjacent shielding elements 106b-1, 106b-2 will not become electrically connected to one another during assembly. It will be appreciated that the use of anisotropic conductive medium represents just one technique (albeit a particularly efficient one) for attaching IC chips to application circuitry, and the presence of the tessellation based protective (RDL) shield may be beneficial even in scenarios where anisotropic conductive medium is not used. For bonding techniques that do not involve the use of anisotropic conductive medium such a restriction on the isolating gaps / region need not be imposed.

[0046] Beneficially the use a tessellating pattern 106b, such as that illustrated in Figure 1, in which the shielding elements 106b-1, 106b-2 are arranged in a manner in which the edges of adjacent shielding elements 106b-1, 106b-2 are not aligned with one another can help to mitigate the risk of stress induced damage to the IC chip 100 during assembly. Specifically, by arranging the shielding elements 106b-1, 106b-2 in this manner the edges of the shielding elements 106b-1, 106b-2 (and hence the isolating gaps / regions between the shielding elements 106b-1, 106b-2) do not form a contiguous straight line that extends fully across (or a substantial proportion of) the width and / or length of the IC chip 100 in any direction. The presence of any such contiguous straight lines could result in the IC chip 100 having non-uniform mechanical properties. Alternatively, or additionally, any such contiguous straight line could represent a line of weakness (e.g., in the manner of a fold line or fault line) that might be prone to damage during assembly (e.g., as a result of the stress arising from the pressures and temperatures involved relieving itself along the that line of weakness). Moreover, any such contiguous straight line could allow adhesive to flow into and along that line more easily, and hence the conductive particles to enter (and possibly build up within) that line, thus increasing the risk of damage from the conductive particles during assembly and the possibility of electrical connections inadvertently forming between the adjacent shielding elements 106b-1, 106b-2. It will be appreciated that the use of a tessellating pattern that does not avoid the formation of such contiguous straight line may, nevertheless, still provide significant improvements in the shielding provided to the IC and a reduction in a risk of stress induced damage.

[0047] The use of hexagonal (and part hexagonal) shielding elements 106b-1, 106b-2 represents a particularly simple and efficient way to form the tessellating pattern 106b. Specifically, a hexagon represents the highest order simple regular polygonal shape that can be used to produce a regular tessellation. Moreover, whilst other simple regular polygonal shapes could be used as the basis for producing a regular tessellation (e.g., squares or triangles), the use of such shapes for the shielding elements 106b-1, 106b-2 would result in the edges of adjacent shielding elements 106b-1, 106b-2 being aligned with one another in a manner that causes the formation of contiguous straight lines that extend fully across (or a substantial proportion of) the width and / or length of the IC chip 100. The use of a hexagon based tessellating pattern also allows the internal area of the shielding elements 106b-1, 106b-2 to be maximised for a given maximum dimension - i.e., having the smallest difference between the minimum and maximum dimensions for a given shape. Hence, the extent of the shielding provided by such a pattern can be maximised.

[0048] Notwithstanding the benefits provided by the use of a hexagon based regular tessellating pattern, other tessellating patterns could potentially be used including patterns based on a plurality of different regular and / or irregular polygonal shapes (and parts thereof), or a pattern based on a single irregular polygonal shape (and parts thereof).

[0049] Beneficially, configuring the shape of each connection region 106a to have edges that are angled to align with the (e.g., hexagonal) shielding elements also helps to increase the amount of rotation that can be tolerated during assembly (i.e., the rotational tolerance of the IC chip 100), for given size / area of connection region compared, for example, to using a simple rectangular connection region 106a. Having an improved rotational tolerance is of particular advantage for two-terminal IC chips 100, such as that illustrated, in which the connection regions 106a have a significant separation from one another, for example to allow the chip to be used to bridge parallel conductive traces of application circuitry such as antenna traces or the like.

[0050] It will be appreciated that additional support for the IC chip 100 may be provided by means of active or inactive structures and may be formed as a functional part or a non-functional part of the application circuitry on the substrate (e.g., flexible, or rigid PCB or the like) on which that application circuitry is formed. For example, metal structures in the form of conductive routing traces, extensions of contact pads, dummy circuits and / or the like, may be designed for the express purpose of providing additional mechanical support for the IC chip 100 during (and following) assembly. For example, antenna tracks comprising additional turns of a coil loop type antenna, may be introduced that pass between the IC chip 100 and the application circuitry substrate during assembly for providing the additional mechanical support. Alternatively (or additionally) conductive tracks may be routed from outside the area of the IC chip 100 to a pad or the like that is located within the perimeter of the IC chip 100 (as opposed to at the edges) during assembly for providing the additional mechanical support. Alternatively (or additionally) floating (unconnected) metal traces / structures may be formed on the application circuitry substrate for location between the middle (and / or somewhere near the middle) of the IC chip 100 and the application circuitry substrate during assembly. Such traces / structures may be configured to provide additional support to the IC chip 100 and hence allow (e.g., for a flexible IC chip) the IC chip 100 to sit “flat” on the surface of the traces / structures and not “sag” in-between contact pads (or the like), that are located at either end of the IC chip 100, during assembly. IC Chip Fabrication

[0051] A procedure for fabricating an IC chip 100, such as that illustrated in Figure 1, will now be described, by way of example only, with reference to Figure 2.

[0052] Figure 2 is a simplified illustration showing a generalised procedure that may be used for fabricating the IC chip 100. Specifically, Figure 2 illustrates, at (a) to (d), a series of simplified illustrative cross-sections through the (partially formed I completed) IC chip 100, each cross-section corresponding to a different stage of the fabrication procedure.

[0053] It will be appreciated that whilst Figure 2 illustrates formation of a single IC chip 100 for reasons of descriptive clarity, in a typical manufacturing scenario many (e.g., tens, hundreds, or even thousands of) such IC chips will be fabricated together on a single starting wafer of an appropriate material.

[0054] As seen at (a) in Figure 2, a substrate 102 of an appropriate starting material is initially provided upon which the IC can be formed. For a flexible IC chip, this starting material may, for example, comprise a flexible polymer such as polyimide, or some other suitable substrate material.

[0055] It will be appreciated that the substrate 102 may be formed on a rigid carrier (not shown) made of a rigid material (e.g., to facilitate manufacture of an IC on a flexible substrate to form a flexible IC chip). A rigid carrier may, for example, be formed from a transparent material such as glass although it will be appreciated that the rigid carrier may be formed of any other suitable flexible material, for example, polycarbonate, quartz, silicon, or any other known materials suitable for supporting the flexible substrate. Where the substrate 102 is formed on such a carrier the material forming the substrate 102 may, for example, be deposited using thin-film processes such as, for example: physical vapour deposition (e.g. sputter), chemical vapour deposition (e.g. plasma-enhanced chemical vapour deposition (PECVD)), vacuum deposition (e.g. thermal or electron-beam evaporation); coating (e.g. spin, dip, blade, bar, spray, or slotdie), printing (e.g. jet, gravure, offset, screen, or flexographic), pulsed-laser deposition (PLD), atomic layer deposition (ALD), lamination and / or any other suitable processes.

[0056] As seen at (b) in Figure 2, the next stage of the fabrication procedure comprises forming an IC layer 104 comprising at least one IC 104a on the substrate 102. For example, as those skilled in the art will be familiar with, the material forming each of one or more layers (e.g., conducting, semiconducting, and / or insulating layers) forming the IC 104a may be respectively deposited onto the flexible substrate 102. These IC layers may be patterned using conventional photoresist-based lithography, doped to form p-type and n-type regions where required, and / or etched using a suitable etchant, to form the required IC structure - for example an IC structure comprising: devices such as diodes, transistors, capacitors, and / or resistors, at appropriate locations; appropriate conductive paths interconnecting the devices; and insulating regions where necessary. It will be appreciated that other processes may alternatively (or additionally) be used for fabricating the IC 104a. For example, one or more imprint lithography processes and / or any other appropriate patterning technique, such as printing, may be used for patterning one or more IC layers. Moreover, where the substrate 102 is not formed of a crystalline semiconductor (e.g., in the case of a flexible substrate), a crystalline or polycrystalline semiconductor IC may be formed in a separate process and subsequently embedded into the substrate 102.

[0057] As part of this stage of the fabrication procedure conductive paths 104b may be formed, if necessary, for connecting the IC 104a to an external connection region of the IC chip 100 (for subsequent connection with application circuitry of an electronic device).

[0058] As seen at (c) in Figure 2, the next stage of the fabrication procedure comprises completing the IC layer 104 by forming / depositing an appropriate insulating / dielectric layer 104c over the IC 104a (or at least active parts of the IC) to protect I passivate the IC 104a. This insulating / dielectric layer 104c may, for example, comprise a polymer, SiO2, HfO2, SiNx and / or AI2O3 layer (or any suitable combination thereof). Nevertheless, these are only examples, the insulating / dielectric layer 104c may comprise other materials.

[0059] As seen at (d) in Figure 2, the next stage of the fabrication procedure comprises formation of the connection regions 106a and tessellating pattern 106b of shielding elements 106b-1, 106b-2 (only the regular polygon shaped shielding elements 106b-1 of which are visible in Figure 2(d)). This stage involves forming appropriate vias 104d in the insulating / dielectric layer 104c for allowing a connection to be made to the IC 104a (e.g., via the conductive paths 104b). These vias 104d are filled during subsequent formation of the metallisation layer 106 to provide an electrically conductive external connection to the connection regions 106a.

[0060] Beneficially, as seen in Figure 2(d), in the illustrated example, the connection regions 106a and tessellating pattern 106b are formed from a common metallisation layer 106 that is deposited on the IC layer 104 and then patterned in a common patterning step, e.g., using a conventional photoresist-based lithography process. Thus, the provision of the tessellating pattern 106b does not add appreciably to the complexity of the fabrication process and can be integrated into existing processes relatively easily without the introduction of additional masking steps.

[0061] Following formation of the IC 104a on the substrate 102 and subsequent passivation and metallisation steps, the IC chip 100 may be singulated from any other IC chips formed at the same time and removed from any carrier that may be used. For example, the IC chip 100 (or ‘die’) may be separated from other IC chips (possibly on a rigid carrier, wafer frame or the like) by dicing the substrate 102 upon which the respective IC of each IC chip is formed, along straight lines (known as scribe lines) between the ICs, typically using a laser, an abrasive water jet, a saw, or some other appropriate dicing procedure.

[0062] Once singulated, the IC chip 100 may be individually picked (e.g., off a carrier or wafer frame on which it is located) for subsequent assembly with application circuitry (e.g., an antenna, other electronic circuitry, and / or the like) to form an electronic device (e.g., an RFID tag or the like). Assembly

[0063] A procedure for assembling an IC chip 100, such as that illustrated in Figure 1, with application circuitry to form an electronic device will now be described, by way of example only, with reference to Figures 3 to 5.

[0064] Figure 3 is an illustration showing simplified illustrative cross-sections respectively through the IC chip 100 and through a corresponding circuit component 200 with which that IC chip 100 is to be assembled.

[0065] As seen in Figure 3, the circuit component 200 with which the IC chip 100 is to be assembled comprises an application circuit substrate 202 on which application circuitry 206 is provided. The application circuitry 206 comprises a plurality of application circuitry connection regions 206a configured for interconnection with the connection regions 106a of the IC chip 100. It will be appreciated that the application circuitry connection regions 206a may be in the form of dedicated connection regions 206a (e.g., dedicated contact pads, bond pads, or the like) or may simply form part of a circuit trace or track forming part of the application circuitry 206 (e.g., part of an antenna trace, a routing track, and / or the like).

[0066] The IC chip 100 and application circuitry 206 are shown, in Figure 3, as being correctly aligned with one another for subsequent assembly. It will be appreciated that in reality there may be a relative linear and / or rotational misalignment between the IC chip 100 and the application circuitry 206 arising from typical manufacturing tolerances and the like. To counter this, it will be appreciated that the application circuitry connection regions 206a and IC chip connection regions 106a may be mutually configured to ensure a minimum surface area of electrical connectivity between the application circuitry connection regions 206a and the corresponding IC chip connection regions 106a, fora maximum relative linear and / or rotational misalignment between the IC chip 100 and the application circuitry 206.

[0067] In the illustrated example, the application circuitry 206 also comprises a plurality of additional conductive features 206b configured for providing additional support for the IC chip 100. It will be appreciated that these conductive features 206b may be active or inactive, may be formed as a functional or as a non-functional, part of the application circuitry 206 on the application circuit substrate 202. For example, the conductive features 206b may comprise part of conductive routing traces, extensions of contact pads, dummy circuits and / or the like, and may be designed for the express purpose of providing additional mechanical support for the IC chip 100 during (and following) assembly. For example, the conductive features 206b may be in the form of additional turns (or part thereof) of the antenna tracks forming a coil loop type antenna. Alternatively (or additionally) the conductive features 206b may comprise conductive tracks (or part thereof) that are routed from outside the area of the IC chip 100 to a conductive feature 206b in the form of a pad or the like that is located within the perimeter of the IC chip 100 (as opposed to at the edges) for providing the additional mechanical support. Alternatively (or additionally) the conductive features 206b may comprise floating (unconnected) metal traces / structures located between the middle (and / or somewhere near the middle) of the IC chip 100 and the application circuit substrate 202. Such conductive features 206b may be configured to provide additional support to the IC chip 100 and hence beneficially allow (e.g., fora flexible IC chip) the IC chip 100 to sit “flat” on the surface of the conductive features 206b rather than “sag” between connection regions 206a of the application circuit, that are located (in this example) at positions corresponding to either end of the IC chip 100.

[0068] It will be appreciated that the application circuitry 206 will be configured to conform with a set of design rules associated with the system into which the IC chip 100 is being mounted. This set of design rules includes, for example, rules on minimum feature sizes, rules on the spacing between different features, etc. As described above and as illustrated in Figure 3, the maximum dimension, A, of the shielding elements 106b-1, 106b-2 (only the regular polygon shaped shielding elements 106b-1 of which are visible in Figure 23) is configured to be less than a minimum gap size, t, between the conductive elements of the application circuitry 206 with which the IC chip 100 is to be assembled (e.g., according to the set of design rules). Moreover, the isolating gaps / regions between the shielding elements 106b-1, 106b-2 are beneficially configured to have a minimum width, 6, that is larger than a maximum dimension of the conductive particles of an anisotropic conductive medium that is to be used during the assembly of the IC chip 100 with the application circuitry 206.

[0069] Figure 4 is an illustration showing simplified illustrative cross-sections respectively through the IC chip 100 and through a corresponding circuit component 200 with which that IC chip 100 is to be assembled following a first stage of an assembly procedure.

[0070] As seen in Figure 4, during the first stage of the assembly procedure, a layer of anisotropic conductive medium 300 is deposited on the application circuit substrate 202 to cover the application circuitry 206.

[0071] Figure 5 is an illustration showing simplified illustrative cross-sections respectively through the IC chip 100 and through a corresponding circuit component 200 with which that IC chip 100 is to be assembled during a second stage of the assembly procedure.

[0072] As seen in Figure 5, during the second stage of the assembly procedure, the IC chip 100 is appropriately aligned with the application circuitry 206 of the circuit component 20 - e.g., an alignment in which the connection regions 106a of the IC chip 100 are aligned with the connection regions 206a of the application circuit 206 within acceptable tolerances. The surface of the IC chip 100 on which the metallisation layer 106 is formed is pressed into the anisotropic conductive medium layer 300 provided on that circuit component 200 to form an electrical connection between the connection regions 106a of the IC chip 100 and the corresponding the connection regions 206a of the application circuit 206.

[0073] Appropriate pressure P-P’ is applied between the IC chip 100 and the circuit component 200 to ensure that conductive particles in the anisotropic conductive medium are sufficiently pressed into the connection regions 106a of the IC chip 100 and the corresponding the connection regions 206a to form an electrical connection having the required electrical characteristics. Heat is also applied to the assembly to cure the polymer matrix of the anisotropic conductive medium and hence secure the IC chip 100 in place with the required electrical connectivity to the application circuitry. It will be appreciated that an appropriate tool, such as a thermodes or the like, may be used to apply the pressure (while heating the IC chip 100).

[0074] Beneficially, during this process, the tessellating pattern 106b of shielding elements protects the IC 104b from damage caused by the conductive particles in the anisotropic conductive medium 300. Moreover, the tessellating pattern 106b of shielding elements provides a generally flat, relatively thick, layer that mitigates the risk of pressure induced distortion of the IC chip 100 during assembly. The risk of pressure induced distortion of the IC chip 100 is further reduced by the presence of the additional conductive features 206b as part of the application circuitry that are configured for providing additional support for the IC chip 100. Nevertheless, even without such features, the tessellating pattern 106b of shielding elements provides some additional rigidity and structural benefits by spreading the forces arising from the applied pressure across the IC chip 100 as the IC chip 100 is pressed into the anisotropic conductive medium 300. Modifications and Alternatives

[0075] A detailed example has been described above. As those skilled in the art will appreciate, a number of modifications and alternatives can be made to the above example whilst still benefiting from the inventions embodied therein.

[0076] For example, referring to Figure 1, rather than the partial shielding elements 106b-2 at the perimeter of a connection regions 106a being isolated from that contact region 106a as shown, the partial shielding elements 106b-2 could form an extension of the contact region as illustrated in Figure 6, which is a simplified illustration of an alternative contact region design that may be used in the IC chip 100. Specifically, as seen in Figure 6, each partial shielding element 106c that would otherwise be located adjacent the boundary of a trapezoidal connection region (as delineated by the broken lines in Figure 6) is not isolated from the connection region 106a but instead forms an extension of that connection region 106a. Effectively, therefore, the connection region has a polygonal shape that tessellates with a plurality of the regular polygon shaped shielding elements adjacent the boundary of that connection region. This can be beneficial for increasing the effective surface area of the connection region 106a and further increasing rotational tolerance.

[0077] It will also be appreciated that whilst the formation of the tessellating pattern of shielding elements as part of the same metallisation layer as the IC chip connection regions is advantageous in terms of keeping process complexity to a minimum, the tessellating pattern of shielding elements could be formed from a different layer of the IC chip. Fabricating the tessellating pattern of shielding elements from a different layer could, for example, allow the use of a layer of a different material and / or having different characteristics (e.g., thickness, and or electrical characteristics) for the tessellating pattern of shielding elements than for the connection regions. Where the tessellating pattern is formed of a different layer the tessellating pattern could, for example, be formed of an insulating / dielectric material.

[0078] Moreover whilst, as described above, the substrate carrying the IC may be a flexible substrate formed of a flexible material such as an appropriate flexible polymer material, the flexible substrate may be formed from any other materials that provide suitable electrical, chemical, and / or structural properties. The flexible substrate may be formed from a single common material, may be formed from a plurality of different materials, or may be formed from a plurality of different types of the same material. A flexible substrate may, for example, comprise one or more materials selected from the following list of materials: flexible glass, polymer materials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0079] Where a polymer based material is used, the substrate may comprise one or more polymers selected from: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides, polyamides (e.g. Nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1 Methoxy 2 propyl acetates, Benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS), polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0080] Where a metal oxide based material is used, the substrate may comprise one or more metal oxides selected from: AI2O3, SiOxNy, SiO2, Si3N4, or any other suitable metal oxide. Where a resin based material is used, the substrate may comprise one or more resins selected from: a UV-curable resin or any other suitable resin. Where a resist based material is used, the substrate may comprise one or more resists selected from: nanoimprint resists, photoresists such as, for example, Bisphenol A novolac epoxy (SU-8) or polyhydroxybenzyl silsesquioxane, or any other suitable resist. Where a foil based material is used the substrate may comprise one or more foils selected from: polymeric foils or any other suitable foil. Where an insulator-coated metal is used, the substrate may comprise one or more insulator-coated metals selected from: insulator coated stainless-steel or any other suitable insulator-coated metal.

[0081] Various other modifications will be apparent to those skilled in the art and will not be described in further detail here.

Claims

1. An integrated circuit chip comprising:a substrate on which is formed an integrated circuit;at least one connection region for forming an external electrical connection to the integrated circuit; anda plurality of shielding elements for providing protection of the integrated circuit and / or supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device;wherein the shielding elements are arranged in a tessellating pattern with gaps between adjacent shielding elements within the tessellating pattern.

2. An integrated circuit chip as claimed in claim 1, wherein the shielding elements have a maximum dimension that is smaller than a minimum gap size defined for spacing of elements of the external circuitry.

3. An integrated circuit chip as claimed in claim 1 or 2, wherein the gaps have a width that is greater than an expected maximum dimension of a conducting particle forming part of an anisotropic conducting medium to be used for securing the integrated circuit chip to the external circuitry to form the electronic device.

4. An integrated circuit chip as claimed in any preceding claim, wherein each of the shielding elements respectively forming the tessellating pattern is a polygon shaped shielding element.

5. An integrated circuit chip as claimed in claim 4, wherein at least a subset of the shielding elements are regular polygon shaped shielding elements.

6. An integrated circuit chip as claimed in claim 5, wherein the tessellating pattern comprises a regular tessellation comprising the regular polygon shaped shielding elements.

7. An integrated circuit chip as claimed in claim 5 or 6, wherein at least a subset of the regular polygon shaped shielding elements are hexagon shaped shielding elements.

8. An integrated circuit chip as claimed in claim 7, wherein a subset of the shielding elements each has a respective shape that corresponds to part of the regular polygon shaped shielding elements.

9. An integrated circuit chip as claimed in claim 7 or 8, wherein the at least one connection region has a polygonal shape having at least one edge that extends at a first angle, relative to an edge of the integrated circuit chip, that matches a second angle at which a side of an adjacent regular polygon shaped shielding element extends relative to that edge of the integrated circuit chip.

10. An integrated circuit chip as claimed in claim 9, wherein the at least one connection region is trapezoidal in shape.

11. An integrated circuit chip as claimed in claim 9, wherein the at least one connection region has a polygonal shape that tessellates with a plurality of the regular polygon shaped shielding elements adjacent the boundary of the at least one connection region.

12. An integrated circuit chip as claimed in any preceding claim, wherein the tessellating pattern extends substantially to opposing edges of the integrated circuit chip in at least one of a transverse and a longitudinal direction relative to the integrated circuit chip.

13. An integrated circuit chip as claimed in any preceding claim, wherein the tessellating pattern extends substantially to and around at least part of the boundary of the at least one connection region.

14. An integrated circuit chip as claimed in any preceding claim, wherein the tessellating pattern and at least one connection region are mutually configured to extend substantially an entire surface of the integrated circuit chip.

15. An integrated circuit chip as claimed in any preceding claim, wherein the substrate is a flexible substrate, and the integrated circuit chip is a flexible integrated circuit chip.

16. A method of fabricating an integrated circuit chip, the method comprising:providing a substrate;forming, on the substrate, an integrated circuit;forming at least one connection region for forming an external electrical connection to the integrated circuit; andforming a plurality of shielding elements for providing protection of the integrated circuit and / or supporting the integrated circuit during assembly of the integrated circuit chip with external circuitry to form an electronic device;wherein the shielding elements are arranged in a tessellating pattern with gaps between adjacent shielding elements within the tessellating pattern.

17. A method as claimed in claim 16, wherein the at least one connection region and tessellating pattern of shielding elements are formed from a common layer of conductive material.

18. A method as claimed in claim 17, the conductive material of the common layer is deposited in a deposition step forming part of the method.

19. A method as claimed in any of claims 16 to 18, wherein the at least one connection region and tessellating pattern of shielding elements are patterned as part a common patterning step forming part of the method.

20. An electronic device comprising:electronic circuitry formed on an electronic device substrate; andan integrated circuit chip, as claimed in any of claims 1 to 15, electrically connected to the electronic circuitry to form the electronic device.

21. An electronic device as claimed in claim 20, wherein at least one supporting element is provided on the electronic substrate for providing mechanical support to the integrated circuit chip.

22. An electronic device as claimed in claim 21, wherein the at least one supporting element comprises at least one structure comprising: an active structure; an inactive structure; a functional part of the electronic circuitry; a non-functional part of the electronic circuitry; at least part of a conductive routing trace; an extension of a contact region or pad; and / or at least part of a dummy circuit.

23. An electronic device as claimed in any of claims 20 to 22, wherein the electronic circuitry comprises at least one antenna.

24. An electronic device as claimed in any of claims 20 to 23, wherein the electronic device is a radio frequency identification (RFID) device.

25. An electronic device as claimed in any of claims 20 to 24, wherein the electronic device substrate is a flexible electronic device substrate.

26. A method of assembling an electronic device, the method comprising:providing an electronic device substrate on which electronic circuitry of the electronic device is formed;providing integrated circuit chip as claimed in any of claims 1 to 15; andelectrically connecting the integrated circuit chip to the electronic circuitry to form the electronic device.

27. A method as claimed in claim 26, wherein the electrically connecting comprises: depositing a layer of an anisotropic conducting medium on the electronic device substrate; positioning the integrated circuit chip relative to the electronic circuitry to align at least one connection region of the integrated circuit chip with at least one corresponding electrical connection region of the electronic circuitry; and pressing the integrated circuit chip, when in the aligned position, into the anisotropic conducting medium to form an electrical connection between the at least one connection region of the integrated circuit chip and the at least one corresponding electrical connection region of the electronic circuitry.

28. A method as claimed in claim 27, further comprising curing the anisotropic conducting medium to secure the integrated circuit chip in position.

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