Microfluidic chip

Abstract

A microfluidic chip, comprising a first substrate (10), wherein the first substrate (10) comprises: a first wiring layer (101), which comprises a first wiring (L1) having a first line width (d1), a first driving electrode, and a first control electrode; an insulating layer (102), which is located on the first wiring layer (101); a second wiring layer (103), which is located on the insulating layer (102) and comprises a second wiring (L2) having a second line width (d2); a dielectric layer (104), which is located on the second wiring layer (103); and a hydrophobic layer (105), which is located on the dielectric layer (104), wherein the first wiring (L1) is configured to connect the first driving electrode and the first control electrode, the second wiring (L2) is configured to be connected, by means of a via hole passing through the insulating layer (102), to the first wiring (L1), which is connected to a different first driving electrode, and the orthographic projection of the first wiring (L1) on the first substrate (10) overlaps with the orthographic projection of the second wiring (L2) on the first substrate (10), the area of the overlapping region being greater than the product of the first line width (d1) and the second line width (d2).

Description

Technical Field This disclosure relates to the field of biomedical detection, specifically, to a microfluidic chip. Background Microfluidic technology is a precise technique for controlling and manipulating microscale fluids. With this technology, researchers can integrate basic operations such as sample preparation, reaction, separation, and detection onto a centimeter sized chip. Microfluidic technology is generally applied in the analysis process of trace drugs in fields such as biology, chemistry, and pharmaceuticals. Digital microfluidic chips use droplets as manipulation objects and control their movement through electric field force, thermal force, electrostatic force, etc. To cope with complex biochemical processes, passive digital microfluidic chips adopt a multi-layer metal design to control a large number of driving electrodes, which inevitably leads to metal wiring overlap between different metal layers. Electrostatic breakdown is prone to occur at these overlapping positions, leading to chip driving failure. Summary With respect to the above issues, this disclosure proposes a microfluidic chip. An aspect of this disclosure provides a microfluidic chip comprising a first substrate, the first substrate comprising: a first wiring layer comprising a first wiring with a first line width, a first driving electrode, and a first control electrode; an insulation layer located on the first wiring layer; a second wiring layer located on the insulation layer and comprising a second wiring with a second line width; a dielectric layer located on the second wiring layer; and a hydrophobic layer located on the dielectric layer, wherein the first wiring is configured to connect the first driving electrode and the first control electrode, and the second wiring is configured to connect first wirings that are connected to different first driving electrodes by a via passing through the insulation layer, orthographic projections of the first wiring and the second wiring on the first substrate overlap, an area of an overlapping region is greater than a product of the first line width and the second line width. According to an embodiment of this disclosure, the first wiring has a third line width greater than the first line width at an overlapping position, and / or the second wiring has a fourth line width greater than the second line width at an overlapping position. According to an embodiment of this disclosure, the third line width is 3 to 5 times the first line width, and / or the fourth line width is 3 to 5 times the second line width. According to an embodiment of this disclosure, the third line width is 4 times the first line width, and / or the fourth line width is 4 times the second line width. According to an embodiment of this disclosure, a first transition portion is arranged between a portion of the first wiring with the first line width and a portion of the first wiring with the third line width, so that the line width of the first wiring smoothly transitions from the first line width to the third line width, and / or a second transition portion is arranged between a portion of the second wiring with the second line width and a portion of the second wiring with the fourth line width, so that the line width of the second wiring smoothly transitions from the second line width to the fourth line width. According to an embodiment of this disclosure, a distance from the first transition portion to the overlapping position is greater than or equal to 50 um, and / or a distance from the second transition portion to the overlapping position is greater than or equal to 50 pm. According to an embodiment of this disclosure, the first wiring and the second wiring intersect at a first angle at the overlapping position, with the first angle ranging from 10° to 70°. According to an embodiment of this disclosure, the first angle ranges from 10° to 30°. According to an embodiment of this disclosure, the first wiring layer further comprises a first floating line, orthographic projections of the first floating line and the second wiring on the first substrate intersect perpendicularly, and an overlapping region of orthographic projections of the first floating line and the second wiring on the first substrate is adjacent to an overlapping region of orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, the second wiring layer further comprises a second floating line, orthographic projections of the second floating line and the first wiring on the first substrate intersect perpendicularly, and an overlapping region of orthographic projections of the second floating line and the first wiring on the first substrate is adjacent to an overlapping region of orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, the first wiring layer further comprises a first overlapping line, orthographic projections of the first overlapping line and the second wiring on the first substrate overlap, and the first overlapping line is connected to the second wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, the second wiring layer further comprises a second overlapping line, orthographic projections of the second overlapping line and the first wiring on the first substrate overlap, and the second overlapping line is connected to the first wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, areas of orthographic projections of at least one via through which the first overlapping line is connected to the second wiring and at least one via through which the second overlapping line is connected to the first wiring on the first substrate are smaller than areas of an overlapping region of orthographic projections of the first floating line and the second wiring on the first substrate and an overlapping region of orthographic projections of the second floating line and the first wiring on the first substrate, and areas of an overlapping region of orthographic projections of the first floating line and the second wiring on the first substrate and an overlapping region of orthographic projections of the second floating line and the first wiring on the first substrate are smaller than an area of the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, the first wiring layer further comprises a first floating electrode, which is arranged adjacent to the end of the wiring led out from the first driving electrode and / or the first control electrode. According to an embodiment of this disclosure, the second wiring layer further comprises a second driving electrode, a second control electrode and a second floating electrode, orthographic projections of the first driving electrode and the second driving electrode on the first substrate overlap, and the first driving electrode and the second driving electrode are connected by at least one via passing through the insulation layer, orthographic projections of the first control electrode and the second control electrode on the first substrate overlap, and the first control electrode and the second control electrode are connected by at least one via passing through the insulation layer, and the second floating electrode is arranged adjacent to an end of the extended second wiring, and / or the second floating electrode is arranged adjacent to an end of a wiring led out from the second driving electrode and / or the second control electrode. According to an embodiment of this disclosure, the second floating electrode comprises a first floating sub-electrode and a second floating sub-electrode, the first floating sub-electrode is arranged adjacent to an end of the extended second wiring, and the second floating subelectrode is arranged adjacent to an end of a wiring led out from the second driving electrode. According to an embodiment of this disclosure, the second wiring layer further comprises a charge neutralization electrode, the charge neutralization electrode comprises the first floating sub-electrode and the second floating sub-electrode, as well as a floating belt connecting the first floating sub-electrode and the second floating sub-electrode, the charge neutralization electrode surrounds the second wiring and the second driving electrode, and is arranged to be spaced apart from the end of the extended second wiring and the end of the wiring led out from the second driving electrode. According to an embodiment of this disclosure, a first groove is arranged on the dielectric layer, such that the end of the extended second wiring and a portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and a portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove; and a second groove is arranged at a position of the hydrophobic layer which corresponds to the first groove of the dielectric layer, such that the end of the extended second wiring and the portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and the portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove and the second groove. Another aspect of this disclosure further provides a microfluidic chip comprising a first substrate, the first substrate comprising: a first wiring layer comprising a first wiring, a first driving electrode, and a first control electrode; an insulation layer located on the first wiring layer; a second wiring layer located on the insulation layer and comprising a second wiring; wherein orthographic projections of the first wiring and the second wiring on the first substrate overlap; a dielectric layer located on the second wiring layer; a hydrophobic layer located on the dielectric layer; and an electrostatic discharge component for releasing static electricity generated at an overlapping position of the first wiring and second wiring, and being arranged adjacent to the overlapping position. According to an embodiment of this disclosure, the electrostatic discharge component comprises a first floating line arranged on the first wiring layer, orthographic projections of the first floating line and the second wiring on the first substrate intersect perpendicularly, and an overlapping region of the orthographic projections of the first floating line and the second wiring on the first substrate is adjacent to an overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate, and / or the electrostatic discharge component comprises a second floating line arranged on the second wiring layer, orthographic projections of the second floating line and the first wiring on the first substrate intersect perpendicularly, and an overlapping region of the orthographic projections of the second floating line and the first wiring on the first substrate is adjacent to an overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, the electrostatic discharge component comprises a first overlapping line arranged on the first wiring layer, orthographic projections of the first overlapping line and the second wiring on the first substrate overlap, and the first overlapping line is connected to the second wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to an overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate, and / or the electrostatic discharge component further comprises a second overlapping line arranged on the second wiring layer, orthographic projections of the second overlapping line and the first wiring on the first substrate overlap, and the second overlapping line is connected to the first wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, areas of orthographic projections of at least one via through which the first overlapping line is connected to the second wiring and / or at least one via through which the second overlapping line is connected to the first wiring on the first substrate are smaller than areas of an overlapping region of the orthographic projections of the first floating line and the second wiring on the first substrate and / or an overlapping region of the orthographic projections of the second floating line and the first wiring on the first substrate, and areas of the overlapping region of the orthographic projections of the first floating line and the second wiring on the first substrate and / or the overlapping region of the orthographic projections of the second floating line and the first wiring on the first substrate are smaller than an area of the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate. According to an embodiment of this disclosure, the electrostatic discharge component comprises a first floating electrode arranged on the first wiring layer, and the first floating electrode is arranged adjacent to an end of a wiring led out from the first driving electrode and / or the first control electrode. According to an embodiment of this disclosure, the second wiring layer further comprises a second driving electrode, a second control electrode and a second floating electrode, orthographic projections of the first driving electrode and the second driving electrode on the first substrate overlap, and the first driving electrode and the second driving electrode are connected by at least one via passing through the insulation layer, orthographic projections of the first control electrode and the second control electrode on the first substrate overlap, and the first control electrode and the second control electrode are connected by at least one via passing through the insulation layer, and the electrostatic discharge component comprises a second floating electrode arranged on the second wiring layer, the second floating electrode is arranged adjacent to an end of the extended second wiring, and / or the second floating electrode arranged adjacent to an end of a wiring led out from the second driving electrode and / or the second control electrode. According to an embodiment of this disclosure, the second floating electrode comprises a first floating sub-electrode and a second floating sub-electrode, the first floating sub-electrode is arranged adjacent to an end of the extended second wiring, and the second floating subelectrode is arranged adjacent to an end of a wiring led out from the second driving electrode. According to an embodiment of this disclosure, the second wiring layer further comprises a charge neutralization electrode, the charge neutralization electrode comprises the first floating sub-electrode and the second floating sub-electrode, as well as a floating belt connecting the first floating sub-electrode and the second floating sub-electrode, the charge neutralization electrode surrounds the second wiring and the second driving electrode, and is arranged to be spaced apart from the end of the extended second wiring and the end of the wiring led out from the second driving electrode. According to an embodiment of this disclosure, a first groove is arranged on the dielectric layer, such that the end of the extended second wiring and a portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and a portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove; and a second groove is arranged at a position of the hydrophobic layer which corresponds to the first groove of the dielectric layer, such that the end of the extended second wiring and the portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and the portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove and the second groove. Another aspect of this disclosure further provides a microfluidic chip comprising a first substrate, the first substrate comprising: a first wiring layer comprising a first wiring, a first driving electrode, and a first control electrode; an insulation layer located on the first wiring layer; a second wiring layer located on the insulation layer and comprising a second wiring, a second driving electrode and a second control electrode; a dielectric layer located on the second wiring layer; and a hydrophobic layer located on the dielectric layer, wherein the first wiring is configured to connect the first driving electrode and the first control electrode, and the second wiring is configured to connect first wirings that are connected to different first driving electrodes by a via passing through the insulation layer, orthographic projections of the first driving electrode and the second driving electrode on the first substrate overlap, and the first driving electrode and the second driving electrode are connected by at least one via passing through the insulation layer, orthographic projections of the first control electrode and the second control electrode on the first substrate overlap, and the first control electrode and the second control electrode are connected by at least one via passing through the insulation layer, and wherein the first wiring layer further comprises a first floating electrode, the first floating electrode is arranged adjacent to an end of a wiring led out from the first driving electrode and / or the first control electrode, and / or wherein the second wiring layer further comprises a second floating electrode, the second floating electrode is arranged adjacent to an end of the extended second wiring, and / or the second floating electrode is arranged adjacent to an end of a wiring led out from the second driving electrode and / or the second control electrode. According to an embodiment of this disclosure, the second floating electrode comprises a first floating sub-electrode and a second floating sub-electrode, the first floating sub-electrode is arranged adjacent to an end of the extended second wiring, and the second floating subelectrode is arranged adjacent to an end of a wiring led out from the second driving electrode. According to an embodiment of this disclosure, the second wiring layer further comprises a charge neutralization electrode, the charge neutralization electrode comprises the first floating sub-electrode and the second floating sub-electrode, as well as a floating belt connecting the first floating sub-electrode and the second floating sub-electrode, the charge neutralization electrode surrounds the second wiring and the second driving electrode, and is arranged to be spaced apart from the end of the extended second wiring and the end of the wiring led out from the second driving electrode. According to an embodiment of this disclosure, a first groove is arranged on the dielectric layer, such that the end of the extended second wiring and a portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and a portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove; and a second groove is arranged at a position of the hydrophobic layer which corresponds to the first groove of the dielectric layer, such that the end of the extended second wiring and the portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and the portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove and the second groove. The microfluidic chips according to various embodiments of this disclosure, by optimizing the wiring at the overlapping position and releasing static electricity at fixed positions different from the overlapping position, an electrostatic protection structure is proposed, achieving electrostatic protection at the overlapping position, preventing electrostatic breakdown at critical positions, and avoiding device functional failure caused by static electricity. As a result, the chip yield can be significantly improved, the reliability of the chip at the application end can be enhanced, and the manufacturing cost of the chip can be reduced. Detailed Description of the Drawings The accompanying drawings are used to provide further understanding of the embodiments of this disclosure and constitute a part of the specification. The accompanying drawings are used together with the embodiments of this disclosure to explain this disclosure and do not constitute limitations on this disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. The embodiments described in this disclosure are illustrated in the various figures of the accompanying drawings by way of example not limitation, where similar reference signs indicate similar elements, and for illustrative purposes, the figures are not drawn to scale. Figure 1A schematically shows a wiring scheme of microfluidic chips in relevant technologies; Figure IB is an enlarged view of region A in Figure 1 A; Figure IC shows a simulation result of the wiring scheme shown in Figure 1 A; Figure 2A is a schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 2B is a cross-sectional view taken along line I-I in Figure 2A; Figure 2C is an enlarged view of region A in Figure 2A; Figure 2D shows a simulation result of the wiring scheme shown in Figure 2A; Figure 3A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 3B is an enlarged view of region F in Figure 3A; Figure 3C shows a simulation result of the wiring scheme shown in Fig. 3A; Figure 4A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 4B is an enlarged view of region B in Figure 4A; Figure 5 is another schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 6A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 6B is a cross-sectional view taken along line I-I in Figure 6A; Figure 6C is a cross-sectional view taken along the I'-I' line in Figure 6A; Figure 7A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 7B is an enlarged view of region C in Figure 7A; Figure 8A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 8B is an enlarged view of region E in Figure 8A; Figure 8C is a cross-sectional view taken along the line 1"-1" in Figure 8B; Figures 9A and 9B show different ways of setting the overlapping lines of microfluidic chips according to the embodiments of his disclosure; Figure 10A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure; Figure 1 OB is a cross-sectional view taken along the line I'"-!'" in Figure 10A; Figure 10C is an enlarged view of region C in Figure 10A; Figure 11 shows a flowchart of a method for preparing a microfluidic chip according to an embodiment of this disclosure; Figure 12 shows another flowchart of a method for preparing a microfluidic chip according to an embodiment of this disclosure; and Figure 13 shows a further flowchart of a method for preparing a microfluidic chip according to an embodiment of this disclosure. Embodiments Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure can have other embodiments, and in the absence of conflicts, the various embodiments of this disclosure and features in the embodiments can be combined with each other. As used herein, the term "and / or" includes any and all combinations of at least one relevant listed item. The terms used herein are only intended to describe specific embodiments and are not intended to limit this disclosure. As used in this disclosure, the singular forms of "one" and "the" are also intended to include the plural form, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this disclosure, the presence of the described features, entirety, steps, operations, elements, and / or - 10 - components is specified, but it does not exclude the presence or addition of at least one of other features, entireties, steps, operations, elements, components, and / or group thereof. Microfluidic technology can individually control each droplet, and each unit of the electrode array on the chip has the same structure. Microfluidic chips require small amounts of samples and reagents, have a simple structure, are easy to integrate on a large scale, and are convenient and flexible for manipulating droplets. Moreover, the size and shape of droplets are controllable, making them advantageous in miniaturization, integration, low cost, high sensitivity, and high flexibility. The use of microfluidic chips can greatly accelerate the speed of sample movement, extraction, separation, mixing, and detection, thus demonstrating great potential in multiple fields such as physics, chemistry, biology, and medicine. Due to their significant cost advantage, passive digital microfluidic chips are currently the mainstream chip solution in commercially available digital microfluidic chip products. Digital microfluidic chips are widely used in complex biochemical processes due to their advantages of programmability, flexible droplet control, and high parallelism. These biochemical processes have the characteristics of multiple types of reagents, complex temperature fields, and long process times, which place high demands on the reliability of the chips. To cope with complex biochemical processes, passive digital microfluidic chips adopt a multi-layer wiring design to control a large number of driving electrodes, which inevitably results in overlapping wiring between different wiring layers. Due to the complex manufacturing process and diverse working environments of digital microfluidic chips, electrostatic discharge is prone to occur during chip use or manufacturing. In addition, chips inevitably experience charge accumulation in normal environments, and the insulation layer can only withstand limited electric field strength. When the charge accumulates to a certain extent, it will cause electrode breakdown of the chip. Static breakdown occurring at the wiring overlapping position between different wiring layers will result in chip driving failure. This will not only lead to a decrease in the yield of chips on the client side and an increase in manufacturing costs, but also significantly reduce the reliability of chips on the application side, thereby limiting the further development of digital microfluidic chips. The substrate of microfluidic chips can include a glass substrate, as well as a first wiring layer, an insulation layer, a second wiring layer, a dielectric layer, and a hydrophobic layer sequentially stacked on the glass substrate. Figure 1A schematically shows a wiring scheme of microfluidic chips in relevant technologies, and Figure IB is an enlarged view of region A in Figure 1A. Referring to Figures 1A and IB, in the relevant art, the first wiring LI arranged in the first wiring layer and the second wiring L2 arranged in the second wiring layer have a uniform line width (e.g., 25 pm) and intersect perpendicularly, that is, the projection of the first wiring LI on the substrate intersects perpendicularly with the projection of the second wiring L2 on the substrate. According to this wiring layout scheme, electrostatic breakdown is prone to occur in the overlapping region of the wiring, causing short circuits at positions that should not be conductive, resulting in droplet driving failure. All overlapping positions of the wiring can be approximated as parallel plate capacitors, so the so-called electrostatic breakdown is the capacitor breakdown caused by the accumulation of static charges. The condition for capacitor breakdown is that the internal electric field strength of the capacitor is greater than the maximum breakdown field strength of the insulating material. Thus it can be seen that the anti-static ability of the wiring layout scheme depends on the capacitance electric field strength of this wiring layout scheme. According to the theory of electrostatic fields, the potential V and the electric field strength E at any position in an electric field can be expressed by the following formula: E = -VV V(808rE)=ps wherein E is the electric field strength, V is the potential, s0 is the vacuum dielectric constant, sr is the relative dielectric constant of the insulation layer, ps is the surface charge density. In an ideal parallel plate capacitor, the electric field is uniformly distributed, resulting in a uniform distribution of its surface charges. However, the upper and lower substrates of actual parallel plate capacitors cannot be infinitely large, so the surface charge distribution is not uniform, and the charge at the edge position is relatively higher compared to the charge in the middle region. This can be likened to the tip discharge effect, which results in different charge distributions for wirings of different shapes, meaning that the breakdown resistance of wirings of different shapes varies. This effect can be simulated and analyzed through finite element models. Figure IC shows a simulation result of the wiring scheme shown in Figure 1A. The simulation model consists of five layers, from top to bottom: an air layer, a second wiring layer, an insulation layer, a first wiring layer, and an air layer. The second wiring layer is set to a constant potential of 2.5 kV, the first wiring layer is set to a floating potential (when electrostatic breakdown occurs, the entire chip is in an ungrounded state, and all other metals, except for the situation that static electricity is introduced into electrodes or wirings, are at a floating potential), the insulation layer is set to have a thickness of 1 pm, and a relative dielectric constant of 6.5. From the distribution of field strength in the simulation result, it can be seen that the field strength at the edge of the overlapping position is greater than that at the center of the overlapping position. With respect to this issue, this disclosure proposes a highly reliable digital microfluidic chip. Figure 2A is a schematic top view of a microfluidic chip according to an embodiment of this disclosure. Figure 2B is a cross-sectional view taken along line I-I in Figure 2A. Figure 2C is an enlarged view of region A in Figure 2A. Figure 2D shows a simulation result of the wiring scheme shown in Figure 2A. Referring to Figures 2Ato 2C, the microfluidic chip according to the embodiment of this disclosure comprises a first substrate 10. The first substrate 10 comprises: a first wiring layer 101 comprising a first wiring LI with a first line width dl, a first driving electrode, and a first control electrode; a second wiring layer 103 comprising a second wiring L2 with a second line width d2; and an insulation layer 102 located between the first wiring layer 101 and the second wiring layer 103; a dielectric layer 104 located on the second wiring layer 103; and a hydrophobic layer 105 located on the dielectric layer 104. The first wiring LI is configured to connect the first driving electrode and the first control electrode located on the first wiring layer 101, and the second wiring L2 is configured to connect first wirings LI that are connected to different first driving electrodes by a via passing through the insulation layer 102. The orthographic projections of the first wiring LI and the second wiring L2 on the first substrate 10 overlap, and an area of the overlapping region is greater than a product of the first line width dl and the second line width d2. According to an embodiment of this disclosure, the first wiring LI may have a third line width d3 greater than the first line width dl at an overlapping position D. The second wiring L2 may have a fourth line width d4 greater than the second line width d2 at the overlapping position D. That is to say, the first wiring LI has a first line width dl at the non-overlapping region and a third line width d3 at the overlapping region, and the second wiring L2 has a second line width d2 at the non-overlapping region and a fourth line width d4 at the overlapping region. In practical applications, to cope with complex biochemical processes, the control electrodes (for example, Pogopin electrodes can be used as an example in the embodiments of this disclosure, and it should be noted that the types of control electrodes are not limited in this disclosure) and driving electrodes in digital microfluidic chips are not in one-to-one correspondence. Instead, one control electrode controlling multiple driving electrodes is achieved by multi-layer wirings and vias. In the instance of Figure 2A, the wiring way of connecting two control electrodes (circular electrodes in the figure) with four driving electrodes (square electrodes in the figure) is shown, that is, the manipulation of the four driving electrodes is achieved through two control electrodes. However, it should be recognized that Figure 2A is only used as an instance to illustrate the solution of this disclosure rather than limiting this disclosure. The number of control electrodes and driving electrodes is not limited to the number shown in the figure, it may include a different number of control electrodes and driving electrodes than shown in the figure. In addition, it should be recognized that microfluidic chips can also include different types of electrodes than those shown in the figure. In the instance of Figure 2 A, the control electrode at the left side is used to manipulate the second and fourth driving electrodes, while the control electrode at the right side is used to manipulate the first and third driving electrodes. Due to this "one to multiple" control method, it is necessary to connect the control electrode with multiple drive electrodes. The first wiring LI located in the first wiring layer 101 is a wiring in a direction from the control electrode to the drive electrode, for example, Figure 2A shows a wiring in the longitudinal direction, and the second wiring L2 located in the second wiring layer 103 is a wiring that spans different first wirings LI in the transverse direction. Therefore, in this wirings design, it is inevitable that there will be wiring overlaps (such as the overlapping position D in region A), and electrostatic breakdown is prone to occur at these overlapping positions, resulting in chip driving failure. In addition, referring to Figure 2A, the first wiring LI located in the first wiring layer 101 and the second wiring L2 located in the second wiring layer 103 can be conducted by conductive vias passing through the insulation layer 102. The intersecting black dots in Figure 2A indicate the positions where the first wiring LI and the second wiring L2 are conducted through conductive vias. To reduce the probability of electrostatic damage to the control electrode, in the embodiments of this disclosure, the control electrode adopts a circular design, and the control electrode located in the first wiring layer 101 and the control electrode located in the second wiring layer 103 are conducted through 9 vias. The dielectric layer 104 and hydrophobic layer 105 located at the control electrode position need to be perforated to expose the electrode below. According to the embodiments of this disclosure, the diameter of the control electrode may be about 1 mm, the diameter of the via may be about 100 pm, and the spacing between the vias may be about 100 pm. It should be noted that in order to ensure the yield of vias during the process, the number of vias needs to be greater than 3. According to the embodiments of this disclosure, the third line width d3 may be 3 to 5 times the first line width dl, for example, the third line width d3 may be 4 times the first line width dl; the fourth line width d4 is 3 to 5 times the width d2 of the second line, for example, the fourth line width d4 is 4 times the width d2 of the second line. According to the embodiments of this disclosure, the first line width dl may be same as or different from the second line width d2, and the third line width d3 may be the same as or different from the fourth line width d4. For example, the first line width dl and the second line width d2 can be set to 25 pm, and the third line width d3 and the fourth line width d4 can be set to 96 pm. According to the embodiments of this disclosure, a first transition portion LT1 is arranged between a portion of the first wiring LI with the first line width dl and a portion of the first wiring LI with the third line width d3, so that the line width of the first wiring LI smoothly transitions from the first line width dl to the third line width d3; a second transition portion LT2 is arranged between a portion of the second wiring L2 with the second line width d2 and a portion of the second wiring L2 with the fourth line width d4, so that the line width of the second wiring L2 smoothly transitions from the second line width d2 to the fourth line width d4. As shown in Figure 2C, two first transition portions LT1 are respectively provided above and below the overlapping position D on the first wiring LI, so that the line width of the first wiring LI smoothly transitions from the first line width dl to the third line width d3 in order from top to bottom, and then smoothly transitions from the third line width d3 to the first line width dl; two second transition portions LT2 are respectively provided on the left and right sides of the overlapping position D on the second wiring L2, so that the line width of the second wiring L2 smoothly transitions from the second line width d2 to the fourth line width d4 in - 15 - order from left to right, and then smoothly transitions from the fourth line width d4 to the second line width d2. It should be recognized that although the outer edge of the transition portion is shown as an inclined straight line in Figure 2C, this disclosure is not limited to this, and any contour that can smoothly transition the line width of the wiring can be used, for example, the outer edge of the transition portion can be an arc-shaped edge. According to the embodiments of this disclosure, a distance SI from the first transition portion LT1 to the overlapping position D is greater than or equal to 50 pm; a distance S2 from the second transition portion LT2 to the overlapping position D is greater than or equal to 50 pm, which can prevent sudden changes or noise in the electric field near the overlapping position D. It should be recognized that the above distances and line widths are only examples rather than limitations to this disclosure. Through experimental testing, it was found that in the wiring scheme of the microfluidic chip according to this embodiment, the electrostatic breakdown voltage at the overlapping position is greater than that at the overlapping position of the wiring scheme shown in Figure 1A. That is, compared with the wiring scheme shown in Figure 1A, the microfluidic chip according to this embodiment has stronger anti-static breakdown ability. Referring to Figure 2D, compared with the simulation result shown in Figure IC, under the same parameter conditions, the field strength in the Z direction (i.e., the direction perpendicular to the substrate) is about 4% of that shown in Figure IC, i.e., the simulation result is consistent with the experimental result. The component of field strength in the Z direction acts vertically on the insulation layer, and its distribution can directly reflect the trend of capacitance damage, which can be used to determine which design is more prone to electrostatic breakdown. Under the same potential parameters, the wiring scheme with lower Z-direction field strength has stronger anti-static breakdown ability. In the microfluidic chip according to this embodiment, under the same other conditions, the area of the overlapping region of the wiring at the overlapping position is larger, that is, the area of the overlapping region is greater than the product of the first line width and the second line width, thereby having a stronger anti-static breakdown. However, it should be noted that a larger area of the overlapping region may lead to an increase in the overall area of the chip, so it is necessary to comprehensively consider the shape of the wiring in the overlapping region. According to the embodiments of this disclosure, one of the first wiring LI and the second wiring L2 has a wider line width at the overlapping position D, i.e., the first wiring LI has a third line width d3 greater than the first line width dl at the overlapping position D, or the second wiring L2 has a fourth line width d4 greater than the second line width d2 at the overlapping position D. By setting only one of the first wiring LI and the second wiringL2 to have a wider line width at the overlapping position D, the increase in chip size caused by the increase in the area of the overlapping region can be relatively reduced. According to other embodiments of this disclosure, it is also possible to improve the crossing way at the overlapping position to achieve an area of the overlapping region greater than the product of the first line width and the second line width, in order to enhance the antistatic effect. Figure 3A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure. Figure 3B is an enlarged view of region F in Figure 3A. Figure 3C shows a simulation result of the wiring scheme shown in Fig. 3A. According to the embodiment of this disclosure, the first wiring LI and the second wiring L2 intersect at a first angle a at the overlapping position D, with the first angle a ranging from 10° to 70°. As shown in Figures 3A and 3B, according to the embodiments of this disclosure, the first wiring LI and the second wiring L2 can intersect at a non-right angle at the overlapping position D, and the acute angle obtained by the intersection (i.e., the first angle a) can range from 10° to 70°. Preferably, the first angle a can range from 10° to 30°. Referring to Figure 3C, compared with the simulation result shown in Figure IC, under the same parameter conditions, the field strength in the Z direction (i.e., the direction perpendicular to the substrate) is about 30% of that shown in Figure IC. After verification, the electrostatic breakdown voltage of the wiring scheme shown in Figures 1A and IB is about 2.5 kV, while the breakdown voltage of the wiring scheme according to this embodiment is about 4.3 kV, with an increase of about 70%. That is, the simulation result is consistent with the experimental result. According to the simulation result, the right angle wiring scheme at the overlapping position is more prone to electrostatic breakdown, which is consistent with the experimental result. Through theoretical analysis, it can be concluded that when 40°<a<70°, the Z-direction field strength at the overlapping position D is about 70% of that in the right angle wiring scheme; when 10°<a<30°, the Z-direction field strength at the overlapping position D is reduced by about an order of magnitude compared to that in the right angle wiring scheme. It should be recognized that although the widening of the wiring at the overlapping position D is not shown in this embodiment, the various measures provided in the previous embodiments for improving the anti-static ability can be combined in various ways without conflict. The schemes formed by various combinations are within the scope of protection of this disclosure. In ordinary chips, electrostatic discharge has randomness and is highly prone to electrostatic breakdown at the overlapping position (i.e., overlapping position D) of the wiring, leading to the driving failure of the chip to droplets. In the aforementioned embodiments, the anti-static ability at the overlapping position of the wiring is improved, but the position which is prone to breakdown remains unchanged, that is, the position which is prone to breakdown is still at the overlapping position of the wiring. According to the embodiments of this disclosure, in addition to enhancing the anti-static ability at the overlapping position of the wiring, weak points for electrostatic discharge can also be designed to change the position which is prone to breakdown of the chip, thereby achieving protection at the overlapping position of the wiring. Figure 4A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure. Figure 4B is an enlarged view of region B in Figure 4A. According to the embodiment of this disclosure, the second wiring layer 103 further comprises a second driving electrode 1031, a second control electrode 1033 and a floating electrode 1032 (i.e., a second floating electrode). The floating electrode 1032 is arranged adjacent to an end of the extended second wiring L2, and / or adjacent to an end of a wiring led out from the second driving electrode 1031 and / or the second control electrode 1033. In the context of this disclosure, the term "adjacent" means that the distance between two components is close enough but not in contact with each other to achieve a specific technical effect, such as releasing static electricity or electrostatic protection. Those skilled in the art can know the sufficient proximity distance between two components required to achieve the technical effect based on the technical effect to be achieved. It should be recognized that in the embodiments of this disclosure, the driving electrode may comprise a first driving electrode arranged in the first wiring layer 101 and a second driving electrode arranged in the second wiring layer 103. The projections of the first driving electrode and the second driving electrode on the first substrate 10 overlap, and the first driving electrode and the second driving electrode are connected by at least one via passing through the insulation layer 102 (see Figure 2B). Similar to the driving electrode, in the embodiments of this disclosure, the control electrode (i.e., Pogopin electrode) may comprise a first control electrode arranged in the first wiring layer 101 and a second control electrode arranged in the second wiring layer 103. The projections of the first control electrode and the second control electrode on the first substrate 10 overlap, and the first control electrode and the second control electrode are connected by at least one via passing through the insulation layer 102. In the context of this disclosure, the statement "the second wiring layer comprises a driving electrode" essentially indicates that "the second wiring layer comprises a portion of a driving electrode which is arranged in the second wiring layer", while the statement "the driving electrode comprised in the second wiring layer" essentially indicates "a portion of the driving electrode which is arranged in the second wiring layer". Similarly, the statement "the first wiring layer comprises a driving electrode" essentially indicates that "the first wiring layer comprises a portion of the driving electrode which is arranged in the first wiring layer", while the statement "the driving electrode comprised in the first wiring layer" essentially indicates "a portion of the driving electrode which is arranged in the first wiring layer". Similarly, in the context of this disclosure, the statement "the second wiring layer comprises a control electrode" essentially indicates that "the second wiring layer comprises a portion of the control electrode which is arranged in the second wiring layer", while the statement "the control electrode comprised in the second wiring layer" essentially indicates "a portion of the control electrode which is arranged in the second wiring layer". Similarly, the statement "the first wiring layer comprises a control electrode" essentially indicates that "the first wiring layer comprises a portion of the control electrode which is arranged in the first wiring layer", while the statement "the control electrode comprised in the first wiring layer" essentially indicates "a portion of the control electrode which is arranged in the first wiring layer". Unless otherwise specified, it should be understood in the above manner and will not be repeated below. According to the embodiment of this disclosure, the floating electrode 1032 comprises a first floating sub-electrode 1032 1, a second floating sub-electrode 1032 2. and a third floating sub-electrode 1032 3. The first floating sub-electrode 1032 1 is arranged adjacent to an end of the extended second wiring L2, the second floating sub-electrode 1032 2 is arranged adjacent to an end of a wiring led out from the second driving electrode 1031, and the third floating subelectrode 1032 3 is arranged adjacent to an end of a wiring led out from the second control electrode 1033. As shown in Figure 4A, compared to Figure 2A, the second wiring L2 continues to extend, and floating electrodes 1032 are provided at the ends of all extended second wirings L2, as well as below all second driving electrodes 1031 and on the side of the second control electrode 1033, wherein a wiring connected to the second driving electrode 1031 is provided below the second driving electrode 1031, and the second floating sub-electrode 1032 2 is arranged at the end of the wiring, a wiring connected to the second control electrode 1033 is arranged on the side of the second control electrode 1033, and the third floating sub-electrode 1032 3 is arranged at the end of the wiring. The wirings led out from the second driving electrode 1031 and the second control electrode 1033 can be arranged in the same layer as the second wiring L2, that is, be arranged in the second wiring layer 103, and can have the same line width as the second wiring L2, for example, have a line width of 25 pm. It should be recognized that the above line widths are only examples and not limitations of this disclosure. It should be recognized that the above positions for arranging the floating electrodes are for reference only and do not limit this disclosure. Those skilled in the art can choose the position for setting the floating electrode as needed, and do not need to arrange the floating electrode at all positions shown in the figure. Referring to Figure 4B, the distance between the end of the extended second wiring L2 and the floating electrode 1032 is, for example, 2 pm. Through actual testing, it is known that the static breakdown voltage at this position is about 1.7 kV, which is lower than the breakdown voltage at the overlapping position D. Therefore, during the accumulation of static charges, static charges will first release from this position, thus achieving the purpose of protecting the overlapping position D. Figure 5 is another schematic top view of the microfluidic chip according to an embodiment of this disclosure. According to the embodiment of this disclosure, the second wiring layer 103 further comprises a charge neutralization electrode 1034. The charge neutralization electrode 1034 comprises the first floating sub-electrode 1032 1 and the second floating sub-electrode 1032 2. as well as a floating belt 1032 4 connecting the first floating sub-electrode 1032 1 and the second floating sub-electrode 1032 2. The charge neutralization electrode 1034 surrounds the - 20 - second wiring L2 and the second driving electrode 1031, and is arranged to be spaced apart from the second wiring L2 and the end of the wiring led out from the second driving electrode 1031. On the basis of the scheme shown in Figure 4A, the first floating sub-electrodes 1032_1 and the second floating sub-electrodes 1032 2 are connected using a floating belt 1032 4 to form the charge neutralization electrode 1034 shown in Figure 5. Furthermore, it should be recognized that although the first floating sub-electrode 1032 1 and the second floating sub-electrode 1032_2 are shown in Figure 4A as being formed on the second wiring layer 103, according to other embodiments of this disclosure, the floating electrodes may also be formed on the first wiring layer 101 (i.e., the first floating electrode). When the first floating electrode is formed in the first wiring layer 101, the first floating electrode can be formed at the end of the wiring led out from the first driving electrode (i.e., a portion of the driving electrode which is arranged in the first wiring layer 101) and / or the first control electrode (i.e., a portion of the control electrode which is arranged in the first wiring layer 101). For example, the first wiring layer 101 comprises a first driving electrode connected to the first wiring LI, and the floating electrode formed on the first wiring layer 101 can be arranged adjacent to the end of the wiring led out from the first driving electrode. For another example, the first wiring layer 101 comprises a first control electrode connected to the first wiring LI, and the first floating electrode formed on the first wiring layer 101 can be arranged adjacent to the end of the wiring led out from the first control electrode. The specific setting method is similar to the setting method of the floating electrode 1032 (i.e., the second floating electrode) described in conjunction with Figures 4A and 4B, and will not be repeated here. According to other embodiments of this disclosure, the charge neutralization electrode can also be formed on the first wiring layer 101, and comprises various first floating electrodes, as well as a floating belt connecting the various first floating electrodes. In this case, the charge neutralization electrode is arranged to be spaced apart from the end of the wiring led from the first driving electrode and / or the first control electrode. Figure 6A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure. Figure 6B is a cross-sectional view taken along line I-I in Figure 6A. Figure 6C is a cross-sectional view taken along the I'- T line in Figure 6A. Referring to Figures 6A to 6C, according to the embodiment of this disclosure, a first groove G1 is arranged on the dielectric layer 104, such that the end of the extended second wiring L2 and a portion of the charge neutralization electrode 1034 adjacent to the end of the extended second wiring L2, as well as the end of the wiring led out from the second driving electrode 1031 and a portion of the charge neutralization electrode 1034 adjacent to the end of the wiring led out from the second driving electrode 1031 are exposed by the first groove G1. According to the embodiment of this disclosure, a second groove G2 is arranged at a position of the hydrophobic layer 105 which corresponds to the first groove G1 of the dielectric layer 104, such that the end of the extended second wiring L2 and the portion of the charge neutralization electrode 1034 adjacent to the end of the extended second wiring L2, as well as the end of the wiring led out from the second driving electrode 1031 and the portion of the charge neutralization electrode 1034 adjacent to the end of the wiring led out from the second driving electrode 1031 are exposed by the first groove G1 and the second groove G2. According to other embodiments of this disclosure, the charge neutralization electrode can be formed in the first wiring layer 101. In this case, a third groove is arranged at a position of the insulation layer 102 located between the first wiring layer 101 and the second wiring layer 103 which corresponds to the first groove G1 of the dielectric layer 104 and the second groove G2 of the hydrophobic layer 105, such that the end of the wiring led out from the first driving electrode comprised in the first wiring layer 101 and a portion of the charge neutralization electrode adjacent to the end of the wiring led out from the first driving electrode are exposed by the first groove Gl, the second groove G2 and the third groove. According to the embodiment of this disclosure, the first wiring layer 101 and the second wiring layer 103 can be made of conductive materials such as metals (e.g. molybdenum (Mo)) or metal oxides (e.g. indium tin oxide (ITO)), and their thicknesses can be greater than 50 nm. The insulation layer 102 can be made of materials such as silicon nitride and silicon oxide, and its thickness can be greater than 400 nm, preferably, its thickness can be 1 pm. The dielectric layer 104 can be made of materials such as silicon nitride, silicon oxide, polyimide, etc. To reduce the production cost of the driving voltage, according to the embodiment of this disclosure, the thickness of the dielectric layer 104 can be 400 nm, and a silicon nitride material with a dielectric constant of 6.5 is selected for fabrication of the dielectric layer 104. The hydrophobic layer 105 can be made of Teflon and its thickness can be 100 nm. It should be recognized that the above thickness is only an example and not a limitation of this disclosure. In the schemes shown in Figures 6A to 6C, the medium at the weak point for electrostatic discharge is air. In theory, the breakdown field strength of air is about 3 * 10A4 V / cm, while the breakdown field strength of silicon nitride used to form the dielectric layer 104 is about 10A7 V / cm. That is to say, air medium is more prone to breakdown compared to silicon nitride medium. Therefore, the breakdown voltage at the position where the second wiring L2 exposed by the first groove G1 and the second groove G2 is adjacent to the charge neutralization electrode 1034 is lower than that at the wiring overlapping position (i.e., the overlapping position D), which can provide protection at the overlap position D. In addition, because air is used as the medium, the dielectric layer here will return to the insulating state after electrostatic charge neutralization, which can provide protection at the overlapping position D again. In the schemes shown in Figures 6Ato 6C, since the charge neutralization electrode 1034 is a complete electrode surrounding the wiring, when static charges accumulate to a certain extent, all weak points (i.e., positions where the charge neutralization electrode is adjacent to the end of the extended second wiring or the end of the wiring led out from the second driving electrode) will be conducted, allowing for further uniform distribution of static charges on the chip, better reducing the field strength at the overlapping position D, and thus achieving better protection at the overlapping position D According to other embodiments of this disclosure, another weak point setting way is provided. Figure 7A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure. Fig. 7B is an enlarged view of region C in Figure 7A. According to the embodiment of this disclosure, the first wiring layer 101 further comprises a first floating line FL1, and the orthographic projections of the first floating line FL1 and the second wiring L2 on the first substrate 10 intersect perpendicularly. According to the embodiment of this disclosure, the second wiring layer 103 further comprises a second floating line FL2, and the orthographic projections of the second floating line FL2 and the first wiring LI on the first substrate 10 intersect perpendicularly. Referring to Figures 7A and 7B, a first floating line FL1 is respectively arranged at left and at right of the overlapping position D, and a second floating line FL2 is respectively arranged above and below the overlapping position D. A new overlapping position is formed between the first floating line FL1 and the second wiring L2, and a new overlapping position is formed between the second floating line FL2 and the first wiring LI. The distance from the first floating line FL1 and / or the second floating line FL2 to the overlapping position D can be, for example, about 600 pm, and the first floating line FL1 and / or - 23 - the second floating line FL2 can have the first line width dl of the first wiring LI and the second line width d2 of the second wiring L2, respectively. For example, the first floating line FL1 and / or the second floating line FL2 can have a line width of 25 pm. In addition, the first floating line FL1 and the second floating line FL2 may have a length of, for example, about 700 pm. It should be recognized that the above distances, line widths, and lengths are only examples and not limitations of this disclosure. In this embodiment, the length of the floating line should be greater than its width, and the width of the floating line should be smaller than the line width at the overlapping position D that needs to be protected. Due to the fact that the breakdown voltage of the overlapping wiring with a line width of 25 pm is lower than that of the overlapping wiring with a widened line width (e.g. 96 pm), static electricity will firstly be released at the newly formed overlapping position (i.e., the overlapping position between the first floating line FL1 and the second wiring L2 and / or the overlapping position between the second floating line FL2 and the first wiring LI), thereby forming protection at the overlapping position D. In the aforementioned embodiments of this disclosure, the reliability of the chip is improved by enhancing the anti-static ability at the overlapping position. According to other embodiments of this disclosure, similar effects can also be achieved by capturing static charges. Figure 8A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure. Figure 8B is an enlarged view of region E in Figure 8A. Figure 8C is a cross-sectional view taken along the line I"-I" in Figure 8B. According to the embodiment of this disclosure, the first wiring layer 101 further comprises a first overlapping line OPL1, and the orthographic projections of the first overlapping line OPL1 and the second wiring L2 on the first substrate 10 overlap, and the first overlapping line OPL1 is connected to the second wiring L2 through at least one via passing through the insulation layer 102. Referring to Figures 8Ato 8C, two layers of overlapping wirings (i.e., the first overlapping wiring OPL1 in the first wiring layer 101 and the second wiring L2 in the second wiring layer 103) are arranged on at least one side of the overlapping position D, and these two layers of wirings are conducted through vias. In general, due to the direct exposure of the control electrode in the air, static electricity is easily introduced from the control electrode. Due to the relatively high number of interface defects at the position of the via wall, electrostatic charges are easily captured at the via wall. In addition, the relative increase in metal area leads to an increase in the number of free electrons, which can neutralize static charges to reduce the charge density at the overlapping position D and thereby provide protection at the overlapping position D. In the schemes shown in Figures 8A to 8C, the line widths of the first overlapping line OPL1 located in the first wiring layer 101 and the second wiring L2 located in the second wiring layer 103 can both be 25 pm, and the distance between the first overlapping line OPL1 and the overlapping position D can be about 100 pm, and the length of the first overlapping line OPL1 can be about 500 pm. As shown in the figures, three square vias with a side length of about 10 pm and a spacing of about 10 pm are respectively arranged at both ends of the first overlapping line OPL1. It should be recognized that the above line width, distance, length, side length, spacing, and shape are only examples and not limitations of this disclosure. For example, the shape and number of vias may be different from those shown in the figure. After actual testing, according to this design, the breakdown voltage at the overlapping position D is about 4 kV. Figures 9A and 9B show other ways of setting the overlapping lines. As shown in Figure 9A, a first overlapping line OPL1 is arranged at left and at right of the overlapping position D respectively. According to the embodiment of this disclosure, the second wiring layer 103 further comprises a second overlapping line OPL2, which overlaps with the orthographic projection of the first wiring LI on the first substrate 10, and which is connected to the first wiring LI through at least one via passing through the insulation layer 102. As shown in Figure 9B, a first overlapping line OPL1 is respectively arranged at left and at right of the overlapping position D, and a second overlapping line OPL2 is respectively arranged above and below the overlapping position D. According to the embodiments of this disclosure, overlapping lines can be added above, below, at left, and at right of the overlapping position D to further enhance the protection of the overlapping position D. Considering the randomness of introducing static charges, static charges may accumulate at the overlapping position D through the first wiring layer 101 or the second wiring layer 103. Therefore, arranging overlapping lines with vias around the overlapping position D can achieve maximum protection at the overlapping position D. To ensure the production yield and anti-static effect of vias during the manufacturing process, the number of vias arranged at each end of the overlapping line can be greater than two. It should be recognized that although the widening of the wiring at the overlapping position D is not shown in this embodiment, the various measures provided in the previous embodiments to improve the anti-static ability can be combined with each other in various ways without conflict. The schemes formed by various combinations fall within the scope of protection of this disclosure. Figure 10A is another schematic top view of a microfluidic chip according to an embodiment of this disclosure. Figure 1 OB is a cross-sectional view taken along the line I"'-!"' in Figure 10A. Figure 10C is an enlarged view of region C in Figure 10A. According to the embodiment of this disclosure, the microfluidic chip further comprises a second substrate 20 opposite the first substrate 10. The second substrate 20 comprises a conductive layer 201 and a hydrophobic layer 202. As shown in Figure 10B, according to the embodiment of this disclosure, the first substrate 10 may comprise a glass substrate 100, as well as a first wiring layer 101, an insulation layer 102, a second wiring layer 103, a dielectric layer 104, and a hydrophobic layer 105 sequentially stacked on the glass substrate 100. The second substrate 20 may comprise a glass substrate 200, as well as a conductive layer 201 and a hydrophobic layer 202 sequentially stacked on the glass substrate 200. The hydrophobic layer 105 of the first substrate 10 and the hydrophobic layer 202 of the second substrate 20 face each other. The hydrophobic layer 202 of the second substrate 20 can be made of the same material as the hydrophobic layer 105 of the first substrate 10, and the conductive layer 201 of the second substrate 20 can be made of conductive materials such as ITO, with a thickness greater than 30 nm. In addition, the microfluidic chip further comprises a sealant 30 arranged between the first substrate 10 and the second substrate 20, for sealing the microfluidic chip and supporting the first substrate 10 and the second substrate 20. To ensure strength, the width of the sealant 30 can be greater than 2 mm and aligned with the edges of glass substrate 100 and glass substrate 200. Figures 10A and 10B further show the charge neutralization electrode 1033 formed in the second wiring layer 103 surrounding the wirings. The charge neutralization electrode 1033 is exposed to air through the first groove G1 formed in the dielectric layer 104 and the second groove G2 formed in the hydrophobic layer 105. In order to prevent external charges from entering the chip through the sealant 30, the distance between the sealant 30 and the charge neutralization electrode 1033 can be greater than 4 mm. It should be recognized that the above thickness, width, and distance are only examples and not limitations of this disclosure. As shown in Figure 10C, the scheme of this embodiment includes various measures to improve the anti-static ability, including (but not limited to): widening the wiring at the overlapping position D, arranging floating lines perpendicular to the wirings and in different layers, and arranging overlapping lines that overlap with the wirings and are in different layers. In addition, charge neutralization electrodes surrounding the wirings are also shown in Figures 10A and 10B. As shown in Figure 10C, areas of orthographic projections of the via connecting the first overlapping line OPL1 and the second wiring L2 and the via connecting the second overlapping line OPL2 and the first wiring LI on the first substrate 10 are smaller than areas of an overlapping region of orthographic projections of the first floating line FL1 and the second wiring L2 on the first substrate 10 and an overlapping region of orthographic projections of the second floating line FL2 and the first wiring LI on the first substrate 10. Areas of an overlapping region of orthographic projections of the first floating line FL1 and the second wiring L2 on the first substrate 10 and an overlapping region of orthographic projections of the second floating line FL2 and the first wiring LI on the first substrate 10 are smaller than an area of the overlapping region of the orthographic projections of the first wiring LI and the second wiring L2 on the first substrate 10. In general, static charges are introduced into the chip from the outside, so the overlapping lines with vias are closer to the overlapping position D relative to the floating lines. In this way, if a large amount of static charges enters the chip, the static charges will be released first at the floating line (i.e. weak point); If there are still residual charges or new accumulated charges, the vias and overlapping lines located behind the floating line will further play a role in reducing the charge density at the overlapping position D. It should be recognized that the positional relationship between the overlapping line and the floating line is not limited to the positional relationship shown in Figure 10C, but there can be other positional relationships, such as the floating line being closer to the overlapping position D than the overlapping line. Various measures are taken together to protect the overlapping position. After multiple occurrences of electrostatic breakdown rendering one measure ineffective, other measures can continue to provide protection. In addition, in practical situations, the introduction and release of static charges have a certain degree of randomness, and setting up static protection at multiple locations on microfluidic chips can maximize the response to the randomness of static breakdown. The microfluidic chips according to various embodiments of this disclosure, by optimizing the wiring at the overlapping position and releasing static electricity at fixed positions, an electrostatic protection structure is proposed, achieving electrostatic protection at the overlapping position, preventing electrostatic breakdown at critical positions, and avoiding device functional failure caused by static electricity. As a result, the chip yield can be significantly improved, the reliability of the chip at the application end can be enhanced, and the manufacturing cost of the chip can be reduced. Figure 11 shows a flowchart of a method for preparing a microfluidic chip according to an embodiment of this disclosure. Referring to Figure 11, this disclosure further provides a method for preparing a microfluidic chip. The microfluidic chip comprises a first substrate. The first substrate comprises a first wiring layer, a second wiring layer, and an insulation layer located between the first wiring layer and the second wiring layer. The method comprises the following steps S100 to S101. In step SI00, a first wiring with a first line width is prepared in the first wiring layer. In step S101, a second wiring with a second line width is prepared in the second wiring layer. The orthographic projections of the first wiring and the second wiring on the first substrate overlap. Step S100 involves preparing a first wiring at the overlapping position to have a third line width greater than the first line width, and step S101 involves preparing a second wiring at the overlapping position to have a fourth line width greater than the second line width. Figure 12 shows another flowchart of a method for preparing a microfluidic chip according to an embodiment of this disclosure. Referring to Figure 12, this disclosure further provides a method for preparing a microfluidic chip. The microfluidic chip comprises a first substrate. The first substrate comprises a first wiring layer, a second wiring layer, and an insulation layer located between the first wiring layer and the second wiring layer. The method comprises the following steps S200 to S202. In step S200, the first wiring and the first overlapping line are prepared in the first wiring layer. In step S201, the second wiring and the second overlapping line are prepared in the second wiring layer. In step S202, at least one via is prepared in the insulation layer. The orthographic projections of the first wiring and the second wiring on the first substrate overlap. The orthographic projections of the first overlapping line and the second wiring on the first substrate overlap, and the first overlapping line is connected to the second wiring through at least one via. The orthographic projections of the second overlapping line and the first wiring on the first substrate overlap, and the second overlapping line is connected to the first wiring through at least one via. Figure 13 shows a further flowchart of a method for preparing a microfluidic chip according to an embodiment of this disclosure. Referring to Figure 13, this disclosure further provides a method for preparing a microfluidic chip. The microfluidic chip comprises a first substrate. The first substrate comprises a first wiring layer, a second wiring layer, and an insulation layer located between the first wiring layer and the second wiring layer. The method comprises the following steps S300 to S301. In step S300, the first wiring is prepared in the first wiring layer. In step S301, the second wiring is prepared in the second wiring layer. The orthographic projections of the first wiring and the second wiring on the first substrate overlap, and the first wiring and the second wiring intersect at a first angle at the overlapping position, with the first angle ranging from 10° to 70°. The methods for preparing microfluidic chips according to various embodiments of this disclosure, by optimizing the wiring at the overlapping position and releasing static electricity at fixed positions, an electrostatic protection structure is proposed, achieving electrostatic protection at the overlapping position, preventing electrostatic breakdown at critical positions, and avoiding device functional failure caused by static electricity. As a result, the chip yield can be significantly improved, the reliability of the chip at the application end can be enhanced, and the manufacturing cost of the chip can be reduced. The method for preparing microfluidic chips provided in this disclosure is used to prepare microfluidic chips according to various embodiments of this disclosure and achieve corresponding technical effects. For specific content, please refer to the embodiments described in conjunction with Figures 2Ato 10C, which will not be repeated here. In this disclosure, the terms first, second, third, etc. can be used to describe various elements, and these elements should not be limited by these terms. These terms can be used to distinguish one element from another. In this disclosure, the mention of a layer, region, or substrate "on" or extending "onto" another component means that it can be directly on or extend onto another component, or there may also be intermediate components present. In addition, when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to another component and / or connected or coupled to another component via one or more intermediate components. Relative terms such as "below", "above", "upper", "under", "horizontal", or "vertical" can be used herein to describe the relationship between one component, layer, or region relative to another component, layer, or region, as illustrated in the respective figures. It will be understood that these terms are intended to encompass different orientations of the device, in addition to the orientations depicted in the various figures. In this disclosure, references to "one embodiment," "some embodiments," "one or more embodiments," or "embodiments" imply that specific features, structures, materials, or characteristics described in conjunction with the embodiments are included in at least one embodiment of this disclosure. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in embodiments" may not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner. Although this disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. For those skilled in the art, it will be clear that various modifications and variations can be made to the methods and devices of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure intends to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A microfluidic chip comprising a first substrate, the first substrate comprising:a first wiring layer comprising a first wiring with a first line width, a first driving electrode, and a first control electrode;an insulation layer located on the first wiring layer;a second wiring layer located on the insulation layer and comprising a second wiring with a second line width;a dielectric layer located on the second wiring layer; anda hydrophobic layer located on the dielectric layer,wherein the first wiring is configured to connect the first driving electrode and the first control electrode, and the second wiring is configured to connect first wirings that are connected to different first driving electrodes by a via passing through the insulation layer,orthographic projections of the first wiring and the second wiring on the first substrate overlap, an area of an overlapping region is greater than a product of the first line width and the second line width.

2. The microfluidic chip according to claim 1, wherein,the first wiring has a third line width greater than the first line width at an overlapping position, and / orthe second wiring has a fourth line width greater than the second line width at the overlapping position.

3. The microfluidic chip according to claim 2, wherein,the third line width is 3 to 5 times the first line width, and / orthe fourth line width is 3 to 5 times the second line width.

4. The microfluidic chip according to claim 3, wherein,the third line width is 4 times the first line width, and / orthe fourth line width is 4 times the second line width.

5. The microfluidic chip according to claim 2, wherein,a first transition portion is arranged between a portion of the first wiring with the first line width and a portion of the first wiring with the third line width, so that the line width of the first wiring smoothly transitions from the first line width to the third line width, and / ora second transition portion is arranged between a portion of the second wiring with thesecond line width and a portion of the second wiring with the fourth line width, so that the line width of the second wiring smoothly transitions from the second line width to the fourth line width.

6. The microfluidic chip according to claim 5, wherein,a distance from the first transition portion to the overlapping position is greater than or equal to 50 pm, and / ora distance from the second transition portion to the overlapping position is greater than or equal to 50 pm.

7. The microfluidic chip according to any one of claims 1 to 6, wherein the first wiring and the second wiring intersect at a first angle at the overlapping position, with the first angle ranging from 10° to 70°.

8. The microfluidic chip according to claim 7, wherein the first angle ranges from 10° to 30°.

9. The microfluidic chip according to any one of claims 1 to 8, wherein the first wiring layer further comprises a first floating line, orthographic projections of the first floating line and the second wiring on the first substrate intersect perpendicularly, an overlapping region of orthographic projections of the first floating line and the second wiring on the first substrate is adjacent to an overlapping region of orthographic projections of the first wiring and the second wiring on the first substrate.

10. The microfluidic chip according to any one of claims 1 to 9, wherein the second wiring layer further comprises a second floating line, orthographic projections of the second floating line and the first wiring on the first substrate intersect perpendicularly, an overlapping region of orthographic projections of the second floating line and the first wiring on the first substrate is adjacent to an overlapping region of orthographic projections of the first wiring and the second wiring on the first substrate.

11. The microfluidic chip according to any one of claims 1 to 10, wherein the first wiring layer further comprises a first overlapping line, orthographic projections of the first overlapping line and the second wiring on the first substrate overlap, and the first overlapping line is connected to the second wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate.

12. The microfluidic chip according to any one of claims 1 to 11, wherein the second wiring layer further comprises a second overlapping line, orthographic projections of the second overlapping line and the first wiring on the first substrate overlap, and the second overlapping line is connected to the first wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate.

13. The microfluidic chip according to claim 12, wherein,areas of orthographic projections of at least one via through which the first overlapping line is connected to the second wiring and at least one via through which the second overlapping line is connected to the first wiring on the first substrate are smaller than areas of an overlapping region of orthographic projections of the first floating line and the second wiring on the first substrate and an overlapping region of orthographic projections of the second floating line and the first wiring on the first substrate, andareas of an overlapping region of orthographic projections of the first floating line and the second wiring on the first substrate and an overlapping region of orthographic projections of the second floating line and the first wiring on the first substrate are smaller than an area of the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate.

14. The microfluidic chip according to any one of claims 1 to 13, wherein,the first wiring layer further comprises a first floating electrode, which is arranged adjacent to an end of the wiring led out from the first driving electrode and / or the first control electrode.

15. The microfluidic chip according to any one of claims 1 to 14, wherein,the second wiring layer further comprises a second driving electrode, a second control electrode and a second floating electrode,orthographic projections of the first driving electrode and the second driving electrode on the first substrate overlap, and the first driving electrode and the second driving electrode are connected by at least one via passing through the insulation layer,orthographic projections of the first control electrode and the second control electrode on the first substrate overlap, and the first control electrode and the second control electrode are connected by at least one via passing through the insulation layer, andthe second floating electrode is arranged adjacent to an end of an extended second wiring,and / or the second floating electrode is arranged adjacent to an end of a wiring led out from the second driving electrode and / or the second control electrode.

16. The microfluidic chip according to claim 15, wherein the second floating electrode comprises a first floating sub-electrode and a second floating sub-electrode,the first floating sub-electrode is arranged adjacent to an end of the extended second wiring, the second floating sub-electrode is arranged adjacent to an end of a wiring led out from the second driving electrode.

17. The microfluidic chip according to claim 16, wherein the second wiring layer further comprises a charge neutralization electrode,the charge neutralization electrode comprises the first floating sub-electrode and the second floating sub-electrode, as well as a floating belt connecting the first floating subelectrode and the second floating sub-electrode,the charge neutralization electrode surrounds the second wiring and the second driving electrode, and is arranged to be spaced apart from the end of the extended second wiring and the end of the wiring led out from the second driving electrode.

18. The microfluidic chip according to claim 17, wherein,a first groove is arranged on the dielectric layer, such that the end of the extended second wiring and a portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and a portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove, anda second groove is arranged at a position of the hydrophobic layer which corresponds to the first groove of the dielectric layer, such that the end of the extended second wiring and the portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and the portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove and the second groove.

19. A microfluidic chip comprising a first substrate, the first substrate comprising:a first wiring layer comprising a first wiring, a first driving electrode, and a first control electrode;an insulation layer located on the first wiring layer;a second wiring layer located on the insulation layer and comprising a second wiring;wherein orthographic projections of the first wiring and the second wiring on the first substrate overlap;a dielectric layer located on the second wiring layer;a hydrophobic layer located on the dielectric layer; andan electrostatic discharge component for releasing static electricity generated at an overlapping position of the first wiring and second wiring, and being arranged adjacent to the overlapping position.

20. The microfluidic chip according to claim 19, wherein,the electrostatic discharge component comprises a first floating line arranged on the first wiring layer, orthographic projections of the first floating line and the second wiring on the first substrate intersect perpendicularly, and an overlapping region of the orthographic projections of the first floating line and the second wiring on the first substrate is adjacent to an overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate, and / orthe electrostatic discharge component comprises a second floating line arranged on the second wiring layer, orthographic projections of the second floating line and the first wiring on the first substrate intersect perpendicularly, and an overlapping region of the orthographic projections of the second floating line and the first wiring on the first substrate is adjacent to an overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate.

21. The microfluidic chip according to any one of claims 19 to 20, wherein,the electrostatic discharge component comprises a first overlapping line arranged on the first wiring layer, orthographic projections of the first overlapping line and the second wiring on the first substrate overlap, and the first overlapping line is connected to the second wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to an overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate, and / orthe electrostatic discharge component further comprises a second overlapping line arranged on the second wiring layer, orthographic projections of the second overlapping line and the first wiring on the first substrate overlap, and the second overlapping line is connected to the first wiring through at least one via passing through the insulation layer, an orthographic projection of the at least one via on the first substrate is adjacent to the overlapping region ofthe orthographic projections of the first wiring and the second wiring on the first substrate.

22. The microfluidic chip according to claim 21, wherein,areas of orthographic projections of at least one via through which the first overlapping line is connected to the second wiring and / or at least one via through which the second overlapping line is connected to the first wiring on the first substrate are smaller than areas of an overlapping region of the orthographic projections of the first floating line and the second wiring on the first substrate and / or an overlapping region of the orthographic projections of the second floating line and the first wiring on the first substrate, andareas of the overlapping region of the orthographic projections of the first floating line and the second wiring on the first substrate and / or the overlapping region of the orthographic projections of the second floating line and the first wiring on the first substrate are smaller than an area of the overlapping region of the orthographic projections of the first wiring and the second wiring on the first substrate.

23. The microfluidic chip according to any one of claims 19 to 22, wherein,the electrostatic discharge component comprises a first floating electrode arranged on the first wiring layer, and the first floating electrode is arranged adjacent to an end of a wiring led out from the first driving electrode and / or the first control electrode.

24. The microfluidic chip according to any one of claims 19 to 23, wherein,the second wiring layer further comprises a second driving electrode, a second control electrode and a second floating electrode,orthographic projections of the first driving electrode and the second driving electrode on the first substrate overlap, and the first driving electrode and the second driving electrode are connected by at least one via passing through the insulation layer,orthographic projections of the first control electrode and the second control electrode on the first substrate overlap, and the first control electrode and the second control electrode are connected by at least one via passing through the insulation layer, andthe electrostatic discharge component comprises a second floating electrode arranged on the second wiring layer, the second floating electrode is arranged adjacent to an end of the extended second wiring, and / or the second floating electrode is arranged adjacent to an end of a wiring led out from the second driving electrode and / or the second control electrode.

25. The microfluidic chip according to claim 24, wherein the second floating electrode comprises a first floating sub-electrode and a second floating sub-electrode,the first floating sub-electrode is arranged adjacent to an end of the extended second wiring, the second floating sub-electrode is arranged adjacent to an end of a wiring led out from the second driving electrode.

26. The microfluidic chip according to claim 25, wherein the second wiring layer further comprises a charge neutralization electrode,the charge neutralization electrode comprises the first floating sub-electrode and the second floating sub-electrode, as well as a floating belt connecting the first floating subelectrode and the second floating sub-electrode,the charge neutralization electrode surrounds the second wiring and the second driving electrode, and is arranged to be spaced apart from the end of the extended second wiring and the end of the wiring led out from the second driving electrode.

27. The microfluidic chip according to claim 26, wherein,a first groove is arranged on the dielectric layer, such that the end of the extended second wiring and a portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and a portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove, anda second groove is arranged at a position of the hydrophobic layer which corresponds to the first groove of the dielectric layer, such that the end of the extended second wiring and the portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and the portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove and the second groove.

28. A microfluidic chip comprising a first substrate, the first substrate comprising:a first wiring layer comprising a first wiring, a first driving electrode, and a first control electrode;an insulation layer located on the first wiring layer;a second wiring layer located on the insulation layer and comprising a second wiring, a second driving electrode and a second control electrode;a dielectric layer located on the second wiring layer; anda hydrophobic layer located on the dielectric layer,wherein the first wiring is configured to connect the first driving electrode and the firstcontrol electrode, and the second wiring is configured to connect first wirings that are connected to different first driving electrodes by a via passing through the insulation layer,orthographic projections of the first driving electrode and the second driving electrode on the first substrate overlap, and the first driving electrode and the second driving electrode are connected by at least one via passing through the insulation layer,orthographic projections of the first control electrode and the second control electrode on the first substrate overlap, and the first control electrode and the second control electrode are connected by at least one via passing through the insulation layer, andwherein the first wiring layer further comprises a first floating electrode, which is arranged adjacent to an end of a wiring led out from the first driving electrode and / or the first control electrode, and / orwherein the second wiring layer further comprises a second floating electrode, the second floating electrode is arranged adjacent to an end of the extended second wiring, and / or the second floating electrode is arranged adjacent to an end of a wiring led out from the second driving electrode and / or the second control electrode.

29. The microfluidic chip according to claim 28, wherein the second floating electrode comprises a first floating sub-electrode and a second floating sub-electrode,the first floating sub-electrode is arranged adjacent to an end of the extended second wiring, the second floating sub-electrode is arranged adjacent to an end of a wiring led out from the second driving electrode.

30. The microfluidic chip according to claim 29, wherein the second wiring layer further comprises a charge neutralization electrode,the charge neutralization electrode comprises the first floating sub-electrode and the second floating sub-electrode, as well as a floating belt connecting the first floating subelectrode and the second floating sub-electrode,the charge neutralization electrode surrounds the second wiring and the second driving electrode, and is arranged to be spaced apart from the end of the extended second wiring and the end of the wiring led out from the second driving electrode.

31. The microfluidic chip according to claim 30, wherein,a first groove is arranged on the dielectric layer, such that the end of the extended second wiring and a portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and aportion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove, anda second groove is arranged at a position of the hydrophobic layer which corresponds to the first groove of the dielectric layer, such that the end of the extended second wiring and the 5 portion of the charge neutralization electrode adjacent to the end of the extended second wiring, as well as the end of the wiring led out from the second driving electrode and the portion of the charge neutralization electrode adjacent to the end of the wiring led out from the second driving electrode are exposed by the first groove and the second groove.

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