Multi-dielectric printed circuit board

Abstract

To provide a mixed material printed circuit board, a system, and a manufacturing, which show a plurality of regions of high and low dielectric constant (Dk) which adapts need for both serial and parallel interfaces.SOLUTION: A printed circuit board (PCB) comprises a first layer comprising a first dielectric material substantially exclusively. The PCB comprises a second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to the first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE, and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE, and the first Tg and the second Tg are greater than 150°C.SELECTED DRAWING: None

Description

[Background technology]

[0001] Parallel I / O interface speeds for Double Data Rate (DDR) and Synchronous Dynamic Random Access Memory (SDRAM) have steadily increased with each interface generation. As interface speeds increase, so does the demand for high-performance printed circuit boards (PCBs) with data buses that meet the high-speed requirements of modern interfaces. Such PCBs must carry high-speed serial data in the multi-gigabit-per-second (Gb / s) range (e.g., USB4 / PCIe Gen 5&6 / Thunderbolt® with transfer speeds faster than 20 Gb / s) and parallel bus clock speeds exceeding 3.5 GHz without loss of signal integrity. High-speed buses for parallel data transfer require PCB materials with relatively high dielectric constants (Dk), while serial I / O buses on the same PCB require low-Dk materials to reduce capacitance loss. Since PCBs are manufactured from only one formulation of prepreg polymer and are created to have a uniform composition, serial and parallel interfaces on the same layer of the PCB must share the same dielectric environment. As a result, conventional PCB manufacturing methods cannot create PCBs that have two or more dielectric materials in the same layer, which may necessitate compromises in design or performance. [Brief explanation of the drawing]

[0002] Embodiments of this disclosure will be better understood from the detailed description given below and from the accompanying drawings of various embodiments of this disclosure. However, these should not be construed as limiting this disclosure to any particular embodiment, but are merely for illustrative and understanding purposes.

[0003] [Figure 1A] This is a cross-sectional view in the xz plane of a mixed dielectric printed circuit board (PCB) comprising two dielectric materials, according to some embodiments of the present disclosure.

[0004] [Figure 1B] Figure 1A is a plan view in the xy plane of a mixed dielectric layer comprising two dielectric materials of a PCB, according to some embodiments of the present disclosure.

[0005] [Figure 2A] This is a cross-sectional view in the xz plane of a mixed dielectric PCB comprising three dielectric materials according to some embodiments of the present disclosure.

[0006] [Figure 2B] Figure 2A is a plan view of the xy plane in a mixed dielectric layer comprising three dielectric materials of a PCB, according to some embodiments of the present disclosure.

[0007] [Figure 3A] Figure 2A is a plan view in the xy plane of a partial stack-up of the PCB shown, illustrating the vertical interconnection of HSIO trace phases between conductive layers according to some embodiments of the present disclosure.

[0008] [Figure 3B] This is a cross-sectional view in the xz plane of a partial stack-up of the PCB shown in Figure 3A, according to some embodiments of the present disclosure.

[0009] [Figure 4A] Figure 1A is a plan view in the xy plane of a conductive layer in a partial stack-up of a PCB shown in some embodiments of the present disclosure.

[0010] [Figure 4B] This is a cross-sectional view in the xz plane of a partial stack-up of the PCB shown in Figure 4A, according to some embodiments of the present disclosure.

[0011] [Figure 5] This is a process flowchart for the creation of PCB 100 according to some embodiments of the present disclosure.

[0012] [Figure 6A] A diagram showing a method for creating a hybrid dielectric PCB having a hybrid dielectric layer according to some embodiments of the present disclosure. [Figure 6B] A diagram showing a method for creating a hybrid dielectric PCB having a hybrid dielectric layer according to some embodiments of the present disclosure. [Figure 6C] A diagram showing a method for creating a hybrid dielectric PCB having a hybrid dielectric layer according to some embodiments of the present disclosure. [Figure 6D] A diagram showing a method for creating a hybrid dielectric PCB having a hybrid dielectric layer according to some embodiments of the present disclosure. [Figure 6E] A diagram showing a method for creating a hybrid dielectric PCB having a hybrid dielectric layer according to some embodiments of the present disclosure. [Figure 6F] A diagram showing a method for creating a hybrid dielectric PCB having a hybrid dielectric layer according to some embodiments of the present disclosure. [Figure 6G] A diagram showing a method for creating a hybrid dielectric PCB having a hybrid dielectric layer according to some embodiments of the present disclosure.

[0013] [Figure 7] A cross-sectional view in the x-z plane of an exemplary implementation of a hybrid dielectric PCB according to some embodiments of the present disclosure.

[0014] [Figure 8] A block diagram showing a computing device as part of a system-on-chip (SoC) package in an implementation of a high-speed serial and parallel memory I / O interface controller coupled to high-speed serial interface I / O routing on a hybrid dielectric PCB having one or more hybrid dielectric layers according to some embodiments of the present disclosure.

Embodiments for Carrying Out the Invention

[0015] Disclosed herein is a mixed-material printed circuit board exhibiting multiple regions of high and low dielectric constants (Dk) to accommodate the needs of both serial and parallel interfaces. Parallel interfaces require I / O buses on high-Dk material PCBs, while serial interfaces ideally function on low-Dk material PCBs. Placing the two types of interfaces on the same substrate (e.g., prepreg) with a homogeneous composition results in one performance being sacrificed while the other is prioritized. The PCB of this disclosure solves this problem by providing layers and / or regions comprising both high-Dk and low-Dk prepreg materials.

[0016] Here, the term "stack-up" generally refers to a vertical stack in which dielectric and conductive layers are arranged alternately to form a printed circuit board. The stack-up is shown in cross-section to indicate the order, thickness, and type of layers that make up the PCB.

[0017] Here, the term "prepreg" generally refers to a composite material comprising a glass fiber fabric impregnated with a semi-cured epoxy. Prepregs are typically in the form of sheets that may be laminated on top of a PCB stackup.

[0018] Here, the term “dielectric constant” refers to the reference value of the dielectric constant of a material. The dielectric constant is denoted by the symbol Dk throughout this disclosure.

[0019] Figures labeled "section," "side," "plan," and "isometric" correspond to orthogonal planes in the Cartesian coordinate system. Therefore, section and side views are taken in the xz plane, plan views in the xy plane, and equivalent views in the three-dimensional Cartesian coordinate system (xyz). Where appropriate, axes are included in the drawings to indicate the orientation of the figure.

[0020] Figure 1A shows a cross-sectional view in the xz plane of a mixed dielectric PCB 100 according to several embodiments of the present disclosure.

[0021] The PCB 100 comprises an exemplary stack-up of alternating conductive and dielectric layers. In the illustrated embodiment, a plurality of conductive layers labeled L1, L2, L3, L4, L5, L6, L7, and L8 are alternately arranged with dielectric layers 101, 102, 103, 104, 105, 106, and 107. In some embodiments, dielectric layers 101, 103, 104, 105, and 107 comprise a single dielectric material 108, thereby exhibiting a substantially uniform dielectric constant Dk1 (e.g., relative permittivity ε r ) across the lateral extent of each layer. In some embodiments, the hybrid dielectric layers 102 and 106 comprise at least two dielectric materials 108 and 109 separated into adjacent dielectric regions 111, 112, 113, and 114, respectively. In some embodiments, the dielectric regions 112 and 114 may be embedded regions within the host regions 111 and 113, as shown in FIGS. 1B and 2B. The dielectric material 109 may exhibit a dielectric constant Dk2 (Dk2 < Dk1). As an example, the dielectric material 108 may comprise FR4, a common dielectric used in PCB manufacturing. FR4 may have a dielectric constant Dk1 of 4.4 when measured at 1 GHz. The dielectric material 109 may exhibit a dielectric constant Dk2 of 3.4 when measured at 2 GHz. The dielectric materials 108 and 109 may also exhibit a loss tangent Df (e.g., tan δ) having an upper limit of 0.02. Other low-Dk dielectric materials having suitable material constants may be used as the dielectric materials 108 and 109. For example, low-Dk prepreg patches may be fitted into a larger prepreg sheet comprising a high-Dk material. An example of this process will be described later.

[0022] In some embodiments, the dielectric materials 108 and 109 have substantially the same coefficient of thermal expansion (CTE). As an example, material 108 has a coefficient of thermal expansion of 14×10 -6Material 109 may have an in-plane (e.g., x and y) CTE of m / °C (e.g., 14 ppm / °C). Material 109 may have an in-plane CTE of 15 ppm / °C. The optimal CTE values ​​of dielectric materials 108 and 109 may be within 10% to 20% of each other. The substantially matching CTE values ​​of adjacent materials may prevent the formation of gaps, for example, at the boundaries (e.g., boundary 115 or 116) between adjacent dielectric regions 111 and 112 in the mixed dielectric layer 102, or between 113 and 114 in the mixed dielectric layer 106.

[0023] Conductive layers L2 and L7 adjacent to the mixed dielectric layers 102 and 106, respectively, may comprise ground planes 117 and 118, respectively. In some embodiments, conductive layers L3 and L6, also adjacent to the mixed dielectric layers 102 and 106, may comprise high-speed serial input / output (HSIO) interface routings 119 and 120 on the planes of regions 112 and 114 of the adjacent dielectric layers 102 and 106, respectively. Regions 119 and 120 may each comprise a dielectric material 109 exhibiting a dielectric constant Dk2.

[0024] In some embodiments, the conductive layers L2 and L7 also include high-speed parallel trace routings 121 and 122 on the surfaces of regions 111 and 113 within the dielectric layers 102 and 106, respectively. The high-speed parallel trace routings 121 and 122 may be interfaces for, for example, high-speed memory controllers and storage devices. Regions 111 and 113 may each comprise a dielectric material 108 exhibiting a dielectric constant Dk1 which may be at least 0.3 to 0.5 units higher than Dk2. Since low Dk may also have a corresponding low Df constant or loss tangent, routed HSIO traces 119 and 120 on the surface of a low-Dk dielectric material (e.g., dielectric 109) may reduce dissipative power loss from high-speed signals.

[0025] The location of the traces of the HSIO signal trace routings 119 and 120 on the surface of low-Dk material may allow for improved signal integrity compared to routing on the surface of high-Dk material. The low dielectric constant of dielectric 109 may restrict capacitive coupling to power routing, particularly to ground planes 117 and 118. Lower capacitive coupling to adjacent ground planes may reduce distortion of high-speed digital signals (e.g., 10 gigabits / second or more in recent PCIe implementations such as PCIe v.3 and above) and allow higher frequency signals to propagate along the HSIO trace while maintaining acceptable signal integrity. Alternative methods for reducing capacitance between the HSIO trace, ground plane and power trace may include reducing the trace width and the z-height of the dielectric.

[0026] To obtain effectively small HSIO routing capacitance through standard PCB materials (e.g., FR4) compatible with multiple gigabits / second signal speeds, reducing line width is impractical from a manufacturing standpoint, as the required line width is less than 10 micrometers. Thicker dielectric layers may be undesirable as they can increase the overall z-height of the PCB. Replacing standard dielectric materials with low-Dk materials eliminates the need to reduce line width beyond practical manufacturing limits or dielectric layer thickness beyond the maximum z-height specification.

[0027] In contrast, the high-speed parallel trace routings 121 and 122 may extend over the planes of regions 111 and 113, respectively. The host region 111 of the mixed dielectric layer 102 and the host region 113 of the mixed dielectric layer 106 each comprise a high-Dk dielectric material (e.g., FR4, or other material having Dk > 3.9). High-Dk materials are better suited to parallel interfaces with multiple parallel data lines than serial data interfaces with relatively few data lines because they enhance capacitive coupling to the ground plane (e.g., ground plane 117 or 118). The enhanced capacitive coupling of multiple parallel lines can reduce crosstalk due to inductive coupling between individual lines within the high-speed parallel trace routings 121 and 122. The large capacitance may effectively reduce inductance by shunting some of the inductance of the high-speed trace routings 121 and 122.

[0028] Additional conductive structures in the stack shown in Figure 1A may include data trace routings 123 and 124 in the top layer L1 and bottom layer L8, respectively. Conductive layers L4 and L5 may include power conductor trace routings 125 and 126. The dielectric material 108 conformally penetrates the conductive layers and conformally embeds the conductors, as shown. A single dielectric layer 104 comprising the dielectric material 108 may be separate power conductor layers L4 and L5. Solder resists 127 on the top and bottom of the stack-up of PCB 100 are also shown.

[0029] Figure 1B shows a plan view in the xy plane of the mixed dielectric layer 106 of the PCB 100 according to some embodiments of the present disclosure.

[0030] In the embodiment shown in Figure 1B, region 114 may comprise a prepreg patch comprising a low-Dk, low-loss dielectric material 109. In the embodiment shown, the embedded region 114 is surrounded by a host region 113, thereby the boundary 126 between the embedded region 114 and the host region 113 extends around the periphery of the embedded region 114 (e.g., including the tips 128 and 129). In the embodiment shown, region 113 may comprise a prepreg sheet comprising a high-Dk (e.g., standard FR4) dielectric material 108 as described above. The host region 113 may extend over a lateral range having a length w1 (x direction) and width w2 (y direction) of the PCB 100 (e.g., extending from tip to tip in the x and y directions). The embedded region 114 may comprise a low-Dk, low-loss dielectric material 109 as described above. The embedded region 114 has lateral ranges w3 and w4 in the x and y directions, respectively, which may be shorter than the lateral ranges w1 and w2 of the host region 113. In some embodiments, one of the lateral ranges w3 or w4 of the embedded region 114 may be substantially equal to w1 or w2 of the host region 113, respectively. In some embodiments, the embedded region 114 is positioned at the corners of the host region 113, so that the two outer tips 128 and 129 of the embedded region 114 coincide with the tips 130 and 131 of the host region 113.

[0031] As described later, high-speed trace routing (e.g., HSIO routing 120) adjacent to the dielectric layer 106 (e.g., L6) may extend over both the host region 113 and the embedded region 114, crossing the boundary 126. In some embodiments, the high-speed trace routing may be confined to the embedded region 114 and interconnected perpendicularly with other conductors in the high-speed trace routing within PCB 100 or in another layer (e.g., mixed dielectric layer 102).

[0032] Figure 2A shows a cross-sectional view in the xz plane of a mixed dielectric PCB 200 according to several embodiments of the present disclosure.

[0033] The stack-up of PCB 200 is substantially similar to the stack-up of PCB 100 shown in Figure 1A. PCB 200 comprises a mixed dielectric layer 102, which contains two dielectric materials 108 and 109 in the host region 111 and the embedded region 112, respectively. PCB 200 further comprises a mixed dielectric layer 201, which contains a third low-Dk low-loss dielectric material 202 in the embedded region 203. In the illustrated embodiments, the embedded region 203 is adjacent to the host region 113. In some embodiments, an embedded region 114 containing the low-Dk low-loss dielectric material 109 is also adjacent to the embedded region 203. In some embodiments, the low-Dk low-loss dielectric material 202 exhibits a Dk3 lower than the Dk2 of the low-Dk low-loss dielectric material 109. In some embodiments, the dielectric constant Dk3 is less than 3. In some embodiments, the dielectric loss tangent Df3 (e.g., loss loss tangent tanδ) of the low-Dk low-loss material 202 may be lower than the Df2 of the low-Dk dielectric material 109. For example, Df3 may be in the range of 0.001 to 0.005 (measured above 1 GHz), while Df2 may be in the range of 0.005 to 0.02 (e.g., at 2 GHz). Examples of low-Dk low-loss materials include, but are not limited to, prepregs comprising fluoropolymers (e.g., PTFE), polyimides (e.g., Kapton®, UPILEX), ceramics such as alumina, or ceramic-organic composite materials such as RF-35.

[0034] In the illustrated embodiment, the HSIO trace routing 205 is located on region 203, comprising a very low-loss dielectric as described above. The HSIO trace routing 205 may be a high-speed data bus requiring an ultra-low-loss dielectric material (e.g., exhibiting Dk < 0.01 and Df < 0.005) for optimal signal integrity at signal speeds faster than 20 gigabits / second.

[0035] Figure 2B shows a plan view in the xy plane of the mixed dielectric layer 201 of the PCB 200 according to some embodiments of the present disclosure.

[0036] In some embodiments, the mixed dielectric layer 201 comprises embedded low-Dk regions 114, 203, and 204 contained within the host region 113. The embedded regions 114 and 203 are described above. In some embodiments, the embedded region 204 may comprise a dielectric material 205 exhibiting a dielectric constant Dk4, which may be intermediate between the Dk2 of dielectric material 109 and the Dk3 of dielectric material 202. In some embodiments, Dk4 is intermediate between the Dk1 and Dk2 of dielectric material 108. The embedded regions 109 and 202 may comprise prepreg patches embedded in the host region 113. In some embodiments, the host region 108 comprises a prepreg sheet having a high-Dk material (e.g., FR4) as described above. In some embodiments, the embedded regions 114, 203, and 204 each comprise a prepreg material in which each prepreg material exhibits a corresponding dielectric constant Dk2, Dk3, or Dk4, respectively.

[0037] In the illustrated embodiment, the embedded regions 114, 201, and 203 have lateral ranges that are within the maximum lateral range of the PCB 200. For example, the host region 113 (e.g., comprising dielectric material 108) has substantially the same dimensional range as the PCB 200, with maximum xy dimensions w5 and w6 (in the x and y directions, respectively). For example, region 114 may have x and y lateral dimensions w7 and w8, which are shorter than the maximum lateral ranges w5 and w6, respectively. Similarly, regions 202 and 205 have x and y lateral dimension pairs w9 / w10 and w11 / w12, respectively.

[0038] In the illustrated embodiments, the embedded regions 114, 203, and 204 are each completely surrounded by the host region 113, thereby giving each embedded region 114, 203, and 204 boundaries 206, 207, and 208, respectively, that extend around the periphery of the corresponding embedded region. In some embodiments, the embedded regions 114, 203, and 204 may share boundaries with one another without intervening material from the host region 113 between the embedded region boundaries (not shown).

[0039] The plurality of embedded regions may support multiple data interfaces on a single PCB. As an example, the low-loss dielectric material 109 of the embedded region 114 may have a dielectric constant Dk2 that supports a double data rate (DDR) memory interface with parallel routing of multiple data lines for medium data speeds (e.g., DDR4 data rate > 10 gigabits per second). The low-loss dielectric material 202 with a dielectric constant Dk3 < Dk2 may support a multi-lane serial interface for a PCI Express (PCIe) HSIO interface having a high data transfer speed (e.g., 8 to 32 gigabits per second per lane). The low-loss dielectric material 205 may be an ultra-low-loss material having a dielectric constant Dk4 (e.g., Dk4 ~ 2.5 < Dk3 < Dk2) and may support a faster HSIO interface (e.g., Thunderbolt™ v3) where the achievable data rate can approach 40 gigabits per second. The host region 113 comprising a higher-loss dielectric material (e.g., FR4 showing a Dk1 of 4.4) may support a low-speed memory or disk drive data bus.

[0040] FIG. 3A shows a plan view in the x-y plane of a partial stack-up of a PCB 100 showing a vertical interconnect of HSIO trace phases between conductive layers, according to some embodiments of the present disclosure.

[0041] In the plan view of Figure 3A, the conductive surfaces L3 and L6 of PCB 100 are exposed, showing the HSIO trace routing 120 on L6 and the HSIO trace routing 119 on L3. The mixed dielectric layer 102 is adjacent to L3 and is partially shown to indicate only a portion of the HSIO trace routing 119 extending over the host region 111. The HSIO trace routing 120 is confined to a region 114 terminating at a boundary 116, comprising a low-Dk dielectric material 109. In the illustrated example, the HSIO trace routings 119 and 120 are grouped into multiple I / O lanes, each lane having two traces. The HSIO trace routing 119 extends to the tip 302 of the mixed dielectric layer 102 over the host region 111, comprising a high-Dk dielectric material 108. Vias 301 may interconnect the HSIO trace routing 119 on L3 to the HSIO trace routing 120 on L6. The HSIO trace routing 119 may be coupled to a high-speed data interface (not shown) coupled to L3. The HSIO trace routing 120 on L6 may be coupled to a serial device interface (not shown) in region 114.

[0042] Figure 3B shows a cross-sectional view in the xz plane of a partial stack-up of PCB 100 shown in Figure 3A, according to some embodiments of the present disclosure.

[0043] The cross-sectional view in Figure 3B shows the vertical interconnection between the L6 HSIO trace routing 120 and the L3 HSIO trace routing 119, mediated by via 301. Via 301 extends through dielectric layers 105, 104, and 103 (shown combined as a single layer in the figure). In the illustrated embodiment, the HSIO trace routing 120 extends over the low-Dk dielectric material 109, passes over the high-Dk dielectric material 108 within the host region 113 of the mixed dielectric layer 106, and then reaches via 301. In other embodiments, the HSIO trace routing 120 may terminate within the embedded region 114 and may not need to cross the boundary 116 to reach the host region 113.

[0044] FIG. 4A shows a plan view of the conductive layer L6 of the partial stack-up of the PCB 100 in the x-y plane according to some embodiments of the present disclosure.

[0045] In the plan view of FIG. 4A, the high-speed parallel interface routing 120 extends in the x-direction over the embedded region 114 from the boundary 401 (left boundary) to the boundary 116 (right boundary). At the boundaries 401 and 116, the high-speed parallel interface routing 120 is interconnected with the high-speed parallel interface routing 122 that extends laterally over the host region 113. In the illustrated embodiment, the high-speed parallel interface routing 122 has a width w13 as shown in the insertion view and has a strip-line characteristic impedance Z of each trace according to the values of the dielectric constant Dk1 and the thickness of the dielectric material 108 (e.g., the thickness t shown in FIG. 4B). 01 may be generated. The width w13 may be adjusted to closely match the bonding impedance Z of the device coupled to the high-speed parallel interface routing 122 01 (e.g., 50 Ω). A dielectric discontinuity may exist at the boundary 116 between the host region 113 (having Dk1) and the embedded region 114 (having Dk2 (Dk2 < Dk1)).

[0046] According to some embodiments, the high-speed parallel interface routing 120 may be impedance-matched to the high-speed parallel interface routing 122 to increase the return loss when a high-speed signal crosses the boundary 116. The high-speed parallel interface routing 120 is sized to have a line width w14 and has a characteristic impedance Z on the dielectric material 109. 02 may be generated. In some embodiments, the dimensional transition between w13 of the high-speed parallel interface routing 122 and w14 of the high-speed interface routing 120 may exist at the dielectric boundary 116, thereby making Z 02 substantially match Z 01 (e.g., Z01 =Z 02 )。An example of the width transition of each trace 122 is shown in the insert diagram of FIG. 4A. The junction 402 monotonically widens the line 403 of the high-speed parallel interface routing 120 from w13 to w14 in the vicinity of the boundary 116 to form a gradual transition to the high-speed parallel interface 122. Similarly, a tapered line width transition may exist in the high-speed parallel interface routing 120 or 122 in the vicinity of the boundary 401.

[0047] FIG. 4B shows a cross-sectional view in the x-z plane of a partial stack-up of the PCB 100 shown in FIG. 4A according to some embodiments of the present disclosure.

[0048] In the illustrated embodiment, an enlarged view of the cross-section near the dielectric boundary 116 is shown. The high-speed parallel interface routing 122 is coupled to the high-speed parallel interface routing 120 at the dielectric boundary 116. During operation, a signal coupled to the high-speed parallel interface routing 122 may be routed through the embedded region 114 to a receiving device located above the host region 113.

[0049] The high-speed parallel interface routing 120 may include a tapered junction 402 that matches the transmission line impedance at the dielectric boundary 116. As described above, the tapered junction 402 may provide a smooth transition of the line width w13 of an individual trace in the high-speed parallel interface routing 120 to the width w14 of the trace in the high-speed parallel interface routing 122. The line widths w1 and w2 are optimized to match Z 02 to Z 01 so as to reduce the reflected power loss therewith.

[0050] The characteristic transmission line impedances Z of the high-speed parallel interface routings 120 and 122 respectively 02 and Z 01These may be matched by optimizing w13 and w14 according to the dielectric materials 108 and 109 (e.g., Dk1 and Dk2) and the thickness t of the mixed dielectric layer 106. The target impedance values ​​may be, for example, 45Ω, 80Ω, and 90Ω.

[0051] Figure 5 shows a process flowchart 500 for creating a PCB 100 according to several embodiments of the present disclosure.

[0052] In operation 501, a partially completed PCB stack-up is accepted. The partially completed PCB stack-up comprises a core having a dielectric cladding of two copper layers on both sides. One of the copper layers may be exposed at the top of the stack-up, and the copper layer may be patterned in a subsequent operation.

[0053] In operation 502, one copper layer of the core may be patterned to form HSIO interface routing (e.g., HSIO interface routing 120) and parallel interface routing (e.g., high-speed parallel interface routing 122). Patterning may be performed by through-mask etching. The mask may be a lithographically patterned photoresist. The conductive layer may correspond to L3 or L6 in the stack-up of PCB 100, for example.

[0054] In operation 503, a high-Dk dielectric material (e.g., dielectric material 108, Dk1>4) is laminated on top of a patterned copper layer. The high-Dk dielectric material may comprise a prepreg material. One or more openings may be pre-formed in the high-Dk dielectric material before lamination. One or more openings in the high-Dk material may be aligned on the HSIO interface routing in the conductive layer.

[0055] In operation 504, a patch comprising a low Dk dielectric material (e.g., dielectric material 109, Dk2 < Dk1) may be fitted into one or more openings in a high Dk (e.g., first prepreg) material. The low Dk dielectric material may comprise a second prepreg material.

[0056] In operation 505, the low Dk material patch is fastened to the core by a plurality of rivets inserted along the peripheral region of the low Dk material patch. The rivets may penetrate the core and the underlying conductive and dielectric layers in the partially completed PCB stackup. The peripheral region of the low Dk material patch may comprise a prohibited access region to eliminate circuit routing and other metallization.

[0057] In operation 506, the high Dk prepreg and the low Dk prepreg patch may be bonded to the conductive and dielectric portions of the core by thermocompression bonding to create a hybrid dielectric layer (e.g., hybrid dielectric layer 106). The partially completed PCB stackup may be further constructed and completed after operation 506. Some of the above operations may be repeated to include additional hybrid dielectric layers (e.g., hybrid dielectric layer 102).

[0058] FIGS. 6A - 6G illustrate a method of creating a hybrid dielectric PCB 100 comprising a hybrid dielectric layer 106 according to some embodiments of the present disclosure.

[0059] Figure 6A shows a partial stack-up of PCB 100. The partial stack-up comprises a dielectric layer 107 having a dielectric material 108. The dielectric material 108 may be a relatively high Dk material, such as but not limited to FR4 and other members of the FR X family. For example, the dielectric layer 107 may be an FR4 sheet having a thickness of about 100 microns (e.g., 4 mils). Other suitable special formulations may be used for specific material properties. In particular, the material may be selected with respect to properties such as Tg, CTE, and dielectric constant Dk and loss tanδ or Df. The thickness of the dielectric material 108 may be selected according to the design specifications for capacitance and transmission line characteristic impedance. For example, matching the CTE between adjacent materials may avoid the formation of gaps at region boundaries or boundary shifts due to thermal expansion and contraction during heating and cooling (e.g., during and after the thermal compression bonding of prepregs in assembly). A suitable match of Tg between adjacent materials may be used to allow the fluid material components to blend at the region boundary when they soften or liquefy during thermal compression bonding.

[0060] The dielectric layer 107 may be a core layer comprising conductive layers 118 and 124 bonded to both sides of the dielectric layer 107. The conductive layer is 17 to 35 microns (e.g., ft 2 (0.09m 2 The dielectric material 108 may comprise a copper foil laminate having a thickness of 0.5 oz to 1 oz (14.2 to 28.3 g) per unit. The dielectric material 108 may be a high Dk prepreg material (e.g., Dk1). The dielectric material may be laminated on the copper layer 117 and bonded to the copper layer 117 by thermal compression bonding. In some embodiments, an opening 601 is formed in the dielectric material 108 by cutting out a region from the dielectric material 108 by mechanical or laser cutting to create a side wall 128. The opening 601 may have a rectangular shape in plan view, but the opening 601 may have any preferred shape.

[0061] In Figure 6B, the dielectric material 109 is placed within the opening 601. The dielectric material 109 may be a low-Dk material comprising a prepreg material exhibiting a dielectric constant Dk2. As mentioned above, Dk2 is lower than the dielectric constant of the dielectric material 108 (e.g., Dk1). The dielectric material 109 may be pre-cut to the size of the opening 601 such that the sidewall 602 of material 109 abuts against the sidewall 128 of material 108.

[0062] In the exemplary operation shown in Figure 6B, the dielectric material 109 may be placed within the opening 601 without pre-coating its surface with adhesive. Bonding and curing of the prepreg material may be carried out in subsequent operations.

[0063] In Figure 6C, multiple rivets 603 may be inserted into the opening 601 along the periphery of the material 109. The rivets 603 may penetrate the lower layer of the partial stack-up of the PCB 100 as shown, securing the material 109 into the opening 601 for further processing. The rivets 603 may be installed by an automated riveting device. The rivets may be installed along the peripheral portion of the dielectric material 109 to avoid routing in the internal portion of the dielectric material 109. In some embodiments, the mixed dielectric layer 106 is complete with other dielectric materials (e.g., dielectric material 201).

[0064] In Figure 6D, copper foil 604 is laminated on a dielectric layer 106 of a partial stack-up of PCB 100 to form a conductive layer L6. The copper foil 604 may be laminated on the dielectric layer 106 by thermal compression bonding. In some embodiments, rivets 603 may be covered with copper foil 604. In some embodiments, the copper foil 604 has a thickness in the range of about 17 to 35 microns (e.g., 0.6 to 1.2 mils). In a subsequent operation, the copper foil 604 may be patterned to a lithographically defined mechanism by a copper etching method.

[0065] In Figure 6E, the copper foil 604 is patterned to form a conductive mechanism in L6. In some embodiments, the conductive mechanism in L6 comprises an HSIO interface routing 120 on a low-Dk dielectric material 109 and a high-speed parallel interface routing 122 on a high-Dk dielectric material 108. The patterning of the conductive mechanism in L6 may be performed in a copper etch bath. The photoresist etch mask may be made by laminating a positive or negative photoresist on the copper foil 604, then exposing and developing it through a lithography mask.

[0066] In Figure 6F, the dielectric layer 105 is formed by laminating dielectric material 108 on L6. Dielectric material 108 may be a prepreg layer substantially identical to the prepreg described above, applied to the lower dielectric layers such as dielectric layer 106 and dielectric layer 107 in the partial stack-up shown in Figure 6A. A thermal compression bonding procedure may be used to bond and cure the prepreg layer to the L6 mechanism and the dielectric materials 108 and 109 of the mixed dielectric layer 106. Some of the dielectric material 108 may conformally cover the L6 mechanism (e.g., HSIO interface routing 120 and high-speed parallel interface routing 122), as shown.

[0067] In Figure 6G, the stack-up of PCB 100 is completed up to the top conductive layer L1, including the addition of the solder mask 127. The peripheral area 605, which includes the rivets 603, is separated from the main part of the stack-up 606 by a preferred laser or mechanical cutting method, indicated by vertical dashed lines. The side wall 607 formed by the cutting (e.g., by laser cutting or mechanical sawing) may be, for example, one of the tips 129 or 130 of PCB 100. The peripheral area 605 may include a no-entry zone that excludes all trace routing and other conductive mechanisms of all conductive surfaces L1-L8 from the peripheral area 605, thereby confining all routing and conductive mechanisms to the main part 606.

[0068] Figure 7 shows a cross-sectional view in the xz plane of an exemplary mounting of a mixed dielectric PCB 700 according to several embodiments of the present disclosure.

[0069] In the illustrated embodiments, the stack-up of the mixed dielectric PCB 700 is similar to the stack-up of the mixed dielectric PCB 100 shown in Figure 1A. The PCB 700 includes vias 701 and 702 that extend vertically within the PCB 700 to provide vertical interconnects between conductive layers L1-L6. Device 703 is coupled to via 701 through pad 704. In the illustrated embodiments, via 701 is electrically coupled to routing 119 on L3 and 120 on L6. In some embodiments, routing 119 is an HSIO interface routing. In some embodiments, device 703 may be an HSIO interface, such as a PCIe chip package or daughterboard card slot, having interconnect pins arranged in a dual inline pin (DIP) architecture. One DIP row may have ground pins coupled to trace 124 of the top conductive layer L1 by a solder joint 705, and a second DIP row may have signal pins coupled to pad 704 of the top conductive layer L1 through a solder joint 706. Pad 704 may be integrated with via 701 as shown. In the illustrated embodiment, via 701 provides a vertical interconnect between HSIO interface 703 coupled to the top layer L1 and HSIO interface routings 119 and 120 of L3 and L6, respectively.

[0070] In a manner similar to that of the HSIO interface 703, device 707 is coupled to via 702 through pad 708. Device 707 may be a high-speed parallel interface, such as DDR memory. In some embodiments, device 707 may be a daughterboard, a chip package, or a DIP slot for interface connection of devices, or for interface connection from routing on one layer to another within PCB 700. In the illustrated embodiment, pad 708 is integrated with via 702, allowing the high-speed parallel interface 707 to be vertically interconnected to the L3 and L6 high-speed parallel interface routings 121 or 122.

[0071] Figure 8 shows a block diagram of a computing device 800 as part of a system-on-chip (SoC) package in an implementation of a high-speed serial and parallel I / O interface controller coupled to high-speed serial interface I / O routing on a mixed dielectric PCB 700 comprising one or more mixed dielectric layers, according to some embodiments of the present disclosure.

[0072] According to some embodiments, the computing device 800 represents a server, desktop workstation, or mobile workstation, including but not limited to a laptop computer, computing tablet, mobile phone or smartphone, wireless-enabled electronic reader, or other wireless mobile device. The multi-chip IC package, including but not limited to a single or multi-core microprocessor (e.g., representing a central processing unit), logic dies, RF dies, high-power dies, memory dies, antenna dies, etc., comprises, for example, a package substrate.

[0073] In some embodiments, the computing device has wireless connectivity (e.g., Bluetooth®, WiFi®, and 5G networks). Generally, specific components are shown, and it will be understood that not all components of such a device are shown for computing device 800.

[0074] Various embodiments of this disclosure may also include a network interface 870, such as within a wireless interface, so that embodiments of the system may be incorporated into a wireless device, such as a mobile phone or personal information terminal. The wireless interface includes a millimeter-wave generator and an antenna array. The millimeter-wave generator may be part of a monolithic microwave integrated circuit.

[0075] According to some embodiments, the processor 810 represents a CPU or GPU and may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processor 810 may be coupled to a memory controller or a high-speed serial I / O interface controller, as disclosed. The processing operations performed by the processor 810 include the execution of an operating platform or operating system on which applications and / or device functions are performed. The processing operations include operations related to I / O (input / output) with human users or other devices, operations related to power management, and / or operations related to connecting the computing device 800 to another device. The processing operations may also include operations related to audio I / O and / or display I / O.

[0076] In one embodiment, the computing device 800 includes an audio subsystem 820 representing hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone outputs, as well as a microphone input. Devices for such functionality may be integrated into or connected to the computing device 800. In one embodiment, a user interacts with the computing device 800 by providing voice commands that are received and processed by the processor 810.

[0077] The display subsystem 830 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and / or tactile display for the user to interact with the computing device 800. The display subsystem 830 includes a display interface 832, which includes a specific screen or hardware device used to provide a display to the user. In one embodiment, the display interface 832 includes logic separate from the processor 810 that performs at least some processing related to the display. In one embodiment, the display subsystem 830 includes a touchscreen (or touchpad) device that provides both output and input to the user.

[0078] The I / O controller 840 represents hardware devices and software components related to user interaction. The I / O controller 840 is capable of managing hardware that is part of the audio subsystem 820 and / or the display subsystem 830. In addition, the I / O controller 840 indicates connection points to additional devices that connect to the computing device 800, through which the user may interact with the system. For example, devices that can be attached to the computing device 800 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboards or keypad devices, or other I / O devices used with specific applications, such as card readers or other devices.

[0079] As described above, the I / O controller 840 can interact with the audio subsystem 820 and / or the display subsystem 830. For example, input through a microphone or other audio device can provide input or commands to one or more applications or functions of the computing device 800. In addition, it can provide audio output instead of or in addition to the display output. In another example, if the display subsystem 830 includes a touchscreen, the display device also acts as an input device that can be managed at least partially by the I / O controller 840. There may also be additional buttons or switches on the computing device 800 that provide I / O functions managed by the I / O controller 840.

[0080] In one embodiment, the I / O controller 840 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in the computer 800. Inputs may provide some direct user interaction, as well as environmental inputs that affect the system's operation (such as noise filtering, display adjustments for brightness detection, camera flash application, or other features).

[0081] In one embodiment, the computing device 800 includes a power management system 850 that manages mechanisms related to battery power usage, battery charging, and power-saving operation. The memory subsystem 860 includes memory devices that store information in the computing device 800. The memory may include non-volatile (the state does not change when power to the memory device is cut off) and / or volatile (the state is uncertain when power to the memory device is cut off) memory devices. The memory subsystem 860 may store application data, user data, music, photographs, documents, or other data, as well as system data (whether long-term or short-term) related to the execution of applications and functions of the computing device 800.

[0082] Embodiments are also provided as a machine-readable medium (e.g., memory 860) for storing computer executable instructions. Examples of machine-readable medium (e.g., memory 860) include, but are not limited to, flash memory, optical discs, CD-ROMs, DVD-ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable medium suitable for storing electronic or computer executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) using data signals over a communication link (e.g., a modem or network connection).

[0083] Connectivity via the network interface 870 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) that enable the computing device 800 to communicate with external devices. The computing device 800 may be a separate device, such as another computing device, a wireless access point or base station, or peripherals such as a headset, printer, or other device.

[0084] The network interface 870 may include several different types of connectivity. For generalization, the computing device 800 is represented using cellular connectivity 872 and radio connectivity 874. Cellular connectivity 872 generally refers to cellular network connectivity provided by a radio carrier, such as through GSM® (Pan-European Mobile Communications System) or its variations or derivatives, CDMA (Code Division Multiple Access) or its variations or derivatives, TDM (Time Division Multiplexing) or its variations or derivatives, or other cellular service standards. Radio connectivity (or radio interface) 874 refers to non-cellular radio connectivity and may include personal area networks (such as Bluetooth® nearfield), local area networks (such as Wi-Fi®), and / or wide area networks (such as WiMAX®), or other radio communications.

[0085] The peripheral connection 880 includes hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) that make up the peripheral connection. It will be understood that the computing device 800 can be both a peripheral device to other computing devices ("output" 882) and a peripheral device connected to it ("in" 884). The computing device 800 generally has a "docking" connector that connects to other computing devices for purposes such as managing the content of the computing device 800 (e.g., downloading and / or uploading, modifying, synchronizing). In addition, the docking connector can enable the computing device 800 to connect to specific peripheral devices, thereby enabling the computing device 800 to control content output to, for example, audiovisual or other systems.

[0086] In addition to dedicated docking connectors or other dedicated connection hardware, the computing device 800 can make peripheral connections 880 via common or standards-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of a number of different hardware interfaces), DisplayPort including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI®), FireWire, or other types.

[0087] Furthermore, specific features, structures, functions, or characteristics may be combined in any preferred manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment in any case, provided that the specific features, structures, functions, or characteristics associated with the first and second embodiments are not mutually exclusive.

[0088] While this disclosure has been described in relation to its specific embodiments, many alternatives, modifications, and variations of such embodiments will be obvious to those skilled in the art in light of the foregoing description. The embodiments of this disclosure shall encompass all such alternatives, modifications, and variations as being within the broad scope of the appended claims.

[0089] In addition, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented drawings for the sake of simplicity in the examples and discussion, and to avoid obscuring the disclosure. Furthermore, to avoid obscuring the disclosure, and in light of the fact that details regarding the implementation of block diagram arrangements depend heavily on the platform on which the disclosure is to be implemented (i.e., such details should be well within the scope of expertise of those skilled in the art), arrangements may be shown in the form of block diagrams. Where certain details (e.g., circuits) are described in order to describe exemplary embodiments of the disclosure, it should be obvious to those skilled in the art that the disclosure can be practiced without these specific details or using variations thereof. Therefore, the descriptions should be considered illustrative rather than restrictive.

[0090] The following examples relate to further embodiments. Details in the examples may be used in any one of one or more embodiments. Any mechanism of the apparatus described herein may also be implemented in terms of methods or processes.

[0091] Example 1 is a printed circuit board (PCB) comprising a first layer having substantially exclusively a first dielectric material, and a second layer having the first dielectric material in a first region and a second dielectric material in a second region adjacent to the first region, wherein the first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE), and a first glass transition temperature (Tg), and the second dielectric material has a second dielectric constant, a second CTE, and a second Tg, wherein the first dielectric constant is higher than the second dielectric constant, the first CTE is substantially equal to the second CTE, and the first and second Tg are higher than 150°C.

[0092] Example 2 incorporates all the features of Example 1, wherein the first boundary between the first and second regions extends around the periphery of the second region.

[0093] Example 3 incorporates all the features of Example 2, wherein the first dielectric material is mixed with the second dielectric material at the first boundary.

[0094] Example 4 incorporates all the features of Example 2 or 3, wherein the first side wall of the first region is adjacent to the second side wall of the second region at the first boundary.

[0095] Example 5 incorporates all the features of Example 4, wherein the first distance between the first sidewall and the second sidewall is between zero and 10 microns.

[0096] Example 6 incorporates all the features of any one of Examples 1 to 5, wherein the second layer further comprises a third dielectric material in a third region adjacent to the first region.

[0097] Example 7 incorporates all the features of Example 6, wherein the second boundary between the first and third regions extends around the periphery of the third region.

[0098] Example 8 incorporates all the features of Example 6 or 7, wherein the third dielectric material has a third dielectric constant lower than the second dielectric constant, a third Tg substantially equal to the first and second Tg, and a third CTE substantially equal to the first and second CTE.

[0099] Example 9 incorporates all the features of any one of Examples 1 to 8, wherein the first core layer is located between the first and second layers, the first core layer has a first surface and a second surface facing it, the first copper layer is located on the first surface, the second copper layer is located on the second surface, and the first core layer comprises a fourth dielectric material having a fourth dielectric constant lower than the first dielectric constant.

[0100] Example 10 incorporates all the features of Example 9 and further comprises a third layer, the third layer having a fourth region and a fifth region adjacent to the fourth region, the fourth region comprising a fifth material having a fifth dielectric constant, and the fifth region comprising a sixth material having a sixth dielectric constant.

[0101] Example 11 incorporates all the features of Example 10, wherein the second core layer is located between the first and third layers, the second core layer has a third surface and a fourth surface facing it, the third copper layer is located on the third surface, the fourth copper layer is located on the fourth surface, and the second core layer comprises a seventh dielectric material having a seventh dielectric constant lower than the first dielectric constant.

[0102] Example 12 incorporates all the features of any one of Examples 1 to 11, wherein the first dielectric constant is at least 0.3 units higher than the second dielectric constant.

[0103] Example 13 is a printed circuit board (PCB) comprising: a first layer having substantially exclusively a first dielectric material; a second layer having the first dielectric material in a first region and a second dielectric material in a second region adjacent to the first region, wherein the first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE), and a first glass transition temperature (Tg); the second dielectric material has a second dielectric constant, a second CTE, and a second Tg, wherein the first dielectric constant is higher than the second dielectric constant, the first CTE is substantially equal to the second CTE, and the first and second Tgs are higher than 150°C; and a first routing on the first region of the second layer and a second routing on the second region of the second layer.

[0104] Example 14 incorporates all the features of Example 13, wherein the first routing is a first portion of parallel memory interface routing or chip package routing that extends over a second region of the second layer.

[0105] Example 15 incorporates all the features of Example 14, with the second part of the parallel memory interface routing placed on top of the first layer.

[0106] Example 16 incorporates all the features of any one of Examples 13-15, wherein the HSIO serial interface routing is the first HSIO serial interface routing, and the second HSIO serial interface routing is located on the third region of the second layer.

[0107] Example 17 incorporates all the features of Example 16, with the HSIO serial interface routing or chip package routing extending over the first region of the second layer.

[0108] Example 18 incorporates all the features of any one of Examples 13 to 17, wherein the second layer comprises a third region, the third region having a third material having a third dielectric constant substantially different from that of the second dielectric constant.

[0109] Example 19 incorporates all the features of any one of Examples 1 to 18, further comprising a third layer having a fourth region and a fifth region adjacent to the fourth region, wherein the fourth region comprises a fourth material having a first dielectric constant and the fifth region comprises a fifth material having a second dielectric constant.

[0110] Example 20 is a method for creating a printed circuit board (PCB) comprising: accepting a PCB layer stack having a core, the core having a dielectric layer exclusively comprising a first dielectric material, the first dielectric material having a first dielectric constant, the first conductive layer being on a first surface of the first dielectric layer, and the second conductive layer being on a second opposing surface of the first dielectric layer; patterning the first conductive layer to form high-speed interface routing having high-speed input / output (HSIO) interface routing and high-speed parallel interface routing; laminating a first prepreg sheet having the first dielectric material and one or more openings on the first conductive layer; and riveting a second prepreg sheet having a second dielectric constant substantially different from the first dielectric constant into one or more openings in the second dielectric layer.

[0111] Example 21 incorporates all the features of Example 20, and further comprises patterning a second copper layer to form high-speed input / output (HSIO) interface routing and high-speed parallel interface routing.

[0112] Example 22 incorporates all the features of Example 21, wherein the second dielectric layer is laminated on the first conductive layer, and one or more openings are aligned on the HSIO interface routing.

[0113] Example 23 incorporates all the features of any one of Examples 20 to 22, wherein riveting the second prepreg sheet into one or more openings comprises driving multiple rivets along the peripheral area of ​​the second prepreg sheet to fasten the second prepreg sheet to the PCB core.

[0114] Example 24 incorporates all the features of any one of Examples 20 to 23, further comprising riveting a third prepreg sheet into one or more openings, wherein riveting the third prepreg sheet involves driving a plurality of rivets along the peripheral area of ​​the third prepreg sheet to fasten the third prepreg sheet to the PCB core.

[0115] The abstract is submitted with the understanding that it is not intended to limit the scope or meaning of the claims. The following claims are thus incorporated into the detailed description, and each claim stands on its own as a distinct embodiment.

Claims

1. a first layer consisting essentially of a first dielectric material; a second layer having the first dielectric material in a first region and a second dielectric material in a second region adjacent the first region; the first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE), and a first glass transition temperature (Tg); the second dielectric material having a second dielectric constant, a second CTE, and a second Tg; the first dielectric constant is higher than the second dielectric constant; the first CTE is substantially equal to the second CTE; the first Tg and the second Tg are greater than 150°C; Printed circuit board (PCB).

2. The PCB of claim 1 , wherein a first boundary between the first region and the second region extends around a perimeter of the second region.

3. 3. The PCB of claim 2, wherein a first sidewall of the first region is adjacent to a second sidewall of the second region at the first boundary.

4. 4. The PCB of claim 3, wherein a first distance between the first sidewall and the second sidewall is between zero and 10 microns.

5. The PCB of any one of claims 1 to 4, wherein the second layer further comprises a third dielectric material in a third region adjacent to the first region.

6. The PCB of claim 5 , wherein a second boundary between the first region and the third region extends around a perimeter of the third region.

7. 7. The PCB of claim 5 or 6, wherein the third dielectric material has a third dielectric constant lower than the second dielectric constant, a third Tg substantially equal to the first Tg and the second Tg, and a third CTE substantially equal to the first CTE and the second CTE.

8. 8. The PCB of claim 1, wherein a first core layer is between the first layer and the second layer, the first core layer having a first surface and a second surface opposite the first surface, a first copper layer is on the first surface, a second copper layer is on the second surface, and the first core layer comprises a fourth dielectric material having a fourth dielectric constant lower than the first dielectric constant.

9. 9. The PCB of claim 8, further comprising a third layer, the third layer having a fourth region and a fifth region adjacent to the fourth region, the fourth region including a fifth material having a fifth dielectric constant, and the fifth region including a sixth material having a sixth dielectric constant.

10. 10. The PCB of claim 9, wherein a second core layer is between the first layer and the third layer, the second core layer having a third surface and a fourth surface opposite the third surface, a third copper layer is on the third surface, a fourth copper layer is on the fourth surface, and the second core layer comprises a seventh dielectric material having a seventh dielectric constant lower than the first dielectric constant.

11. The PCB of any one of claims 1 to 10, wherein the first dielectric constant is at least 0.3 units higher than the second dielectric constant.

12. 1. A printed circuit board (PCB), comprising: a first layer consisting essentially of a first dielectric material; a second layer having the first dielectric material in a first region and a second dielectric material in a second region adjacent the first region; the first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE), and a first glass transition temperature (Tg); the second dielectric material having a second dielectric constant, a second CTE, and a second Tg; the first dielectric constant is higher than the second dielectric constant; the first CTE is substantially equal to the second CTE; a PCB, wherein the first Tg and the second Tg are greater than 150°C; a first routing overlying the first region of the second layer; a second routing overlying the second region of the second layer; and A system comprising:

13. 13. The system of claim 12, wherein the first routing is a first portion of a parallel memory interface routing or a chip package routing that extends over the second region of the second layer.

14. 14. The system of claim 13, wherein a second portion of the parallel memory interface routing is above the first layer.

15. 15. The system of claim 12, wherein the second routing is a portion of an HSIO serial interface routing or a chip package routing that extends over the first region of the second layer.

16. 16. The system of claim 15, wherein the HSIO serial interface routing is a first HSIO serial interface routing and a second HSIO serial interface routing is on a third region of the second layer.

17. 17. The system of claim 12, wherein the second layer comprises a third region, the third region comprising a third material having a third dielectric constant that is substantially different from the second dielectric constant.

18. 18. The system of claim 12, further comprising a third layer, the third layer having a fourth region and a fifth region adjacent to the fourth region, the fourth region comprising a fourth material having the first dielectric constant, and the fifth region comprising a fifth material having the second dielectric constant.

19. receiving a PCB layer stack including a core, the core having a first dielectric layer consisting essentially of a first dielectric material, the first dielectric material having a first dielectric constant, a first conductive layer on a first side of the first dielectric layer, and a second conductive layer on an opposing second side of the first dielectric layer; patterning the first conductive layer to form high speed interface routing, the high speed interface routing having high speed input / output (HSIO) interface routing and high speed parallel interface routing; laminating a first prepreg sheet having the first dielectric material and having one or more openings on the first conductive layer; riveting a second prepreg sheet having a second dielectric constant substantially different from the first dielectric constant into the one or more openings in the first prepreg sheet; 1. A method for making a printed circuit board (PCB), comprising:

20. 20. The method of claim 19, wherein laminating the first prepreg sheet onto the first conductive layer comprises aligning the one or more openings over the HSIO interface routing.

21. 21. The method of claim 19, wherein riveting the second prepreg sheet into the one or more openings comprises driving a plurality of rivets along a peripheral area of ​​the second prepreg sheet to fasten the second prepreg sheet to the core.

22. 22. The method of any one of claims 19 to 21, further comprising riveting a third prepreg sheet into the one or more openings, wherein riveting the third prepreg sheet comprises driving a plurality of rivets along a peripheral area of ​​the third prepreg sheet to fasten the third prepreg sheet to the core.

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