Contextual formation of jb diode and schottky diode in MPS device based on silicon carbide and MPS device

Abstract

To provide a SiC-based electronic device, and a method of manufacturing an electronic device.SOLUTION: A merged-PiN-Schottky, MPS, device 50 includes: a solid body (a drift layer 52, a substrate 53) having a first electrical conductivity N; a doped region 59 extending into the solid body while facing a front side 52a of the drift layer 52, and having a second electrical conductivity P opposite to the first electrical conductivity N; and a semiconductor layer 61 extending on the front side 52a of the drift layer 52 and comprising a material of a transition metal dichalcogenide, TMD. A region 61' of the semiconductor layer (61) has the P-type electrical conductivity and extends in electrical contact with the doped region 59, and a region 61" of the semiconductor layer 61 has the N-type electrical conductivity and extends adjacent to the region 61' having the P-type electrical conductivity and in electrical contact with a respective portion of the front side 52a of the drift layer 52.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for fabricating MPS (Merged PiN Schottky) devices, and is particularly directed to SiC-based devices. [Background technology]

[0002] As is well known, a wide band gap, particularly a band gap energy value Eg greater than 1.1 eV, a low on-state resistance (R ON Semiconductor materials with high thermal conductivity, high operating frequencies, and high saturation velocities of charge carriers are ideal for fabricating electronic components such as diodes or transistors, especially for power applications. A material designated to have the above properties and to be used for fabricating electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC), is favored over silicon with respect to the properties previously listed.

[0003] Compared with similar devices implemented on silicon substrates, electronic devices implemented on silicon carbide substrates have many advantages, such as low output resistance in conduction, low leakage current, high operating temperature, and high operating frequency. In particular, SiC Schottky diodes have shown higher switching performance, making SiC electronic devices particularly desirable for high-frequency applications. Current applications impose requirements on the electrical characteristics and long-term reliability of the devices.

[0004] FIG. 1 shows an MPS device 1 of known type in cross section in a Cartesian (three-axis) reference system of the X, Y and Z axes.

[0005] The MPS device 1 comprises a substrate 3 made of N-type SiC with a first dopant concentration, a surface 3a opposite to a surface 3b, and a thickness equal to about 350 μm, a drift layer 2 (epitaxially grown) made of N-type SiC with a second dopant concentration lower than the first dopant concentration, extending on the surface 3a of the substrate 3 and having a thickness in the range of 5-10 μm, and an ohmic contact region 6 (e.g. made of nickel silicide) extending on the surface 3b of the substrate 3. a cathode metallization 16 extending over the ohmic contact region 6; an anode metallization 8 extending over the upper surface 2 a of the drift layer 2; a plurality of junction barrier (JB) elements 9 in the drift layer 2 facing the upper surface 2 a of the drift layer 2, each including a respective implanted region 9′ of P type and an ohmic contact 9″ of metallic material; and an optional end termination region or guard ring 10, which is in particular an implanted region of P type completely surrounding the junction barrier (JB) element 9.

[0006] A Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8. In particular, a Schottky (semiconductor-metal) junction is formed by respective portions of the drift layer 2 in direct electrical contact with respective portions of the anode metallization 8.

[0007] The region of the MPS device 1 that includes the JB element 9 and the Schottky diode 12 (ie, the region contained within the guard ring 10 ) is the active area 4 of the MPS device 1 .

[0008] 2A and 2B, the manufacturing steps of the MPS device 1 of FIG. 1 include a masked implantation step of doping species (e.g., boron or aluminum) having a second conductivity type (P) (FIG. 2A). The implant is indicated by arrow 18 in FIG. 2A. A mask 11 is used for the implantation, which is in particular a silicon oxide or TEOS hard mask. Thus, implanted region 9′ and end termination region 10 are formed. Next, referring to FIG. 2B, a thermal annealing step is performed to remove mask 11 and activate the doping species implanted in the step of FIG. 2A. The thermal annealing is performed, for example, at a temperature higher than 1600° C. (e.g., in the range of 1700-1900° C., and in some cases even higher).

[0009] 3A-3C, further steps are performed to form ohmic contacts 9″. Referring to FIG. 3A, a deposition mask 13 made of silicon oxide or TEOS is formed to cover the surface areas of drift layer 2 (and, if present, end terminations 10) other than implanted regions 9′. That is, mask 13 has through openings 13a in implanted regions 9′ (and optionally in at least part of end terminations 10). Referring to FIG. 3B, a nickel deposition is then performed on mask 13 and inside through openings 13a (metal layer 14 in FIG. 3B). The nickel so deposited reaches and contacts implanted regions 9′ and end terminations 10 through through openings 13a.

[0010] Referring to FIG. 3C, a subsequent thermal annealing at high temperature (rapid thermal processing in the range of 900° C.-1050° C. for a time interval of 1 minute to 120 minutes) makes it possible to form ohmic contacts 9″ made of nickel silicide by chemical reaction between the deposited nickel and the silicon of the drift layer 2 in the through openings 13 a. In fact, the deposited nickel reacts at the points of contact with the surface material of the drift layer 2 to form Ni2Si (i.e. ohmic contacts). Then, steps of removal of the metal extending on the mask 13 and removal of the mask 13 are carried out.

[0011] The inventors have verified that, as shown exemplarily in FIG. 4, a limited reaction still occurs between the nickel of metal layer 14 and mask 13 where they are in direct contact. FIG. 4 is a plan view in the XY plane of a portion of the device of FIG. 3B, particularly the area bounded by the dotted line and identified with reference numeral 15 in FIG. 3B. FIG. 4 relates to an intermediate manufacturing step between FIGS. 3B and 3C, i.e., mask 13 is still present, but nickel layer 14 has been removed. As can be seen in FIG. 4, irregular regions, or islands 17, extend above mask 13, resulting from an undesired reaction between the nickel and silicon of mask 13. The inventors have further discovered that similar depressions or jagged regions extend below mask 13, i.e., on surface 2a of drift layer 2. In FIG. 4, these depressions or jagged regions are identified with reference numeral 16 and are made of a conductive material (including nickel). If the extent of these depressions or jagged regions 16 in the XY plane, especially along X, is greater than the corresponding extent of the implanted region 9', a short circuit may occur, resulting in device failure. In particular, if an undesired conductive region extends into a zone dedicated to the Schottky contact, an ohmic or quasi-ohmic contact (a low-barrier Schottky contact) will be formed on the N-type zone (which is, from an electrical point of view, resistive), and therefore a continuous current flow will occur in both forward and reverse bias, resulting in the loss of diode properties. [Prior art documents] [Non-patent literature]

[0012] [Non-Patent Document 1] Driss Mouloua et al., "Recent Progress in the Synthesis of MoS2 Thin Films for Sensing, Photovolatic and Plasmonic Applications: A Review," Materials 2021, 14, 3283 [Non-patent document 2] Matteo Bosi, "Growth and synthesis of mono and few-layers transition metal dichalcogenides by vapor techniques: a review," RSC adv., 2015, 5, 75500 [Non-patent document 3] Islam, MR et.al., "Tuning the Electrical Property via Defect Engineering of Single Layer MoS2 by Oxygen Plasma," Nanoscale 2014, 6, 10033-10039 [Non-patent document 4] Khondaker, SI et. al., "Bandgap Engineering of MoS2 Flakes via Oxygen Plasma: A Layer Dependent Study," J. Phys. Chem. C 2016, 120, 13801-13806 Summary of the Invention [Problem to be solved by the invention]

[0013] SUMMARY OF THE INVENTION It is an object of the present invention to provide an electronic device and a method for manufacturing an electronic device that overcomes the drawbacks of the prior art. [Means for solving the problem]

[0014] According to the present invention there is provided an electronic device and a method for manufacturing an electronic device as defined in the claims.

[0015] In order that the invention may be better understood, preferred embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view of an MPS device according to a known embodiment. [Figure 2A] 2A-2C are cross-sectional views illustrating intermediate manufacturing steps of the MPS device of FIG. 1 according to the prior art. [Figure 2B] 2A-2C are cross-sectional views illustrating intermediate manufacturing steps of the MPS device of FIG. 1 according to the prior art. [Figure 3A] 2C is a cross-sectional view of a step of forming an ohmic contact in the MPS device of FIG. 1 after the steps of FIGS. 2A and 2B according to the prior art. [Figure 3B] 2C is a cross-sectional view of a step of forming an ohmic contact in the MPS device of FIG. 1 after the steps of FIGS. 2A and 2B according to the prior art. [Figure 3C] 2C is a cross-sectional view of a step of forming an ohmic contact in the MPS device of FIG. 1 after the steps of FIGS. 2A and 2B according to the prior art. [Figure 4] 3A-3C according to the prior art. [Figure 5] 1 is a cross-sectional view of an MPS device according to one embodiment of the present invention. [Figure 6A] 6A-6C are cross-sectional views illustrating steps in fabricating the MPS device of FIG. 5 in accordance with the present invention. [Figure 6B] 6A-6C are cross-sectional views illustrating steps in fabricating the MPS device of FIG. 5 in accordance with the present invention. [Figure 6C] 6A-6C are cross-sectional views illustrating steps in fabricating the MPS device of FIG. 5 in accordance with the present invention. [Figure 6D] 6A-6C are cross-sectional views illustrating steps in fabricating the MPS device of FIG. 5 in accordance with the present invention. [Figure 7A] 6D is a schematic diagram illustrating steps for forming a MoS2 semiconductor layer that can be used in the context of the fabrication steps of FIG. 6D. [Figure 7B] 6D is a schematic diagram illustrating steps for forming a MoS2 semiconductor layer that can be used in the context of the fabrication steps of FIG. 6D. [Figure 7C] 6D is a schematic diagram illustrating steps for forming a MoS2 semiconductor layer that can be used in the context of the fabrication steps of FIG. 6D. [Figure 7D] 6D is a schematic diagram illustrating steps for forming a MoS2 semiconductor layer that can be used in the context of the fabrication steps of FIG. 6D. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present invention will be described with reference to SiC-based merged PiN Schottky (MPS) devices, but as will become apparent from the following description, the invention is generally applicable to MPS devices based on different types of semiconductors, particularly GaN.

[0018] FIG. 5 shows a merged PiN Schottky (MPS) device 50 according to one aspect of the present invention in cross section in a Cartesian (three-axis) reference system consisting of axes X, Y, and Z.

[0019] The MPS device 50 comprises a substrate made of N-type SiC (in particular 4H-SiC) having a surface 53a opposite to a surface 53b, a thickness in the range of 50 μm-350 μm, more particularly in the range of 160 μm-200 μm, for example equal to 180 μm, and a first N+ dopant concentration. Alternatively, the substrate 53 can be made of GaN.

[0020] A (epitaxially grown) drift layer 52 made of N-type SiC (alternatively, GaN) having a second N-dopant concentration lower than the first dopant concentration extends over a surface 53a of the substrate 53 and has a thickness in the range of 5-15 μm. Regions or layers of ohmic contacts 56 (made, for example, of nickel silicide) extend over a surface 53b of the substrate 53. A bottom metallization 57 made, for example, of Ti / NiV / Ag or Ti / NiV / Au extends over the regions of the ohmic contacts 56.

[0021] One or more P-type doped regions 59 (hereinafter referred to as "junction barrier elements" or "JB elements") extend into the drift layer 52 facing the upper surface 52a of the drift layer 52. Two JB regions 59 are illustrated in this figure by way of non-limiting example. Each JB element 59 is a P-type, specifically P+, implanted region, as previously described. Each JB element may have a doping density of, for example, 1×10 18 atoms / cm 3 It has a higher dopant concentration than

[0022] An end termination region, or guard ring, 60 (optional), is specifically a P-type (P+) implanted region that externally defines the active area of ​​the device.

[0023] According to one aspect of the invention, a semiconductor layer 61, for example made of MoS2 (molybdenum sulfide, also known as molybdenite or molybdenum disulfide), extends over the top surface 52a of drift layer 52. Semiconductor layer 61 is in electrical contact with both JB element 59 (i.e., in direct contact with the P+ implanted region) and with a portion of top surface 52a of N-type drift layer 52 lateral to JB element 59.

[0024] Typically, layer 61 is made of a material related to the group of transition metal chalcogenides (particularly nickel-chalcogenides) (TMDs) that possess semiconducting properties. TMDs are materials with the formula MX2, where M is a transition metal from Groups 4-10 (e.g., Mo, W, Nb, Ta, etc.) and X is a chalcogen (e.g., S, Se, Te). A non-limiting list includes MoSe2, MoTe2, WS2, WSe2, WTe2, and NbS2, in addition to the aforementioned MoS2. These materials have a typical layered structure, i.e., formed by stacking different crystalline layers bonded to each other by weak van der Waals bonds. Each crystalline layer is formed by a transition metal atom bonded to a chalcogen atom according to the formula MX2 by a strong covalent bond. The symmetry of a single layer is hexagonal or rhombohedral, with the atoms coordinated in an octahedral or trigonal columnar arrangement. A special property of thin films of semiconducting TMDs such as MoS2 is that the width of the bandgap and work function depend on the thickness (i.e., number of layers) of the stack. For example, a thin film consisting of a single MoS2 layer (having a thickness of 0.65 nm) has a "direct" bandgap of 1.8-1.9 eV, while a layer consisting of two or more MoS2 layers has an "indirect" bandgap of 1.2 eV.

[0025] Furthermore, according to a further aspect of the invention, the material of the semiconductor layer 61 is selected as a function of the materials of the substrate 53 and the epitaxial layer 52. In particular, the material of the semiconductor layer 61 is such that it exhibits a good lattice match with the material of the epitaxial layer 52. For example, the inventors have found that the use of MoS2 on a SiC or GaN substrate or epitaxial layer satisfies this condition.

[0026] An upper metallization 63 extends over and is in electrical contact with the semiconductor layer 61 (particularly, is in direct electrical contact with the semiconductor layer 61).

[0027] A passivation layer 69 extends over and at least partially protects the top metallization 63. The passivation layer 69 has at least one opening therethrough exposing the top metallization 63 and is in electrical contact with the top metallization 63 (e.g., via wire bonding or other techniques) to bias the device during use.

[0028] According to one aspect of the invention, semiconductor layer 61 is selectively doped to selectively modify its conductivity to form ohmic contacts at each JB element 59 and at the Schottky contacts lateral to the JB elements 59 (i.e., at the surface regions of N-type drift layer 52). In this regard, semiconductor layer 61 has a region 61' having P-type conductivity at each JB element 59 and a region 61" having N-type conductivity at the surface portion of drift layer 52 having N-type conductivity (the latter forming respective Schottky diodes 62).

[0029] Along the X-axis, the regions 61' and the regions 61" alternate with each other. Furthermore, along the X-axis, each region 61' is adjacent to at least one respective region 61".

[0030] Each P-type region 61' extends vertically (i.e., along the Z-axis) through the thickness of semiconductor layer 61 to be in electrical contact with and be vertically aligned (at least partially) with a respective JB element. Similarly, each region 61" extends vertically (i.e., along the Z-axis) through the thickness of semiconductor layer 61 to be in electrical contact with a respective surface region of N-type layer 52.

[0031] Each region 61', together with the respective JB element with which it is in electrical contact, forms a respective junction barrier diode 58; similarly, each region 61", together with the respective surface portion of layer 52 with which it is in electrical contact, forms a respective Schottky diode 62.

[0032] The region of MPS device 50 containing JB diode 58 and Schottky diode 62 (ie, the region enclosed within guard ring 60) is the active area of ​​MPS device 50.

[0033] The inventors have found that the work function of MoS2 material can be changed, modified, or adjusted through appropriate functionalization of MoS2, particularly functionalization to modify the conductivity (N-type or P-type) of MoS2. Furthermore, alternatively or additionally to the above, the work function of MoS2 material can be changed, modified, or adjusted by selecting an appropriate number of stacked MoS2 layers. For example, in the context of the present invention, the "semiconductor layer 61" can be a single MoS2 layer (i.e., one layer having a two-dimensional structure) or a MoS2 multi-layer (i.e., having a three-dimensional structure).

[0034] For example, the work function of a MoS2 multilayer can be tuned (e.g., between 4.4 eV and 5.6 eV) through appropriate doping with oxygen (O2) to produce P-type conductivity in a single doped region.

[0035] As a further example, the work function of a single MoS2 layer can be tuned (e.g., between 4.1 eV and 6 eV) through appropriate doping via oxygen (O2) to generate P-type conductivity in a single doped region.

[0036] In the context of the present invention, the term "semiconductor layer 61" encompasses both multi-layers and single layers.

[0037] By selectively varying the conductivity of the MoS2 layer 61 and / or the number of sub-layers (multi-layer or single layer) that make it up, it is possible to modify the potential barrier of the MoS2 layer 61.

[0038] For example, for N-type doped MoS2 forming a Schottky contact with an N-type 4H-SiC substrate, the barrier height is about 1.3 eV for multilayers and about 1 eV for single layers.

[0039] For example, for P-type doped MoS2 forming ohmic contact with a P+ implanted region in an N-type 4H—SiC substrate, the barrier height is about 0.6 eV for multilayers and about 0.2 eV for single layers.

[0040] The steps for fabricating MPS device 50 are described with reference to Figures 6A-6D.

[0041] 6A, a wafer 100 is positioned that includes a substrate 53 of SiC (specifically, 4H-SiC, although other prototypes may be used). As previously mentioned, other materials may also be used, such as GaN.

[0042] The substrate 53 has a first conductivity type (in this example, an N-type dopant) and has a front surface 53a and a rear surface 53b that are opposite each other along the Z axis. The substrate 53 has a thickness of, for example, 1×10 19 -1×10 20 atoms / cm 3 The N+ dopant concentration is in the range of

[0043] The front of wafer 100 corresponds to front surface 53a, and the back of wafer 100 corresponds to back surface 53b.

[0044] It has an electrical conductivity N that is lower than that of the substrate 53, e.g., 1×10 14 -5×10 16 atoms / cm 3 A drift layer 52 made of silicon carbide having an N-dopant concentration in the range of is formed, for example by epitaxial growth, on a front surface 53a of a substrate 53. Drift layer 52 is composed of SiC, specifically 4H—SiC, although other SiC polytypes, or alternatively, GaN, could also be used.

[0045] The drift layer 52 extends through its thickness between a top side 52a and a bottom side 52b (the latter in direct contact with the front surface 53a of the substrate 53).

[0046] 6B, a hard mask 70 is then formed on the top side 52a of the drift layer 52, for example by depositing photoresist, or TEOS, or other material suitable for that purpose. The hard mask 70 has a thickness in the range of 0.5 μm-2 μm, or any thickness that will block the implants described below with reference to FIG. 6B. The hard mask 70 extends into the region of the wafer 100 where the active areas 54 of the MPS devices 50 will be formed in a later step.

[0047] In plan view, in the XY plane, hard mask 70 covers the region of top side 52 a of drift layer 52 that will form Schottky cell (diode 62), and leaves exposed the region of top side 52 a of drift layer 52 that will form implanted region 59, already described with reference to FIG. 5 .

[0048] Then, using the hard mask 70, a step is carried out in which a doping species (e.g., boron or aluminum) having a second type of conductivity (in this case P) is implanted (the implant is indicated in the figure by arrows 72). During the step of Figure 6B, the guard ring 60, if present, is also formed.

[0049] In an exemplary embodiment, the implantation step of FIG. 6B is performed using 1×10 18 atoms / cm 3 To form implanted region 59 with a dopant concentration greater than 1×10 12 atoms / cm 2 -1×10 15 atoms / cm 2 The implanted region includes one or more implants of a doping species having a second conductivity type at a dose in the range of 0.4 μm-1 μm and at an implant energy in the range of 30 keV-400 keV, thereby forming an implanted region having a depth measured from the surface 52 a in the range of 0.4 μm-1 μm.

[0050] Thereafter, referring to FIG. 6C, the mask 70 is removed, and referring to FIG. 6D, the semiconductor layer 61 made of, for example, MoS2 is formed.

[0051] The processes for forming the semiconductor layer 61 that can be used in the context of the present invention are known per se in the prior art.

[0052] See, for example, Driss Mouloua et al., "Recent Progress in the Synthesis of MoS2 Thin Films for Sensing, Photovolatic and Plasmonic Applications: A Review," Materials 2021, 14, 3283.

[0053] See also Matteo Bosi, "Growth and synthesis of mono and few-layers transition metal dichalcogenides by vapor techniques: a review," RSC adv., 2015, 5, 75500.

[0054] An exemplary process for forming semiconductor layer 61 by CVD ("Chemical Vapor Deposition") deposition of MoS2 on epitaxial layer 52, which in this example is SiC, is described below. This process is described with reference to Figures 7A-7C, which illustrate a schematic of a dual-zone reactor 90 containing a quartz cylindrical body and formed by two regions 90a, 90b that can be heated independently of each other.

[0055] Referring to FIG. 7A, sulfur (S) and molybdenum (Mo, or MoO x , for example x=3) is used as a precursor for growing MoS2. A sulfur precursor (particularly in powder form) is placed in a region 90a in a crucible 92 at a distance (about 7-15 cm) from the location on the wafer where MoS2 growth is to occur. A molybdenum precursor (also particularly in powder form) is placed in each crucible 93 in a region 90b adjacent to the wafer 100 where MoS2 growth is to occur (i.e., the region 90b between the wafer 100 and the sulfur crucible).

[0056] 7B, region 90a is heated to a temperature T1 in the range of 100-200° C. (specifically, in the range of 150-160° C.) to evaporate sulfur and deposit it on wafer 100. Region 90b is heated to a temperature T2 in the range of 700-800° C., which is higher than temperature T1, to evaporate molybdenum and deposit it on wafer 100.

[0057] This process is carried out in the presence of a carrier gas introduced into reactor 90 in the direction indicated by arrow 91 in Figures 7A-7C. The gas, for example, argon (Ar), is introduced at about 100 sccm. The direction of the gas pushes sulfur and molybdenum vapors toward wafer 100.

[0058] Referring to FIG. 7C, at the level of the wafer 100, sulfur and molybdenum are deposited thereon to form a MoS2 layer 61 by chemical reaction.

[0059] The number of MoS2 sublayers (single or multiple) formed on the wafer 100 during the reaction between sulfur vapor and molybdenum vapor can be controlled by adjusting one or more of the temperature T2, the duration of the growth process, and the flow of sulfur vapor (by adjusting the flow of the carrier gas).

[0060] Alternatively, it is possible to deposit a MoS2 multilayer and then selectively remove one or more layers through etching techniques of a type known per se, up to reducing this multilayer to a single layer.

[0061] Other relative arrangements of the crucibles 92, 93 and the wafer 100 within the reactor 90 are also possible. For example, with reference to Figure 7D, the crucible 93 can be positioned below the wafer 100. In this case, the wafer 100 is oriented with its top surface (on which the layer 61 is to be formed) facing the crucible 93.

[0062] Other techniques or methods may also be used in the context of the present invention for forming the semiconductor layer 61. Such methods (known in the literature) are both bottom-up and top-down and include atomic layer deposition (ALD), pulsed laser deposition (PLD), and sputtering.

[0063] The semiconductor layer 61 so formed exhibits N-type conductivity in the absence of further doping, and it is still possible if the concentration of the majority conductive species is to be further adjusted.

[0064] 6D, a mask 80 (e.g., made of photoresist) having openings 80a in areas of the semiconductor layer 61 that need to be functionalized to modify its conductivity is formed on the semiconductor layer 61. Surface areas 61a of the semiconductor layer 61 are exposed in the photoresist through the openings 80a. These openings 80a are at least partially aligned with the respective JB elements 59 (along the Z axis, or in plan view in the XY plane).

[0065] The wafer 100 provided with the mask 80 is placed in a reactor in which an oxygen plasma is generated for functionalization of the semiconductor layer 61. The oxygen reacts with the material of the semiconductor layer 61 exposed through the openings 80a to provide selective P-type doping. Doped regions 61' (of P-type) have been described with reference to FIG. 5 and, for the purposes of the context, regions 61" (of N-type) are formed.

[0066] The functionalization of MoS2 to form the P-type region 61' can be performed, for example, via plasma treatment, using various chemical species (O2, CHF3, CF4, and SF6), which are known per se. See, for example, Islam, MR et al., "Tuning the Electrical Property via Defect Engineering of Single Layer MoS2 by Oxygen Plasma," Nanoscale 2014, 6, 10033-10039. See also Khondaker, SI et al., "Bandgap Engineering of MoS2 Flakes via Oxygen Plasma: A Layer Dependent Study," J. Phys. Chem. C 2016, 120, 13801-13806.

[0067] The electrical conductivity of the regions 61″ of the semiconductor layer 61 covered by the mask 80 is not altered by the O mediated functionalization step, and these regions therefore maintain their N-type conductivity.

[0068] The mask 80 is then removed.

[0069] The manufacturing steps then proceed in a manner not shown in the figures, with the formation of top metallization and passivation layers in a manner known per se, which will not be further described or illustrated. The formation of ohmic contacts and bottom metallization on the back side of the wafer is also known per se and will therefore not be further described.

[0070] The advantages of the present invention are apparent upon review of the features of the present invention provided in accordance with this disclosure.

[0071] In particular, the "IFSM robustness" value of the SiCMPS diode is maximized, the manufacturing flow is simplified, and the problems described for the prior art regarding bumps or nickel residue are avoided or eliminated.

[0072] Finally, it will be apparent that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the present invention as defined in the claims.

Claims

1. A method for fabricating a combined PiN Schottky MPS device (50), comprising: performing an implantation at a front side (52 a) of a solid body (52, 53) having a first electrical conductivity (N), the doping species having a second electrical conductivity (P) opposite the first electrical conductivity (N), thus forming an implanted region (59) extending from the front side (52 a) into the solid body; forming a semiconductor layer (61) on the front side (52a) made of a material that is a transition metal nichalcogenide (TMD) having the first electrical conductivity (N); Selectively functionalizing the first region (61') of the semiconductor layer (61) via chemical species to generate the second electrical conductivity type (P) in the first region (61'). It has The first region is in electrical contact with the implanted region (59) and is adjacent to a second region of the semiconductor layer (61) having the first electrical conductivity (N) in electrical contact with a respective surface portion of the front side (52a) having the first electrical conductivity (N).

2. 2. The method of claim 1, wherein the first region (61') extends through the thickness of the semiconductor layer (61) and reaches at least partially to the front side (52a) of the solid body (52, 53) in the implanted region (59).

3. 3. The method of claim 1, wherein the functionalizing of the first region (61') comprises forming an ohmic contact at the interface between the solid body (52, 53) and the implanted region (59).

4. 4. The method of claim 3, wherein forming the ohmic contact comprises forming a junction barrier JB diode.

5. 2. The method of claim 1, wherein the step of forming the semiconductor layer (61) includes forming a Schottky diode at an interface between the second region (61") and the solid body beside the implanted region (59).

6. The material of the solid body (52, 53) is SiC, 4H-SiC, GaN, AlN, diamond, Ga ２ O ３ 2. The method of claim 1, wherein the method is one of:

7. The semiconductor material (61) is MoS ２ , MoSe ２ , MoTe ２ , W.S. ２ , WSe2, WTe ２ 2. The method of claim 1, wherein the method is one of:

8. forming a first electrical terminal common to the JB diode and the Schottky diode including a first metal layer on the semiconductor layer (61); forming a second electrical terminal (57) common to the JB diode and the Schottky diode including a second metal layer on a rear side (53b) of the solid body opposite the front side (52a); 10. The method of claim 1 further comprising:

9. placing a substrate (53); epitaxially growing an epitaxial layer (52) on the substrate (53) that forms a drift layer of the MPS device (50); 2. The method of claim 1, further comprising: forming a first epitaxial layer on the substrate; and forming the first epitaxial layer on the substrate.

10. 2. The method of claim 1, wherein the step of forming the semiconductor layer (61) comprises performing a CVD growth process, or an ALD process, or a sputtering process, or a PLD process.

11. The first electrical conductivity is N-type, the second electrical conductivity is P-type, and the step of functionalizing the first region (61') is ２ 2. The method of claim 1, further comprising doping the first region (61') via:

12. In a combined PiN Schottky MPS device (50), a solid body (52, 53) having a first electrical conductivity (N); an injection region (59) facing the front side (52a) of the solid body (52, 53) and extending into the solid body (52, 53), the injection region (59) having a second electrical conductivity (P) opposite to the first electrical conductivity (N); a semiconductor layer (61) extending on said front side (52a) made of a material that is a transition metal nichalcogenide (TMD); It has a first region (61') of the semiconductor layer (61) having the second electrical conductivity (P) and extending in electrical contact with the implanted region (59), and a second region (61'') of the semiconductor layer (61) having the first electrical conductivity (N) and extending adjacent to the first region (61') and in electrical contact with respective surface portions of the front side (52a) having the first electrical conductivity (N).

13. 13. The device according to claim 12, wherein the first region (61') extends through the thickness of the semiconductor layer (61) and reaches at least partially to the front side (52a) of the solid body (52, 53) in the implantation region (59).

14. A device according to claim 12 or 13, wherein the first region (61') forms an ohmic contact with the implanted region (59).

15. 15. The device of claim 14, wherein in the first region (61'), the semiconductor layer (61) forms a junction barrier JB diode with the implanted region (59).

16. 13. The device according to claim 12, wherein in the second region (61"), the semiconductor layer (61) forms a Schottky diode together with the solid body (52, 53).

17. The material of the solid body (52, 53) is SiC, 4H—SiC, GaN, AlN, diamond, Ga ２ O ３ 13. The device of claim 12, wherein the device is one of:

18. The material of the semiconductor layer (61) is MoS ２ , MoSe ２ , MoTe ２ , W.S. ２ , WSe ２ , WTe ２ 13. The device of claim 12, wherein the device is any one of the following:

19. a first electrical terminal common to the JB diode and the Schottky diode, the first electrical terminal comprising a first metal layer on the semiconductor layer (61); a second electrical terminal (57) common to the JB diode and the Schottky diode and including a second metal layer on the rear side (52b) of the solid body opposite the front side (52a); 13. The apparatus of claim 12, further comprising:

20. 13. The device of claim 12, wherein the solid body comprises a substrate (53) and an epitaxial layer (52) on the substrate (53), the epitaxial layer (52) being a drift layer of the MPS device (50).

21. 13. The device of claim 12, wherein the first electrical conductivity is N-type and the second electrical conductivity is P-type.

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