Semiconductor element and method of manufacturing the same

Abstract

To provide a semiconductor element and a method of manufacturing the same.SOLUTION: A semiconductor device includes a semiconductor stack, a protective layer on the semiconductor stack and having a topmost surface, an electrode on the semiconductor stack and electrically connected to the semiconductor stack, and a conductive bump on the electrode and having an outermost surface protruding outward, a topmost point and a maximum width. The thickness of the conductive bump is measured from the topmost point to the topmost surface. The ratio of the thickness to the maximum width is between 0.1 and 0.4.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a light emitting device, and more particularly to a structure of a light emitting device having conductive bumps and a manufacturing method thereof. [Background technology]

[0002] Light-emitting diodes (LEDs) are widely used in the fields of lighting and displays due to their low energy consumption, long life, small volume, fast response, and stable light output.

[0003] With the continuous evolution of LED technology, the brightness of LED die will be continuously improved, and the size of LED die will be gradually reduced, for example, to smaller than 100μm, 50μm, or even 30μm. The applications of LED die are not limited to general lighting and LCD screen backlights. LED die directly used as pixels in LED displays may become a trend in next-generation displays.

[0004] A single LED display requires millions to tens of millions of LED dies, and handling such a large number of LED dies requires high-speed, accurate alignment and reliable die-attach technology. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a structure of a light emitting device having conductive bumps and a method for manufacturing the same. [Means for solving the problem]

[0006] A semiconductor device is provided, which includes a semiconductor stack layer, a protective layer located on the semiconductor stack layer, an electrode located on the semiconductor stack layer and electrically connected to the semiconductor stack layer, and a conductive bump located on the electrode, wherein the distance from the top of the conductive bump to the uppermost surface of the protective layer is defined as the thickness of the conductive bump, and the ratio of the thickness of the conductive bump to the maximum width of the conductive bump is 0.1 to 0.4.

[0007] A method for manufacturing a semiconductor device is provided, which includes: providing a substrate; forming semiconductor stack layers on the substrate; forming electrodes on the semiconductor stack layers; forming bond pads on the electrodes; forming an adhesive on the bond pads; providing laser energy to irradiate the bond pads and the adhesive, so that the bond pads form conductive bumps after fusing, the conductive bumps being located on the electrodes and the adhesive covering the conductive bumps; and cleaning the adhesive. [Brief explanation of the drawings]

[0008] [Figure 1A] FIG. 2 is a top view of a semiconductor element array according to an embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view taken along line AA' in FIG. 1A. [Figure 1C] FIG. 10 is a top view of a semiconductor element array according to another embodiment of the present invention. [Figure 1D] FIG. 1D is a cross-sectional view taken along line AA' in FIG. 1C. [Figure 1E] FIG. 10 is a cross-sectional view of a semiconductor element array according to another embodiment of the present invention. [Figure 2A] 1 is a three-dimensional view of a semiconductor device according to an embodiment of the present invention; [Figure 2B] 2B is a cross-sectional view of the semiconductor element shown in FIG. 2A taken along line BB'. [Figure 2C] FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. [Figure 2D] FIG. 10 is a three-dimensional view of a semiconductor device according to another embodiment of the present invention. [Figure 2E] FIG. 2E is a cross-sectional view of the semiconductor element taken along line BB′ in FIG. 2D. [Figure 3A] 1 is a top view of a semiconductor device according to an embodiment of the present invention; [Figure 3B] 3B is a cross-sectional view of the semiconductor element taken along line CC' in FIG. 3A. [Figure 3C] 3B is a cross-sectional view of the semiconductor element taken along line DD' in FIG. 3A. [Figure 4A] FIG. 2 is a cross-sectional view of a semiconductor element array 2000 according to an embodiment of the present invention. [Figure 4B] 4B is a cross-sectional view of the semiconductor element array shown in FIG. 4A after one semiconductor element has been removed. [Figure 4C] 4B is a top view of the semiconductor element array shown in FIG. 4A after one semiconductor element has been removed. [Figure 4D] FIG. 3 is a cross-sectional view of a semiconductor element array 3000 according to another embodiment of the present invention. [Figure 4E] FIG. 3 is a cross-sectional view of a semiconductor element array 3001 according to another embodiment of the present invention. [Figure 5A] 1 is a flowchart illustrating a method for transferring a semiconductor device according to an embodiment of the present invention. [Figure 5B] 1 is a flowchart illustrating a method for transferring a semiconductor device according to an embodiment of the present invention. [Figure 5C] 1 is a flowchart illustrating a method for transferring a semiconductor device according to an embodiment of the present invention. [Figure 5D] 1 is a flowchart illustrating a method for transferring a semiconductor device according to an embodiment of the present invention. [Figure 6A] 10 is a flowchart for transferring a semiconductor device in another embodiment of the present invention. [Figure 6B] 10 is a flowchart for transferring a semiconductor device in another embodiment of the present invention. [Figure 6C] 10 is a flowchart for transferring a semiconductor device in another embodiment of the present invention. [Figure 7A] 1 is a flowchart for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 7B] 1 is a flowchart for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 7C] 1 is a flowchart for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 7D] 1 is a flowchart for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 8A] 10 is a flowchart for manufacturing a semiconductor device in another embodiment of the present invention. [Figure 8B] 10 is a flowchart for manufacturing a semiconductor device in another embodiment of the present invention. [Figure 8C] 10 is a flowchart for manufacturing a semiconductor device in another embodiment of the present invention. [Figure 8D] 10 is a flowchart for manufacturing a semiconductor device in another embodiment of the present invention. [Figure 9A] FIG. 10 is a three-dimensional view of a semiconductor device according to another embodiment of the present invention. [Figure 9B] 9B is a cross-sectional view of the semiconductor element taken along line BB' in FIG. 9A. [Figure 10A] 1 illustrates a semiconductor device being fixed to a target substrate in one embodiment of the present invention. [Figure 10B] FIG. 10 illustrates a semiconductor device being fixed to a target substrate in another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] 1A is a top view of a semiconductor device array 1000 according to one embodiment of the present invention. The semiconductor device array 1000 includes a plurality of semiconductor devices 1 arranged in an array on a substrate. The semiconductor devices 1 may be semiconductor devices such as light-emitting diodes (LEDs), laser diodes (LDs), transistors, etc. The semiconductor device array 1000 may be composed of semiconductor devices 1 of the same type or different types. The substrate 10 may be a substrate for growing the semiconductor devices 1, or may serve as a carrier (mounting body) for the semiconductor devices 1 after the growth substrate is removed. The substrate 10 may be made of Ge, GaAs, InP, Sapphire, SiC, Si, LiAlO2, ZnO, GaN, AlN, metal, glass, thermal release tape, UV release tape, chemical release tape, heat-resistant tape, blue tape, or tape with a dynamic release layer (DRL). Each semiconductor element 1 has a pair of conductive bumps 2a, 2b on one side facing away from the substrate 10, which are used for electrical and physical connection to an external circuit (e.g., a circuit board, a backplane, etc.). In a top view, the projected shape of the conductive bumps is approximately rectangular, as shown in FIGS. 1A and 3A.

[0011] 1B is a cross-sectional view taken along line A-A' in FIG. 1A. The semiconductor element 1 has a pair of electrodes 3a and 3b on one side away from the substrate 10. The conductive bumps 2a and 2b are disposed directly on the electrodes 3a and 3b, respectively. The upper surfaces of the conductive bumps 2a and 2b are arc-shaped and not parallel to the upper surfaces of the electrodes 3a and 3b.

[0012] The conductive bumps 2a, 2b and the electrodes 3a, 3b are preferably made of different materials. The material of the electrodes includes a metal, such as Au, Ag, Cu, Cr, Al, Pt, Ni, Ti, or an alloy thereof, or a combination of stack layers thereof. The material of the conductive bumps 2a, 2b may include a low-melting-point metal or a low-liquid-melting-point (LIP) alloy, whose melting point or liquidus melting point temperature is lower than 210°C, such as Bi, Sn, In, or an alloy thereof. In one embodiment, the melting point of the low-melting-point metal or the liquidus melting point alloy is lower than 170°C. The low-melting-point alloy material may be a SnIn alloy or a SnBi alloy.

[0013] FIG. 1C is a top view of a semiconductor element array 1001 according to another embodiment of the present invention. The semiconductor element array 1001 includes a plurality of semiconductor elements 1 arranged in a predetermined pattern on a substrate 10. The substrate 10 has a substantially circular outer shape. For information about the material of the substrate, please refer to the description in the relevant paragraph above. FIG. 1D is a cross-sectional view taken along line A-A' in FIG. 1C. An adhesive structure 4 is provided between the semiconductor element 1 and the substrate 10. The semiconductor element 1 is temporarily fixed to the substrate 10 via the adhesive structure 4. The semiconductor element 1 has a pair of electrodes 3a and 3b on one side away from the substrate 10. The conductive bumps 2a and 2b are disposed directly on the electrodes 3a and 3b, respectively. The upper surfaces of the conductive bumps 2a and 2b are arc-shaped and are not completely parallel to the upper surfaces of the electrodes 3a and 3b. The adhesive structure 4 may include a polymer, such as polyimide or benzocyclobutane (BCB). For the materials of the conductive bumps 2a, 2b and electrodes 3a, 3b, please refer to the explanations in the relevant paragraphs above. As shown in FIG. 1D , the outer edge (referred to as the outer edge) 42 of the adhesive structure 4 is approximately aligned with the outermost edge (referred to as the outermost edge) 19 of the semiconductor element 1. The adhesive portion 4 has a thickness H4, which is approximately 2 to 3 μm or 1 to 10 μm. In another embodiment, the outer edge 42 is not aligned with the outermost edge 19 of the semiconductor element 1, and the adhesive structure 4 may be recessed (inwardly contracted) into or protrude from the outermost edge 19 of the semiconductor element 1. The adhesive structure 4 has a maximum width W5, and the semiconductor element 1 has a maximum width W6. W5 is approximately the same as W6. In another embodiment, W5 may be smaller or larger than W6.

[0014] FIG. 1E is a cross-sectional view of a semiconductor element array 1001′ according to another embodiment of the present invention. The semiconductor element array 1001′ includes a plurality of semiconductor elements 1 arranged on a substrate 10 in a predetermined pattern. For information about the material of the substrate, please refer to the explanation in the relevant paragraph above. An adhesive structure 4 is provided between the semiconductor element 1 and the substrate 10. The semiconductor element 1 is temporarily fixed to the substrate 10 via the adhesive structure 4. The semiconductor element 1 has a pair of electrodes 3a and 3b on one side away from the substrate 10. Conductive bumps 2a and 2b are directly disposed on the electrodes 3a and 3b, respectively. For information about the material of the adhesive structure 4 and the structure and material of the conductive bumps 2a and 2b and the electrodes 3a and 3b, please refer to the explanation in the relevant paragraph above. As shown in FIG. 1E, the adhesive structure 4 includes a plateau portion 43 and a continuous portion 44. The continuous portion 44 is a continuous (uninterrupted) structure and is distributed continuously on the substrate 10, passing under all of the semiconductor elements 1 and between two adjacent semiconductor elements 1. Each plateau 43 is located between the semiconductor element 1 and the continuous portion 44, protrudes upward from the continuous portion 44, and corresponds to one semiconductor element 1. The outer edge 42 of the plateau 43 is aligned with or close to the outermost edge 19 of the semiconductor element 1. The adhesive portion 4 has a thickness H4, which is approximately 2 to 3 μm. The continuous portion 44 has a thickness H5, which is greater than 0 μm and less than 1 μm. In another embodiment, the outer edge 42 is not aligned with the outermost edge 19 of the semiconductor element 1, and the plateau 43 may be recessed into or protrude out of the outermost edge 19 of the semiconductor element 1. The plateau 43 has a maximum width W5, and the semiconductor element 1 has a maximum width W6. W5 is approximately equal to W6. In another embodiment, W5 may be smaller or larger than W6.

[0015] FIG. 2A is a three-dimensional view of a semiconductor element 1 according to one embodiment of the present invention. The maximum side length of the semiconductor element 1 is 100 μm or less than 50 μm. For example, the maximum side length of the semiconductor element is approximately 40 μm, and the width is approximately 20 μm. The conductive bumps 2a and 2b have opposite polarities (positive and negative), and the minimum horizontal distance D between them is less than 40 μm. For example, the maximum side length of the semiconductor element is approximately 40 μm, and D is approximately 15 μm. The conductive bumps 2a and 2b completely cover the electrodes (e.g., electrodes 3a and 3b in FIG. 1B) and have arc shapes and protruding apexes 21a and 21b. As shown in FIG. 1A, the apexes 21a and 21b are located approximately at the geometric centers of the conductive bumps 2a and 2b and / or the electrodes.

[0016] 2B is a cross-sectional view of the semiconductor element 1 taken along line BB' in FIG. 2A. The semiconductor element 1 is placed on a substrate 10 and includes a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack layer 14 is an inclined surface and is inclined relative to the substrate 10. The semiconductor stack layer 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. The first semiconductor layer 11 and the second semiconductor layer 13 provide electrons and holes, respectively, so that the electrons and holes can recombine in the active layer 12 to emit light. The first semiconductor layer 11, the active layer 13, and the second semiconductor layer 13 are made of III-V semiconductor materials, such as Al. x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P, where 0≦x, y≦1, (x+y)≦1. Depending on the material of the active layer, the LED die can emit red light with a peak value between 610 nm and 650 nm, green light with a peak value between 530 nm and 570 nm, cyan light with a peak value between 500 nm and 485 nm, blue light with a peak value between 450 nm and 490 nm, violet light with a peak value between 400 nm and 450 nm, or ultraviolet light with a peak value between 280 nm and 400 nm. The maximum thickness of the semiconductor stack layers 14 is about 10 μm or less. In one embodiment, the lower surface 17 of the first semiconductor layer 11 contacts the substrate 10 and is a roughened surface. In another embodiment, the lower surface 17 of the first semiconductor layer 11 is a substantially flat surface (not shown). In another embodiment, the substrate 10 is a growth substrate for epitaxially growing the semiconductor stack layers 14, and the entire upper surface of the substrate 10 facing the semiconductor stack layers 14 is a roughened surface (not shown), for example, a patterned sapphire substrate (PSS). In one embodiment, the semiconductor device 1 includes a carrier (not shown), which is located below the semiconductor stack layers 14 and is used to support the semiconductor stack layers 14. The carrier may be a substrate for epitaxial growth or a non-epitaxial growth of the semiconductor stack layers 14. For information about the material of the carrier, see the description of the relevant paragraph regarding the substrate 10 above. Note that the selection of the material needs to be compatible with theoretical and practical feasibility.

[0017] The semiconductor stack layer 14 has a platform 16, which is used to expose the first semiconductor layer 11 to the outside of the active layer 12 and the second semiconductor layer 13. The protective layer 15 covers the upper surface of the second semiconductor layer 13, the sidewalls of the first semiconductor layer 11, the sidewalls of the active layer 12, the sidewalls of the second semiconductor layer 13, and the upper surface of the first semiconductor layer 11 located within the platform 16. The protective layer 15 may be in direct contact with the substrate 10. In another embodiment, the protective layer 15 does not contact the substrate 10. The protective layer 15 has a first opening 5a within the platform 16 to expose a portion of the first semiconductor stack layer 11. The protective layer 15 has a second opening 5b in the second semiconductor layer 13 to expose a portion of the second semiconductor layer 13. The first electrode 3a is located within the platform 16 and has a portion formed on the protective layer 15, which portion covers the protective layer 15 located within the platform 16 and the portion of the protective layer 15 located outside the platform 16. The first electrode 3a has a first recess 6a formed in the first opening 5a and electrically connected to the first semiconductor layer 11. The first electrode 3a has a stepped profile where it is located on the platform 16. The second electrode 3b has a portion located on the protective layer 15 other than the second opening 5b, and a second recess 6b formed in the second opening 5b and electrically connected to the second semiconductor layer 13.

[0018] The protective layer 15 may be a single layer or a multi-layer structure and has electrical insulating properties. The single layer material may include oxides, nitrides, or polymers. The oxides may be Al2O3, SiO2, TiO2, Ta2O5 (Tantalum Pentoxide), or AlO x The nitride may contain AlN, S i N x The polymer may include polyimide or benzocyclobutane (BCB). The materials of the multilayer structure may include Al2O3, SiO2, TiO2, Nb2O5, SiN x , or a combination of these materials. The multilayer structure may form a Distributed Bragg Reflector (DBR).

[0019] As shown in FIG. 2B , the first conductive bump 2a is formed directly above the first electrode 3a. The first conductive bump 2a can completely or partially fill the first recess 6a of the first electrode 3a, and its outermost surface 22a has a macroscopically smooth, outwardly protruding arc shape. The first conductive bump 2a has an apex 21a, which is the region of the first conductive bump 2a that is furthest from the substrate 10. As shown in FIG. 2B , the outermost surface 22a of the first conductive bump 2a is not parallel to the bottom surface of the first conductive bump 2a or the top surface of the first electrode 3a. The bottom surface 17 of the first semiconductor layer 11 is a roughened surface, and the roughness of the outermost surface 22a of the first conductive bump 2a is less than the roughness of the bottom surface 17 of the first semiconductor layer 11 and less than the roughness of the top surface of the first electrode 3a.

[0020] As shown in FIG. 2B , the second conductive bump 2b directly covers the second electrode 3b. The second conductive bump 2b can completely or partially fill the second recess 6b of the second electrode 3b, and its outermost surface 22b has a macroscopically smooth, outwardly protruding arc shape. The second conductive bump 2b has an apex 21b, which is the region where the second conductive bump 2b is furthest from the substrate 10. As shown in FIG. 2B , the outermost surface 22b of the second conductive bump 2b is not parallel to the bottom surface of the second conductive bump 2b or the top surface of the second electrode 3b. The roughness of the outermost surface 22b of the second conductive bump 2b is less than the roughness of the bottom surface 17 of the first semiconductor layer 11 and is also less than the roughness of the top surface of the second electrode 3b. Preferably, the apex 21a of the first conductive bump 2a and the apex 21b of the second conductive bump 2b are located at approximately the same height, which is advantageous for the semiconductor device 1 to be subsequently stably fixed on the substrate. However, in practice, there may be a difference in height to the extent permitted by the manufacturing process. The bottom surfaces of the first conductive bump 2a and the second conductive bump 2b are typically formed conformally on the first electrode 3a and the second electrode 3b, respectively, and their lowest points are often not at the same height. As shown in FIG. 2B , the first conductive bump 2a has a vertical distance from the top 21a to the top surface 151 of the protective layer 15, which is designated as a first thickness H1. The first conductive bump 2a also has a first (maximum) width W1, where H1 / W1 is between 0.1 and 0.4, preferably between 0.1 and 0.25. The second conductive bump 2b has a vertical distance from the top 21b to the top surface 151 of the protective layer 15, which is designated as a second thickness H2. The second conductive bump 2b also has a second (maximum) width W2, where H2 / W2 is between 0.1 and 0.4, preferably between 0.1 and 0.25. H1 / W1 and H2 / W2 may be the same or different. The second thickness H2 of the second conductive bump 2b is 4 to 6 μm.

[0021] By more densely packing the first recesses 6a of the first electrode 3a with the first conductive bumps 2a and the second recesses 6b of the second electrode 3b with the second conductive bumps 2b, the reliability of the physical and electrical connection between the semiconductor device 1 and the circuit board (not shown) can be improved and the probability of failure (e.g., breakdown) can be reduced. Specifically, if the semiconductor device 1 has the structure shown in FIG. 2B but does not have the conductive bumps 2a / 2b, when the semiconductor device 1 is fixedly connected to the circuit board with solder, the solder between the first electrode 3a and the circuit board (not shown) may form holes near the first recesses 6a, and the solder between the second electrode 3b and the circuit board (not shown) may form holes near the second recesses 6b. These holes can reduce the strength of the fixed connection between the semiconductor device 1 and the circuit board.

[0022] When the conductive bump formation process includes a heat treatment step, under a specific (predetermined) combination of conductive bump and electrode materials, the conductive bumps can have discretely distributed metal particles therein after the heat treatment step, as shown in FIG. 2C. FIG. 2C is a cross-sectional view of a semiconductor device 1 in another embodiment of the present invention. For the structure of FIG. 2C, please refer to FIG. 2B and the related paragraphs. The first conductive bump 2a and the second conductive bump 2b each contain discretely distributed particles 7 of irregular size and shape. The material of the particles 7 is different from that of the conductive bumps 2a and 2b but is the same as that of part of the electrodes 3a and 3b, such as gold, platinum, or an alloy of the aforementioned materials. The shape of the particles 7 can be elongated, polygonal, leaf-like, or droplet-like.

[0023] FIGS. 2D and 2E show a semiconductor device 1' according to another embodiment of the present invention. For its structure, please refer to FIGS. 2A and 2B and the related paragraphs. As shown in FIG. 2D, the conductive bumps 2a and 2b have outwardly protruding arc shapes and apexes 21a and 21b. The apexes 21a and 21b are not at the same height. The apex 21a is slightly lower than the apex 21b. FIG. 2E is a cross-sectional view of the semiconductor device 1' taken along line BB' in FIG. 2D. The conductive bump 2a is located above the platform 16. When the conductive bump 2a is close to the volume of the conductive bump 2b, some of the conductive bump 2a needs to fill the platform 16. Therefore, the apex 21a of the conductive bump 2a is slightly lower than the apex 21b of the conductive bump 2b. In one embodiment, the first thickness H1 of the first conductive bump 2a is 0.4 to 1 μm smaller than the first thickness H1 of the first conductive bump 2a.

[0024] FIG. 3A is a top view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 3B is a cross-sectional view of the semiconductor device 1 taken along line CC' in FIG. 3A. FIG. 3C is a cross-sectional view of the semiconductor device 1 taken along line DD' in FIG. 3A. The semiconductor device 1 includes a semiconductor stack layer 14, an electrode 3, and a conductive bump 2 located on the semiconductor stack layer 14. The conductive bump 2 and the electrode 3 have a substantially rectangular projected shape in FIG. 3A. In a cross-sectional view, the outermost surface 22 of the conductive bump 2 has a macroscopically smooth, outwardly protruding arc shape. As shown in FIG. 3B, the outermost surface 22 contacts the upper surface of the electrode 3, and a tangent to the conductive bump 2 at the contact point forms an included angle θ1 with the upper surface of the electrode 3. The included angle θ1 is close to 90 degrees, preferably 70 degrees < θ1 < 90 degrees. As shown in FIG. 3C, the outermost surface 22 contacts the upper surface of the electrode 3, and a tangent to the conductive bump 2 at the contact point forms an included angle θ2 with the upper surface of the electrode 3. The included angle θ2 is smaller than the included angle θ1, and preferably 30 degrees < θ2 < 70 degrees. In other words, as shown in Figure 3A, the cross-sectional shape of the conductive bump 2 in a direction parallel to the side length of the electrode 3 is different from the cross-sectional shape of the electrode 3 in the diagonal direction.

[0025] FIG. 4A illustrates a semiconductor device array 2000 according to one embodiment of the present invention. The semiconductor device array 2000 includes a plurality of semiconductor devices 1 (for convenience, only three semiconductor devices 1 are shown in one dimension, but the semiconductor device array 2000 may include m*n semiconductor devices 1, where m and n are positive integers greater than or equal to 0 and are not simultaneously 0) and a carrier 30. The semiconductor devices 1 are disposed on the carrier 30 with the conductive bumps 2 facing the carrier 30 (also known as a flip chip). The carrier 30 can support and secure the semiconductor devices 1. The carrier 30 includes a mounting plate 31 and an adhesive layer 32. The mounting plate 31 can be made of a transparent material, such as glass, sapphire, or a polymer material, that can transmit light of a specific wavelength emitted by a light-emitting diode or laser diode. The adhesive layer 32 can include a thermally removable adhesive, a photolabile adhesive, a chemically removable adhesive, a heat-resistant adhesive, blue tape, or tape with a dynamic release layer. In another embodiment, the adhesive layer may include a polymer, such as polyimide or benzocyclobutane (BCB). When the semiconductor device 1 is flip-chip mounted on the carrier 30, the smooth, protruding outermost surface 22 of the conductive bump 2 directly contacts the adhesive layer 32. As shown in FIG. 4A, the conductive bump 2 can be partially recessed into the adhesive layer 32. The recessed portion has a maximum width W3 parallel to the surface of the adhesive layer 32, and the conductive bump 2 itself has a maximum width W4, where W4 > W3. Furthermore, the outermost surface 22 of the conductive bump 2 has a smooth arc shape. The projected area of ​​the recessed portion of the conductive bump 2 in a given projection direction (e.g., the area of ​​the indentation 34 in FIG. 4C) is smaller than the area of ​​the electrode, and the adhesive strength is also relatively low, which is advantageous for the subsequent transfer process of the semiconductor device 1 from the carrier 30 to another location. The transfer process of the semiconductor device 1 will be described later.

[0026] 4B and 4C are side and top views of the semiconductor element array 2000 in FIG. 4A after one semiconductor element 1 has been removed. As shown in FIG. 4C, a removal area 33 (as indicated by the dotted line) is defined on the top surface of the carrier 30, representing the area exposed on the carrier 30 after the semiconductor element 1 has been removed, i.e., the projected area of ​​the semiconductor element 1 in the top view. The removal area 33 includes an indentation 34. The indentation 34 is the area where the conductive bump 2 is pressed into the adhesive layer 32, and the indentation 34 has a projected area in the top view. Experimental results have shown that when the ratio of the projected area of ​​the indentation 34 of the conductive bump to the projected area of ​​the semiconductor element 1 is less than 0.2, the semiconductor element 1 can be easily picked up from the carrier 30 and transferred to another location.

[0027] 4D and 4E are diagrams illustrating a semiconductor device array according to another embodiment of the present invention. FIG. 4D illustrates a semiconductor device array 3000, for which reference may be made to FIG. 4A and the related paragraphs. The semiconductor device array 3000 includes a plurality of semiconductor devices 1 and a carrier 30. The carrier 30 includes a mounting plate 31 and an adhesive layer 32. The semiconductor devices 1 are disposed on the carrier 30 with the conductive bumps 2 facing the carrier 30. The conductive bumps 2 and electrodes 3 are completely embedded in and completely covered by the adhesive layer 32. The adhesive layer 32 also covers the lower surfaces of the semiconductor devices 1 that are not covered by the electrodes 3. By being temporarily fixed on the adhesive layer 32, the relative positions of the plurality of semiconductor devices 1 are maintained and do not change during subsequent processes. FIG. 4E illustrates a semiconductor device array 3001, for which reference may be made to FIG. 4D and the related paragraphs. The semiconductor device array 3001 includes a plurality of semiconductor devices 1 and a carrier 30. The carrier 30 includes a mounting plate 31 and a plurality of mutually separated adhesive layers 32, each of which corresponds to one semiconductor element 1 in horizontal position and width. There is a gap (space) 33 between two adjacent adhesive layers 32 that is greater than zero. The semiconductor elements 1 are disposed on the carrier 30 with the conductive bumps 2 facing the carrier 30. The conductive bumps 2 and electrodes 3 are completely recessed in the adhesive layer 32 and can be completely covered by the adhesive layer 32. The adhesive layer 32 also covers the lower surface of the semiconductor element 1 that is not covered by the electrodes 3.

[0028] 5A to 5D are diagrams illustrating steps for transferring semiconductor elements 1 in one embodiment of the present invention. As shown in FIG. 5A, multiple semiconductor elements 1 are arranged in an array on a carrier 30. Each semiconductor element 1 contacts the adhesive layer 32 of the carrier 30 through a portion of the surface of its conductive bumps 2 and is temporarily fixed on the carrier 30. A pickup tool 40 is provided to move the semiconductor elements 1 from the carrier 30 to another location. The pickup tool 40 has multiple pickup sections 41, each corresponding to a position of a semiconductor element 1 waiting to be picked up. As shown in FIG. 5B, the pickup tool 40 moves to approach the multiple semiconductor elements 1, bringing the pickup sections 41 into contact with the semiconductor elements 1, and then moves upward to allow the semiconductor elements 1 picked up by the pickup sections 41 to leave the carrier 30. Note that the viscosity between the pickup sections 41 and the semiconductor elements 1 must be greater than the viscosity between the semiconductor elements 1 and the carrier 30 during the pickup step (pickup). The semiconductor elements 1 not contacted by the pickup sections 41 remain on the carrier 30. As shown in FIG. 5C, the pickup tool 40 moves above a predetermined position on the target substrate 50 with the semiconductor device 1 temporarily fixed on the pickup portion 41. At this predetermined position, the semiconductor device 1 directly or indirectly contacts the target substrate 50 and can ultimately be placed or fixed directly on the target substrate 50. As shown in FIG. 5D, the semiconductor device 1 leaves the pickup tool 40 and remains on the target substrate 50, and the pickup tool 40 moves to the same or a different carrier 30 to pick up another semiconductor device 1. After transfer, the semiconductor device 1 is placed on the target substrate 50 with its conductive bumps 2 facing the target substrate 50. The target substrate 50 may be a circuit board applied to a display, a TFT substrate, a substrate with a redistribution layer (RDL), or a sub-substrate (sub-mount) for a package. In another embodiment, the target substrate 50 may be a temporary carrier similar to the carrier 30 described above. In FIGS. 5A to 5D, the contact between the semiconductor device 1 and the carrier 30 is not limited to the manner shown in FIG. 4A, but may also be the manner shown in FIG. 4D or 4E.

[0029] 6A to 6C illustrate steps for transferring a semiconductor device 1 in another embodiment of the present invention. FIG. 6A illustrates a diagram showing a plurality of semiconductor devices 1 placed on a carrier 30 in an array. Each semiconductor device 1 contacts the adhesive layer 32 of the carrier 30 through a portion of the surface of the conductive bumps 2 and is temporarily fixed to the carrier 30. Subsequently, the structure of FIG. 6A is inverted or the target substrate 50 is moved so that the semiconductor device 1 is positioned between the carrier 30 and the target substrate 50 but does not directly contact the target substrate 50. For example, as shown in FIG. 6B, the semiconductor device 1 is suspended above the target substrate 50. Laser energy L1 is applied from the side of the mounting plate 31 to irradiate a specific (predetermined) position on the adhesive layer 32, which corresponds to one semiconductor device 1 to be transferred. The laser energy L1 can be a single-shot laser or a multi-shot laser. In one embodiment, a single or multiple-shot laser may be applied to one semiconductor element 1 or one position on one adhesive layer 32 in one irradiation process. In another embodiment, a single or multiple-shot laser may be applied to multiple positions on one semiconductor element 1 or one adhesive layer 32 in one irradiation process. As shown in FIG. 6C , after the application of laser energy L1, the adhesive layer 32 reduces the adhesive force between the semiconductor element 1 and the adhesive layer 32, or the downward movement force of the semiconductor element 1 becomes greater than the adhesive force of the adhesive layer 32 relative to the semiconductor element 1, causing the semiconductor element 1 to drop from the carrier 30 onto the target substrate 50. After the transfer, the semiconductor element 1 is placed on the target substrate 50 with the conductive bumps 2 separated from the target substrate 50. In another embodiment, in the step of FIG. 6B , the semiconductor element 1 may first be in direct contact with the target substrate 50 and then be irradiated with laser energy L1, thereby more accurately aligning the semiconductor element 1 with the target substrate 50. After the step of FIG. 6C, the adhesive layer 32 remaining on the conductive element 1 can be removed by selectively subjecting the semiconductor element 1 to a removal step.The removing step may include dry etching or wet etching, and the dry etching may be an oxygen plasma etching process. In Figures 6A to 6C, the contact manner between the semiconductor element 1 and the carrier 30 is not limited to the manner shown in Figure 4A, and may be the manner shown in Figure 4D or 4E.

[0030] 7A to 7D are diagrams illustrating steps for fabricating a semiconductor device 1 according to one embodiment of the present invention. As shown in FIG. 7A, a plurality of semiconductor units 100 are disposed on a substrate 10. Each semiconductor unit 100 includes a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor units 100 are disposed on the substrate 10 in such a manner that the first electrode 3a and the second electrode 3b are separated from the substrate 10. The first electrode 3a and the second electrode 3b each have a recess. For an explanation of the related structure, please refer to the description in the relevant paragraph above. Next, adhesive 80 (two lumps) is formed at two separate locations on the first electrode 3a and the second electrode 3b, respectively. The adhesive 80 includes a resin 81 and a plurality of conductive particles 82 dispersed in the resin 81. In one embodiment, the adhesive 80 may be formed by printing, coating, spraying, or dispensing. The printing method may include aerosol jet printing or ink-jet printing. The resin 81 may be made of thermosetting plastics or flux. Thermosetting plastics may include epoxy, silicone, PMMA (polymethyl methacrylate), and episulfide. The melting point of the conductive particles 82 is lower than the curing temperature of the resin 81. In one embodiment, the conductive particles 82 may be made of gold, silver, or copper. In another embodiment, the conductive particles 82 may be made of a low-melting-point metal or a low-liquid-melting-point alloy. In one embodiment, the melting point or liquidus temperature of the low-melting-point metal or low-liquid-melting-point alloy is lower than 210°C. In another embodiment, the melting point or liquidus temperature of the low-melting-point metal or low-liquid-melting-point alloy is lower than 170°C. The low-liquid-melting-point alloy material may be a tin alloy, for example, a tin-indium alloy or a tin-bismuth alloy.

[0031] As shown in FIG. 7B, laser energy L2 is used to irradiate the adhesive 80 or a region nearby it to heat the adhesive 80. The laser energy L2 may include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L2 is an infrared pulse mode laser beam, the wavelength of which is in the range of 750 nm to 2,000 nm, and the light spot size is 0.004 to 0.002 cm. 2 The beam diameter is 100-500 μm, the pulse duration is less than 20 milliseconds (ms), the repetition frequency is 500-4000 Hz, the duty cycle is 1%-10%, the laser power is 100 W, and the laser energy is 595-850 J / cm 2 As shown in FIG. 7C, during the heating process, the conductive particles 82 gather on the first electrode 3a and the second electrode 3b, forming first conductive bumps 2a and second conductive bumps 2b with protruding arc-shaped outer surfaces. The resin 81 can migrate onto the first conductive bumps 2a and 2b, as well as the region 18 between the first electrode 3a and the second electrode 3b. After heating, the first conductive bumps 2a and 2b harden, and the resin 81 covering them remains heated but uncured and in a liquid or semi-liquid state. Subsequently, as shown in FIG. 7D, a cleaning step is performed to remove the uncured resin 81, thereby exposing the first conductive bumps 2a and the second conductive bumps 2b to the external environment and allowing them to contact a carrier during subsequent transfer. The washing step can be performed using a solvent, and the solvent may include NMP (N-Methylpyrrolidinone), MEK (Methyl Ethyl Ketone), ACE (Acetone), or ACE (Isopropyl Alcohol).

[0032] 8A to 8D are diagrams illustrating steps for fabricating a semiconductor device 1 in another embodiment of the present invention. As shown in FIG. 8A, a plurality of semiconductor units 100 are disposed on a substrate 10. Each semiconductor unit 100 includes a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor units 100 are disposed on the substrate 10 in a manner that the first electrode 3a and the second electrode 3b are separated from the substrate 10. The first electrode 3a and the second electrode 3b each have a recess. For an explanation of the related structure, please refer to the relevant paragraph above. A first bonding pad 23a and a second bonding pad 23b are formed on the first electrode 3a and the second electrode 3b, respectively, by electroplating, chemical plating, or vapor deposition. An upper surface 24a of the first bonding pad 23a and an upper surface 24b of the second bonding pad 23b are substantially conformal to the upper surfaces of the first electrode 3a and the second electrode 3b, i.e., the contours of both are similar and have recesses and / or roughened textures. A mass of adhesive 83 is formed on the semiconductor unit 100, the first bonding pad 23a, and the second bonding pad 23b. In this example, the adhesive 83 contains only resin. In another embodiment, the adhesive 83 contains resin and a relatively low concentration of conductive particles (compared to the conductive particles in FIG. 7A). In one embodiment, the adhesive 80 may be formed by printing, coating, spraying, or dispensing. The printing method may include aerosol jet printing or inkjet printing. For the material of the first bonding pad 23a and the second bonding pad 23b, please refer to the description in the paragraph related to the conductive bumps 2a and 2b above. For the material of the resin, please refer to the description in the relevant paragraph above.

[0033] As shown in FIG. 8B, laser energy L3 is applied to the first and second bonding pads 23a and 23b, thereby heating the adhesive 83, the first and second bonding pads 23a and 23b. The laser energy L3 may include ultraviolet (UV) laser light, visible light laser light, or infrared (IR) laser light. In one embodiment, the laser energy L3 is an infrared laser light having a wavelength in the range of 750 nm to 2,000 nm. As shown in FIG. 8C, during the heating process, the first and second bonding pads 23a and 23b melt into the adhesive 83 and gather on the first and second electrodes 3a and 3b (if the resin contains conductive particles, the conductive particles may migrate partially or completely toward the first and second electrodes 3a and 3b after being heated), forming first and second conductive bumps 2a and 2b with protruding arc-shaped outer surfaces. The adhesive 83 can migrate onto the first conductive bump 2a, the second conductive bump 2b, and the region 18 between the first electrode 3a and the second electrode 3b. After heating, the first conductive bump 2a and the second conductive bump 2b are cured, and the adhesive 83 (or resin) covering them is heated but not completely cured, remaining in a liquid or semi-liquid state. Subsequently, as shown in FIG. 8D, a cleaning step is performed to remove the uncured adhesive 83 (or resin), thereby exposing the first conductive bump 2a and the second conductive bump 2b to the external environment and allowing them to contact a carrier during subsequent transfer. For details about the cleaning step, please refer to the description in the relevant paragraph of FIG. 7D above.

[0034] In another embodiment, the cleaning steps of FIGS. 7D and 8D may not completely remove the adhesive between the conductive bumps 2a and 2b and may remain on the semiconductor element 100. To avoid affecting the subsequent transfer and die-attach processes, the maximum height of the remaining adhesive is preferably no higher than that of the conductive bumps 2a and 2b. FIG. 9A is a three-dimensional view of a semiconductor element 20 according to another embodiment of the present invention. FIG. 9B is a cross-sectional view of the semiconductor element 20 taken along line BB′ in FIG. 9A. As shown in FIG. 9A, there are two separate first and second conductive bumps 2a and 2b on the top side of the semiconductor element 20. Between the first and second conductive bumps 2a and 2b, there is at least one remaining mass of adhesive 84 covering the semiconductor element 20. In the top view, the remaining adhesive 84 has an irregular shape and an unfixed area. As shown in FIG. 9B , the semiconductor device 20 includes a semiconductor stack layer 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack layer 14 is an inclined surface that is inclined relative to the substrate 10. The semiconductor stack layer 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. A remaining adhesive 84 is located on the protective layer 15 between the first conductive bump 2a and the second conductive bump 2b. The top surface of the remaining adhesive 84 is not higher than the maximum height of the first conductive bump 2a and the second conductive bump 2b and has a rough outer surface. Because the height of the remaining adhesive 84 does not exceed the conductive bumps 2a and 2b, it does not affect the subsequent transfer and die-attach processes.

[0035] FIG. 10A illustrates a semiconductor device 1 being die-attached to a target substrate 51 in one embodiment of the present invention. The target substrate 51 may be a circuit board with conductive circuits, a TFT substrate, a substrate with a redistribution layer (RDL), or a sub-substrate for a package, as applied to a display. A plurality of conductive connection pads 52 are formed on the target substrate 51. The semiconductor device 1 may have any of the above structures. The conductive bumps are heated, melted, and hardened to form an adhesive layer 53, thereby connecting the semiconductor device 1 to the conductive connection pads 52. The semiconductor device 1 can receive power and / or drive signals through the conductive connection pads 52 and the adhesive layer 53. The adhesive layer 53 can selectively cover the side surfaces 521 of the conductive connection pads 52. During the process of heating the conductive bumps to form the adhesive layer 53, dispersed metal particles may appear in the adhesive layer 53 due to adjustment of process parameters such as the heating temperature and heating time. FIG. 10B illustrates a semiconductor device 1 being die-attached to a target substrate 51 in another embodiment of the present invention. After the bonding layer 53 is cured, irregular particles 8 appear in the bonding layer 53. In other words, the bonding layer 53 is dispersed with particles 8 having irregular shapes. The material of the particles 8 is different from that of the bonding layer 53 but is the same as the material of some of the electrodes 3a, 3b and / or conductive connection pads 52 of the semiconductor element 1, such as gold, platinum, or an alloy of the aforementioned materials. In one embodiment, the heating and curing method may involve applying laser energy, which may include an ultraviolet (UV) laser beam, a visible light laser beam, or an infrared (IR) laser beam. In one embodiment, the wavelength of the infrared laser beam is in the range of 750 nm to 2,000 nm.

[0036] Although the preferred embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and any modification to the present invention without departing from the spirit of the present invention falls within the technical scope of the present invention. [Explanation of symbols]

[0037] 1, 20 Semiconductor elements 2, 2a, 2b Conductive bumps 3, 3a, 3b electrode 4 Adhesive structure 5a First hole 5b Second hole 6a First recess 6b Second recess 7, 8 particles 10 Substrate 11 First semiconductor layer 12 Active layer 13 Second semiconductor layer 14 semiconductor stack layers 15 Protective layer 16 flat platform 17 Lower surface 18 areas 19 Outermost edge 21, 21a, 21b top 22, 22a, 22b outermost surface 23a First Bonding Pad 23b Second bonding pad 24a, 24b top surface 30 Carrier (mounting body) 31 Loading plate 32 Adhesive layer 33 areas 34 Indentation 40 Pickup Tool 41 Pickup section 50, 51 Target board 52 conductive connection pads 53 Bonding layer 80, 84 Adhesive 81, 83 Resin 82 Conductive particles 151 Top surface 521 Side surface 1000, 1001, 1001', 2000 semiconductor element array θ1, θ2 included angle D distance H1, H2, H3, H4, H5 thickness L1, L2, L3 laser energy W1, W2, W3, W4 width

Claims

1. A semiconductor device, semiconductor stack layers; a protective layer overlying the semiconductor stack layers and having a top surface; an electrode located on and electrically connected to the semiconductor stack layer; and a conductive bump located on the electrode and having an outwardly protruding outermost surface, a top, and a maximum width; The semiconductor device, wherein the distance from the top to the uppermost surface is defined as the thickness of the conductive bump, and the ratio of the thickness to the maximum width is 0.1 to 0.

4.

2. 2. The semiconductor device according to claim 1, The semiconductor device further comprises a plurality of particles discretely distributed within the conductive bump.

3. 3. The semiconductor device according to claim 2, A semiconductor element, wherein the material of the plurality of particles is the same as a portion of the material of the electrode and is different from the material of the conductive bump.

4. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a semiconductor stack layer on the substrate, the semiconductor stack layer having a side surface; forming an electrode on the side of the semiconductor stack layer; forming an adhesive on the electrode; and forming a conductive bump on the electrode; The adhesive covers the conductive bumps.

5. The method of claim 4, comprising: The method further comprising washing the adhesive.

6. The method of claim 4, comprising: The method further includes forming a conductive bump with the first laser energy.

7. The method of claim 6, comprising: forming a bond pad on the electrode; irradiating the bond pad with the first laser energy to form the conductive bump.

8. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a semiconductor stack layer on the substrate; forming an electrode on the semiconductor stack layers; forming a conductive bump on the electrode with a first laser energy; Providing a target substrate; and causing the conductive bumps to bond onto the target substrate with second laser energy.

9. The method of claim 6, 7 or 8, comprising: The method, wherein the first laser energy or the second laser energy comprises an ultraviolet (UV) laser beam, a visible laser beam, or an infrared (IR) laser beam.

10. The method of claim 4 or 8, The conductive bump comprises a plurality of discretely distributed particles.

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