Hardware scheme for dynamic adjustment of DC-DC converter peak current and safe LDO disable

Abstract

To provide a hardware scheme for dynamic adjustment of a DCDC converter peak current and safe LDO disable.SOLUTION: A system 100 includes a controller, a DC (direct current) DC converter coupled to the controller to supply a load current to the load, and an LDO (low dropout) regulator coupled to the DCDC converter. The controller includes digital logic that determines a load current, turns on the LDO regulator when the load current is above a predetermined threshold, and turns off the LDO regulator when the load current is below the predetermined threshold.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - reference to related applications This application claims priority to Indian Provisional Patent Application No. 202141052087, filed on November 13, 2021, under the title "Hardware Scheme for Dynamic Regulation of DCDC Converter Peak Current and Safe LDO Disable", the entire disclosure of which is incorporated herein by reference.

Background Art

[0002] A DC (direct current) - DC voltage converter receives an input voltage and converts that input voltage to an output voltage in order to drive a load. In one example, some microcontrollers include a DC - DC converter and a low - dropout voltage regulator (LDO regulator), which create a regulated DC supply voltage to drive the load. The DC - DC converter is used as a primary voltage regulator, and the LDO regulator is enabled for load sharing when higher load currents or current spikes need to be handled. When the load current drops to a level that can be properly handled by the DC - DC converter, the LDO regulator is disabled.

Summary of the Invention

[0003] According to at least one example described herein, a device includes a controller and a DC - DC converter coupled to the controller and configured to provide a load current to a load. The device also includes an LDO regulator coupled to the DC - DC converter. The controller includes digital logic configured to determine the load current. The digital logic is further configured to turn on the LDO regulator when the load current exceeds a predetermined threshold. The digital logic is also configured to turn off the LDO regulator when the load current falls below the predetermined threshold.

[0004] According to at least one example described herein, a device includes a controller including digital logic. The digital logic includes a measurement window generator configured to generate a measurement window. The digital logic also includes a pulse counter configured to provide a count of charge pulses on an inductor coupled to a DC-DC converter during the measurement window. The digital logic also includes a latch configured to determine a percentage load based on the count of charge pulses. The digital logic also includes a comparator configured to compare the percentage load to a load threshold, the comparator further configured to disable an LDO regulator based on the comparison.

[0005] According to at least one example described herein, a method includes supplying a load current to a load using a DC-DC converter. This method also includes counting charging pulses during a measurement window, the charging pulses generating the load current. Furthermore, this method includes determining the percentage loading based on the count of charging pulses. This method includes turning off the LDO regulator in response to the percentage loading falling below a predetermined threshold. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram of a system for dynamic regulation of DC-DC converter peak current and safe LDO regulator disablement, following various examples.

[0007] [Figure 2] This is a block diagram of a DC-DC load meter, following various examples.

[0008] [Figure 3] This is a collection of waveforms illustrating the operation of a DC-DC load meter, following various examples.

[0009] [Figure 4]This is a system block diagram for a safe LDO turn-off scheme, following various examples.

[0010] [Figure 5] This is a collection of waveforms demonstrating safe LDO disabled operation according to various examples.

[0011] [Figure 6] This is a block diagram of a system for adaptive DC-DC peak current regulation, following various examples.

[0012] [Figure 7] This is a hardware finite state machine for adaptive IPEAK schemes, following various examples.

[0013] [Figure 8] This is a collection of waveforms for adaptive IPEAK schemes, following various examples.

[0014] [Figure 9] This is a flowchart illustrating methods for safely and reliably disabling an LDO regulator, following various examples.

[0015] In drawings, the same reference number or other reference indicator is used to indicate the same or similar features (functionally and / or structurally). [Modes for carrying out the invention]

[0016] DC-DC voltage converters (hereinafter referred to as DCDC converters) and LDO regulators can be useful for creating a stable voltage supply. To improve system efficiency, the DCDC converter is the primary voltage regulator, and the LDO regulator is enabled for load sharing to handle higher load currents or current spikes. Due to inductor form factor constraints, the DCDC converter may not be able to handle large load currents. Therefore, the LDO regulator shares the load current with the DCDC converter when enabled. When the load current drops to a level that the DCDC converter can handle, the LDO regulator can be disabled. For maximum efficiency, the DCDC converter is designed to have a peak (e.g., maximum) current setting at an optimal level. When the load current is higher than the peak current setting, the LDO regulator is enabled for load sharing.

[0017] Several alternative mechanisms for turning LDO regulators on and off utilize analog circuit elements. However, analog circuit elements can turn off the LDO regulator when the DC-DC converter cannot handle the load current. The LDO regulator then turns on again, creating an on / off cycle for the LDO regulator. This continuous on / off cycle for the LDO regulator can introduce ripple into the regulated power supply, affecting the system's radio frequency (RF) performance.

[0018] In the examples of this application, digital logic and hardware manage the DC-DC converter and LDO regulator. A DC-DC load meter senses the load current carried by the DC-DC converter by counting the number of charge pulses carried to an energy storage device (e.g., an inductor and / or capacitor) over a predefined duration. The number of pulses represents the load current carried by the DC-DC converter. In response to the value of the load current sensed by the DC-DC load meter, the LDO regulator can be safely enabled and disabled. The DC-DC converter also has a peak current setting that can be adjusted based on changes in load current to achieve higher efficiency. The user can set predetermined high and low thresholds for adjusting the peak current setting of the DC-DC converter. If the load current rises above the high threshold, the peak current setting of the DC-DC converter can be increased. By increasing the peak current setting, the DC-DC converter may be able to handle the load current without turning on the LDO regulator in some examples, which helps avoid rapid on / off cycles for the LDO regulator. When the load current drops below a low threshold, the peak current setting of the DC-DC converter can be reduced, thereby improving the efficiency of the DC-DC converter.

[0019] The examples in this application provide a flexible and reliable scheme for safely enabling and disabling LDO regulators. These examples can be managed via digital logic without requiring software in some cases. In other cases, software may be useful for adjusting peak current settings by reading load current values ​​sensed by a DC-DC load meter. The examples in this application avoid LDO regulator on / off cycles that degrade the RF performance of the system. DC-DC operating efficiency is improved in the examples in this application. Furthermore, the user is provided with the flexibility to define high and low thresholds for peak current based on the needs of their specific application.

[0020] Figure 1 is a block diagram of a system 100 for dynamic adjustment of DC-DC converter peak current and safe LDO regulator disablement, according to various examples in this application. In this example, system 100 provides load current to load 102. System 100 includes a controller 104, a DC-DC converter 106, and an LDO regulator 108. The controller 104 may be a processor, microprocessor, microcontroller, power management integrated circuit, system-on-chip, or any other device suitable for performing the operation described in this application. The controller 104 includes a register 110, a DC-DC load meter 112, digital logic 114, and memory 116. In some examples, components shown in controller 104 may be implemented outside of controller 104. The controller 104 is coupled to the DC-DC converter 106 and the LDO regulator 108. The DC-DC converter 106 and the LDO regulator 108 provide load current to load 102 according to the examples in this application.

[0021] In one exemplary operation, the DC-DC converter 106 provides load current to the load 102. The DC-DC converter 106 has an adjustable peak current setting used to control when the DC-DC converter 106 switches between charging and discharging the energy storage element. As an example, the peak current setting (e.g., I PEAKThe peak current setting can be a number from 0 to 7. The peak current setting can be stored in memory 116 or register 110. The peak current setting can be selected based on the load current demand to improve the efficiency of the DCDC converter 106. As described later, the DCDC load meter 112 and digital logic 114 can be configured to sense the load current supplied to the load 102. In response to sensing the load current, the peak current setting can be changed to achieve improved efficiency. For example, if the load current demand is 5 milliamperes (mA), a peak current setting of 10 mA may be more efficient than a peak current setting of 15 mA. If the load current demand increases, the peak current setting can be increased by the controller 104 using digital logic 114 to meet this increased demand. Also, if an LDO regulator 108 is required to help meet such load current demand, the DCDC load meter 112 and digital logic 114 can enable the LDO regulator 108. If the load current demand decreases, or if the DC-DC converter 106 can handle the load current, the digital logic 114 may disable the LDO regulator 108. Details of the operation of the DC-DC load meter 112 and the digital logic 114 will be described later.

[0022] Figure 2 is a block diagram of a DCDC load meter 112 according to various examples in the present application. One exemplary operation of the DCDC load meter 112 will be described later with reference to Figure 3. Referring again to Figure 2, in one example, the DCDC load meter 112 may be implemented using hardware and digital logic. The DCDC load meter 112 includes a DCDC pulse measurement window generator 202 (hereinafter referred to as window generator 202). The window generator 202 includes a clock input 204, a DCDC load meter enable input 206, and an output 208. The DCDC load meter 112 also includes a pulse "on" counter 210 (e.g., PON counter 210). The PON counter 210 includes a DCDC PON input 212 that receives an input pulse, a reset input 214, an enable input 216, and an output 218.

[0023] The DCDC load meter 112 also includes a DCDC load latch 220. The DCDC load latch 220 includes an input 222, a clock input 224, and an output 226. The DCDC load meter also includes a counter 228. The counter 228 includes an input 230, a global LDO (GLDO) enable input 232, and an output 234. The DCDC load meter 112 also includes a comparator 236. The comparator 236 has a first input 238 and a second input 240. The comparator 236 also has an enable input 242 and an output 244.

[0024] The DC-DC load meter 112 also includes a counter 246. The counter 246 includes an input 248 and a DC-DC load meter enable input 250. The counter 246 includes an output 252. The DC-DC load meter also includes an AND gate 254. The AND gate 254 includes a first input 256 and a second input 258. The AND gate 254 includes an output 260.

[0025] Waveforms 262 and 264 are also shown in Figure 2. The operation of waveforms 262 and 264 will be described further later with respect to Figure 3. In Figure 2, waveform 262 is provided by the window generator 202 at output 208. Waveform 262 indicates a measurement window for the operation described herein. The measurement window represents a window of time during which charging pulses are counted to determine the value of the load current supplied to the load 102. Waveform 262 is provided to the reset input 214 of the PON counter 210, the clock input 224 of the DCDC load latch 220, the input 230 of the counter 228, and the input 248 of the counter 246. Waveform 262 provides timing pulses to the various components of the DCDC load meter 112 to enable the synchronized operation of the components.

[0026] Waveform 264 is a collection of charging pulses supplied to an energy storage device (e.g., an inductor and / or capacitor) coupled to the DC-DC converter 106. The DC-DC converter 106 uses these charging pulses to supply load current to the load 102. In the DC-DC load meter 112, the charging pulses represented by waveform 264 are supplied to the PON counter 210 at the DC-DC PON input 212. The PON counter 210 counts the number of charging pulses in waveform 264 during the measurement window.

[0027] In operation, the window generator 202 receives a clock signal (e.g., a 48 megahertz (MHz) clock signal) at the clock input 204. A DCDC load meter enable signal is provided at the DCDC load meter enable input 206 to turn on the DCDC load meter 112. In one example, the DCDC load meter enable signal may be provided by the controller 104. After the DCDC load meter enable signal is received by the window generator 202, the window generator generates a waveform 262 at output 208. Waveform 262 includes a pulse indicating the start of the measurement window. The measurement window is the duration during which the PON counter 210 counts the charge pulses. In one example, the measurement window is the charge time of the DCDC converter 106 plus the discharge time of the DCDC converter 106, all multiplied by 100. In some examples, the charge and discharge times may vary based on the load. In some other examples, an additional clock cycle may be added to the measurement window. Waveform 262 is provided to the PON counter 210 at the reset input 214. When pulses from waveform 262 are supplied to the PON counter 210, the PON counter 210 begins counting the number of charge pulses received at the DCDC PON input 212, as represented by waveform 264. Also, as shown in Figure 2, the PON counter 210 is enabled by a DCDC load meter enable signal received at input 216, in a similar manner to how the window generator 202 is enabled.

[0028] The PON counter 210 counts the number of charging pulses during the measurement window. After the measurement window is complete (indicated by another pulse from waveform 262 provided to the reset input 214), the PON counter 210 provides the count of charging pulses to the DCDC load latch 220. The PON counter is then reset and can therefore count the number of charging pulses in the next measurement window.

[0029] The value obtained at the DCDC load latch 220 is a percentage loading measurement. For example, if the measurement window is 100 cycles and the PON counter 210 counts 90 charging pulses during the measurement window, the DCDC load value is 90% (e.g., 90 / 100). This value is used to load the load current into the active I of the DCDC converter 106. PEAK This is expressed as a percentage of the setting. This DC-DC load value is provided to the AND gate 254.

[0030] The DC-DC load meter 112 includes counters 228 and 246. Counter 228 is used for a safe LDO enable / disable scheme, which will be described later. Counter 228 counts the number of measurement windows from waveform 262, which is provided to input 230 of counter 228. After a predetermined number of measurement windows (e.g., two measurement windows), a signal is provided from counter 228 to comparator 236 to generate a comparator enable signal at output 244. The digital comparator enable signal will be described later with respect to Figures 4 and 5. Counter 228 keeps the LDO regulator 108 enabled for at least a predetermined number of measurement windows to help prevent rapid LDO on / off cycles.

[0031] Furthermore, counter 246 counts the number of measurement windows by receiving waveform 262 at input 248. Counter 246 is enabled using a DCDC load meter enable signal provided at input 250. After counter 246 has counted more than a predetermined number of measurement windows (e.g., two measurement windows), counter 246 provides a signal at output 252. The signal from output 252 is provided to AND gate 254 to enable AND gate 254. After a predetermined number of measurement windows, AND gate 254 is enabled and provides a DCDC load value at output 260. The DCDC load value at output 260 is provided after a predetermined number of measurement windows for stability and reliability.

[0032] Figure 3 is a collection of waveforms 300 illustrating the operation of the DC-DC load meter 112 according to various examples in this application. Waveforms 300 include a waveform 262 called the load meter window marker (lm_window_marker). Waveform 262 includes a pulse indicating the start of the measurement window. Waveform 264 represents a charging pulse called dcdc_pon. Waveform 302 represents the load current supplied to the load 102, called I_load. Waveform 304 represents the load meter measurement window (lm_meas_window). Waveform 306 represents the pulse count from the PON counter 210 (dcdc_pon_counter). Waveform 308 represents the DC-DC load status (dcdc_load_status), which is the DC-DC load value measured as a percentage of the peak current.

[0033] An example of the operation begins at time t0. In this example, the peak current setting is 25mA. The peak current setting sets a limit on the maximum current that can be carried by the DC-DC converter 106. However, the peak current through the inductor may be higher than the peak current setting. In Figure 3, before time t0, the DC-DC load value is 70% (shown in waveform 308). Therefore, waveform 308 shows 70 as the initial DC-DC load value, and this value remains 70 until a measurement window occurs and the DC-DC load value is updated. The load current at time t0 (waveform 302) is 22.5mA, which is 90% of the peak current setting of 25mA. At time t0, a pulse indicating the start of the measurement window occurs on waveform 262. As shown in Figure 2, the pulse on waveform 262 causes the PON counter 210 to start counting pulses. Counting also begins for this measurement window.

[0034] In this example, at time t0, the measurement window (waveform 304) starts counting from 1 to 100. After reaching a count of 100, the measurement window is completed and a new measurement window can start. Also at time t0, the PON counter 210 starts counting pulses on waveform 264 (dcdc_pon). At time t1, this measurement window (waveform 304) reaches a count of 100. At time t2, the PON counter 210 has counted 90 pulses on waveform 264. Therefore, the DC-DC load state is 90% at this point. Consequently, after time t1, waveform 308 updates the new DC-DC load state to 90.

[0035] Immediately after time t1, another pulse appears on waveform 262. This pulse indicates the start of a new measurement window. In this example, the load current (waveform 302) drops to 12.5 mA during this second measurement window. A load current of 12.5 mA is 50% of the peak current setting of 25 mA. The second measurement window begins at time t2. At time t2, waveform 304 indicates that the count for this measurement window has been reset and that the count from 1 to 100 has started again. Also at time t2, the PON counter 210 is reset and starts counting pulses on waveform 264 again, starting with the first pulse at time t2.

[0036] The second measurement window continues until time t3. At time t3, the measurement window (waveform 304) reaches 100 counts. At time t3, the PON counter 210 has counted 50 pulses on waveform 264. Therefore, the DC-DC load state is 50% at this point. Consequently, after time t3, waveform 308 updates the DC-DC load state to 50.

[0037] After time t3, the third measurement window begins. During this measurement window, the load current is 2.5mA, which is 10% of the peak current setting. As shown in Figure 3, at time t4, the third measurement window ends with a pulse count of 10, as shown in waveform 306. After time t4, waveform 308 updates the DC-DC load state to 10.

[0038] This process continues as long as the DCDC load meter 112 is enabled. The PON counter 210 counts pulses and updates the DCDC load state after each measurement window. In some examples, two or more measurement windows may occur before the DCDC load state is updated. The DCDC load state indicates the percentage of load current compared to the peak current for the DCDC converter 106. As described herein, if the DCDC load state exceeds a predetermined threshold, the peak current setting may be increased so that the DCDC converter 106 can provide more current to the load 102. The LDO regulator 108 may also be enabled to share the load current if necessary. The threshold can be set by the user. For example, the upper threshold may be 80%. In this example, if the DCDC load state exceeds 80%, the peak current setting for the DCDC converter 106 may be increased. The user may also set a lower threshold. For example, the lower threshold may be 50%. If the DCDC load state falls below 50%, the peak current setting for the DCDC converter may be reduced. With a lower peak current setting, the DC-DC converter 106 has a lower maximum amount of current that it can provide to drive the load, but it may operate more efficiently than when it has a higher peak current setting.

[0039] Figures 2 and 3 show that the DC-DC load meter may use digital hardware and logic to sense the load current carried by the DC-DC converter 106. Charging pulses are counted over a predetermined time window, and these pulses represent the load current. After the DC-DC load state is determined, additional actions may be taken, such as enabling or disabling the LDO regulator 108, or adjusting the peak current setting. These additional actions are described later.

[0040] Figure 4 is a block diagram of system 400 for a safe LDO turn-off scheme according to various examples in the present application. System 400 provides a mechanism for safely enabling and disabling the LDO regulator 108 while avoiding undesirable on / off cycles of the LDO regulator 108. In one example, the LDO regulator 108 is enabled when the DC-DC converter 106 cannot handle a load for a given peak current setting. For example, when the DC-DC converter 106 is operating at a particular current setting (e.g., 3 on a scale from 0 to 7), there is a certain maximum current that the DC-DC converter 106 can deliver to the load. In one example, this current may be 15 mA. If there is a current spike exceeding this maximum value, the LDO regulator 108 is enabled for current sharing. Also in the examples in the present application, the controller 104 may increase the peak current setting for the DC-DC converter 106 to handle the load. In this example, the peak current setting may be increased from 3 to 4 or 5. After the peak current setting is increased and the DC-DC converter 106 is able to handle the load current, the LDO regulator 108 may be disabled. If the peak current setting is at its maximum and the DC-DC converter 106 cannot handle the load, the LDO regulator 108 may be enabled. The LDO regulator 108 remains on until the load current drops to a level that the DC-DC converter 106 can handle. In some examples of this application, a digital comparator compares the output of the DC-DC load meter 112 to a predetermined threshold that is programmed and stored in a register during device startup. In some such examples, this threshold cannot be changed by the user. The threshold provides some margin over the maximum DC-DC load current for the selected peak current setting. This margin is described below. System 400 includes hardware and digital logic that implement the scheme described above.

[0041] System 400 includes component 402, which is a component for the LDO regulator 108 disable scheme. Component 404 is a component that enables an adaptive peak current scheme for adjusting the peak current setting as described above. In one example, the components in system 400 may be located within the controller 104.

[0042] Component 402 includes a DC-DC load meter 112, a DC-DC load threshold encoder 406, a comparator 408, an OR gate 410, and an AND gate 411. Component 404 includes a DC-DC peak current (I PEAK ) Adaptive unit 412, DC-DC load register 414, high threshold register 416, low threshold register 418, multiplexer 420, I PEAK Includes register 422.

[0043] The DCDC load meter 112 includes four inputs: a clock input 204, a DCDC PON input 212, an LDO enable input 232, and a DCDC load meter enable input 206. The DCDC load meter 112 provides a comparator enable signal at output 244 and a DCDC load value at output 260. The inputs and outputs of the DCDC load meter 112 are described above with reference to Figure 2.

[0044] The DC-DC load threshold encoder 406 includes a DC-DC load threshold input 424. The DC-DC load threshold input 424 can provide the DC-DC load threshold encoder 406 with a value to be stored in a register. The DC-DC load threshold encoder 406 generates an output value at output 426. The output value is provided to the first input 428 of the comparator 408. The second input 430 of the comparator 408 receives the DC-DC load value from output 260. The comparator 408 includes an output 432 that disables the LDO regulator 108 as described later.

[0045] The OR gate 410 has three inputs: an LDO enable input 232 and an adaptive I PEAKIt includes an enable signal 434 and a load meter enable 436. Adaptive I PEAK The enable signal 434 can be a value stored in a register. The load meter enable 436 can receive a value stored in a register. The OR gate 410 includes an output 438 provided to the AND gate 411. Also, a VDDS good signal 440 is provided to the AND gate 411. The VDDS good signal 440 indicates that the primary voltage supply is sufficient to operate the DCDC converter 106. The AND gate 411 provides an output signal at the output 442.

[0046] The OR gate 410 inputs provide a plurality of conditions under which the DCDC load meter 112 can be enabled. First, when the LDO regulator 108 is enabled for load current sharing, the LDO enable input 232 is provided to the OR gate 410, and the OR gate 410 provides an enable signal from the output 442 to the DCDC load meter enable input 206. Second, the DCDC load meter 112 can be enabled via software using configuration bits that can be set to enable the DCDC load meter 112 via the load meter enable 436. Third, the DCDC load meter 112 can be enabled using the adaptive I PEAK enable signal 434 provided to the OR gate 410. In one example, I PEAK The enable signal can be stored in a register. I PEAK The enable signal 434 will be described later.

[0047] In one exemplary operation, the DCDC load meter 112 provides the measured DCDC load value (as a percentage) from the output 260 to the comparator 408. Also, a comparator enable signal at the output 244 is provided from the DCDC load meter 112 to the comparator 408. The DCDC load value and the comparator enable signal are provided as described above with respect to FIG. 2. In one example, the comparator enable signal is generated only after two measurement cycles of the DCDC load meter 112.

[0048] Comparator 408 compares the DC-DC load value at input 430 with the DC-DC load threshold at input 428. If the comparison shows that the DC-DC load value is lower than the DC-DC load threshold from DC-DC load threshold encoder 406, comparator 408 disables the LDO regulator 108.

[0049] For the DCDC load threshold encoder 406, the DCDC load threshold input 424 provides an internally programmed register value representing a predetermined load threshold. The DCDC load threshold encoder 406 converts the two bits in the DCDC load threshold input 424 into one of the possible threshold settings. For example, if the DCDC load threshold encoder 406 generates 90% as a reference value for the comparator 408, and the DCDC load value from the DCDC load meter 112 is 90% or less, the LDO regulator 108 can be safely disabled. The DCDC load threshold encoder 406 provides some margin over the maximum current that the DCDC converter 106 can carry. This margin helps avoid a false LDO disable signal. The LDO regulator 108 is disabled by the comparator 408 when the DCDC load value falls below a threshold (90%, 85%, etc.) from the DCDC load threshold encoder 406. An LDO disable signal from output 432 can be provided to an analog circuit element that disables the LDO regulator 108.

[0050] Component 404 of the adaptive peak current scheme receives the DCDC load value from the output 260 of the DCDC load meter 112. PEAK The adaptive unit 412 receives a DC-DC load value at input 444. The DC-DC load value can also be stored in the DC-DC load register 414. Adaptive I PEAK The enable signal 434 is transmitted to input 446 via DC-DC I PEAK Provided to adaptive unit 412. Adaptability I PEAK The enable signal 434 is the same signal provided to the input of the OR gate 410. This signal is adaptive I PEAKTurn on the scheme. DCDC I PEAK The adaptive unit 412 receives a high threshold from the high threshold register 416 at input 448 and a low threshold from the low threshold register 418 at input 450. PEAK The adaptive unit 412, in output 452, updated I PEAK Provides a value. DCDC I PEAK Updated I from adaptive unit 412 PEAK The value is the new I PEAK This is the setting. PEAK If the enable signal 434 is not active, the multiplexer 420 will PEAK From the register that stores the user default settings for I PEAK Select a value. This default value may be stored in a configurable register. PEAK When the enable signal 434 is active, a new I is output from the multiplexer 420. PEAK The value is I PEAK It is stored in register 422. New I PEAK DCDC I for selecting a value PEAK The operation of the adaptive unit 412 will be described later with reference to Figures 6 and 7. In one example, DCDC I PEAK The digital logic and state machine within the adaptive unit 412 is a new I PEAK You can choose a value.

[0051] Figure 5 is a collection of waveforms 500 illustrating the operation of safe LDO disabled operation according to various examples in the present invention. In one example, the safe LDO disabled scheme can be performed by digital logic as shown in Figure 4. Waveform 502 shows the load current I LOAD Waveform 504 represents the DC-DC load meter 112 window marker (lm_window_marker). Waveform 506 represents the I that can be stored in a memory-mapped register (MMR). PEAK This represents the value (ipeak_mmr). In one example, I PEAK The value can be set between 0 and 4, in which case 0 is the lowest I PEAK The value is 4, and 4 is the highest I PEAKThe waveform 508 is the DC-DC load value (dcdc_load_status) expressed as a percentage. In one example, the DC-DC load value may be the value at output 260. Waveform 510 is the LDO enable state (gldo_enable). A low value on waveform 510 indicates that the LDO regulator 108 is disabled, and a high value on waveform 510 indicates that the LDO regulator 108 is enabled. Waveform 512 is the LDO disable signal (gldo_disable), which is high to disable the LDO regulator 108 by gldo_enable. Waveform 514 represents the DC-DC load threshold. This value may be stored in a register and provided to the DC-DC load threshold encoder 406 as described above with respect to Figure 4. The DC-DC load threshold is a percentage value and is set to 95% in this example. Waveform 516 is the maximum I PEAK This represents the value (ipeak_max), which is 4 in this example.

[0052] In one example of operation, the initial load current is 35 mA (waveform 502). At time t0, the load current increases to 45 mA. In response to the increase in load current, the LDO enable signal (waveform 510) rises. In one example, such an increase in load current can be sensed by an analog circuit element. The load meter window marker (waveform 504) indicates the pulse that starts the load meter measurement window. At time t1, the load meter measurement cycle ends. The DCDC load meter shows a value of 100 after the measurement cycle (waveform 508). The LDO regulator remains on after time t1 (waveform 510). As shown in waveform 514, the DCDC load threshold is 95%. Since the load meter value (waveform 508) is 100 and the DCDC load threshold is 95, the LDO regulator 108 remains enabled after time t1. However, PEAK The settings can be increased. At time t2, I PEAK The setting is increased from 3 to 4 (waveform 506). PEAKThe settings can be increased using the component 404 shown in Figure 4, or as described later with respect to Figures 6 and 7.

[0053] At time t3, the second measurement window begins (waveform 504). At time t4, the DCDC load meter reports that the DCDC load state is 90% (waveform 508). A 90% DCDC load state is below the 95% DCDC load threshold (waveform 514). As described above with respect to Figure 4, the DCDC load state and DCDC load threshold are provided to the comparator 408. If the DCDC load state is below the DCDC load threshold, the comparator 408 disables the LDO regulator 108. As shown in waveform 512, the LDO disable signal becomes high at time t5. In response to the LDO disable signal becoming high, the LDO enable signal (waveform 510) becomes low at time t6. Therefore, the LDO regulator 108 is disabled.

[0054] Figure 5 shows the LDO regulator 108 and I PEAK This indicates that all settings can be changed in response to changes in load current. PEAK When the setting is at its maximum value, the LDO regulator 108 may remain on until the load current falls below the DC-DC load threshold.

[0055] Figure 6 is a block diagram of a system 600 for adaptive DC-DC peak current control according to various examples in the present application. In one example, user-configurable bits enable an adaptive DC-DC converter peak current control scheme in hardware or digital logic. Adaptive I in Figure 4 PEAK Enable signal 434 is an example of this bit. Also, the user can adapt I PEAK High and low thresholds (as percentages) can be configured for the adjustment scheme. For example, the high threshold may be set to 80% and the low threshold to 50%. Adaptability I PEAKWhen the scheme is enabled, the DCDC load meter output is compared to high and low thresholds by hardware or digital logic. If the DCDC load meter output is between the high and low thresholds, PEAK The settings are retained. If the DCDC load meter output is higher than the high threshold, the hardware will PEAK The setting is increased by 1 count. At the same time, LDO regulator 108 is I PEAK It can be turned on for a short time during setting adjustments. PEAK After setting adjustments, if the DCDC converter 106 can handle the load current, the LDO regulator 108 is turned off. If the DCDC load meter output falls below a low threshold, the hardware... PEAK The setting is reduced by one count. When the peak current setting is reduced, the LDO regulator 108 remains disabled because there is no need for load current sharing in such scenarios.

[0056] System 600 includes comparator 602, comparator 604, and hardware finite state machine (HW FSM) 606. In system 600, the DC-DC load value is compared to a high threshold and a low threshold. Based on the outputs from comparators 602 and 604, the HW FSM 606 performs an I PEAK Adjust the settings.

[0057] In one example, adaptability I PEAK The enable signal 434 enables comparators 602 and 604, thereby enabling adaptive I PEAK Enable the scheme. The high threshold register 416 stores the user-configured high threshold, and the low threshold register 418 stores the user-configured low threshold. These thresholds may be expressed as percentages, such as 80% and 50%. The DCD load value is I PEAK If the setting is between 80% and 50%, that information is provided to the HW FSM606, PEAK No changes will be made to the settings. The DCD load value exceeds the high threshold (for example, I PEAK If it exceeds 80% of the setting, PEAKThe setting can be incremented by the HW FSM606. When the DC-DC load value falls below a low threshold (e.g., I PEAK If it falls below 50% of the setting, PEAK The settings can be reduced by the HW FSM606. The HW FSM606 is updated I PEAK The settings are provided in its output 608.

[0058] Figure 7 shows the adaptability I according to various examples in this application. PEAK The hardware finite state machine 606 for the scheme is shown. In one example, the HW FSM606 may be implemented in the controller 104. In another example, the HW FSM606 may be implemented in any suitable hardware.

[0059] Adaptability I PEAK If the scheme is not enabled, the HW FSM606 remains in idle state 702. Adaptability I PEAK The scheme can be enabled by the user. After the scheme is enabled, the HW FSM606 moves to the active state 704. If no update is received from the DCDC load meter 112, the HW FSM606 remains in the active state (load meter update = 0). Subsequently, if the DCDC load meter 112 reports a certain value, the HW FSM606 moves to the load check state 706 (load meter update = 1). After the DCDC load meter 112 reports a load value, that load value is checked against the high and low thresholds of the user configuration in the load check state 706.

[0060] If the measured value is between the low threshold and the high threshold, PEAK The setting is I PEAK It is held in hold state 708. After state 708, HW FSM606 returns to active state 704. If the value in load check state 706 falls below the low threshold, HW FSM606 moves to state 710, I PEAK The setting is reduced (Dec I PEAK). After state 710, HW FSM606 returns to active state 704. If the value in load check state 706 exceeds the high threshold, HW FSM606 moves to state 712, I PEAK The setting is incremented (Inc I PEAK ). After state 712, the LDO regulator 108 is enabled for a short duration and automatically disabled in state 714. Also, if the peak current setting is at its maximum value, the LDO regulator 108 may remain on until the load drops within the capacity of the DC-DC converter 106.

[0061] Figure 8 shows the adaptability I according to various examples in this application. PEAK This is a collection of 800 waveforms for the scheme. Adaptability I PEAK The scheme can be implemented in hardware or digital logic. For example, I PEAK Setting 0 corresponds to a peak current of 25mA, I PEAK Setting 1 corresponds to a peak current of 35mA. The high threshold and low threshold are 80% and 50%, respectively. If the DC-DC load meter output value reaches 90% at setting 0 (e.g., 22.5mA), the hardware will... PEAK Increase the setting from 0 to 1. PEAK After the setting is changed to 1, the peak current is 35mA. The DC-DC load meter value of 22.5mA is the new 1 of 35mA. PEAK It is between 80% and 50% of the setting. If the load current drops to 10mA, I PEAK The setting can be reduced from 1 to 0. Therefore, adaptability I PEAK The scheme improves efficiency by maintaining the peak current setting at an optimal level for the load current. Furthermore, adjusting the peak current setting avoids the need to use the LDO regulator 108 for load sharing when the DC-DC converter 106 can handle the load current. This adaptability I PEAK Without this scheme, the LDO regulator 108 would have to be switched on and off much more frequently to handle the increased load current.

[0062] Waveform 802 represents the load current (I_load). Waveform 804 is the clock signal (clk). Waveform 806 represents the load meter window marker (lm_window_marker). Waveform 808 represents the collection of charge pulses (dcdc_pon) supplied to the inductor coupled to the DC-DC converter 106. Waveform 810 represents the pulse count from the PON counter 210 (dcdc_pon_counter). Waveform 812 represents the load meter measurement window (lm_meas_window). Waveform 814 represents the DC-DC load status (dcdc_load_status), which is the DC-DC load value measured as a percentage of the peak current. Waveform 816 can be stored in the register. PEAK This represents the setting (ipeak_mmr). Waveform 818 represents a user-configurable low threshold, which is 50% in this example. Waveform 820 represents a user-configurable high threshold, which is 80% in this example.

[0063] In one example of operation, the first measurement window ends at time t0. At time t0, the load current is 22.5 mA (waveform 802), which is I PEAK When the setting is 0, it is 90% of the peak current. At time t0, I PEAK The setting is 0, and the DCDC load state is 70 (waveform 814). At the end of the first measurement window at time t0, the PON counter 210 has counted 90 pulses due to the load current being 22.5mA (waveform 810). Therefore, after time t0, the DCDC load state is updated to 90 (waveform 814). The DCDC load state is updated at time t1 (waveform 814). Since the DCDC load state is updated to 90 at time t1, the DCDC load state exceeds the high threshold of 80. Therefore, I PEAK The setting must be incremented. At time t2, I PEAK The setting increments from 0 to 1 (waveform 816). 1 is I PEAKIn this setting, the peak current is 35mA. The load current at time t1 is still 22.5mA, which is 80% of the new peak current setting of 35mA. Therefore, I PEAK After updating the setting from 0 to 1, the load current will be between the 50% and 80% threshold set by the user.

[0064] Time t0 marks the beginning of the second measurement window, as indicated by the load meter window marker in waveform 806. The end of the second measurement window occurs at time t3. At time t3, the PON counter 210 has counted 65 pulses, due to the load current being 22.5mA with a peak current setting of 35mA (waveform 810). At time t5, the DCDC load state is updated (waveform 814). PEAK The setting remains at 1 at time t5.

[0065] Time t4 marks the beginning of the third measurement window. The third measurement window ends at time t6. During the third measurement window, the load current drops to 10mA (waveform 802). Therefore, the PON counter 210 counts 30 pulses during the third measurement window (waveform 810). At time t7, the DCDC load state is updated to 30 (waveform 814). A DCDC load state of 30 falls below the low threshold of 50 (waveform 818). Therefore, I PEAK The setting can be reduced from 1 to 0. At time t8, I PEAK The setting is reduced from 1 to 0 (waveform 816). After each measurement window, the DCDC load state is updated, and if the DCDC load state is outside the high and low thresholds, I PEAK This process of updating the settings may continue after time t8, as described above.

[0066] Figure 9 is a flowchart of Method 900 for safely and reliably disabling the LDO regulator 108, according to various examples in this application. The steps of Method 900 can be performed in any suitable order. In some examples, the hardware components described above with respect to Figures 1, 2, and 4 can perform Method 900. In some examples, any suitable hardware or digital logic can perform Method 900.

[0067] Method 900 begins at 910, where a DC-DC converter, such as DC-DC converter 106, provides load current to load 102. The DC-DC converter can be any suitable voltage regulator.

[0068] Method 900 continues in 920, where a counter counts charging pulses during a certain measurement window, and the charging pulses generate a load current. As an example, a PON counter 210 counts charging pulses. The charging pulses can be carried to an inductor coupled to a DC-DC converter 106 for a predefined duration.

[0069] Method 900 continues in 930, where the latch determines the percentage loading based on the count of charge pulses. In one example, the DC-DC load latch 220 determines the percentage loading. The DC-DC load latch 220 receives the count of charge pulses from the PON counter 210.

[0070] Method 900 continues at 940 where, in response to the percentage loading falling below a predetermined threshold, a disable signal turns off an LDO regulator such as LDO regulator 108. If LDO regulator 108 was previously enabled for load sharing with DCDC converter 106, LDO regulator 108 is turned off. In one example, a digital comparator such as comparator 408 performs a comparison and turns off LDO regulator 108 in response to the percentage loading from the DCDC load value at output 260 falling below the DCDC load threshold from DCDC load threshold encoder 406. When the percentage loading falls below the DCDC load threshold, DCDC converter 106 can handle the load requirements and LDO regulator 108 is not needed.

[0071] Examples in the present application provide a flexible and reliable operating scheme for safely turning off an LDO regulator. The scheme described in the present application avoids unexpected LDO regulator 108 on / off cycles that can cause ripples on the regulated voltage supply rail and result in degraded RF performance on the device. Examples in the present application improve DCDC operation efficiency since the peak current setting is adjusted based on DCDC load conditions. In one example, a 5% improvement in DCDC efficiency can be observed by using an optimal I PEAK setting for a specific load current instead of a maximum I PEAK setting. In an example of the present application, LDO regulator 108 is turned on for load current sharing only when DCDC converter 106 cannot handle the load current demand itself even using the maximum I PEAK setting. In some examples, a software-based scheme can be used for direct control to adjust the I PEAK setting by checking the output of DCDC load meter 112. In other examples, the scheme described in the present application is managed in hardware and does not require a software implementation. The scheme described in the present application may be implemented using digital logic.

[0072] Furthermore, in some examples, the measured load current value is provided after two load meter measurement windows for stable and reliable operation. In some examples, when the LDO regulator 108 is enabled, the LDO regulator 108 remains enabled for at least two load meter measurement windows to avoid frequent LDO regulator 108 on / off cycles. In some examples, the user can define high and low thresholds for the adaptive DC-DC peak current scheme, which provides increased flexibility for various applications.

[0073] The term “coupled” is used throughout this specification. This term may encompass connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A provides signals for controlling device B to perform a certain action, in the first example, device A is coupled to device B, or in the second example, device A is coupled to device B via an intervening component C. In this case, the intervening component C does not substantially alter the functional relationship between device A and device B, and therefore device B is controlled by device A via the control signals provided by device A.

[0074] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) by the manufacturer at the time of manufacture to perform such a function, and / or may be configurable (or reconfigurable) by the user after manufacture to perform such a function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programs, the construction and / or layout of hardware components, and the interconnection of devices, or a combination thereof.

[0075] Unless otherwise stated, “approximately,” “almost,” or “substantially” preceding a value means + / - 10 percent of the stated value. Modifications to the described examples are permitted within the claims, and other examples are also possible.

Claims

1. A device, a direct current-to-direct current (DC-DC) converter configured to provide a load current to a load; a low dropout (LDO) regulator coupled to the DC-DC converter; a controller, determining the load current; turning on the LDO regulator when the load current is above a predetermined threshold; turning off the LDO regulator when the load current is below the predetermined threshold; Counting the number of charge pulses during the measurement window; determining a percentage loading of the DC-DC converter based on the count of the charging pulses; providing said percentage loading to a comparator; The controller configured to: Including, the device.

2. 10. The device of claim 1, The controller: comparing the percentage loading with the predetermined threshold using the comparator; turning off the LDO regulator in response to the comparison; The device further configured as follows.

3. 10. The device of claim 1, The device, wherein the controller is further configured to determine the percentage loading by counting the number of the charge pulses over two or more measurement windows.

4. 10. The device of claim 1, The device, wherein the controller is further configured to enable the comparator after two or more measurement windows.

5. 10. The device of claim 1, The device, wherein the controller is further configured to adjust a peak current setting for the DC-DC converter indicating a maximum current the DC-DC converter can provide to the load.

6. 6. The device of claim 5, The device, wherein the controller is further configured to increase the peak current setting in response to a percentage loading of the DC-DC converter exceeding a threshold.

7. 6. The device of claim 5, The device, wherein the controller is further configured to reduce the peak current setting in response to a percentage loading of the DC-DC converter falling below a threshold.

8. The device of claim 1, The device, wherein the controller includes the comparator.

9. A device, A controller including digital logic, said digital logic comprising: a measurement window generator configured to generate a measurement window; a pulse counter configured to provide a count of charge pulses on an inductor coupled to a direct current-to-direct current (DC-DC) converter during the measurement window; a latch configured to determine a percentage loading based on the count of the charge pulses; a comparator configured to compare the percentage loading to a load threshold and disable a low dropout (LDO) regulator based on the comparison; and a device including the controller,

10. 10. The device of claim 9, The device, wherein the digital logic is further configured to enable the comparator after two or more measurement windows.

11. 10. The device of claim 9, The device further includes an encoder configured to convert a value stored in a register to the load threshold value.

12. 10. The device of claim 9, the digital logic The device further includes peak current adaptation logic configured to receive the percentage loading and adjust a peak current for the DC-DC converter based on the percentage loading.

13. 13. The device of claim 12, The device, wherein the peak current adaptation logic is further configured to compare the percentage loading to a first threshold and a second threshold and adjust the peak current in response to the comparison.

14. 1. A method comprising: providing a load current to a load using a direct current to direct current (DC-DC) converter; counting charge pulses that generate the load current during a measurement window; determining a percentage loading based on the count of the charge pulses; turning off a low dropout (LDO) regulator in response to the percentage loading falling below a predetermined threshold; A method comprising:

15. 15. The method of claim 14, The method wherein the charging pulse is a pulse on an inductor coupled to the DC-DC converter.

16. 1. A method comprising: providing a load current to a load using a direct current to direct current (DC-DC) converter; counting charge pulses that generate the load current during a measurement window; determining a percentage loading based on the count of the charge pulses; turning off a low dropout (LDO) regulator in response to the percentage loading being below a predetermined threshold; adjusting a peak current setting for the DC-DC converter indicating the maximum current the DC-DC converter can provide to the load; A method comprising:

17. 17. The method of claim 16, enabling the comparator after two or more measurement windows; comparing the percentage loading with the predetermined threshold using the comparator; turning off the LDO regulator in response to an output of the comparator; The method further comprises:

18. 17. The method of claim 16, The method further includes increasing the peak current setting if a percentage loading of the DC-DC converter exceeds a threshold.

19. 20. The method of claim 18, The method further includes turning on the LDO regulator in response to the percentage loading exceeding the threshold.

20. 17. The method of claim 16, The method further includes reducing the peak current setting when a percentage loading of the DC-DC converter falls below a threshold.

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