Semiconductor element
Patent Information
- Application Number
- JP2022188692
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2021-11-29
- Filing Date
- 2022-11-25
- Publication Date
- 2025-09-17
Smart Images
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Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a semiconductor device, a method for manufacturing the semiconductor device, and the like. [Background technology]
[0002] In recent years, as the Internet of Things (IoT) has become more widespread in society, various things are being connected to the Internet, and a wide variety of semiconductor elements are beginning to be required. These diverse semiconductor elements use various substrates, and for example, flexible semiconductor elements fabricated using flexible substrates and semiconductor elements that can be manufactured using materials that can be applied to simple processes such as printing are being actively studied.
[0003] Carbon nanotubes (CNTs) have high field-effect mobility and high chemical stability. Furthermore, because CNTs can be dispersed in solutions, they are a material that can be easily processed and can be applied or formed into films on a variety of substrates. Therefore, CNTs are considered a candidate material for forming semiconductor layers, and semiconductor elements using CNTs are being actively investigated. Specifically, vigorous research is being conducted on CNT field-effect transistors (CNT-FETs), which use CNTs as the channel.
[0004] Patent Document 1 discloses a method of dropping CNT ink into a channel layer formation region between a source electrode and a drain electrode, drying the ink, and forming a channel layer composed of CNTs between the source electrode and the drain electrode. Patent Document 2 discloses a method of dropping a dispersion solution in which CNT bundles are dispersed in an organic solvent between the source electrode and the drain electrode, and heating the dropped dispersion solution to form a channel portion. Patent Document 3 discloses a method of manufacturing a field-effect transistor, including the steps of applying a CNT dispersion solution containing polysaccharides, arabinogalactan, or gum arabic as a polymer dispersant to form a coating film, and drying the coating film to form a semiconductor layer. In the manufacturing method disclosed in Patent Document 3, preferably, the dried coating film, i.e., the semiconductor layer, is washed to improve the on / off ratio.
[0005] Non-Patent Document 1 discloses that a semiconductor layer consisting of a high-density, non-uniform random network of CNTs is covered with a fluorine-based resin to reduce hysteresis. Non-Patent Document 2 discloses that an independent CNT is used as a channel and the semiconductor element is sealed with PMMA (polymethyl methacrylate). [Prior art documents] [Patent documents]
[0006] [Patent Document 1] WO2019 / 066074 publication [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-71898 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-53607 [Non-patent literature]
[0007] [Non-Patent Document 1] Appl. Master. Interface, 2014, 6, 8441. [Non-patent document 2] Nano Lett., 2003, 3, 193. Summary of the Invention [Problem to be solved by the invention]
[0008] The performance of a semiconductor element has a large effect on the performance of a device in which it is used, and therefore semiconductor elements are required to have higher performance, specifically, smaller hysteresis.
[0009] The semiconductor elements disclosed in Patent Documents 1 to 3 have a problem of large hysteresis because they operate with the channel layer or semiconductor layer exposed to the atmosphere. In the semiconductor element disclosed in Non-Patent Document 2, hysteresis is significantly reduced by sealing the semiconductor element with PMMA. However, because only one nano-sized CNT is used, only a small amount of current can flow, and mass production is difficult with current technology. The semiconductor element disclosed in Non-Patent Document 1 has succeeded in reducing hysteresis by sealing the semiconductor layer with a fluorine-based resin. However, the sealing causes the on / off ratio of the semiconductor element to become worse than when it is not sealed. 4 This is insufficient for practical use. Thus, in the prior art, an attempt to reduce hysteresis results in a worsening of the on / off ratio, and conventionally, there has been a trade-off between a small hysteresis and a large on / off ratio.
[0010] In one aspect, the present disclosure provides a semiconductor element using CNTs that has small hysteresis and a large on / off ratio, and a method for producing the same. [Means for solving the problem]
[0011] In one aspect, the present disclosure relates to a semiconductor device comprising: a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode; and a gate insulating layer insulating the semiconductor layer from the gate electrode, wherein the semiconductor layer comprises a carbon nanotube network structure, the semiconductor layer is sealed with a sealing layer, and the semiconductor layer has an average film thickness of 5 nm or less.
[0012] The present disclosure relates to a method for manufacturing a semiconductor element according to one embodiment of the present disclosure, the method comprising a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer that insulates the semiconductor layer from the gate electrode, the method comprising: using a carbon nanotube dispersion to form a semiconductor layer that includes a carbon nanotube network structure and has an average film thickness of 5 nm or less; and forming a sealing layer that seals the semiconductor layer. [Effects of the Invention]
[0013] According to the present disclosure, it is possible to provide a semiconductor element using CNTs that has small hysteresis and a large on / off ratio. [Brief explanation of the drawings]
[0014] [Figure 1] FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic cross-sectional view of the semiconductor element shown in FIG. [Figure 3] FIG. 3 is a schematic diagram illustrating the network structure of carbon nanotubes that constitute the semiconductor element according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 5] 5A to 5C are diagrams showing the steps of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 6] 6A to 6C are diagrams showing the steps of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. [Figure 7] FIG. 7 is an atomic force microscope (AFM) image of the semiconductor layer that constitutes the semiconductor element of Example 1. [Figure 8] FIG. 8 is a schematic diagram illustrating the network structure of carbon nanotubes that constitute a conventional semiconductor element. DETAILED DESCRIPTION OF THE INVENTION
[0015] CNTs are thin, cylindrical structures formed by rolling graphene sheets. The CNT network structure is a wide-area network structure in which adjacent CNTs are entangled and interconnected. However, if the CNT density in the thickness direction of the network structure is high, for example, as shown in Figure 8, there are many areas within the network structure where two CNTs intersect and one or more CNTs are stacked above or below the intersections of these two CNTs. For example, if the CNT network structure is a multilayer structure consisting of multiple stacks of "substantially single-layer CNT films," the gate voltage will not be sufficient to apply to CNTs located relatively far from the gate electrode. This is thought to result in an insufficient decrease in the off current, resulting in a deterioration (decreased) of the on / off ratio. In addition, covering the semiconductor layer with an encapsulation layer to limit exposure of the semiconductor layer containing the CNT network structure to the atmosphere is considered effective from the viewpoint of reducing hysteresis. However, when the CNT network structure is a multilayer structure, the material of the encapsulation layer penetrates between the layers during the manufacturing process. Therefore, it is presumed that it becomes even more difficult to apply gate voltage to CNTs located relatively far from the gate electrode, resulting in a further deterioration of the on / off ratio.
[0016] Thus, in conventional technology, there was a trade-off between a small hysteresis and a large on / off ratio. The present disclosure has discovered that by forming a substantially single-layer CNT network structure and then forming a sealing layer to prevent contact between the semiconductor layer and the atmosphere, it is possible to reduce hysteresis while maintaining a large on / off ratio. The fact that the CNT network structure is substantially single-layered can be confirmed by the average film thickness of the semiconductor layer being 5 nm or less. In this specification, a substantially single-layer CNT network structure may be referred to as a "substantially single-layer CNT film."
[0017] The substantially single-layer CNT film preferably has a CNT network structure in which two CNTs 50 cross each other and are connected in a mesh-like pattern in the planar direction by repeating this process, as shown in Fig. 3. The substantially single-layer CNT film preferably has substantially no, more preferably almost no, and even more preferably no, portions in which three or more CNTs are stacked in the thickness direction (the direction perpendicular to the surface of the semiconductor layer 5). Whether the semiconductor layer is a substantially single-layer CNT film can be confirmed by cross-sectional observation using an atomic force microscope (AFM).
[0018] Hereinafter, a semiconductor device according to one embodiment of the present disclosure will be described with reference to the drawings.
[0019] As shown in FIGS. 1 and 2 , in one embodiment, the semiconductor element of the present disclosure is a CNT field-effect transistor (CNT-FET), preferably a p-type CNT field-effect transistor. The semiconductor element 1 includes a gate electrode 2, a source electrode 3, a drain electrode 4, and a semiconductor layer 5. A gate insulating layer 6 is disposed between the semiconductor layer 5 and the gate electrode 2, and the gate insulating layer 6 insulates the semiconductor layer 5 from the gate electrode 2. The source electrode 3 and the drain electrode 4 are formed on the surface of the semiconductor layer 5 opposite the surface facing the gate insulating layer 6, with a predetermined gap (channel length) between them. A portion (channel region) of the semiconductor layer 5 disposed between the source electrode 3 and the drain electrode 4 is covered with a sealing layer 8 to prevent contact of the semiconductor layer 5 with the atmosphere. In the semiconductor element 1, the semiconductor layer 5 includes a CNT network structure that is easy to manufacture and can pass a large amount of current.
[0020] [Semiconductor layer] The semiconductor layer 5 is composed of a CNT network structure. In this disclosure, a network structure refers to a structure in which the CNTs in the semiconductor layer are not oriented in a specific direction, and each CNT preferably intersects with five or more other CNTs. The CNTs are randomly oriented in two dimensions, meaning that they are scattered in all directions without being aligned in a single direction. This network structure of CNTs allows a large current to flow through the semiconductor layer, and the lack of orientation in a specific direction prevents anisotropy in conductivity. Furthermore, in this network structure, instead of a single CNT connecting the source and drain electrodes, multiple CNTs form a conductive path between the source and drain electrodes. Therefore, even if a trace amount of metallic CNT is mixed in, a good on / off ratio can be obtained without short-circuiting the source and drain electrodes.
[0021] In the present disclosure, the CNT network structure is substantially a single-layer CNT film. From the viewpoints of reducing hysteresis and improving the on / off ratio, the average film thickness of the semiconductor layer 5 is 5 nm or less, preferably 4 nm or less, and more preferably 3 nm or less. From the viewpoint of ensuring a sufficient amount of current, the average film thickness of the semiconductor layer 5 is preferably 0.1 nm or more, more preferably 0.3 nm or more. In the present disclosure, the average film thickness of the semiconductor layer 5 can be measured using an atomic force microscope (AFM).
[0022] Furthermore, to obtain the effect of a substantially single-layer CNT film, it is preferable that the CNTs are in a non-aggregated, unbundled state. A bundled state is a state in which multiple CNTs are attached to each other and bundled together. If such CNTs are used in the semiconductor layer, it will be difficult to apply gate voltage and the on / off ratio will deteriorate, just as in the case of using multi-layered CNTs. A CNT can be said to be in a bundled state when 10% or more of its length overlaps with other CNTs. Since the diameter of a CNT is approximately 1 to 2 nm, if the average thickness of the semiconductor layer is 5 nm or less, the semiconductor layer will be substantially free of bundles (i.e., in a non-bundled state).
[0023] The density of the carbon nanotube network is 100 tubes / μm to obtain sufficient drain current. 2 It is preferable that the density is 8000 fibers / μm or more. Furthermore, if the density is too high, a conductive path is formed between the source and drain electrodes by a small amount of metallic CNT mixed in, causing a short circuit between them, resulting in a decrease in the on / off ratio. In the present disclosure, from the viewpoint of suppressing a decrease in the on / off ratio, the density is set to 8000 fibers / μm 2 It is preferable that:
[0024] The CNTs constituting the semiconductor layer 5 may be single-walled carbon nanotubes (SWCNTs) alone, in which a graphene sheet is wound into one layer, or a mixture of SWCNTs with double-walled carbon nanotubes (DWCNTs) wound into two layers, or multi-walled carbon nanotubes (MWCNTs) wound into three or more layers, but from the viewpoint of reducing leakage current and ensuring a sufficient on / off ratio, it is preferable to be composed essentially of SWCNTs alone, and more preferable to be composed of SWCNTs alone. These CNTs can be distinguished by known means, such as Raman spectroscopy.
[0025] CNTs are classified into metallic CNTs, which exhibit metallic properties, and semiconducting CNTs, which exhibit semiconducting properties. Semiconducting CNTs are preferred as the CNTs constituting the semiconductor layer 5. CNTs may be synthesized by conventionally known synthesis methods, such as the high-pressure carbon monoxide disproportionation method (HiPco method), the improved direct injection pyrolysis synthesis method (e-DIPS method), the arc discharge method, and the laser ablation method. However, SWCNTs synthesized by these general synthesis methods are mixtures containing approximately one-third metallic SWCNTs and approximately two-thirds semiconducting SWCNTs. Therefore, it is preferable to form the semiconductor layer 5 using a CNT dispersion obtained by applying a technique to the mixture to increase the content of semiconducting SWCNTs. The content of semiconducting CNTs in the CNTs constituting the semiconductor layer 5 is preferably 70% by mass or more, more preferably 80% by mass or more, even more preferably 90% by mass or more, and even more preferably 95% by mass or more.
[0026] In the present disclosure, the content of semiconducting CNTs in the semiconductor layer 5 can be considered as the proportion of semiconducting CNTs to the total amount of CNTs (the sum of semiconducting CNTs and metallic CNTs) in the CNT dispersion used to form the semiconductor layer 5. In the present disclosure, the proportions of semiconducting CNTs in the CNT dispersion and in the semiconductor layer 5 can be calculated, for example, from the results of Raman spectrum measurement using a Raman spectrophotometer described in the Examples.
[0027] The average diameter of SWCNTs is preferably 0.5 nm or more, more preferably 0.8 nm or more, from the viewpoint of ensuring sufficient field-effect mobility, and is preferably 3 nm or less, more preferably 2 nm or less, from the viewpoint of providing an appropriate band gap as a semiconductor, suppressing leakage current, and ensuring a sufficient on / off ratio. The average diameter of SWCNTs can be calculated by measuring the diameters of 10 or more CNTs from images obtained using a transmission electron microscope and averaging them.
[0028] The average length of the SWCNTs is preferably 0.1 μm or more, more preferably 0.3 μm or more, and even more preferably 0.5 μm or more, from the viewpoint of reducing CNT intersections and ensuring sufficient mobility. Furthermore, from the viewpoint of reducing leakage current due to mixed metallic CNTs and ensuring a sufficient on / off ratio, the average length is preferably shorter than the distance between the source and drain electrodes (channel length) of the semiconductor element, more preferably 2 / 3 or less of the channel length, and even more preferably 1 / 2 or less of the channel length. For example, it is preferably 100 μm or less, more preferably 50 μm or less, even more preferably 20 μm or less, and even more preferably 10 μm or less. The average length of the SWCNTs can be calculated, for example, by measuring the lengths of 10 or more CNTs from an image obtained using a transmission electron microscope and averaging the lengths.
[0029] In the present disclosure, the semiconductor component of the semiconductor layer 5 preferably does not include an organic semiconductor made of a conjugated polymer, and is more preferably formed solely of carbon nanotubes. If an organic semiconductor made of a conjugated polymer is included, it becomes difficult to form a substantially single-layer CNT film, and the thickness of the semiconductor layer becomes 5 nm or more. Furthermore, since organic semiconductors made of conjugated polymers have poor electrical properties such as low mobility, the inclusion of an organic semiconductor made of a conjugated polymer other than carbon nanotubes in the semiconductor layer impairs the excellent electrical properties of the CNT-FET, such as high mobility.
[0030] Examples of organic semiconductors made of conjugated polymers include polythiophene-based polymers, polypyrrole-based polymers, polyaniline-based polymers, polyacetylene-based polymers, poly-p-phenylene-based polymers, and poly-p-phenylenevinylene-based polymers.
[0031] Like organic semiconductors made from conjugated polymers, carbon nanotubes also have a conjugated system of carbon atoms and can be considered a type of organic semiconductor. However, the charge transport mechanism in the semiconductor layer of field-effect transistors (CNT-FETs) that use a carbon nanotube network structure as the semiconductor layer is significantly different from that of field-effect transistors (OFETs) that use other organic semiconductors as the semiconductor layer. In CNT-FETs, charges are transported along the mesh-like CNT network, resulting in high charge mobility and enabling high-speed operation. In contrast, in OFETs, the semiconductor layer is formed from the crystalline structure of the organic semiconductor, and charges are transported by hopping between adjacent organic semiconductor molecules, resulting in low charge mobility and not being suitable for high-speed operation.
[0032] [Sealing layer] In the semiconductor device 1 of the present disclosure, the semiconductor layer 5 is sealed with a sealing layer 8 that prevents the semiconductor layer 5 from coming into contact with the outside air in order to make the semiconductor layer 5 waterproof and dustproof. The sealing layer 8 may be composed of a single layer, or may be composed of a laminate of multiple layers. The sealing layer 8 may be formed from a conventionally known material, but from the viewpoint of reducing hysteresis, it preferably contains a compound having a solubility parameter value (hereinafter also referred to as "SP value") of 15 or less, calculated by the Fedors method using the following formula (1). From the same viewpoint, the SP value of the material of the sealing layer 8 is more preferably 14 or less, even more preferably 11 or less, and even more preferably 9 or less. Furthermore, from the viewpoint of availability, it is preferably 3 or more, more preferably 4 or more, and even more preferably 5 or more. The unit of the SP value is (cal / cm 3 ) 1 / 2 is. δ=[ΣE coh / ΣV] 1 / 2 (1) In the above formula (1), ΣE cohdenotes the cohesive energy, and ΣV denotes the molar volume.
[0033] Furthermore, in order to avoid affecting the electrical characteristics of the semiconductor element, the lower the relative dielectric constant of the material for encapsulation layer 8, the better, preferably 5.0 or less, more preferably 4.0 or less. There is no particular lower limit for the relative dielectric constant, but it is usually 1.0 or more. The relative dielectric constant of the material forming encapsulation layer 8 is a value measured by the method described in the Examples. In addition, the material for encapsulation layer 8 is preferably an electrically inactive compound that does not dope electrons or holes into the semiconductor layer.
[0034] The material for the encapsulation layer 8 is preferably a hydrophobic polymer, and specifically, from the viewpoint of not causing a side reaction with the SWCNTs during encapsulation and not deteriorating the performance of the semiconductor element, at least one polymer selected from acrylic resins, styrene resins, vinyl resins, olefin resins, and fluorine resins is preferably used.
[0035] Examples of acrylic resins include polymethyl methacrylate (PMMA), polybutyl methacrylate, and polycyclohexyl methacrylate. Examples of styrene resins include polystyrene (P-St), acrylonitrile-styrene copolymer (AS), and acrylonitrile-butadiene-styrene copolymer (ABS). Examples of vinyl resins include polyvinyl acetate, polyvinyl chloride resin (PVC), polyvinyl alcohol (PVA), polyvinyl butyral, and polyvinylpyrrolidone (PVP). Examples of olefin resins include polyethylene, polypropylene, cycloolefin polymer (COP), and cycloolefin copolymer (COC). Examples of fluorine-based resins include commercially available products such as CYTOP (registered trademark) CTL-809A (manufactured by AGC Corporation). The material for sealing layer 8 may be one of these resin materials or a combination of two or more of them. Furthermore, among these, the material of the sealing layer 8 is preferably one or more polymers selected from polyvinyl alcohol (PVA: SP value 14.6), polyvinylpyrrolidone (PVP: SP value 13.4), polyvinyl chloride resin (PVC: SP value 11.0), polystyrene (P-St: SP value 10.5), polymethyl methacrylate (PMMA: SP value 9.9), and CYTOP (registered trademark) CTL-809A (SP value 8.7, manufactured by AGC).
[0036] The average thickness of the sealing layer 8 in the region (channel region) between the source electrode 3 and the drain electrode 4 (the sum of the average thicknesses of the layers when the sealing layer is formed by laminating multiple layers) is preferably 200 nm or more, more preferably 500 nm or more, and even more preferably 1000 nm or more, from the viewpoint of ensuring sufficient barrier properties against moisture, oxygen, etc. and reducing hysteresis. There is no particular upper limit to the average thickness of the sealing layer, but it is preferably 1 mm or less. In the present disclosure, the average thickness of the sealing layer 8 can be measured using an atomic force microscope (AFM) or a stylus-type surface profilometer.
[0037] [Source electrode, drain electrode] The source electrode 3 and the drain electrode 4 are electrically connected by the CNT network structure of the semiconductor layer 5, which functions as a channel. The materials for the source electrode 3 and the drain electrode 4 are not particularly limited as long as they are conductive, and examples include metals such as titanium, copper, gold, platinum, chromium, aluminum, palladium, and molybdenum, semiconductors such as polysilicon, and conductive metal oxides such as indium tin oxide (ITO). The source electrode 3 and the drain electrode 4 may have a multilayer structure made of two or more metals. Methods for forming these electrodes include conventionally known methods, such as vacuum deposition, electron beam deposition, sputtering, plating, CVD, ion plating coating, inkjet deposition, and printing, depending on the material.
[0038] The channel length (L) and channel width (W) may be conventionally known dimensions, with the channel length (L) being, for example, 10 μm or more and 1000 μm or less, and the channel width (W) being, for example, 10 μm or more and 10,000 μm or less, but the present disclosure is not limited to these.
[0039] [Gate electrode, gate insulating film] The semiconductor element 1 according to one embodiment of the present disclosure is a so-called bottom-gate semiconductor element, in which the silicon substrate functions as the gate electrode 2, and a thermal oxide film SiO2 formed on one main surface of the silicon substrate functions as the gate insulating film 6. In the example shown in FIGS. 1 and 2, the entire surface of one main surface of the silicon substrate is covered with the gate insulating film 6, but it is sufficient that at least the region where the source electrode 3, the drain electrode 4, and the semiconductor layer 5 are arranged is covered with the gate insulating layer 6.
[0040] The gate insulating layer 6 may have a single-layer structure, a multi-layer structure, or a partially multi-layer structure. The total thickness of the gate insulating layer 6 is preferably 10 nm or more, more preferably 20 nm or more, from the viewpoint of sufficiently reducing the gate leakage current. Furthermore, from the viewpoint of reducing the operating voltage, it is preferably 500 nm or less, more preferably 200 nm or less. Examples of materials for the gate insulating layer include inorganic compounds such as silicon oxide, silicon nitride, and hafnium oxide, and organic compounds such as vinylphenol resin, paraxylene resin, vinylidene fluoride resin, and polyimide.
[0041] The semiconductor device of the present disclosure is not limited to a configuration in which a silicon substrate functions as the gate electrode 2, but may also be a configuration in which a substrate is provided with an insulating surface on which at least an electrode is disposed, and a gate electrode is disposed on the substrate. The substrate may be, for example, an inorganic material such as glass, sapphire, alumina sintered body, silicon wafer, or a substrate of any of these with an oxide film covering its surface, or may be a sheet made of polyimide (PI) resin, polyester resin, polyamide resin, epoxy resin, polysulfone resin, polyamide resin, or the like, or a film-like flexible material made of any of these.
[0042] The material for the gate electrode is not particularly limited as long as it is conductive, and examples thereof include metals such as gold, platinum, chromium, titanium, and aluminum. The gate electrode is formed, for example, by depositing these metals at a desired position. A separately prepared metal thin film may be disposed at a desired position on the substrate to serve as the gate electrode. Methods for forming these electrodes include conventionally known methods such as vacuum deposition, electron beam deposition, sputtering, plating, CVD, ion plating coating, inkjet printing, and the like, depending on the material.
[0043] The semiconductor element of the present disclosure can be of various types, such as a back gate type, a side gate type, and a top gate type, depending on the position of the gate electrode.
[0044] 4, in order to enhance the adsorptivity of CNTs, the semiconductor element of the present disclosure preferably has a structure in which the surface of the gate insulating layer 6 is treated with a surface treatment agent to form an adsorption layer 9, and the adsorption layer 9 is disposed between the semiconductor layer 5 and the gate insulating layer 6 and in contact with them. Because the presence of a compound having an anionic group on the gate insulating layer 6 can cause charge trapping, which can increase hysteresis or reduce the on / off ratio, it is preferable that the adsorption layer 9 be formed from a compound having no anionic group.
[0045] The adsorption layer 9 is preferably formed of, for example, a silane coupling agent having no anionic group, such as 3-aminopropyltriethoxysilane (APTES), methyltriethoxysilane (MTES), methyltrimethoxysilane (MTMS), N-2-(aminoethyl)-3-aminopropyltrimethoxysilane, octadecyltrichlorosilane (OTS), fluorine-substituted octatrichlorosilane (PFOTS), tetracyanoquinodimethane, etc. The adsorption layer 9 may be formed, for example, by dissolving these materials in an organic solvent and applying the resulting solution to the gate insulating layer 6 by a coating method such as dip coating, or by a vapor phase method.
[0046] [Method of manufacturing semiconductor devices] Next, a method for manufacturing the semiconductor element 1 shown in Figures 1 and 2 will be described. Figures 5A to 5C and Figures 6A to 6C are cross-sectional views showing the manufacturing method for the semiconductor element 1 in the order of steps.
[0047] 5A, a gate electrode 2 is prepared, one of whose main surfaces is covered with a gate insulating film 6. Specifically, a silicon substrate (gate electrode 2) is prepared, the one of whose main surfaces is thermally oxidized to have a silicon oxide (SiO2) layer (gate insulating film 6).
[0048] Next, as shown in FIG. 5B, the CNT dispersion is applied to the entire surface of the gate insulating film 6 opposite the surface facing the gate electrode 2 to form a coating film 15. The coating is then left to stand for a while to allow the CNTs to fully adsorb to the surface of the gate insulating film 6. Then, before drying, excess CNTs are removed from the coating film 15 to reduce the thickness of the coating. The remaining coating is then dried to form a substantially single-layer CNT film as the semiconductor layer 5′, as shown in FIG. 5C. The CNT dispersion can be applied by a method such as dripping the CNT dispersion using a dispenser, printing methods such as inkjet printing, screen printing, and offset printing, spin coating, or dip coating. Among these, the dripping method using a dispenser and spin coating are preferred from the viewpoint of forming a highly homogeneous CNT network structure. The CNTs are adsorbed to the surface to which the CNT dispersion is applied (the surface of the gate insulating film 6, or the surface of the adsorption layer 9 (see FIG. 4) if the CNT dispersion is applied to the surface of the adsorption layer 9) through hydrophobic interactions between the CNTs and the surface to be coated. Excess CNTs are preferably removed from the coating film 15 by a washing treatment described below before drying. A substantially single-layer CNT film can be formed by appropriately adjusting the thickness of the coating film 15 before washing, the CNT concentration in the CNT dispersion, the time between application of the CNT dispersion and washing, and the like.
[0049] (CNT dispersion) The CNT dispersion contains CNTs and a dispersion medium, and optionally a dispersant for CNTs. The CNT concentration in the CNT dispersion is preferably 0.1 μg / mL or more, more preferably 0.5 μg / mL or more, and even more preferably 1.0 μg / mL or more, from the viewpoint of ensuring a sufficient amount of current, and is preferably 7.0 μg / mL or less, more preferably 5.0 μg / mL or less, and even more preferably 3.0 μg / mL or less, from the viewpoint of forming a substantially single-layered, homogeneous CNT network structure.
[0050] The dispersion medium is preferably an aqueous medium, and the aqueous medium is preferably pure water, ion-exchanged water, purified water, or distilled water, and more preferably pure water. The aqueous medium may contain, in addition to water, a lower alcohol such as methanol, ethanol, or isopropyl alcohol, or a water-soluble organic solvent such as acetone, tetrahydrofuran, or dimethylformamide.
[0051] In one embodiment of the present disclosure, it is preferable to form the semiconductor layer 5 using, for example, a CNT dispersion obtained by applying a technique for increasing the content of semiconducting CNT in a mixture of metallic CNT and semiconducting CNT. In one embodiment of the present disclosure, it is preferable to form the semiconductor layer 5 using, for example, a semiconducting SWCNT dispersion obtained by a method described in JP 2021-080121 A, JP 2021-080120 A, JP 2021-080119 A, or JP 2019-202912 A. These semiconducting SWCNT dispersions contain, for example, an acrylic acid-based resin as a dispersant for CNT. Examples of the acrylic acid-based resins disclosed in these publications include polyacrylic acid, copolymers of acrylic acid and phenoxydioxyethylene acrylate (PDEA), copolymers of acrylic acid and methoxydioxypropylene acrylate (MDPA), copolymers of acrylic acid and polyethylene glycol monoacrylate (average number of moles of ethyleneoxy groups added: 2 to 10), and homopolymers such as polyethylene glycol monomethacrylate (average number of moles of ethyleneoxy groups added: 2 to 45).
[0052] The content of semiconducting CNTs in the CNTs contained in the semiconducting SWCNT dispersion is preferably 70% by mass or more, more preferably 80% by mass or more, even more preferably 90% by mass or more, and even more preferably 95% by mass or more.
[0053] The time period from immediately after forming the coating film 15 until the cleaning process for removing excess CNTs is preferably 1 minute or more, more preferably 5 minutes or more, even more preferably 10 minutes or more, and even more preferably 30 minutes or more, from the viewpoint of ensuring proper adsorption of the CNTs to the underlying layer, i.e., the gate insulating layer 6 or the adsorption layer 9, and from the viewpoint of productivity, is preferably 180 minutes or less, more preferably 120 minutes or less, and even more preferably 90 minutes or less.
[0054] [Cleaning process] In one embodiment of the method for manufacturing a semiconductor element according to the present disclosure, the semiconductor layer 5 is formed by applying a CNT dispersion to a surface to be coated to form a coating film, allowing the CNTs to adsorb onto the surface to be coated, removing excess CNTs from the coating film while it is still wet, and then performing a drying process to form the semiconductor layer. Here, "wet" refers to a state before the dispersion medium, which is a component of the CNT dispersion, has completely evaporated, e.g., a state before the drying process described below is started. The removal of excess CNTs from the coating film 15 is carried out, for example, by a washing process. After the above-mentioned standing time has elapsed and the CNTs have properly adsorbed to the lower layer, the washing process can be carried out, for example, by pouring a washing solution onto the coating film 15 or by immersing a laminate including the coating film 15, the gate insulating layer 6, and the gate electrode 2 in a washing solution in a bath. From the viewpoint of forming a substantially single-layer CNT film with a homogeneous CNT network structure, a preferred washing method is to immerse the laminate including the coating film 15 in a washing solution in a bath. As the washing solution, for example, ultrapure water, alcohols such as ethanol and methanol, or polar solvents such as acetone and tetrahydrofuran (THF) are preferred so as not to remove the CNTs adsorbed to the lower layer and constituting a substantially single-layer CNT film. The immersion time is preferably 1 minute or longer, more preferably 3 minutes or longer, even more preferably 5 minutes or longer, even more preferably 10 minutes or longer, even more preferably 30 minutes or longer, and preferably 180 minutes or shorter, more preferably 120 minutes or shorter, even more preferably 90 minutes or shorter, and even more preferably 80 minutes or shorter.
[0055] The coating film 15 washed as described above is subjected to a drying treatment to volatilize the dispersion medium and form a semiconductor layer 5'. The drying treatment is carried out, for example, by placing the coating film 15 in an atmosphere set at a predetermined temperature. The temperature of the atmosphere is preferably 50°C or higher, more preferably 80°C or higher, even more preferably 100°C or higher, and preferably 250°C or lower, more preferably 220°C or lower, and even more preferably 200°C or lower. The drying time is preferably 5 minutes or longer, more preferably 10 minutes or longer, even more preferably 20 minutes or longer, even more preferably 30 minutes or longer, and preferably 240 minutes or shorter, more preferably 180 minutes or shorter, even more preferably 120 minutes or shorter, and even more preferably 90 minutes or shorter.
[0056] 6A, the source electrode 3 and the drain electrode 4 are formed on the semiconductor layer 5′. The source electrode 3 and the drain electrode 4 may be formed by a conventionally known method, for example, by placing a metal mask on the surface of the semiconductor layer 5′ opposite the surface on the gate insulating film 6 side, and vacuum-depositing a metal material to become the source electrode 3 and the drain electrode 4, respectively, into the openings of the metal mask.
[0057] Next, as shown in FIG. 6B, after removing excess portions of the semiconductor layer 5′ by etching, the silicon substrate 2 on which the source electrode 3 and the drain electrode 4 are formed is heated at 100°C or higher and 200°C or lower for 30 minutes or higher and 60 minutes or lower to remove traces of moisture adsorbed on the gate insulating layer 6 and the semiconductor layer 5 and to anneal the silicon substrate.
[0058] 6C, a sealing layer 8 is formed on a portion (channel region) of the semiconductor layer 5 that is located between the source electrode 3 and the drain electrode 4. Specifically, for example, a resin solution that forms the sealing layer 8 is applied by a coating method such as spin coating, and then dried as necessary to form the sealing layer 8.
[0059] The present application further discloses the following semiconductor element and its manufacturing method.
[0060] <1> a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode; the semiconductor layer includes a carbon nanotube network structure, the semiconductor layer is sealed with a sealing layer; A semiconductor device, wherein the semiconductor layer has an average film thickness of 5 nm or less. <2> a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode; the semiconductor layer includes a network structure of single-walled carbon nanotubes, the semiconductor layer is sealed with a sealing layer having a relative dielectric constant of 5.0 or less, The average film thickness of the semiconductor layer is 0.1 nm or more and 5 nm or less. <1> The semiconductor element according to claim 1. <3> a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode; the semiconductor layer includes a network structure of single-walled carbon nanotubes, the content of semiconducting carbon nanotubes in the carbon nanotubes contained in the semiconductor layer is 70 mass% or more, the semiconductor layer is sealed with a sealing layer containing at least one resin selected from the group consisting of a fluorine-based resin, an acrylic resin, a styrene-based resin, a vinyl-based resin, and an olefin-based resin; The average thickness of the sealing layer is 200 nm or more, The average film thickness of the semiconductor layer is 0.1 nm or more and 5 nm or less. <1> or <2> The semiconductor element according to claim 1. <4> The sealing layer has an SP value calculated by the Fedors method of 3 (cal / cm 3 ) 1 / 2 More than 15(cal / cm 3 ) 1 / 2 including a compound which is <1> ~ <3> 10. The semiconductor element according to claim 9, wherein <5> an adsorption layer disposed between the semiconductor layer and the gate insulating film and in contact with the semiconductor layer and the gate insulating film, the adsorption layer being made of a compound having no anionic group; <1> ~ <4> 10. The semiconductor element according to claim 9, wherein <6> the adsorption layer is formed of a silane coupling agent having no anionic group; <5> The semiconductor element according to claim 1. <7> In the network structure, the density of carbon nanotubes is 100 / μm 2 More than 8000 lines / μm 2 Below is the <1> ~ <6> 10. The semiconductor element according to claim 9, wherein <8> In the network structure, the average length of the carbon nanotubes is shorter than the channel length of the semiconductor device. <1> ~ <7> 10. The semiconductor element according to claim 9, wherein <9> In the network structure, the average diameter of the carbon nanotubes is 0.5 nm or more and 3 nm or less. <1> ~ <8> 10. The semiconductor element according to claim 9, wherein <10> A method for manufacturing a semiconductor device including a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode, A method for manufacturing a semiconductor element, comprising: forming a semiconductor layer containing a carbon nanotube network structure and having an average film thickness of 5 nm or less using a carbon nanotube dispersion; and forming a sealing layer that seals the semiconductor layer. <11> A method for manufacturing a semiconductor device including a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode, forming a coating film by applying the carbon nanotube dispersion liquid to a surface to be coated, allowing the carbon nanotubes to adsorb onto the surface to be coated, removing excess carbon nanotubes from the coating film while the coating film is still wet, and then performing a drying treatment to form the semiconductor layer. <10> 10. A method for manufacturing a semiconductor element according to claim 9. <12> The manufacturing method of the semiconductor device according to <11>, wherein the carbon nanotube concentration of the carbon nanotube dispersion liquid is 0.1 μg / mL or more and 7.0 μg / mL or less. <13> The manufacturing method of the semiconductor device according to <11> or <12>, wherein the removal of the excess carbon nanotubes is performed by immersing the coating film in a cleaning liquid. <14> The manufacturing method of the semiconductor device according to any one of <10> to <13>, including adjusting the carbon nanotube dispersion liquid containing an acrylic resin.
Example
[0061] Hereinafter, the present disclosure will be described in more detail with reference to examples, but these are exemplary and the present disclosure is not limited to these examples.
[0062] 1. Measurement methods of various parameters [Measurement of the weight average molecular weight of the polymer] The weight average molecular weight of the polymer used for the preparation of the SWCNT dispersion liquid was measured under the following conditions using gel permeation chromatography (hereinafter also referred to as "GPC"). <GPC conditions> Measuring device: HLC―8320GPC (manufactured by Tosoh Corporation) Column: α―M + α―M (manufactured by Tosoh Corporation) Eluent: 60 mmol / L, H3PO4 and 50 mmol / L, N,N-dimethylformamide (DMF) solution of LiBr Flow rate: 1.0 mL / min Column temperature: 40 °C Detection: RI Sample size: 0.5 mg / mL Standard substance: Monodisperse polystyrene (manufactured by Tosoh Corporation)
[0063] [Content of semiconductor-type SWCNT] The Raman spectra of the SWCNTs before dispersion and the SWCNT dispersion liquid dried on the slide glass (dispersed SWCNTs) were measured using a laser Raman microscope (Nanophoton Inc. "RAMAN touch") at an excitation wavelength of 633 nm. The RBM (radial breathing mode) peak (100-350 cm) of the Raman spectrum excited at 633 nm was observed. -1 ), there are peaks specific to semiconducting SWCNTs and peaks specific to metallic SWCNTs. m The area A of the peak specific to semiconducting SWCNTs s The ratio (A s / m ) and the peak area A specific to metallic SWCNTs in the SWCNT dispersion m The area A of the peak specific to semiconducting SWCNTs s The ratio (A s / m By calculating '), the semiconducting SWCNT content in the dispersed SWCNTs can be calculated. Using the semiconducting SWCNT content of 67 mass% in the SWCNTs before dispersion as the standard, the semiconducting SWCNT content in the SWCNT dispersion can be calculated using the following formula.
[0064] Semiconducting SWCNT content = [(0.67 / A s / m )×A s / m '×100] / [0.33+(0.67 / A s / m )×A s / m ']
[0065] [Measurement of average diameter and length of SWCNTs] The average diameter and average length of SWCNTs were calculated by measuring the diameter and length of 10 or more CNTs from images obtained using a transmission electron microscope and averaging them.
[0066] [Measurement of the average thickness of the semiconductor layer] Using an atomic force microscope (AFM), the height from the surface of the thermal oxide film (SiO2) to the surface of the semiconductor layer was measured at five random locations, and the average thickness of the semiconductor layer was determined by averaging the measurements.
[0067] [Measuring carbon nanotube density in carbon nanotube networks] An atomic force microscope was used to obtain an image of the region (channel region) between the source and drain electrodes in the semiconductor layer, and the square of the number of CNTs present on one side of a 1 μm square was used to determine the carbon nanotube density (tubes / μm 2 ) was measured.
[0068] [Average thickness of sealing layer] Using a stylus surface profiler, the height from the surface of the semiconductor layer to the surface of the sealing layer between the source electrode and the drain electrode was measured at five random locations, and the average of these measurements was used to determine the average thickness of the sealing layer.
[0069] [Dielectric constant of sealing layer] The relative dielectric constant of the sealing layer was measured by molding the resin used for the sealing layer into a film and measuring it at 25° C. and 1 MHz by a capacitance method using an impedance analyzer.
[0070] [Semiconductor device measurements] The transfer characteristics of the semiconductor device were measured in air. The drain current (Ids) was measured using a semiconductor characteristic evaluation device (manufactured by KEITHLEY Corporation) as the gate voltage (Vgs) was changed. The drain voltage (Vds) was set to -1 V, and the gate voltage (Vgs) was swept back and forth between 20 V and -20 V. The on / off ratio was calculated from the maximum and minimum values of the drain current (Ids). In addition, the hysteresis was calculated from the absolute value |Vgs1 - Vgs2| of the gate voltage difference between the forward (Vgs1) and return (Vgs2) gates at a drain current (Ids) of -100 nA. These results are shown in Table 1 below.
[0071] [Preparation of CNT dispersion] A polymer (weight average molecular weight: 100,000) synthesized using polyethylene glycol (9) monomethacrylate (PEG (9) MA, manufactured by Shin-Nakamura Chemical Co., Ltd., "MG-90G", the average number of added moles of polyoxyethylene is 9) as a raw material monomer according to the method described in JP 2021-80120 A was dissolved in pure water to obtain a 0.5 wt% aqueous solution of PEG (9) MA. 30 mg of SWCNT (manufactured by NanoIntegris, "HiPco-Raw", average diameter 1.0 nm, average length 0.5 μm) was added to 30 g of a 0.5 wt% aqueous solution of PEG (9) MA to obtain a mixed solution. Next, while stirring with a stirrer, the mixture was dispersed for 10 minutes using an ultrasonic homogenizer (Branson "450D") at 30% power and a liquid temperature of 10°C. The dispersed solution was then centrifuged for 60 minutes using an ultracentrifuge (Hitachi Koki Co., Ltd. "CX100GXII", rotor S50) at 50,000 rpm and a liquid temperature of 20°C. 80% of the supernatant was collected from the liquid surface on a volume basis, yielding a CNT dispersion with a semiconducting CNT ratio (semiconducting CNT content) of 98 wt% to the total CNT amount (semiconducting CNT and metallic CNT combined). The SWCNTs used were 100 to 220 cm -1 It has a peak specific to metallic SWCNTs in the vicinity of 220–350 cm -1 There is a peak specific to semiconducting SWCNTs around this area.
[0072] [Example 1] A 1cm thick thermal oxide film (SiO2) is deposited on the surface. 2An adsorption layer of 3-aminopropyltriethoxysilane (APTES) was formed on a silicon substrate with a main surface area by vapor deposition. Next, the CNT dispersion obtained by the above method was diluted with pure water to a concentration of 1.45 μg / mL in terms of CNT mass, which was then applied to the entire surface of the adsorption layer to form a coating, which was then left to stand at room temperature for 1 hour. Then, before drying, the silicon substrate with the coating was immersed in ultrapure water for 60 minutes to remove excess CNT. It was then removed from the ultrapure water and dried in an atmosphere at 180°C for 60 minutes, yielding a semiconductor layer with an average film thickness of 2 nm. AFM images showed that the network density of the carbon nanotubes in the semiconductor layer was 625 tubes / μm. 2 In addition, an atomic force microscope was used to observe an image of a 1 μm square in the region (channel region) between the source and drain electrodes in the semiconductor layer. The CNTs were randomly oriented in two dimensions, with each CNT intersecting with at least five other CNTs. Furthermore, for all CNTs observed in the 1 μm square, the total length of the CNTs overlapping (intersecting) with other CNTs was 3% of their longitudinal length. Next, a 5-nm thick Ti layer was vacuum-deposited through a metal mask, followed by a 100-nm thick Au layer on the Ti layer, to form two-layer (Ti / Au) source and drain electrodes, with a channel length (L) and width (W) of 100 μm and 1,000 μm, respectively. The substrate with the source and drain electrodes formed was heated at 180°C for 1 hour. Next, after removing the excess semiconductor layer by etching, a 1 wt% solution of polystyrene (manufactured by Aldrich) in chloroform was spin-coated (2000 rpm, 30 s) to form a sealing layer with an average thickness of 500 nm. In this way, the semiconductor device shown in Figure 1 was fabricated.
[0073] [Example 2] A semiconductor device was fabricated in the same manner as in Example 1, except that a 9 wt % fluororesin CT-Solv. 180 solution (CYTOP (registered trademark), CTL-809A, manufactured by AGC Corporation) was used instead of the 1 wt % polystyrene chloroform solution, and spin-coated (first step: 500 rpm for 5 seconds, second step: 2000 rpm for 20 seconds), followed by heating at 180°C for 60 minutes to form a sealing layer with an average thickness of 1200 nm.
[0074] [Example 3] A semiconductor device was fabricated in the same manner as in Example 2, except that after spin coating (first step: 500 rpm for 5 seconds, second step: 3000 rpm for 20 seconds), the device was heated at 180°C for 60 minutes to form a sealing layer with an average thickness of 500 nm.
[0075] [Example 4] A semiconductor device was produced in the same manner as in Example 1, except that a sealing layer having an average thickness of 500 nm was formed using a 1 wt % polymethyl methacrylate chloroform solution instead of a 1 wt % polystyrene chloroform solution.
[0076] [Example 5] A semiconductor device was fabricated in the same manner as in Example 1, except that methyltrimethoxysilane (MTMS) was used as the material for the adsorption layer instead of APTES.
[0077] [Example 6] A semiconductor device was fabricated in the same manner as in Example 2, except that a 1 wt% solution of N-2-(aminoethyl)-3-aminopropyltrimethoxysilane in isopropanol (KBM-603, manufactured by Shin-Etsu Chemical Co., Ltd.) was used instead of APTES as the material for the adsorption layer.
[0078] [Example 7] A semiconductor device was produced in the same manner as in Example 1, except that a sealing layer having an average thickness of 500 nm was formed using a 1 wt % acetone solution of polyvinyl chloride instead of a 1 wt % chloroform solution of polystyrene.
[0079] [Example 8] A semiconductor device was fabricated in the same manner as in Example 1, except that a sealing layer having an average thickness of 500 nm was formed using a 1 wt % acetone solution of polyvinylpyrrolidone instead of a 1 wt % chloroform solution of polystyrene.
[0080] [Example 9] A semiconductor device was fabricated in the same manner as in Example 1, except that a 1 wt % polystyrene chloroform solution was replaced with a 1 wt % polyvinyl alcohol aqueous solution, which was spin-coated (2000 rpm, 30 s), and then heated at 100°C for 60 minutes to form a sealing layer with an average thickness of 500 nm.
[0081] [Comparative Example 1] A semiconductor device was fabricated in the same manner as in Example 1, except that a CNT dispersion liquid with a CNT concentration of 7.5 μg / mL was used instead of a CNT dispersion liquid with a CNT concentration of 1.45 μg / mL, and the formation of a sealing layer was omitted. AFM images showed that the density of the carbon nanotube network in the semiconductor layer was 10,000 tubes / μm 2 It was.
[0082] Comparative Example 2 A semiconductor device was produced in the same manner as in Example 2, except that a CNT dispersion liquid with a CNT concentration of 7.5 μg / mL was used instead of a CNT dispersion liquid with a CNT concentration of 1.45 μg / mL.
[0083] Comparative Example 3 A semiconductor device was produced in the same manner as in Example 1, except that a CNT dispersion liquid with a CNT concentration of 7.5 μg / mL was used instead of a CNT dispersion liquid with a CNT concentration of 1.45 μg / mL.
[0084] Comparative Example 4 A semiconductor device was produced in the same manner as in Example 1, except that the formation of the sealing layer was omitted.
[0085] [Table 1]
[0086] Fig. 7 shows an atomic force microscope photograph of the semiconductor layer constituting the semiconductor element of Example 1. As shown in Fig. 7, it can be confirmed that the semiconductor layer has a CNT network structure.
[0087] As shown in Table 1, in Examples 1 to 9, the average thickness of the semiconductor layer is 5 nm or less, and therefore the on / off ratio is significantly larger than that of the semiconductor elements of Comparative Examples 1 to 3. Furthermore, a comparison with Comparative Example 4 shows that the on / off ratio does not decrease in the Examples even when a sealing layer is formed. Thus, the semiconductor elements of the Examples have a large on / off ratio and small hysteresis. [Industrial Applicability]
[0088] As described above, the semiconductor element and the manufacturing method thereof according to the present disclosure can improve the on / off ratio and reduce hysteresis, thereby contributing to improving the performance of devices using the same. [Explanation of symbols]
[0089] 1. Semiconductor element 2. Semiconductor substrate (gate electrode) 3. Source electrode 4. Drain electrode 5 Semiconductor layer 6 Gate insulating layer 8 Sealing Layer 9 Adsorption layer 15 Paint film 50 carbon nanotubes
Claims
1. a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode; the semiconductor layer includes a carbon nanotube network structure, the semiconductor layer is sealed with a sealing layer; A semiconductor element, wherein the semiconductor layer has an average film thickness of 5 nm or less.
2. The semiconductor device according to claim 1 , wherein the semiconductor layer does not contain an organic semiconductor made of a conjugated polymer.
3. The sealing layer has an SP value calculated by the Fedors method of 15 (cal / cm 3 ) 1 / 2 3. The semiconductor device of claim 1, comprising a compound:
4. 3. The semiconductor device according to claim 1, wherein the sealing layer has a relative dielectric constant of 5.0 or less.
5. 3. The semiconductor device according to claim 1, wherein the sealing layer contains at least one resin selected from the group consisting of fluorine-based resins, acrylic resins, styrene-based resins, vinyl-based resins, and olefin-based resins.
6. The semiconductor device according to claim 1 , wherein the sealing layer has an average thickness of 200 nm or more.
7. 3. The semiconductor device according to claim 1, further comprising an adsorption layer disposed between the semiconductor layer and the gate insulating film and in contact with the semiconductor layer and the gate insulating film, the adsorption layer being made of a compound having no anionic group.
8. 3. The semiconductor device according to claim 1, wherein the carbon nanotubes are single-walled carbon nanotubes.
9. In the network structure, the density of the carbon nanotubes is 100 tubes / μm 2 More than 8000 lines / μm 2 3. The semiconductor device according to claim 1, wherein:
10. The semiconductor device according to claim 1 or 2, wherein the average length of the carbon nanotubes in the network structure is shorter than the channel length of the semiconductor device.
11. 3. The semiconductor device according to claim 1, wherein the content of semiconductor carbon nanotubes in the carbon nanotubes contained in the semiconductor layer is 70 mass % or more.
12. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a p-type field effect transistor.
13. A method for manufacturing a semiconductor device including a gate electrode, a source electrode, a drain electrode, a semiconductor layer in contact with the source electrode and the drain electrode, and a gate insulating layer insulating the semiconductor layer from the gate electrode, A method for manufacturing a semiconductor element, comprising: forming a semiconductor layer containing a carbon nanotube network structure and having an average film thickness of 5 nm or less using a carbon nanotube dispersion; and forming a sealing layer that seals the semiconductor layer.
14. The method for manufacturing a semiconductor device according to claim 13, wherein the carbon nanotube concentration in the carbon nanotube dispersion liquid is 0.1 μg / mL or more and 7.0 μg / mL or less.
15. In forming the semiconductor layer, 15. The method for manufacturing a semiconductor element according to claim 13, wherein the carbon nanotube dispersion is applied to form a coating film, the carbon nanotubes are adsorbed onto the surface to be coated, excess carbon nanotubes are removed from the coating film while the coating film is still wet, and then a drying process is performed to form the semiconductor layer.
16. The method for manufacturing a semiconductor device according to claim 15, wherein the removal of the excess carbon nanotubes is carried out by washing with a washing liquid.
17. The method for manufacturing a semiconductor device according to claim 15, wherein the removal of the excess carbon nanotubes is carried out by immersing the coating film in a cleaning solution.
18. The method for manufacturing a semiconductor device according to claim 13 or 14, comprising preparing the carbon nanotube dispersion liquid containing an acrylic acid-based resin.