Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device with improved electrical characteristics and reliability and a manufacturing method thereof.SOLUTION: A manufacturing method of a semiconductor device according to an embodiment includes an insulating structure in which an etch stop structure and a low dielectric constant layer are alternately stacked on a substrate, and a metal wiring electrically connected to the substrate within the insulating structure, and the etch stop structure includes a first etch stop layer including a hydrogen blocking material and a second etch stop layer formed on the first etch stop layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device provided with an etching stop layer containing a hydrogen blocking substance between inter-metal insulating layers.

Background Art

[0002] The semiconductor manufacturing process requires an etching process, etc., and such a process causes damage to the surface of the semiconductor substrate. As the semiconductor device becomes more highly integrated, the interval between patterns becomes smaller, and the surface damage of the substrate may increase. As a result, the dangling bonds of silicon forming the semiconductor substrate increase, which can be a source of electron leakage current and cause leakage current generation in transistors.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention aim to provide a semiconductor device with improved electrical characteristics and reliability and a method for manufacturing the same.

Means for Solving the Problems

[0004] The method for manufacturing a semiconductor device according to the present embodiment includes an insulating structure in which an etching stop structure and a low dielectric constant layer are alternately laminated on a substrate, and a metal wiring electrically connected to the substrate in the insulating structure, and the etching stop structure may include a first etching stop layer containing a hydrogen blocking substance and a second etching stop layer formed on the first etching stop layer.

[0005] A method for manufacturing a semiconductor device according to this embodiment includes the steps of forming an insulating structure on a substrate equipped with a transistor having a gate insulating layer, wherein an etching stop structure and a low dielectric constant layer are alternately stacked, and forming metal wiring electrically connected to the substrate within the insulating structure, wherein the etching stop structure may include a first etching stop layer containing a hydrogen blocking material and a second etching stop layer formed on the first etching stop layer. [Effects of the Invention]

[0006] This technology can ensure reliability by increasing the efficiency of hydrogen passivation and improving the leakage current characteristics of the device. [Brief explanation of the drawing]

[0007] [Figure 1] This is a diagram showing a semiconductor device according to this embodiment. [Figure 2] This figure shows a semiconductor device according to another embodiment. [Figure 3] This figure shows a semiconductor device according to another embodiment. [Figure 4A] This figure shows a method for manufacturing a semiconductor device according to this embodiment. [Figure 4B] This figure shows a method for manufacturing a semiconductor device according to this embodiment. [Figure 4C] This figure shows a method for manufacturing a semiconductor device according to this embodiment. [Figure 4D] This figure shows a method for manufacturing a semiconductor device according to this embodiment. [Figure 4E] This figure shows a method for manufacturing a semiconductor device according to this embodiment. [Figure 4F] This figure shows a method for manufacturing a semiconductor device according to this embodiment. [Figure 4G] This figure shows a method for manufacturing a semiconductor device according to this embodiment. [Modes for carrying out the invention]

[0008] The embodiments described herein will be explained with reference to cross-sectional views, plan views, and block diagrams that are ideal schematic representations of the present invention. Therefore, the forms shown in the illustrative drawings may be modified due to manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in form resulting from the manufacturing process. Therefore, the areas illustrated in the drawings have schematic attributes, and the shapes of the areas illustrated in the drawings are for illustrative purposes only, to illustrate specific forms of the element areas, and not to limit the scope of the invention. The sizes and relative sizes of the components shown in the drawings may be exaggerated for clarity of explanation. Throughout the specification, the same reference numerals refer to the same components, and "and / or" includes each of the items mentioned and all combinations of one or more of them.

[0009] The term "on" or "on top of" an element or layer includes not only directly above another element or layer, but also all cases where another layer or other element is interposed between them. The terms used herein are for illustrative purposes only and are not intended to limit the invention. In this specification, the singular form includes the plural form unless otherwise specified.

[0010] Figure 1 is a diagram showing a semiconductor device according to this embodiment.

[0011] As shown in Figure 1, the semiconductor device may comprise an element region DR and a wiring region LR. The element region DR may comprise a substrate 101 and a plurality of transistors formed on the substrate 101. In this embodiment, the element region DR may comprise transistors Tr. The wiring region LR may comprise a plurality of intermetallic insulating layers 132, 143, 153, a plurality of etching stop structures 140, 150, 160, a plurality of interlayer insulating layers 131, 163, 164, and multilayer level metal wiring M1, M2, M3, M4.

[0012] The substrate 101 can be a material suitable for semiconductor processing. The substrate 101 can comprise a semiconductor substrate. The substrate 101 can consist of a silicon-containing material. The substrate 101 can include silicon, single-crystal silicon, polysilicon, amorphous silicon, silicon germanium, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate 101 may also contain other semiconductor materials such as germanium. The substrate 101 can also comprise a III / V semiconductor substrate, such as a compound substrate like GaAs. The substrate 101 can also comprise an SOI (Silicon On Insulator) substrate.

[0013] The substrate 101 may include an element isolation layer 111 that defines an active region 112. A transistor Tr may be formed on the active region 112, comprising a laminated structure of a gate insulating layer 121, a gate electrode 122, and a gate hard mask 123, and gate spacers 124 formed on the side walls of the laminated structure. Impurity regions 125 may be formed on both sides of the substrate 101 of the transistor Tr. The impurity regions 125 may be referred to as "source / drain regions".

[0014] The multilayer metal wirings M1, M2, M3, and M4 can penetrate multiple intermetallic insulating layers 132, 143, and 153. These multiple intermetallic insulating layers 132, 143, and 153 may contain insulating materials with low dielectric constants to reduce parasitic capacitance between the metal wirings M1, M2, M3, and M4. These intermetallic insulating layers 132, 143, and 153 may be referred to as "low dielectric constant layers." These intermetallic insulating layers 132, 143, and 153 may contain low dielectric constants lower than those of silicon oxide (SiO2). For example, silicon oxide can have a dielectric constant of approximately 3.9 to 4.5. The intermetallic insulating layers 132, 143, and 153 may have a dielectric constant of 3.5 or less, for example, 2.0 to 3.5. For example, the intermetallic insulating layers 132, 143, and 153 may be silicon oxide containing carbon and hydrogen (SiCOH).

[0015] The interlayer insulating layers 131, 163, and 164 can be located between and above the transistor Tr and the substrate 101, and between the fourth metal wiring M4, which is the topmost metal wiring. The interlayer insulating layers 131, 163, and 164 may contain oxides with a higher dielectric constant than the intermetallic insulating layers 132, 143, and 153. For example, the first and second interlayer insulating layers 131 and 163 may contain TEOS (Tetra ethyle ortho silicate) oxide. In other embodiments, the first and second interlayer insulating layers 131 and 163 may also contain silicon oxide with a dielectric constant of 3.9 to 4.5.

[0016] The third interlayer insulating layer 164 may contain a silicon oxide containing hydrogen. The third interlayer insulating layer 164 may contain an insulating material that has a relatively higher hydrogen supply capacity compared to the second interlayer insulating layer 163. For example, the third interlayer insulating layer 164 may contain HDP (High Density Plasma) oxide. The third interlayer insulating layer 164 may be referred to as a "hydrogen passivation layer" or "hydrogen supply layer". When hydrogen is supplied via the hydrogen supply layer, the influence of a film that blocks hydrogen diffusion can be reduced compared to annealing in a hydrogen gas atmosphere.

[0017] A passivation layer 170 may be formed on top of the third interlayer insulating layer 164. The passivation layer 170, together with the third interlayer insulating layer 164, can serve as a hydrogen source for supplying hydrogen to the surface of the substrate 101. The passivation layer 170 can also serve to protect all structures stacked perpendicular to the substrate 101. The passivation layer 170 may include, for example, silicon nitride.

[0018] During the hydrogen passivation process, hydrogen in the third interlayer insulating layer 164 can be diffused to the surface of the substrate 101 through multilayer level metal wirings M1, M2, M3, and M4 that are electrically connected to the substrate 101. The surface of the substrate 101 where hydrogen arrives can be the interface 100 between the transistor Tr and the substrate 101. Therefore, the trap sites at the interface 100 are filled with the diffused hydrogen, significantly reducing the interface trap density. Therefore, the leakage current characteristics of the transistor can be improved.

[0019] The etching stop structures 140, 150, and 160 can include an insulating material having an etching selectivity ratio with respect to the interlayer insulating layers 131, 163, and 164 and the inter-metal insulating layers 132, 143, and 153. The etching stop structures 140, 150, and 160 can have a higher film density and strength than the inter-metal insulating layers 132, 143, and 153. The etching stop structures 140, 150, and 160 can prevent some gas from escaping from the inter-metal insulating layers 132, 143, and 153 or prevent gas from flowing into the etching stop structures 140, 150, and 160. That is, the etching stop structures 140, 150, and 160 can suppress the outgassing of gases such as hydrogen (H2), water vapor (H2O), fluorine, chlorine, etc. from the inter-metal insulating layers 132, 143, and 153. Also, the etching stop structures 140, 150, and 160 can be provided to prevent the inflow of hydrogen or water vapor, etc. into the inter-metal insulating layers 132, 143, and 153.

[0020] The first etching stop structure 140 can include a stacked structure of a first etching stop layer 141 and a second etching stop layer 142. The second etching stop structure 150 can include a stacked structure of a third etching stop layer 151 and a fourth etching stop layer 152. The third etching stop structure 160 can include a stacked structure of a fifth etching stop layer 161 and a sixth etching stop layer 162. The thickness of each of the etching stop structures 140, 150, 160 can be smaller than the thickness of each of the inter-metal insulation layers 132, 143, 153. The thickness of each of the etching stop structures 140, 150, 160 can be smaller than the thickness of each of the inter-layer insulation layers 131, 163, 164. The thicknesses of the first, third, and fifth etching stop layers 141, 151, 161 can be smaller than the thicknesses of the second, fourth, and sixth etching stop layers 142, 152, 162, respectively. For example, when the thickness of the second etching stop layer 142 is 250 Å to 700 Å, the thickness of the first etching stop layer 141 can be 20 Å to 40 Å.

[0021] The first, third, and fifth etching stop layers 141, 151, 161 can serve to prevent hydrogen in the lower layer from diffusing into the upper layer due to heat treatment or the like. That is, the first, third, and fifth etching stop layers 141, 151, 161 block the diffusion of hydrogen in the lower layer upward during the heat treatment process for hydrogen diffusion to the substrate surface, and can prevent hydrogen from being captured by the second, fourth, and sixth etching stop layers 142, 152, 162. That is, the first, third, and fifth etching stop layers 141, 151, 161 can direct the concentration into the hydrogen transmission path and increase the efficiency of the heat treatment process for hydrogen diffusion.

[0022] Each of the first, third, and fifth etching stop layers 141, 151, and 161 may contain a hydrogen blocking material. The first, third, and fifth etching stop layers 141, 151, and 161 may contain an insulating material with a higher silicon content in the film than silicon nitride (Si3N4) having a stoichiometric composition. The first, third, and fifth etching stop layers 141, 151, and 161 may contain silicon-rich silicon nitride (SRN) with a higher silicon content than silicon nitride (Si3N4) having a stoichiometric composition. In particular, each of the first, third, and fifth etching stop layers 141, 151, and 161 may be formed via a pre-treatment step during the deposition process of the second, fourth, and sixth etching stop layers 142, 152, and 162, respectively, which is not a separate deposition process. The first, third, and fifth etching stop layers 141, 151, and 161 can each be formed in situ in the same chamber as the second, fourth, and sixth etching stop layers 142, 152, and 162, respectively.

[0023] The second, fourth, and sixth etching stop layers 142, 152, and 162 may contain an insulating material with a dielectric constant lower than silicon nitride (Si3N4) having a stoichiometric composition. The second, fourth, and sixth etching stop layers 142, 152, and 162 may contain carbon-containing silicon nitride (NDC; Nitride Doped Carbon). The second, fourth, and sixth etching stop layers 142, 152, and 162 may contain Si, C, and N. For example, the second, fourth, and sixth etching stop layers 142, 152, and 162 may contain SiCN.

[0024] In this embodiment, first to third etching stop structures are shown, but in other embodiments, an etching stop structure may also be placed between the first interlayer insulating layer 131 and the first intermetallic insulating layer 132.

[0025] The multilayer level metal wirings M1, M2, M3, and M4 may comprise metal wiring contacts and conductive lines. The metal wiring contacts 135, 145, 155, and 165 can electrically connect the lower conductive line and the upper conductive line. The first metal wiring contact 135 has both ends connected to the substrate 101 and the first conductive line 136, thereby electrically connecting the substrate 101 and the first conductive line 136. The second metal wiring contact 145 has both ends connected to the first conductive line 136 and the second conductive line 146, thereby electrically connecting the first conductive line 136 and the second conductive line 146. The third metal wiring contact 155 has both ends connected to the second conductive line 146 and the third conductive line 156, thereby electrically connecting the second conductive line 146 and the third conductive line 156. The fourth metal wiring contact 165 is connected at both ends to the third conductive line 156 and the fourth conductive line 166, thereby electrically connecting the third conductive line 156 and the fourth conductive line 166. Each conductive line 136, 146, 156, and 166 can extend in one direction while in contact with the upper surface of each metal wiring contact 135, 145, 155, and 165. Although not shown, multiple metal wiring contacts 135, 145, 155, and 165 may be provided at the same level but spaced apart from each other, and each conductive line 136, 146, 156, and 166 can be simultaneously connected to multiple metal wiring contacts arranged at the same level.

[0026] The first to third metal wirings M1, M2, and M3 may contain the same material. For example, the first to third conductive lines M1, M2, and M3 may contain copper (Cu). A barrier layer (not shown) may be formed at the interface between the first to third conductive lines M1, M2, and M3 and the intermetallic insulating layers 132, 143, and 153. The barrier layer may contain titanium, titanium nitride, tantalum, or tantalum nitride.

[0027] The fourth metal wiring contact 145 may be a contact plug located at the top. The fourth metal wiring contact 145 may contain a different material from the first to third metal wirings M1, M2, and M3. The fourth metal wiring contact 145 may contain a conductive material with lower resistance than the first to third metal wirings M1, M2, and M3. For example, the fourth metal wiring contact 145 may contain tungsten W. A barrier layer (not shown) may be formed at the interface between the fourth metal wiring contact 145 and the second interlayer insulating layer 163. The barrier layer may contain tungsten nitride.

[0028] The fourth conductive line 146 can be the uppermost conductive line. The fourth conductive line 146 can be formed on the fourth metal wiring contact 145 and the second interlayer insulating layer 143. The fourth conductive line 146 can have a shape that extends in one direction while in contact with the upper surface of the fourth metal wiring contact 145. The fourth conductive line 146 can contain a conductive material with lower resistance than the fourth metal wiring contact 145. The fourth conductive line 146 can contain a metallic material that reduces corrosion by oxidation. For example, the fourth conductive line 146 can contain aluminum. In the case of aluminum, if the surface is oxidized, aluminum oxide can be provided as an oxide film agent for the underlying aluminum.

[0029] Semiconductor devices can experience a decrease in electrical characteristics due to defects occurring in individual elements during manufacturing processes, such as oxidation and plasma etching. For example, dangling bonds can form at the interfaces between the silicon oxide layer and the silicon substrate of an individual element, or between the gate oxide layer and the substrate. This can increase leakage current and degrade the electrical characteristics of the semiconductor device. In the case of DRAM semiconductor devices, a refresh method is used to store new data, requiring the existing data to be restored at regular intervals. This regular interval is called the refresh period or data retention time. To reduce the power consumption of DRAM and increase its operating speed, it is necessary to reduce the data retention time. However, structural defects in the silicon crystal, such as dangling bonds, can increase leakage current in transistors and reduce the data retention time.

[0030] To repair defects such as dangling bonds, a third interlayer insulating layer 164 is formed on top of the topmost metal wiring (the fourth metal wiring M4 in this embodiment) as a hydrogen supply layer, allowing hydrogen to be supplied to the interface between the substrate 101 and the transistor Tr via a heat treatment process.

[0031] As a comparative example, when a silicon nitride (Si3N4) with a stoichiometric composition of a similar thickness to that of this embodiment is used as the etching stop layer, there is a problem in that the speed characteristics of the device deteriorate due to the increase in the dielectric constant of the overall insulating layer.

[0032] In contrast, this embodiment can maintain a low dielectric constant by applying an etching stop layer with a lower dielectric constant than silicon nitride (Si3N4) having a stoichiometric composition. Furthermore, by applying silicon-rich silicon nitride, which has a higher silicon content and thinner thickness than silicon nitride (Si3N4) having a stoichiometric composition, as the etching stop layer below the etching stop layer, it is possible to prevent the hydrogen in the lower layer from diffusing to the upper layer during the heat treatment process for hydrogen supply without increasing the dielectric constant, thereby leading to concentration in the hydrogen transfer path and increasing the efficiency of the heat treatment process for hydrogen diffusion.

[0033] Figures 2 and 3 show semiconductor devices according to other embodiments. Figure 2 includes etching stop structures 240, 250, and 260 with a different structure from those in Figure 1. Figure 3 includes a substrate and element region with a different structure from those in Figure 1. Among the reference numerals shown in Figures 2 and 3, those that are the same as those in Figure 1 can refer to the same structures as in Figure 1. For the sake of explanation, reference numerals that overlap with those in Figure 1 are omitted or briefly described.

[0034] As shown in Figure 2, the etching stop structures 240, 250, and 260 may contain insulating materials having an etching selectivity ratio with respect to the interlayer insulating layers 131, 163, and 164 and the intermetallic insulating layers 132, 143, and 153. The etching stop structures 240, 250, and 260 can have higher film density and strength than the intermetallic insulating layers 132, 143, and 153. The etching stop structures 240, 250, and 260 can prevent some gas from escaping from the intermetallic insulating layers 132, 143, and 153, or prevent gas from flowing into the etching stop structures 240, 250, and 260. In other words, the etching stop structures 240, 250, and 260 can suppress the outgassing of gases such as hydrogen (H2), water vapor (H2O), fluorine, and chlorine from the intermetallic insulating layers 132, 143, and 153. Furthermore, etching stop structures 240, 250, and 260 can be provided to prevent hydrogen or water vapor from flowing into the intermetallic insulating layers 132, 143, and 153.

[0035] The first etching stop structure 240 may include a laminated structure of first to third etching stop layers 241, 242, and 243. The second etching stop structure 250 may include a laminated structure of fourth to sixth etching stop layers 251, 252, and 253. The third etching stop structure 260 may include a laminated structure of seventh to ninth etching stop layers 261, 262, and 263. The thickness of each etching stop structure 240, 250, and 260 may be less than the thickness of each intermetallic insulating layer 132, 143, and 153. The thickness of each etching stop structure 240, 250, and 260 may be less than the thickness of each interlayer insulating layer 131, 163, and 164. The thicknesses of the first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 can be smaller than the thicknesses of the second, fifth, and eighth etching stop layers 242, 252, and 262. For example, if the thickness of the second etching stop layer 242 is 250 Å to 700 Å, the thicknesses of the first and third etching stop layers 241 and 243 can be 20 Å to 40 Å, but this embodiment is not limited thereto.

[0036] The first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 can prevent diffusion from the lower or upper layer to the upper or lower layer due to heat treatment or other processes. Specifically, the first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 can block hydrogen outgassing, which occurs when hydrogen in the lower layer diffuses upward during a heat treatment process for hydrogen diffusion to the substrate surface. Furthermore, they can prevent hydrogen diffused from the upper layer from being captured by the second, fifth, and eighth etching stop layers 242, 252, and 262 as it descends to the lower layer.

[0037] As a result, the first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 can prevent hydrogen loss due to hydrogen outgassing and unwanted hydrogen capture, and guide hydrogen to concentration in the hydrogen transfer pathway. Therefore, the efficiency of the heat treatment process for hydrogen diffusion into the substrate can be increased.

[0038] In another embodiment, although not shown, an etching stop layer containing a hydrogen blocking material may also be applied to the interface between each metal wiring M1, M2, M3, M4 and the etching stop structures 240, 250, 260.

[0039] Each of the first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 may contain a hydrogen blocking material. The first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 may contain an insulating material with a higher silicon content in the film than silicon nitride (Si3N4) having a stoichiometric composition. The first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 may contain silicon-rich nitride (SRN) with a higher silicon content than silicon nitride (Si3N4) having a stoichiometric composition. In particular, the first, third, fourth, sixth, seventh, and ninth etching stop layers 241, 243, 251, 253, 261, and 263 can be formed via a pre-treatment step during the deposition process of the second, fifth, and seventh etching stop layers 242, 252, and 262, which are not separate deposition processes, or via a pre-treatment step during the deposition process of the upper insulating layer. For example, the first etching stop layer 241 can be formed by a pre-treatment step during the deposition process of the second etching stop layer 242. The third etching stop layer 243 can be formed by a pre-treatment step during the deposition process of the first intermetallic insulating layer 132.

[0040] The second, fifth, and eighth etching stop layers 242, 252, and 262 may contain an insulating material with a dielectric constant lower than silicon nitride (Si3N4) having a stoichiometric composition. The second, fifth, and eighth etching stop layers 242, 252, and 262 may contain carbon-doped silicon nitride (NDC). The second, fifth, and eighth etching stop layers 242, 252, and 262 may contain Si, C, and N. For example, the second, fifth, and eighth etching stop layers 242, 252, and 262 may contain SiCN.

[0041] In this embodiment, first to third etching stop structures are shown, but in other embodiments, an etching stop structure may also be placed between the first interlayer insulating layer 131 and the first intermetallic insulating layer 132.

[0042] As shown in Figure 3, the semiconductor device may comprise an element region DR and a wiring region LR. The element region DR may comprise a substrate 101 and a plurality of transistors formed thereon. If the semiconductor device of the present invention is a memory device, the element region DR may comprise a cell array region R1 and a peripheral circuit region R2 for driving the cell array region R1. The cell array region R1 may comprise a region where memory cells are located. The peripheral circuit region R2 may comprise a word line driver, a sense amplifier, row and column decoders, and a control circuit. If the semiconductor device of the present invention is a non-memory device, the element region DR may not comprise the cell array region R1.

[0043] The cell array region R1 may include a cell transistor region CS and an information storage structure MS on the cell transistor region CS. If the semiconductor memory device of the present invention is a DRAM device, the information storage structure MS may include a capacitor. The capacitor may include a stacked structure of a lower electrode, a dielectric layer, and an upper electrode.

[0044] The cell transistor region CS may comprise a unit memory cell consisting of an active region 112 defined by an element isolation layer 111, a word line WL formed within the active region 112, and a bit line BL formed above the active region 112. The active region 112 may be provided with a plurality of impurity regions separated from each other by the word line WL. On a plane, the bit line BL may extend in a direction intersecting the word line WL. The bit line BL may be electrically connected to the substrate 101 via a bit line contact. The capacitor may be electrically connected to the substrate 101 via a storage node contact. Although this embodiment has been described with reference to a DRAM, the semiconductor memory device of the present invention is not limited to a DRAM and may also be a memory device comprising a variable resistor such as a phase change material.

[0045] The peripheral circuit region R2 may include a peripheral transistor region PS. The peripheral transistor region PS may include an active region 112 defined by the element isolation layer 111 and transistors formed on the active region 112.

[0046] The substrate 101 of the cell array region R1 and the peripheral circuit region R2, the cell transistor region CS, and the peripheral transistor region PS may be provided with a plurality of intermetallic insulating layers 132, 143, 153, a plurality of etching stop structures 140, 150, 160, a plurality of interlayer insulating layers 231, 163, 164, and multilayer level metal wiring M1, M2, M3, M4.

[0047] In this embodiment, multilayer level metal wiring M1, M2, M3, and M4 are provided in both the cell array region R1 and the peripheral circuit region R2. However, in other embodiments, the method can be applied to only one of the regions, either the cell array region R1 or the peripheral circuit region R2, specifically to the multilayer level metal wiring M1, M2, M3, and M4.

[0048] The multilayer metal wirings M1, M2, M3, and M4 can penetrate multiple intermetallic insulating layers 132, 143, and 153. These multiple intermetallic insulating layers 132, 143, and 153 may contain insulating materials with low dielectric constants to reduce parasitic capacitance between the metal wirings M1, M2, M3, and M4. For example, the intermetallic insulating layers 132, 143, and 153 may be silicon oxide (SiCOH) containing carbon and hydrogen.

[0049] The interlayer insulating layers 231, 163, and 164 can be located between and above the transistor Tr and the substrate 101, and between the fourth metal wiring M4, which is the topmost metal wiring. The interlayer insulating layers 231, 163, and 164 may contain oxides with a higher dielectric constant than the intermetallic insulating layers 132, 143, and 153. For example, the first and second interlayer insulating layers 231 and 163 may contain TEOS (Tetra ethyle ortho silicate) oxide. In other embodiments, the first and second interlayer insulating layers 231 and 163 may also contain silicon oxide with a dielectric constant of 3.9 to 4.5. The first interlayer insulating layer 231 in this embodiment can be formed in multilayers 230-1 and 230-2 by the structure of the device region DR.

[0050] The third interlayer insulating layer 164 may contain a silicon oxide containing hydrogen. The third interlayer insulating layer 164 may contain an insulating material that has a relatively higher hydrogen supply capacity compared to the second interlayer insulating layer 163. For example, the third interlayer insulating layer 164 may contain HDP (High Density Plasma) oxide. The third interlayer insulating layer 164 may be referred to as a "hydrogen passivation layer" or "hydrogen supply layer". When hydrogen is supplied via the hydrogen supply layer, the influence of a film that blocks hydrogen diffusion can be reduced compared to annealing in a hydrogen gas atmosphere.

[0051] A passivation layer 170 may be formed on top of the third interlayer insulating layer 164. The passivation layer 170, together with the third interlayer insulating layer 164, can serve as a hydrogen source for supplying hydrogen to the surface of the substrate 101. The passivation layer 170 can also serve to protect all structures stacked perpendicular to the substrate 101. The passivation layer 170 may include, for example, silicon nitride.

[0052] During the hydrogen passivation process, hydrogen within the third interlayer insulating layer 164 can diffuse to the surface of the substrate 101 via multilayer level metal wiring M1, M2, M3, and M4 that are electrically connected to the substrate 101. The surfaces of the substrate 101 to which the hydrogen reaches can be the interface D1 of the gate insulating layer constituting the word line WL in the cell array region R1 and the interface D2 between the peripheral transistor region PS and the substrate 101 in the peripheral circuit region R2. Therefore, the trap sites at each interface D1 and D2 are filled with diffused hydrogen, significantly reducing the interface trap density. Thus, the leakage current characteristics of the transistor can be improved.

[0053] The etching stop structures 140, 150, and 160 may contain insulating materials having an etching selectivity ratio with respect to the interlayer insulating layers 131, 163, and 164 and the intermetallic insulating layers 132, 143, and 153. The etching stop structures 140, 150, and 160 can have higher film density and strength than the intermetallic insulating layers 132, 143, and 153. The etching stop structures 140, 150, and 160 can prevent some gas from escaping from the intermetallic insulating layers 132, 143, and 153, or prevent gas from flowing into the etching stop structures 140, 150, and 160. In other words, the etching stop structures 140, 150, and 160 can suppress the outgassing of gases such as hydrogen (H2), water vapor (H2O), fluorine, and chlorine from the intermetallic insulating layers 132, 143, and 153. Furthermore, etching stop structures 140, 150, and 160 can be provided to prevent hydrogen or water vapor from flowing into the intermetallic insulating layers 132, 143, and 153.

[0054] The etching stop structures 140, 150, and 160 in Figure 3 may include the same layered structure as the etching stop structures 140, 150, and 160 in Figure 1. In other embodiments, the etching stop structures 140, 150, and 160 in Figure 3 may be replaced by the etching stop structures 240, 250, and 260 in Figure 2.

[0055] The first etching stop structure 140 may include a laminated structure of a first etching stop layer 141 and a second etching stop layer 142. The second etching stop structure 150 may include a laminated structure of a third etching stop layer 151 and a fourth etching stop layer 152. The third etching stop structure 160 may include a laminated structure of a fifth etching stop layer 161 and a sixth etching stop layer 162. The thickness of each etching stop structure 140, 150, and 160 may be less than the thickness of each intermetallic insulating layer 111, 123, and 133. The thickness of each etching stop structure 140, 150, and 160 may be less than the thickness of each interlayer insulating layer 131, 163, and 164. The thicknesses of the first, third, and fifth etching stop layers 141, 151, and 161 may be less than the thicknesses of the second, fourth, and sixth etching stop layers 142, 152, and 162, respectively. For example, if the thickness of the second etching stop layer 142 is 250 Å to 700 Å, the thickness of the first etching stop layer 141 can be 20 Å to 40 Å.

[0056] The first, third, and fifth etching stop layers 141, 151, and 161 can prevent hydrogen in the lower layer from diffusing to the upper layer due to heat treatment or other processes. In other words, the first, third, and fifth etching stop layers 141, 151, and 161 can block hydrogen in the lower layer from diffusing to the upper layer during the heat treatment process for hydrogen diffusion on the substrate surface, thereby preventing hydrogen from being captured by the second, fourth, and sixth etching stop layers 142, 152, and 162. In short, the first, third, and fifth etching stop layers 141, 151, and 161 can increase the efficiency of the heat treatment process for hydrogen diffusion by guiding hydrogen to concentrate in the hydrogen transfer path.

[0057] Each of the first, third, and fifth etching stop layers 141, 151, and 161 may contain a hydrogen blocking material. The first, third, and fifth etching stop layers 141, 151, and 161 may contain an insulating material with a higher silicon content in the film than silicon nitride (Si3N4) having a stoichiometric composition. The first, third, and fifth etching stop layers 141, 151, and 161 may contain silicon-rich silicon nitride (SRN) with a higher silicon content than silicon nitride (Si3N4) having a stoichiometric composition. In particular, each of the first, third, and fifth etching stop layers 141, 151, and 161 may be formed via a pre-treatment step during the deposition process of the second, fourth, and sixth etching stop layers 142, 152, and 162, respectively, which is not a separate deposition process. The first, third, and fifth etching stop layers 141, 151, and 161 can each be formed in situ in the same chamber as the second, fourth, and sixth etching stop layers 142, 152, and 162, respectively.

[0058] The second, fourth, and sixth etching stop layers 142, 152, and 162 may contain an insulating material with a dielectric constant lower than silicon nitride (Si3N4) having a stoichiometric composition. The second, fourth, and sixth etching stop layers 142, 152, and 162 may contain carbon-containing silicon nitride (NDC; Nitride Doped Carbon). The second, fourth, and sixth etching stop layers 142, 152, and 162 may contain Si, C, and N. For example, the second, fourth, and sixth etching stop layers 142, 152, and 162 may contain SiCN.

[0059] Multilayer level metal wiring M1, M2, M3, and M4 can be equipped with metal wiring contacts and conductive lines.

[0060] Figures 4A to 4G illustrate a method for manufacturing a semiconductor device according to this embodiment. Although Figures 4A to 4G show a manufacturing method for forming the semiconductor device shown in Figure 1, they can also be applied to the semiconductor device formation methods shown in Figures 2 and 3.

[0061] As shown in Figure 4A, an element isolation layer 12 and an active region 13 are formed on the substrate 11.

[0062] The active region 13 can be defined by the element isolation layer 12. The element isolation layer 12 can be formed by the STI (Shallow Trench Isolation) process.

[0063] Next, a transistor Tr is formed on the substrate 11. The transistor Tr may have the same structure as the transistor Tr shown in Figure 1.

[0064] Next, impurity regions 14 are formed on both sides of the transistor Tr. These impurity regions 14 can be referred to as "source / drain regions." The impurity regions 14 may contain N-type impurities such as arsenic (As) or phosphorus (P).

[0065] Next, a first interlayer insulating layer 15 is formed on the substrate 11 equipped with the transistor Tr. The upper surface of the first interlayer insulating layer 15 can be located at a higher level than the upper surface of the transistor Tr. For example, the first interlayer insulating layer 15 may include TEOS oxide. In other embodiments, the first interlayer insulating layer 15 may also include silicon oxide having a dielectric constant of 3.9 to 4.5.

[0066] Next, a first metal wiring contact 21 is formed, penetrating the first interlayer insulating layer 15 and connected to the substrate 11. The substrate 11 to which the first metal wiring contact 21 is connected can be an impurity region 14. During the subsequent hydrogen passivation process, hydrogen transmitted through the first metal wiring contact 21 can be supplied to the interface 100 between the transistor Tr and the substrate 11 via the impurity region 14.

[0067] As shown in Figures 4B and 4C, a first intermetallic insulating layer 31 with an opening OP is formed on the first interlayer insulating layer 15 and the first metal wiring contact 21.

[0068] To this end, a series of steps can be taken to form a low dielectric constant material layer on the first interlayer insulating layer 15 and the first metal wiring contact 21, form a mask pattern on the low dielectric constant material layer that opens up conductive line regions, and then etch the low dielectric constant material layer using the mask pattern.

[0069] The first intermetallic insulating layer 31 may include a low dielectric material having a dielectric constant lower than that of silicon oxide (SiO2). The first intermetallic insulating layer 31 may be referred to as a "low dielectric layer." For example, silicon oxide can have a dielectric constant of about 3.9 to 4.5. The first intermetallic insulating layer 31 can have a dielectric constant of 3.5 or less, for example, a dielectric constant of 2.0 to 3.5. For example, the first intermetallic insulating layer 31 may be silicon oxide (SiCOH) containing carbon and hydrogen.

[0070] Next, a first conductive line 22 can be formed to gap-fill the opening OP. The first conductive line 22 can be formed by a series of steps, which involve forming a conductive material on the first intermetallic insulating layer 31 having the opening OP, and etching the conductive material with a target that exposes the upper surface of the first intermetallic insulating layer 31. A barrier layer (not shown) may be formed at the interface between the first intermetallic insulating layer 31 and the first conductive line 22. The first metal wiring contact 21 and the first conductive line 22 may be referred to as the first metal wiring M1.

[0071] As shown in Figures 4D to 4F, a first etching stop structure 40 is formed on a first intermetallic insulating layer 31 comprising a first metal wiring M1.

[0072] The first etching stop structure 40 may include a laminated structure of a first etching stop layer 41 and a second etching stop layer 42. The thickness of the first etching stop layer 41 may be less than the thickness of the second etching stop layer 42.

[0073] The first etching stop layer 41 may contain a hydrogen blocking material. The first etching stop layer 41 may contain an insulating material with a higher silicon content in the film than a silicon nitride (Si3N4) having a stoichiometric composition. The first etching stop layer 41 may contain a silicon-rich nitride (SRN) with a higher silicon content than a silicon nitride (Si3N4) having a stoichiometric composition. In particular, the first etching stop layer 41 can be formed via a pre-treatment step during the deposition process of the second etching stop layer 42, which is not a separate deposition process. The first etching stop layer 41 can be formed in situ in the same chamber as the second etching stop layer 42.

[0074] The second etching stop layer 42 may contain an insulating material with a dielectric constant lower than that of silicon nitride (Si3N4) having a stoichiometric composition. The second etching stop layer 42 may contain carbon-containing silicon nitride (NDC; Nitride Doped Carbon). The second etching stop layer 42 may contain Si, C, and N. For example, the second etching stop layer 42 may contain SiCN.

[0075] In this embodiment, the structure of the etching stop structure shown in Figure 1 is shown, but of course, the structure of the etching stop structure shown in Figure 2 can also be applied.

[0076] Next, a second intermetallic insulating layer 43 is formed on the first etching stop structure 40. The second intermetallic insulating layer 43 may contain the same material as the first intermetallic insulating layer 31. The second intermetallic insulating layer 43 may have a thickness greater than the overall thickness of the first etching stop structure 40.

[0077] Next, the second intermetallic insulating layer 43 and the first etching stop structure 40 are etched to form vias V1 and trenches T1.

[0078] Via V1 and trench T1 can be formed in separate processes using their respective masks. In other embodiments, via V1 and trench T1 can also be formed in separate etching processes using a single mask whose width has been adjusted via a trimming process. For example, via V1 can be formed first, followed by trench T1. In other embodiments, trench T1 can be formed first, followed by via V1.

[0079] As shown in Figures 4F and 4G, a second metal wiring M2 is formed in the via (V1, see Figure 4E) and trench (T1, see Figure 4E).

[0080] The second metal wiring M2 may include a second metal wiring contact 45 for embedding vias V1 and a second conductive line 46 for embedding trenches T1. A barrier layer (not shown) may be formed at the interface between vias V1 and trenches T1 and the second metal wiring M2. The barrier layer may include titanium, titanium nitride, tantalum, or tantalum nitride.

[0081] The second metal wiring contact 45 and the second conductive line 46 may be made of the same material. The second metal wiring M2 may be made of copper (Cu), for example. The second metal wiring M2 may be formed in a damascene process that proceeds through a planarization process after forming a conductive material to fill the vias V1 and trenches T1. The second metal wiring M2 may be formed via an electroplating process after forming a seed layer (not shown). A further heat treatment process may be performed after the electroplating process.

[0082] Next, the process shown in Figures 4D and 4E and the conductive material formation process are repeated to form a second etching stop structure 50 and a third intermetallic insulating layer 53, which are provided with a third metal wiring M3, on a second intermetallic insulating layer 43 provided with a second metal wiring M2.

[0083] Next, a third etching stop structure 60 and a second interlayer insulating layer 63 are formed sequentially on the third intermetallic insulating layer 53.

[0084] The third etching stop structure 60 can be formed by the same process as the first and second etching stop structures 40 and 50 (see Figure 4E).

[0085] The second interlayer insulating layer 63 may contain the same material as the first interlayer insulating layer 15. The second interlayer insulating layer 63 may contain, for example, TEOS (Tetra Ethyl Ortho Silicate) oxide. In other embodiments, the second interlayer insulating layer 63 may contain a silicon oxide having a dielectric constant of 3.9 to 4.5.

[0086] Next, vias V2 are formed that penetrate the second interlayer insulating layer 63 and the third etching stop structure 60, exposing a portion of the third metal wiring M3.

[0087] Next, a fourth metal wiring contact 65 is formed to gap-fill via V2. The fourth metal wiring contact 65 may be the uppermost contact plug. The fourth metal wiring contact 65 may contain a different material from the first to third metal wirings M1, M2, and M3. The fourth metal wiring contact 65 may contain a conductive material with lower resistance than the first to third metal wirings M1, M2, and M3. For example, the fourth metal wiring contact 65 may contain tungsten W. A barrier layer (not shown) may be formed at the interface between the fourth metal wiring contact 65 and the second interlayer insulating layer 63. The barrier layer may contain tungsten nitride.

[0088] Next, a fourth conductive line 66 is formed on the fourth metal wiring contact 65 and the second interlayer insulating layer 63. The fourth metal wiring contact 65 and the fourth conductive line 66 can be referred to as the fourth metal wiring M4. In this embodiment, the fourth metal wiring M4 is shown as the top metal wiring, but the embodiment is not limited to this.

[0089] The fourth conductive line 66 may have a shape that extends in one direction while in contact with the upper surface of the fourth metal wiring contact 65. The fourth conductive line 66 may contain a conductive material with lower resistance than the fourth metal wiring contact 65. The fourth conductive line 66 may contain a metallic material that reduces corrosion by oxidation. For example, the fourth conductive line 66 may contain aluminum. In the case of aluminum, if the surface is oxidized, aluminum oxide can be provided as an oxide film agent for the underlying aluminum.

[0090] Next, a third interlayer insulating layer 71 can be formed on the second interlayer insulating layer 63 and the fourth conductive line 66. The third interlayer insulating layer 71 may contain a hydrogen-containing silicon oxide. For example, the third interlayer insulating layer 71 may contain HDP oxide. The third interlayer insulating layer 71 may be referred to as a "hydrogen passivation layer" or "hydrogen supply layer".

[0091] Next, a passivation layer 72 can be formed on the third interlayer insulating layer 71. The passivation layer 72 may include, for example, silicon nitride.

[0092] Next, a heat treatment process AP is performed to supply hydrogen from the third interlayer insulating layer 71 to the surface of the substrate 11 (the interface 100 between the substrate 11 and the transistor Tr).

[0093] The heat from the heat treatment process is applied to the passivation layer 72, and hydrogen can be transferred to the substrate 11 via a hydrogen transfer path that includes metal wiring. The passivation layer 72 can prevent hydrogen detachment in the opposite direction to the hydrogen transfer path during the heat treatment process.

[0094] As described above, various embodiments for solving the problem to be solved have been presented, but it is clear to any person with ordinary skill in the art to which this invention belongs that various changes and modifications can be made within the scope of the technical concept of this invention. [Explanation of Symbols]

[0095] 101 circuit board Tr Transistor 131, 163, 164 Interlayer insulating layer 132, 143, 153 Intermetallic insulating layer M1, M2, M3, M4 metal wiring 135, 145, 155, 165 metal wiring contacts 136, 146, 156, 166 conductive lines 140, 150, 160 Etching stop structure 141, 142, 151, 152, 161, 162 Etching stop layer 170 Passivation Layer

Claims

1. an insulating structure formed by alternately stacking etching stop structures and low dielectric constant layers on a substrate; a metal wiring in the insulating structure, the metal wiring being electrically connected to the substrate; Equipped with The etch stop structure comprises: A semiconductor device comprising a first etch stop layer including a hydrogen blocking material and a second etch stop layer formed on the first etch stop layer.

2. The first etch stop layer is silicon nitride (Si ３ N ４ 2. The semiconductor device according to claim 1, further comprising a silicon-rich silicon nitride film having a silicon content higher than that of silicon nitride.

3. 2. The semiconductor device according to claim 1, wherein the second etching stop layer comprises silicon nitride containing carbon.

4. The semiconductor device of claim 1 , wherein the second etch stop layer comprises SiCN.

5. 2. The semiconductor device according to claim 1, wherein the thickness of the first etching stop layer is smaller than the thickness of the second etching stop layer.

6. The semiconductor device of claim 1 , wherein the thickness of the etch stop structure is less than the thickness of the low-k layer.

7. The semiconductor device according to claim 1 , wherein the low dielectric constant layer contains silicon oxide containing carbon and hydrogen (SiCOH).

8. The semiconductor device according to claim 1 , further comprising a hydrogen supply layer on the insulating structure.

9. The semiconductor device according to claim 1 , wherein the hydrogen supply layer includes a high density plasma (HDP) oxide or a silicon nitride, or a combination thereof.

10. The semiconductor device of claim 1 , wherein the etch stop structure further comprises a third etch stop layer comprising a hydrogen blocking material on the second etch stop layer.

11. The third etch stop layer is silicon nitride (Si ３ N ４ 11. The semiconductor device according to claim 10, further comprising a silicon-rich silicon nitride film having a silicon content higher than that of silicon nitride.

12. 10. The semiconductor device of claim 1, wherein the metal interconnect comprises multi-level metal interconnect.

13. The semiconductor device according to claim 1 , wherein the substrate is provided with a transistor having a gate insulating layer.

14. forming an insulating structure in which an etch stop structure and a low dielectric constant layer are alternately stacked on a substrate on which a transistor having a gate insulating layer is formed; forming a metal wiring in the insulating structure, the metal wiring being electrically connected to the substrate; Including, The etch stop structure comprises: A method for manufacturing a semiconductor device comprising a first etch stop layer including a hydrogen blocking material and a second etch stop layer formed on the first etch stop layer.

15. After the step of forming the metal wiring, The method for manufacturing a semiconductor device according to claim 14, further comprising the step of carrying out a heat treatment process for supplying hydrogen to the surface of the substrate.

16. After the step of forming the metal wiring, forming a hydrogen supply layer on the insulating structure; carrying out a heat treatment process for supplying hydrogen to the substrate surface; The method for manufacturing a semiconductor device according to claim 14, further comprising:

17. 15. The method of claim 14, wherein the first and second etching stop layers are formed in-situ in the same chamber.

18. The first etch stop layer is silicon nitride (Si ３ N ４ 15. The method for manufacturing a semiconductor device according to claim 14, wherein the silicon-rich silicon nitride film contains a silicon content higher than that of the silicon nitride film.

19. The method of claim 14, wherein the second etching stop layer includes silicon nitride containing carbon.

20. The method of claim 14 , wherein the second etch stop layer comprises SiCN.

21. The method for manufacturing a semiconductor device according to claim 14, wherein the low dielectric constant layer contains silicon oxide containing carbon and hydrogen (SiCOH).

22. 17. The method of claim 16, wherein the hydrogen supply layer includes a high density plasma (HDP) oxide, a silicon nitride, or a combination thereof.

23. The method for manufacturing a semiconductor device according to claim 15, wherein the heat treatment step is carried out in a hydrogen or deuterium atmosphere.

24. 15. The method of claim 14, wherein the etch stop structure further comprises a third etch stop layer on the second etch stop layer, the third etch stop layer including a hydrogen blocking material.

25. The first etch stop layer is silicon nitride (Si ３ N ４ 25. The method for manufacturing a semiconductor device according to claim 24, wherein the silicon-rich silicon nitride film contains a silicon content higher than that of the silicon nitride film.

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