Decentralized mechanism for test power control of fine grading

Abstract

To provide a method of carrying out a BIST memory test for an integrated circuit.SOLUTION: A method according to the present invention includes the steps of: receiving a plurality of test power control scenarios from a safety controller by a BISR controller to dynamically adapt one or the plurality of power control scenarios to a set of processor cores by the BISR controller in a hierarchical order; carrying out a BIST memory test of a memory block associated with each of the set of processor cores by processor cores of the set of the processor cores; receiving, from the processor cores, a result of the BIST memory test of the memory block by the BISR controller; and transmitting the result of the BIST memory test to the safety controller by the BISR controller.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Recent electronic integrated circuits integrate the functional components of a computer system onto a single silicon semiconductor, regardless of whether they are for general-purpose or specific end-use arrangements. These large-scale integrated circuits, which include computing power to control and manage a wide range of functions and useful applications, are often referred to as "system-on-chip" or "SoC" devices. Typically, recent SoC architectures include embedded memory blocks and one or more processor cores, and the one or more processor cores execute a digital computer function that retrieves executable instructions from memory, performs arithmetic and logical operations on the digital data retrieved from memory, and stores the results of these operations in memory. To acquire and output the data processed by the processor cores, other digital signals, analog signals, or mixed signals, or even RF functions can be integrated into the SoC. Considering the large amount of digital data involved in the implementation of the complex functions of these recent devices, significant solid-state memory functions, including both volatile and non-volatile memory, are implemented in these SoC devices.

[0002] To optimize performance, memory resources can be distributed throughout recent SoC devices. With this distributed memory in the SoC architecture, the memory resources are physically (or logically) closer to the processing functions that the processing functions should access. For example, by placing local memory resources (embedded memory resources) within the processor core, the access time and memory management load are reduced. In some cases, the embedded memory resources are not accessible via the system bus and are only available in the realized processor core, so these memory resources are tested using logic circuits. For example, these SoC devices can include internal test circuit elements (e.g., "built-in self-test" (BIST) circuit elements) that include a logic interface for testing the embedded memory resources.

Summary of the Invention

[0003] In accordance with at least one example of the present disclosure, an integrated circuit includes a set of processor cores, each processor core in the set of processor cores includes a BIST logic circuit element and a plurality of memory blocks coupled to the BIST logic circuit element. Each processor core further includes a plurality of power control circuit elements, each power control circuit element being coupled to each processor core in the set of processor cores; a plurality of isolation circuit elements, each isolation circuit element being coupled to each processor core in the set of processor cores; a built-in self-healing (BISR) controller coupled to each of the set of processor cores, each of the plurality of power control circuit elements, and each of the plurality of isolation circuit elements; and a safety controller coupled to the BISR controller, the plurality of power control circuit elements, and the plurality of isolation circuit elements.

[0004] A method for performing a BIST memory test of an integrated circuit, according to at least one example of the present disclosure, comprises: a BISR controller receiving a plurality of test power control scenarios from a safety controller, the plurality of test power control scenarios relating to a BIST memory test of a set of processor cores and including a hierarchical order for applying one or more test power control scenarios to a set of processor cores; the BISR controller dynamically applying one or more test power control scenarios to the set of processor cores in the hierarchical order; the processor cores of the set of processor cores performing a BIST memory test of a memory block associated with each of the set of processor cores; the BISR controller receiving the results of the BIST memory test of the memory block from the processor cores; and the BISR controller transmitting the results of the BIST memory test to the safety controller. [Brief explanation of the drawing]

[0005] For detailed explanations of various examples, please refer to the attached drawings.

[0006] [Figure 1]These are block diagrams of integrated circuits following various examples.

[0007] [Figure 2] This is a partial block diagram of an architecture for system testing of integrated circuits, following various examples.

[0008] [Figure 3] This flowchart shows the system testing of integrated circuits according to various examples.

[0009] [Figure 4] This is a partial block diagram of an architecture for manufacturing and testing integrated circuits, following various examples.

[0010] [Figure 5] This flowchart shows the manufacturing tests of integrated circuits according to various examples.

[0011] [Figure 6] This is a block diagram of a computing device following various examples. [Modes for carrying out the invention]

[0012] In many modern SoC devices, embedded memory resources (e.g., embedded memory blocks) occupy a significant portion of the SoC device's chip area, sometimes as much as 70% of the total chip area. Continuous improvements in manufacturing technology have made it possible to implement numerous diverse functional units on a single SoC. These functional units often take the form of blocks of programmable or custom logic circuit elements and embedded memory blocks, and are generally referred to as processor cores or "intellectual property cores" (or the abbreviated "IP").

[0013] The SoC may include a general-purpose test controller programmed by a set of instructions to implement BIST tests on various internal and embedded functions of the processor core and to receive and record the responses of these functions from the BIST tests. Some BIST test techniques involve placing hardwired logic on the SoC, such as a general-purpose test controller on which a memory test algorithm ("BIST program / test routine") is implemented on embedded memory blocks. The test controller executes BIST operations or program routines for the SoC during power-up at manufacturing and during reset / reboot. The test controller exports data obtained from BIST operations using a BIST data path, which is a BIST logic circuit element used to send BIST data for analysis. BIST test techniques include executing a BIST program routine, which involves writing a desired data pattern to embedded memory, then addressing and retrieving the stored data in memory and comparing it with expected data.

[0014] In the context of embedded memory, BISR circuit elements, such as built-in self-repair (BISR) controllers (e.g., the general-purpose test controller described herein), are common in large-scale integrated circuits and constitute an interface between the BIST data path and redundant logic (e.g., fuses). The BISR controller determines whether an embedded memory block should be repaired based on the results of a BIST program routine implemented for the memory block, and if so, uses a fuse to determine the mapping of a repair entity instead of the faulty cell. The BIST data path is a function of the SoC and is a separate, independent data path for testing and retrieving data from the embedded memory block under test, and is different from the data path that accesses the embedded memory block in the normal operation of the SoC (e.g., when the SoC performs functional operations based on programmed algorithms). In this regard, the BISR circuit element includes built-in repair analysis (BIRA) logic, which receives failure information for each repairable memory from the BIST circuit element and assigns repair entities to those embedded memory blocks according to redundant analysis.

[0015] BIST memory testing is a test that can be performed on the embedded memory blocks of a processor core during manufacturing or system testing (such as when the SoC in a vehicle is powered on or rebooted). When the SoC is installed in a vehicle in the field, system testing is the BIST memory test performed when the key is on (e.g., the test mode when the SoC is powered on). In the manufacturing environment, BIST testing is intended to replicate the memory testing performed in the field. For example, in BIST testing, signals are applied to various processor cores in the SoC, and BIST program routines are implemented to identify faulty memory blocks. These faulty blocks may be related to components in the vehicle. As more memory blocks are added to the SoC, reducing test time during manufacturing testing becomes a factor. Adding additional logical interfaces to the SoC to reduce test time increases the silicon area of ​​the SoC that utilizes the memory test logic, and similarly increases the power consumed by the SoC during BIST testing. As mentioned above, embedded memory blocks occupy a large portion of the chip area in an SoC, and the power consumed during BIST testing can be higher than the actual power consumed when the SoC's functions are being performed / implemented during normal operation. Reducing test time can be achieved by implementing parallel testing of embedded memory blocks, which may add additional logic gates (e.g., multiple BIST data paths and BISR controllers) to the SoC for BIST testing. However, implementing parallel testing can increase test power during BIST testing and may increase the size of the SoC to accommodate the additional logic gates for BIST testing. In addition, BIST testing can generate instantaneous current (or high peak power) when entering test mode, which can lead to significant silicon losses during manufacturing.

[0016] Disclosed herein are examples of BIST architectures for SoCs that are arranged to include a BISR controller for measuring the test power of memory blocks within a set of processor cores of the SoC during a BIST test. In one example, the SoC is configured using a distributed architecture in which each of the set of processor cores is coupled to independent power control elements and isolation control elements. The BIST test is implemented using one or more test power control scenarios, each test power control scenario containing different test conditions. In one example, each test power control scenario is programmed with test conditions to obtain expected test power measurements of the processor cores. In one example, the SoC includes power control elements and isolation control elements that can receive commands / signals from a safety controller while the test power control scenario is implemented during the BIST test. In one example, power gating and clock gating signals are applied to the memory blocks of one or more processor cores to set the test conditions for the memory blocks of the processor cores. In one example, the power gating and clock gating signals are selectively controlled to implement adjustments to the coarseness or fineness of the test conditions during the BIST test. In some examples, each test power control scenario maps the address range of the memory block being tested to (1) a first subset of processor cores, including the processor core that is powered (e.g., applies power), clocked (e.g., receives a clock signal), and the memory block being tested; (2) a second subset of processor cores that are powered but not clocked (e.g., do not receive a clock signal); and (3) a third subset of processor cores that are neither powered nor clocked. In some examples, commands / signals for applying the test power control scenario may be sent by a safety controller on the SoC or sent to the safety controller by an external test device coupled to the safety controller. In one example, each test power control scenario may be programmed into the safety controller or test device.In one example, the distributed architecture of the SoC is aligned with a central BIST infrastructure, where each of the set of processor cores is coupled to a BISR controller to receive and analyze BIST data from each of the processor cores acquired during BIST testing. By implementing a common BISR controller coupled to each processor core for BIST testing, the additional test circuit elements used for BIST testing (e.g., a dedicated BISR controller for each memory block) are not required, thus potentially reducing the size of the SoC. Furthermore, selectively controlling processor cores during test power control scenarios and before BIST testing reduces the measured test power of the SoC without increasing the size of the SoC.

[0017] Figure 1 is a block diagram of an integrated circuit configured as SoC100 according to various examples. In one example, SoC100 includes a BIST architecture for BIST testing and includes multiple processor cores 102, 104, 106, non-volatile memory arrays such as flash electrically erasable programmable read-only memory (EEPROM) 112, 113, random access memory (RAM) 114, system bus 116, direct memory access (DMA) bus 118, BISR controller 120, fuse read-only memory (ROM) controller 121, fuse ROM 122, safety controller 123, BIST circuit elements 124, analog-to-digital converter (ADC) core 126, timer 128, general-purpose input / output (GPIO) interface 130, and external memory interface (I / F) 132.

[0018] The SoC100 can be designed for any desired function, and multiple processor cores 102-106 can implement that function. In one example, flash EEPROMs 112, 113, RAM 114, BISR controller 120, fuse ROM 122, BIST circuit elements 124, ADC core 126, timer 128, GPIO interface 130, and external memory I / F 132 are coupled to processor cores 110-106 via system bus 116 and DMA bus 118 so that they are accessible to and from each other. In one example, the SoC100 is configured to implement system tests and / or manufacturing tests on processor cores 102-106 using signals / instructions received from safety controller 123, external automated test equipment (ATE), and / or BISR controller 120. In one example, safety controller 123 sends instructions to implement one or more BIST program routines as part of the BIST test during one or more test power control scenarios / modes. In one example, power gating signals and clock gating signals are applied to the embedded memory blocks of processor cores 102-106 in a predefined hierarchical order, independently and selectively controlling the power and clock applied to the memory blocks of processor cores 102-106, thereby reducing the test power consumed by the SoC100 during BIST testing.

[0019] In one example, processor cores 102-106 perform various programmable arithmetic and logical functions suitable for the end use of the SoC100. Examples of various processor cores 102-106 include specific programmable processors such as a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or other application-specific or customized logic, fixed sequence generators, etc. For the purposes of this explanation, each of these processor cores 102-106 is embedded in memory resources (e.g., embedded memory blocks) M1-M NIn combination with these, a block of programmable or custom logic circuit elements is formed. According to this example, memory blocks M1 to M of processor cores 102 to 106. N This can be implemented as RAM for data storage, flash or other non-volatile memory for storing data or programmed instructions, or a combination of these memory types.

[0020] In one example, the BISR controller 120 is connected to the logical interface within each processor core 102-106. In one example, the BISR controller 120 is connected to the processor cores 102-106 via the respective BIST data paths BISTa, BISTb, and BISTc. In one example, memory blocks M1-M N These BIST data paths may not be directly accessible via the system bus 116 or DMA bus 118, but may only be testable through embedded BIST circuit elements (e.g., embedded BIST data paths) and can only communicate via the corresponding BIST data paths. In some examples, the embedded BIST data paths include BISTa on processor core 102, BISTb on processor core 104, and BISTc on processor core 106. These BIST data paths BISTa, BISTb, and BISTc correspond to BIST interfaces through which BIST data is exported to the BISR controller 120 or another test device / circuit element. In one example, the BIST data is located in memory blocks M1~M NThese are obtained based on program routines executed by each processor core 102-106. In one example, the BIST data paths BISTa, BISTb, and BISTc are physically isolated from the DMA bus 118 and system bus 116 and are configured to communicate BIST data to the BISR controller 120 during BIST testing. In another example, the BIST data paths BISTa, BISTb, and BISTc are configured to communicate BIST data via the system bus 116 and / or DMA bus 118 based on time-division access to the system bus 116 and / or DMA bus 118 during BIST testing (for example, when the processor cores are not accessible to perform functional operations).

[0021] In one example, the BISR controller 120 applies a BIST program routine while the power gating signal and clock gating signal are applied by the safety controller 123 or the automated test device (not shown) according to one or more test power control scenarios stored in the safety controller 123 or the automated test device. In one example, each test power control scenario applies the BIST test as a BIST program routine to the memory blocks of the processor cores 102-106, for example, for system testing or manufacturing testing in a hierarchical order, to the embedded memory blocks M1-M implemented in the processor cores. N This includes programmed test conditions for testing. In one example, each test power control scenario includes different test conditions applied before testing the processor cores in a hierarchical order. In one example, the BISR controller 120 controls the embedded memory blocks M1-M in each of the processor cores 102-106. N BIST data resulting from the execution of BIST program routines and self-test routines performed on the processor cores 102-106 is received via BISTa, BISTb, and BISTc. In one example, BISTa, BISTb, and BISTc each receive memory blocks M1-M1 in the processor cores 102-106. NBased on the BIST program routine for each pass / fail determination, BIST data is acquired and exported to the BISR controller 120 for repair analysis. In one example, the pass / fail determination includes determining parametric failures and / or random defects of memory cells within a memory block based on the expected output of the memory block. The BISR controller 120 generates a fail signature indicating any faulty bit locations in the BIST program routine for embedded memory blocks M1-M of processor cores 102-106. N The circuit elements for this purpose are included. The BISR controller 120 determines whether repair is necessary based on the results of a self-test program routine, and if necessary, determines the mapping of repair entities in place of the failed cells. In one example, the BISR controller 120 of the SoC 100 may include built-in repair analysis (BIRA) logic, which receives failure information for each repairable memory via BISTa, BISTb, and BISTc, and assigns repair entities for these memory blocks according to a redundancy analysis algorithm. The redundancy assignment is then transferred to the fuse ROM controller 121 to configure "fuses" in the fuse ROM 122 according to that assignment.

[0022] In one example, processor cores 102-106 are “portable” in the sense that they can be placed in an integrated circuit layout to provide a specific desired function as a whole, and are “reusable” in the sense that the same processor cores can be used in different overall SoC architectures. The specific form in which a given processor core 102, 104, and 106 are defined can also vary. A “soft” core is a form of data that can be synthesized according to a hardware description language or a gate-level “netlist,” while a “hard” core is defined as a low-level physical description or an actual integrated circuit layout. In one example, processor cores 102-106 (e.g., IP cores) may be supplied by different vendors, may have different functions and BIST architectures, and may be within the same large integrated circuit.

[0023] Other memory resources may also be present within the SoC 100, such as those represented by flash EEPROMs 112, 113, and RAM 114. Each of the flash EEPROMs 112, 113, and RAM 114 is accessible via the system bus 116 or the DMA bus 118. Although the flash EEPROMs 112, 113, and RAM 114 are shown as a single block, these memory resources may, in one example, be implemented as multiple memory blocks. Various memory cell types and arrangements may be used to implement the flash EEPROMs 112, 113, and RAM 114. For example, RAM 114 may be implemented as static RAM (SRAM), dynamic RAM (DRAM), etc. In one example, the flash EEPROMs 112, 113, and RAM 114 may be implemented as flash memory, non-flash EEPROM memory, mask-programmable ROM, one-time-programmable (OTP) ROM, etc. Furthermore, each instance of memory resources may have any one of many access architectures, including single or multiple ports to RAM114.

[0024] In one example, other BIST circuit elements 124 may be provided within the SoC 100. In one example, the BIST isolated circuit elements 124 connect processor cores 102-106 to BIST data paths BISTa, BISTb, and BISTc. In one example, the BIST circuit elements 124 may initiate and evaluate self-test routines for circuit elements outside their functions, including their own embedded BIST data paths (e.g., BISTa, BISTb, and BISTc of processor cores 102-106), for example, when the SoC 100 is powered on. The BISR controller 120 may also receive data corresponding to the contents of flash EEPROMs 112, 113, and 114, such as the results of routines performed by the BIST circuit elements 124 or data including test algorithms applied by an external automated test device. Additionally or alternatively, the BISR controller 120 may have an external interface to receive commands and expected data from an automated test device (not shown) and communicate test results in response. According to several examples, the BISR controller 120 is configured to include a unified repair architecture for performing repair analysis on embedded memory blocks in processor cores 102-106 and unembedded memory blocks in the SoC 100.

[0025] Various peripheral functions may also be provided to the SoC100. In one example, these peripherals include an ADC core 126, a timer 128, and a GPIO interface 130, each coupled to the system bus 116 and DMA bus 118 so that they can access the processor cores 102-106 and each other. Other peripherals such as serial interfaces, network interfaces, and various signal processing functions may also be included in the SoC100. The SoC100 also includes other functions such as an external memory interface 132, power circuit elements, clock circuit elements, and other support functions. In a more general sense, various memory blocks and other functions in the architecture of the SoC100 are not necessarily physically realized in the arrangement shown in Figure 1, but instead may be located in various places within the integrated circuit. In this regard, multiple examples of these memory blocks and other functions may actually be physically and logically distributed throughout the SoC100. These and other variations in the arrangement of the SoC100 are included in the scope of this disclosure. In one example, the SoC100 includes a single BISR controller 120 coupled to each processor core, which can reduce the size of the SoC100 for implementing BIST testing. Furthermore, implementing test power control scenarios during BIST testing reduces the measured test power of the SoC without increasing the size of the SoC.

[0026] Figure 2 is a partial block diagram of a distributed BIST architecture 200 of an SoC with multiple processor cores according to various examples. In one example, the BIST architecture 200 includes SoC201, which is an example of SoC100 in Figure 1. In one example, the BIST architecture 200 implements system testing on SoC201 according to one or more test power control scenarios.

[0027] As shown in FIG. 2, SoC 201 includes a CPU 202, a BIST data path 203, a DSP 204, a BIST data path 205, a GPU 206, a BIST data path 207, a global BIST data path 208, a BISR controller 210, a security controller 212, a CPU isolation circuit element 214, a DSP isolation circuit element 216, a GPU isolation circuit element 218, and a CPU power control circuit element 220, a DSP power control circuit element 222, a GPU power control circuit element 224, and a user interface 226. The CPU 202, DSP 204, and GPU 206 are coupled to the global BIST data path 208. The BISR controller 210 is common to the CPU 202, DSP 204, and GPU 206, and is coupled to the CPU 202, DSP 204, and GPU 206 via the global BIST data path 208 and is coupled to the security controller 212. In one example, SoC 201 is configured using a diversified architecture, whereby independent power control circuit elements and isolation control circuit elements for each of the CPU 202, DSP 204, and GPU 206 are coupled to their respective processor cores (e.g., CPU, DSP, GPU, etc.). Also, the diversified architecture is integrated into a central BIST infrastructure, whereby each of the CPU 202, DSP 204, and GPU 206 is coupled to a single BISR controller 210, whereby the BISR controller 210 receives and analyzes BIST data received from the BIST data paths on the CPU 202, DSP 204, and GPU 206 according to a test power control scenario implemented by the security controller 212 before the BISR controller 210 implements a BIST test. Although SoC 201 is shown with the CPU 202, DSP 204, and GPU 206, additional processor cores may be provided as a matter of design choice.

[0028] In one example, the processor cores of SoC 201 each include embedded memory blocks M1 to M N and the embedded memory blocks M1 to M of their respective processor cores NIt may include a dedicated embedded BIST data path. In one example, CPU 202 includes a BIST data path 203 and an embedded memory block M 1_CPU ~M N_CPU The DSP204 includes the BIST data path 205 and the embedded memory block M 1_DSP ~M N_DSP GPU206 includes BIST data path 207 and embedded memory block M 1_GPU ~M N_GPU Includes: Embedded memory blocks M1~M of CPU202, DSP204, and GPU206. N Each of these includes multiple addressable memory locations that are mapped to redundant memory locations / redundant memory cells (e.g., fuse ROM 122 in Figure 1) that can be used to replace a faulty addressable memory location based on a parametric fault or random defect when system tests are implemented for the SoC201. In one example, BIST data paths 203, 205, and 207 correspond to BIST interfaces through which BIST data is exported from the CPU 202, DSP 204, and GPU 206 to the BISR controller 210 via the BIST data path 208. In one example, the CPU 202, DSP 204, and GPU 206 export BIST data to the BISR controller 210 when one or more test power control scenarios are executed by the BISR controller 210.

[0029] In one example, each processor core is coupled to isolated circuit elements and power control elements distributed via the SoC201. For example, the CPU202 is coupled to the CPU isolated circuit element 214 and the CPU power control element 220, the DSP204 is coupled to the DSP isolated circuit element 216 and the BIST power control element 222, and the GPU206 is coupled to the GPU isolated circuit element 218 and the GPU power control element 224. In one example, the safety controller 212 is coupled to the BISR controller 210, the CPU isolated circuit element 214, the CPU power control element 220, the DSP isolated circuit element 216, the DSP power control element 222, the GPU isolated circuit element 218, and the GPU power control element 224, and when the BIST memory test is initiated by the safety controller 212, it may send commands / instructions to the respective isolated circuit elements and power control elements to set test conditions for the CPU202, DSP204, and GPU206. In one example, when the BIST memory test is initiated by the user interface 226, the user may send instructions / signals to the safety controller 212 via the user interface 226 to set test conditions for the CPU 202, DSP 204, and GPU 206 as part of a test power control scenario. In another example, the safety controller 212 may execute operational routines related to performing functional operations on the CPU 202, DSP 204, and GPU 206, depending on the end use of the SoC 201.

[0030] In one example, the CPU power control circuit element 220, the DSP power control circuit element 222, and the GPU power control circuit element 224 are distributed within the SoC 201 and located near their respective processor cores (e.g., CPU 202, DSP 204, GPU 206). In one example, the safety controller 212 may be configured for fine-grained or coarse-grained power gating. In one example, the CPU power control circuit element 220, the DSP power control circuit element 222, and the GPU power control circuit element 224 may receive control signals from the safety controller 212 via the BISR controller 210 to apply or remove power to the memory blocks of the processor cores according to one or more test power control scenarios during the BIST test. For example, the safety controller 212 may apply a power gating signal to the CPU power control circuit element 220, the DSP power control circuit element 222, and the GPU power control circuit element 224, thereby instructing the BISR controller 210 to turn off the power switches in the CPU power control circuit element 220, the DSP power control circuit element 222, and the GPU power control circuit element 224. In one example, the safety controller 212 may instruct the BISR controller 210 to perform coarse-grained power gating, fine-grained power gating, or a combination of fine-grained and coarse-grained power gating during the BIST test. In one example, the power gating signal may turn off a power switch to interrupt the current applied to the memory block of the CPU 202, DSP 204, or GPU 206. In one example, during a BIST test, a power gating signal may be applied to a memory block in the processor (e.g., to perform fine-grained power gating) while other memory blocks are not power gated, resulting in the power-gated memory block not receiving current while other unpower-gated memory blocks receive current, thereby reducing the measured test power (e.g., measured leakage power).In one example, a processor core may have all its memory blocks power-gated off so that they do not receive current (for example, to implement coarse-grained power gating), while memory blocks in another processor core are not power-gated off. In one example, applying coarse-grained power gating turns off current to all memory blocks in a processor core, further reducing the measured test power of the SoC201 during BIST testing.

[0031] In operation, the SoC201 is configured to apply one or more test power control scenarios to reduce the measured test power (e.g., measured leakage power and measured dynamic power) of the SoC201's processor cores. For example, the safety controller 212 may store one or more programmed test power control scenarios, including customized test power profiles for dynamic power and leakage power for the CPU202, DSP204, and GPU206. For example, each test power control scenario may be programmed within the safety controller 212 and applied during the BIST test to set test conditions for the CPU202, DSP204, and GPU206. For example, each test power control scenario is programmed with test conditions to obtain expected test power measurements for the processor cores in the SoC201. In one example, each test power control scenario may be stored or programmed as a software instruction that can be executed by the safety controller when a system test or manufacturing test is initiated for the CPU202, DSP204, and GPU206, or when it is initiated for individual memory blocks of the CPU202, DSP204, and GPU206.

[0032] In one example, the safety controller 212 may enable dynamic clock gating of the CPU 202, DSP 204, and GPU 206, thereby enabling coarse-grained clock gating, fine-grained clock gating, or a combination of fine-grained and coarse-grained clock gating during BIST testing. For example, the safety controller 212 may send a clock gating signal to the CPU 202, DSP 204, and / or GPU 206 and instruct the BISR controller 210 to turn off the clock applied to the CPU 202, DSP 204, and GPU 206. In one example, the safety controller 212 may instruct the BISR controller 210 to send clock gating signals to the BIST data paths 203, 205, and 207 of each of the CPU 202, DSP 204, and GPU 206. As a result, each of the BIST data paths 203, 205, and 207 turns off the clock signal to the untested embedded memory blocks of the processor core (e.g., one of the CPU 202, DSP 204, and GPU 206), while one or more memory blocks under test within the processor core may receive the clock signal (e.g., perform fine-grained clock gating). In another example, the safety controller 212 may instruct the BISR controller to turn off the clock signal to all memory blocks of the processor core during the BIST test (e.g., perform coarse-grained clock gating). In one example, during fine-grained clock gating, the other memory blocks under test continue to receive the clock signal during the BIST test. In one example, the safety controller 212 may enable dynamic clock gating of the memory blocks under test, thereby instructing the BISR controller 210 to dynamically send a signal to the untested memory blocks to clock gate them off while the memory blocks under test receive the clock signal.In one example, the safety controller 212 may enable dynamic clock gating of the processor core, thereby instructing the BISR controller 210 to turn off the embedded data path of the processor core not under test by clock gating the embedded data path to turn off the applied clock signal.

[0033] In one example, the safety controller 212 may be configured for fine-grained or coarse-grained isolation. In one example, the safety controller 212 may be configured to isolate a memory block from other memory blocks in a processor core (e.g., fine-grained isolation) or isolate a processor core from other processor cores (e.g., coarse-grained isolation) by applying isolation control signals to the CPU isolation circuit element 214, the DSP isolation circuit element 216, and the GPU isolation circuit element 218, thereby instructing the BISR controller 210 to set the output value / state of the logic gate in the memory block of the CPU 202, DSP 204, or GPU 206 that receives the isolation signal to a safe value (e.g., turn on BISR isolation). In one example, during fine-grained isolation control, the safety controller 212 may instruct the BISR controller 210 to send isolation control signals to the CPU isolation circuit element 214, the DSP isolation circuit element 216, or the GPU isolation circuit element 218 to set the output values / states of logic gates in untested memory blocks of the CPU 202, DSP 204, or GPU 206 to logical output values ​​(e.g., logical zero values). This ensures that the untested memory blocks do not override the functional behavior in the tested memory blocks (e.g., do not interfere with the output states of logic gates) (e.g., output states at "safe values"). In another example, during coarse-grained isolation control, the safety controller 212 may instruct the BISR controller 210 to send isolation control signals to the CPU isolation circuit element 214, the DSP isolation circuit element 216, or the GPU isolation circuit element 218. This sets the output values / states of logic gates in all memory blocks of CPU202, DSP204, or GPU206 to logical output values ​​(e.g., logical zero values), thereby preventing CPU202, DSP204, or GPU206 from overriding the functional behavior of logic gates within the processor core being tested (e.g., CPU202, DSP204, or GPU206).In one example, the safety controller 212 may selectively execute a BIST program routine that it can selectively instruct the BISR controller 210 to control the clock gating and / or power gating of memory blocks in one or more processor cores not under test, to ensure that the output state of the logic gates in the memory blocks is a safe value (e.g., a logic zero), so as not to override the functional behavior of the memory blocks in the CPU 202, DSP 204, and GPU 206 that execute the BIST routine. Also in one example, each CPU power control circuit element 220, DSP power control circuit element 222, and GPU power control circuit element 224 may be selectively controlled by the BISR controller 210 via the safety controller 212 to apply a clock gating signal to the embedded data path in the processor core not under test, in order to isolate the entire processor core from the BIST data path. In the examples disclosed herein, the SoC 201 includes a common BISR controller 210 coupled to each processor core, which may reduce the size of the SoC 100 for implementing the BIST test. Furthermore, implementing test power control scenarios during BIST testing reduces the measured test power of the SoC without increasing the size of the SoC.

[0034] Figure 3 is a flowchart illustrating test methods 300 for integrated circuits according to various examples. In one example, test method 300 implements a system test for an integrated circuit using a BIST architecture, which in one example is a BIST architecture 200 including the CPU 202, DSP 204, and / or GPU 206 of the SoC 201 shown and described in Figure 2. In one example, test method 300 implements a system test for the SoC 201 using one or more test power control scenarios that set test conditions for the SoC 201, corresponding to one or more test power control scenarios during the BIST test of the SoC 201.

[0035] Continuing to refer to Figure 2, in step 302, the safety controller 212 may determine to perform a system test in accordance with the BIST test for the processor core. In one example, the safety controller 212 may determine to perform a system test for the CPU 202 in accordance with programmed instructions stored or programmed in the safety controller 212. In one example, the safety controller 212 may receive programmed instructions from the user via the user interface 226. The programmed instructions may include one or more test power control scenarios that cause the safety controller 212 to perform the BIST test for the CPU 202, DSP 204, and GPU 206. In one example, the test power control scenario may identify a hierarchical sequence for testing the CPU 202, DSP 204, and GPU 206, thereby causing the safety controller to send signals / instructions to the BISR controller 210 to apply power signals, clock signals, and isolation control signals to the processor core, after which the BISR controller 210 executes the BIST programme routine in accordance with the BIST test to test the embedded memory blocks of the CPU 202.

[0036] In one example, while receiving instructions to perform a system test on the CPU 202, the safety controller 212 may execute functional instructions that perform operations related to the functionality of the SoC 201. In one example, the safety controller 212 implements a system test on the CPU 202 by initiating the system test by sending control signals to the CPU 202, DSP 204, and / or GPU 206, thereby applying clock gating and power gating signals to processor cores not being tested (e.g., DSP 204 and GPU 206), and then one or more BIST program routines are executed to test the memory blocks of the CPU 202 (e.g., the processor cores being tested).

[0037] In step 304, the safety controller 212 sets a first test power control scenario for the SoC 201. In one example, the first test power control scenario may be one of several test power control scenarios. In one example, the safety controller 212 may set a first test power control scenario for the CPU 202 by applying power gating signals and clock gating signals to the CPU 202, DSP 204, and GPU 206, as specified by the first test power control scenario, and by instructing the BISR controller 210 to set one or more test conditions for the CPU 202, DSP 204, and GPU 206. In one example, each test power control scenario in the multiple test scenarios includes test conditions for the CPU 202, DSP 204, and GPU 206 that are different from other test power control scenarios for the CPU 202, DSP 204, and GPU 206. In one example, the power gating signal and clock gating signal applied to the processor core turn off the clock to the untested processor core or the memory block of the untested processor core, turn on BISR isolation to the untested processor core or the memory block of the untested processor core, and / or turn off power to the untested processor core or the memory block of the untested processor core.

[0038] In one example, the safety controller 212 instructs the BISR controller 210 to send a clock gating signal via the global BIST data path 208 to the BIST data path 205 to turn off the clock signal to the DSP 204 (for example, clock gating the DSP 204) in order to prevent the logic gates in the memory block of the DSP 204 from receiving a clock signal that could switch the logic gates to an output state.

[0039] In one example, the safety controller 212 instructs the BISR controller 210 to send an isolation control signal via the BIST data path 208 to the GPU isolation circuit element 218 in order to turn on the isolation of the GPU 206 (for example, to turn on GPU BISR isolation), thereby enabling the memory block M in the GPU 206. 1_GPU ~M N_GPU The output state / value becomes a safe value.

[0040] In one example, the safety controller 212 instructs the BISR controller 210 to send a power gating signal to the GPU power control circuit element 224 to turn off power to the GPU 206 (for example, by power gating the GPU 206) after turning on GPU BISR isolation. In one example, power gating the GPU 206 after turning on GPU BISR isolation prevents the logic gates of the memory blocks in the GPU 206 from experiencing excessive leakage current (for example, which may result from a short circuit caused by turning off a logic gate with a high output value).

[0041] In one example, after power gating the GPU 206, the safety controller 212 controls the memory block M during system testing. 1_CPU ~M N_CPU By instructing the BISR controller 210 to perform dynamic clock gating to reduce test power during the BIST test, the memory block M of the CPU 202 is controlled. 1_CPU ~M N_CPU This can enable fine-grained clock gating for each of the memory blocks.

[0042] In step 306, the safety controller 212 triggers a system test of the processor core on the SoC 201. In one example, the safety controller 212 may trigger the BISR controller 210 to send control commands / signals to the CPU 202 to perform a system test, which is carried out by the CPU 202 according to one or more BIST program routines.

[0043] In step 308, the BISR controller 210 performs a memory test on the memory blocks on the processor core. For example, the BISR controller 210 performs a memory test on the memory blocks M in the CPU 202 based on the BIST program routine stored in and executed by the CPU 202. 1_CPU ~M N_CPU A fine-grained system test is performed on the memory block M. In one example, in the case of a fine-grained system test, the BISR controller 210 may dynamically clock-gate the untested memory blocks so that the clock signal to the untested memory blocks is turned off while the memory block under test is being tested. The BIST program routine controls the memory block M. 1_CPU ~M N_CPU Based on the expected output, one or more memory blocks M 1_CPU ~M N_CPU To determine whether a memory block M has a parametric fault or a random defect, 1_CPU ~M N_CPU This includes performing various operations (e.g., writing and reading) to sequentially test the system.

[0044] In step 310, the BISR controller 210 transmits a pass / fail judgment to the safety controller 212. In one example, the BISR controller 210 uses the BIST data received via the BIST data path 203 to determine each memory block M of the CPU 202. 1_CPU ~M N_CPU The results of the BIST test are obtained, including the pass / fail determination of one or more cells within the test. In one example, the BISR controller 210 transmits the pass / fail determination to the safety controller 212 via the BIST data path 208.

[0045] In step 312, the safety controller 212 is ready to perform functional operations of the SoC 201. For example, after receiving BIST data from the CPU 202, the safety controller 212 sends commands / signals to the BISR controller 210 to reset / clear the logic gates in the BIST data paths (e.g., BIST data paths 208 and 203). For example, after resetting BIST data paths 203 and 208, the safety controller 212 is ready to execute functional instructions for any desired operation related to the functionality of the SoC 201.

[0046] In step 314, the safety controller 212 may determine to perform a system test on another processor core of the SoC 201, such as the DSP 204. In one example, the safety controller 212 may receive programmed instructions from the user via the user interface 226. In one example, the safety controller 212 may send instructions / signals to the BISR controller 210 after completing a system test on the memory block of the CPU 202, or the user may send instructions / signals to the safety controller 212 via the user interface 226 to initiate a system test on the DSP 204. In one example, the safety controller 212, or the user via the user interface 226, may determine to perform a system test on the DSP 204 according to programmed instructions stored or programmed in the safety controller 212 or sent by the user. The programmed instructions may include one or more test power control scenarios that cause the safety controller 212 to perform a BIST test on the DSP 204. In one example, a test power control scenario may identify a hierarchical sequence in which power signals, clock signals, and isolation control signals are applied to the processor core by the BISR controller 210, and then the BISR controller 210 executes a BIST program routine according to a BIST test to test the embedded memory block of the DSP 204. In one example, while the SoC 201 is turned on (e.g., receiving power and clock signals), and while the CPU 202, DSP 204, and GPU 206 are executing functional instructions to perform functional operations related to the functionality of the SoC 201, the safety controller 212 may send a test execution signal to the BISR controller 210.

[0047] In step 316, the safety controller 212 sets up a second test power control scenario for the DSP 204 of the SoC 201. For example, the safety controller 212 may set up a test power control scenario for the DSP 204 by instructing the BISR controller 210 to apply power gating signals and clock gating signals to the CPU 202, DSP 204, and GPU 206, setting one or more test conditions different from the first test power control scenario for the CPU 202. For example, the safety controller 212 may instruct the BISR controller 210 to send a clock gating signal to the processor core via the BIST data path 208 to turn off the clock to or to the memory block of an untested processor core, an isolation control signal to turn on the BISR isolation to or to the memory block of an untested processor core, and a power gating signal to turn off power to or to the memory block of an untested processor core.

[0048] In one example, the safety controller 212 may instruct the BISR controller 210 to send a clock gating signal via the BIST data path 208 to the BIST data path 203 to turn off the clock signal to the CPU 202 (for example, to clock gate the CPU 202) in order to prevent a logic gate in the memory block of the CPU 202 from switching its output state.

[0049] In one example, the safety controller 212 may instruct the BISR controller 210 to send an isolation control signal to the GPU isolation circuit element 218 via the BIST data path 208 to turn on the BISR isolation of the GPU 206 (for example, to turn on GPU BISR isolation).

[0050] In one example, the safety controller 212 may instruct the BISR controller 210 to send a power gating signal to the GPU power control circuit element 224 (e.g., to power off the GPU 206) to turn off power to the GPU 206 after turning on the GPU BISR isolation. In one example, power gating the GPU 206 after turning on the GPU BISR isolation prevents a short circuit caused by excessive leakage current.

[0051] In one example, after power gating the GPU 206, the safety controller 212, during system testing, controls memory block M 1_DSP ~M N_DSP By instructing the BISR controller 210 to perform dynamic clock gating, fine-grained clock gating for the memory blocks of the DSP 204 can be enabled.

[0052] In step 318, the safety controller 212 triggers a system test of the processor core on the SoC 201. In one example, the safety controller 212 may trigger the BISR controller 210 to send a command to the DSP 204 to perform a system test on the DSP 204 according to one or more BIST program routines by sending a command / signal to the BISR controller 210.

[0053] In step 320, the BISR controller 210 performs a memory test on the memory blocks on the processor core. For example, the BISR controller 210 performs a memory test on the memory blocks M in the DSP 204 based on the BIST program routine stored in and executed by the DSP 204. 1_DSP ~M N_DSPA fine-grained system test is performed on the memory block M. In one example, in the case of a fine-grained system test, the BISR controller 210 may dynamically clock-gate the memory blocks not under test so that the clock signal to the memory blocks not under test is turned off while the memory block under test is being tested. The BIST program routine controls the memory block M. 1_DSP ~M N_DSP Based on the expected output, one or more memory blocks M 1_DSP ~M N_DSP To determine whether memory block M has parametric defects and / or random defects, 1_DSP ~M N_DSP This includes performing various operations (e.g., writing and reading) to sequentially test the system.

[0054] In step 322, the BISR controller 210 transmits a pass / fail judgment to the safety controller 212. In one example, the BISR controller 210, based on the BIST data received via the BIST data path 205, processes the memory block M in the DSP 204. 1_DSP ~M N_DSP A pass / fail judgment is obtained for each of these. In one example, the BISR controller 210 transmits the pass / fail judgment to the safety controller 212 via the BIST data path 208.

[0055] In step 324, the safety controller 212 is ready to perform the functional operations of the SoC 201. For example, after receiving BIST data from the DSP 204, the safety controller 212 sends commands / signals to the BISR controller 210 to reset / clear the logic gates in the BIST data paths (e.g., BIST data paths 208 and 205). For example, after resetting BIST data paths 205 and 208, the safety controller 212 is ready to execute functional instructions for any desired functions related to the functionality of the SoC 201.

[0056] Figure 4 is a partial block diagram of a distributed BIST architecture 400 of an SoC with multiple processor cores according to another example. In this example, the BIST architecture 400 includes an SoC 402 having substantially the same components as the BIST architecture 200, but includes a test device 426 instead of a safety controller 212. In operation, the test device 426 is coupled to a BISR controller 210, and when a BIST memory test is initiated by the test device 426 and performed by the BISR controller 210, it may send instructions / signals to the respective processor cores (e.g., CPU 202, DSP 204, and GPU 206) via the BISR controller 210 in a predefined hierarchical manner for setting test conditions for the CPU 202, DSP 204, and GPU 206. In one example, the test device 426 may transmit power gating signals to the CPU power control circuit element 220, the DSP power control circuit element 222, and the GPU power control circuit element 224 in order to independently control the power applied to the memory blocks of each processor core CPU 202, DSP 204, and GPU 206 when the BIST memory test is initiated by the test device 426. In another example, the test device 426 may transmit independent clock gating signals to the BIST data paths 203, 205, and 207 in order to independently control the clock signals applied to the memory blocks of each processor core CPU 202, DSP 204, and GPU 206 when the BIST memory test is initiated by the test device 426. In one example, the SoC 402 includes a common BISR controller 210 coupled to each processor core, which can reduce the size of the SoC 402 for implementing the BIST test. Furthermore, the test equipment can apply test power control scenarios during BIST testing, thereby reducing the measured test power of the SoC402 without increasing the size of the SoC402.

[0057] Figure 5 is a flowchart illustrating test methods 500 for integrated circuits according to various examples. In one example, test method 500 demonstrates the implementation of manufacturing tests for an integrated circuit using a BIST architecture, where the BIST architecture is, in one example, a BIST architecture 400 including the CPU 202, DSP 204, and GPU 206 of the SoC 402 shown in Figure 4. In one example, test method 500 is implemented using one or more test power control scenarios in which the BISR controller 210 sets test conditions for the SoC 402 during the BIST test of the SoC 402.

[0058] Continuing to refer to Figure 4, in step 502, the SoC402 is powered on with the default core active. The default core is, in one example, the CPU202, but may be configured as any other processor core. In one example, the SoC402 is powered on with the CPU202 executing instructions that perform functional operations while the DSP204 and GPU206 are inactive (e.g., not performing functional operations).

[0059] In step 504, the test device 426 starts manufacturing tests on the default processor core. In one example, the test device 426 performs manufacturing tests on the CPU 202, thereby executing instructions to set the test conditions for implementing BIST tests on the SoC 402.

[0060] In step 506, the test apparatus 426 sets a first test power control scenario for the default processor core of the SoC 402. For example, the test apparatus 426 sets a test power control scenario for the CPU 202 (e.g., the default processor core) by applying power gating signals and clock gating signals to the memory blocks of the CPU 202, DSP 204, and GPU 206 via the BISR controller 210, thereby setting one or more test conditions for the memory blocks of the CPU 202, DSP 204, and GPU 206.

[0061] In one example, the test device 426 instructs the DSP isolation circuit element 216 to send an isolation control signal to the DSP isolation circuit element 216 to set the output value / state of the logic gate in the memory block of the DSP 204 that receives the isolation signal to a safe value (for example, to turn on DSP BISR isolation), and to prevent the logic gate in the memory block of the DSP 204 from switching its output state when power is applied to the DSP 204.

[0062] In one example, the test device 426 instructs the BISR controller 210 to send a power gating signal to the DSP power control circuit element 222 to turn off the power applied to the memory block of the DSP 204 after turning on the DSP BISR isolation.

[0063] In one example, the test device 426 instructs the BISR controller 210 to send an isolation control signal to the GPU isolation circuit element 218 via the BIST data path 208 in order to turn on the BISR isolation of the GPU 206 (for example, to turn on GPU BISR isolation). This ensures that the output state of the logic gates in the memory block of the GPU 206 is at a safe value, and that no leakage current increases when power is removed from the DSP 204 after GPU BISR isolation.

[0064] In one example, the test device 426, after turning on GPU BISR isolation, instructs the BISR controller 210 to send a power gating signal to the GPU power control circuit element 224 in order to turn off the power applied to the memory blocks of the GPU 206.

[0065] In step 508, the test device 426 restarts the SoC 402 in a test power control scenario. For example, the test device 426 sends commands / signals to the CPU 202, DSP 204, and GPU 206 to restart the processor cores using the test power control scenario.

[0066] In step 510, the test apparatus 426 sends a command to trigger a manufacturing test of the default processor core on the SoC 402. For example, the safety controller 212 may instruct the BISR controller 210 to send control commands to the CPU 202 to perform the manufacturing test according to one or more BIST program routines by sending commands / signals to the BISR controller 210.

[0067] In step 512, the BISR controller 210 performs manufacturing tests on the memory blocks of the default processor core. For example, the BISR controller 210 tests the memory blocks M in the CPU 202 based on the BIST program routines stored in and executed by the CPU 202. 1_CPU ~M N_CPU Fine-grained manufacturing tests are performed on the memory block. For example, in the case of a fine-grained system test, the BISR controller 210 may dynamically clock-gate the memory blocks not under test so as to turn off the clock signal to the memory blocks not under test while the memory block under test is being tested via one or more BIST program routines. The BIST program routine controls the memory block M 1_CPU ~M N_CPU Based on the expected output, one or more memory blocks M 1_CPU ~MN_CPU To determine whether a memory block M has a parametric fault or a random defect, 1_CPU ~M N_CPU This includes performing various operations (e.g., writing and reading) to sequentially test the system.

[0068] In step 514, the BISR controller 210 transmits a pass / fail judgment to the test device 426. In one example, the BISR controller 210 transmits a pass / fail judgment to the memory block M 1_CPU ~M N_CPU Based on the BIST data for each memory block M of CPU202, 1_CPU ~M N_CPU The pass / fail judgment is obtained via BIST data paths 203 and 208. In one example, the BISR controller 210 transmits the pass / fail judgment to the test device 426 via the BIST data path 208.

[0069] In step 516, the test device 426 initiates manufacturing tests on the second processor core. In one example, the test device 426 performs manufacturing tests on the DSP204 by sending instructions to implement the BIST tests for the DSP204.

[0070] In step 518, the test apparatus 426 sets up a second test power control scenario for the DSP204 of the SoC402.

[0071] In one example, the test device 426 may configure a second test power control scenario for the DSP 204 by instructing the BISR controller 210 to apply a clock gating signal to the BIST data path 203 via the BIST data path 208 that turns off the clock signal to the CPU 202 (for example, clock gating the CPU 202) in order to prevent the logic gates in the memory block of the CPU 202 from switching the output state.

[0072] In one example, the test device 426 instructs the BISR controller 210 to send an isolation control signal via the BIST data path 208 to the DSP isolation circuit element 216 to turn off BISR isolation to the DSP 204 (for example, to turn off DSP BISR isolation), thereby allowing the logic gates on the DSP 204 to be in any output value / state.

[0073] In one example, the test device 426 instructs the BISR controller 210 to send a power control signal to the DSP power control circuit element 222 to turn on the power applied to the DSP 204 after turning off the DSP BISR isolation.

[0074] In one example, the test device 426 instructs the BISR controller 210 to send an isolation control signal to the GPU isolation circuit element 218 via the BIST data path 208 so that the output value / state of the logic gate in the memory block of the GPU 206 that receives the isolation signal is set to a safe value (for example, to turn on GPU BISR isolation).

[0075] In one example, the test device 426, after turning on GPU BISR isolation, instructs the BISR controller 210 to send a power gating signal to the GPU power control circuit element 224 in order to turn off the power applied to the memory blocks of the GPU 206.

[0076] In one example, after power gating the GPU 206, the test device 426 obtains a pass / fail determination for one or more memory cells within each memory block M when the manufacturing test is performed. 1_DSP ~M N_DSP By instructing the BISR controller 210 to perform dynamic clock gating for each memory block within the DSP204, 1_DSP ~M N_DSP This may enable fine-grained clock gating for [the target system].

[0077] In step 520, the test apparatus 426 triggers a manufacturing test of the second processor core of the SoC201. In one example, the test apparatus 426 may trigger the BISR controller 210 to send control commands to the DSP204 to perform a manufacturing test of the memory block of the DSP204 using fine-grained adjustments according to one or more BIST program routines by sending commands / signals to the BISR controller 210.

[0078] In step 522, the BISR controller 210 performs manufacturing tests on the memory block of the second processor core. For example, the BISR controller 210 performs manufacturing tests on the memory block M in the DSP 204 based on the BIST program routine stored in and executed by the DSP 204. 1_DSP ~M N_DSP A fine-grained manufacturing test is performed on the memory block M. In one example, in the case of a fine-grained system test, the test device 426 may dynamically clock-gate the memory blocks not under test so as to turn off the clock signal to the memory blocks not under test while the memory block under test is being tested via one or more BIST program routines. The BIST program routine controls the memory block M. 1_DSP ~M N_DSP Based on the expected output, one or more memory blocks M 1_DSP ~M N_DSP To determine whether a memory block M has a parametric fault or a random defect, 1_DSP ~M N_DSP This includes performing various operations (e.g., writing and reading) to sequentially test the system.

[0079] In step 524, the BISR controller 210 transmits a pass / fail judgment to the test device 426. In one example, the BISR controller 210 transmits a pass / fail judgment to the memory block M 1_DSP ~M N_DSP Based on the BIST data for each memory block M of the DSP204 1_DSP ~M N_DSPThe pass / fail judgment for the test is obtained via BIST data paths 203 and 208, and the pass / fail judgment is transmitted to the test device 426.

[0080] In step 526, the test device 426 begins manufacturing tests on the third processor core. In one example, the test device 426 performs manufacturing tests on the GPU 206, thereby executing instructions to implement the BIST tests for the GPU 206.

[0081] In step 528, the test apparatus 426 sets up a third test power control scenario for the GPU 206 of the SoC 402. For example, the test apparatus may set up a third test power control scenario for the GPU 206 by instructing the BISR controller 210 to apply an isolation control signal to the GPU isolation circuit element 218 via the BIST data path 208 to turn off the GPU BISR isolation.

[0082] In one example, the test device 426 instructs the BISR controller 210 to send a power control signal to the GPU power control circuit element 224 to turn on the power applied to the GPU 206 after turning off the GPU BISR isolation.

[0083] In one example, the test device 426 instructs the BISR controller 210 to send a clock gating signal to the BIST data path 203 via the BIST data path 208 that turns off the clock signal applied to the CPU 202 (for example, clock gating the CPU 202).

[0084] In one example, the test device 426 instructs the BISR controller 210 to send an isolation control signal to the DSP isolation circuit element 216 to turn on the DSP BISR isolation.

[0085] In one example, the test device 426 turns on the DSP BISR isolation and then instructs the BISR controller 210 to send a power gating signal to the DSP power control circuit element 222 to turn off the power applied to the memory block of the DSP 204.

[0086] In one example, after power-gating the DSP204, the test device 426 uses memory block M 1_GPU ~M N_GPU The GPU 206's memory blocks M are controlled by performing dynamic clock gating on each memory block and instructing the BISR controller 210 to obtain a pass / fail determination for each memory block during system testing. 1_GPU -M N_GPU This enables fine-grained clock gating, thereby reducing test power during BIST testing.

[0087] In step 530, the test apparatus 426 triggers a manufacturing test of the third processor core of the SoC 402. In one example, the test apparatus 426 may trigger the BISR controller 210 to send control commands to the GPU 206 to execute the manufacturing test according to one or more BIST program routines by sending commands / signals to the BISR controller 210.

[0088] In step 532, the BISR controller 210 performs manufacturing tests on the memory block of the third processor core. For example, the BISR controller 210 performs manufacturing tests on the memory block M in the GPU 206 based on the BIST program routine stored in and executed by the GPU 206. 1_GPU ~M N_GPU A manufacturing test of fine particle size will be conducted. In one example, in the case of a system test of fine particle size, the test apparatus 426 is M 1_GPU ~M N_GPU While one or more memory blocks under test are being tested via BIST program routines, the clock signal to memory blocks not being tested is turned off.1_GPU ~M N_GPU can dynamically clock gate memory blocks that are not subject to testing within. The BIST program routine is for memory block M 1_GPU ~M N_GPU Based on the expected output of, one or more memory blocks M 1_GPU ~M N_GPU To determine whether has parametric faults or random defects, memory block M 1_DSP ~M N_DSP Includes performing various operations (e.g., writing and reading) to sequentially test.

[0089] In step 534, the BISR controller 210 sends a pass / fail determination to the test device 426. In one example, the BISR controller 210 receives BIST data for each memory block M of the GPU 206 via the BIST data paths 203 and 208, and uses the BIST data to obtain a pass / fail determination for the memory block M 1_GPU ~M N_GPU For. In one example, the BISR controller 210 sends a pass / fail determination to the test device 426. 1_GPU ~M N_GPU To obtain a pass / fail determination for.

[0090] FIG. 6 is a block diagram of a computing device 600 according to various examples. For example, the computing device 600 can be a system such as an automobile 602, or any type of electronic system operable to process information or incorporated into or coupled (e.g., connected) to such a system. In some examples, the computing device 600 includes a system-on-chip (SoC) 610, a central processing unit (CPU) 612, a storage 614 (e.g., random access memory (RAM)), a power supply 616, input / output (I / O) ports 618, a user interface (UI) 620, a display 622, and a network device 624.

[0091] In some examples, SoC610 is SoC100 as described in Figure 1, and can be programmed to implement a test power control scenario for the embedded memory block of SoC610.

[0092] In some examples, the CPU 612 is a CISC (Complex Instruction Set Computer) CPU, a RISC (Reduced Instruction Set Computer) CPU, an MCU (Microcontroller Unit), or a Digital Signal Processor (DSP). The CPU 612 includes one or more processor cores. One or more processor cores are arranged to execute code to transform one or more processors into a special-purpose machine or to improve the functionality of other components within the computing device 600, providing the desired output without performing similar operations for one or more other processor cores. The CPU 612 includes memory and logic for storing information that is frequently accessed from the storage 614.

[0093] In some examples, storage 614 is memory such as an on-processor cache, off-processor cache, RAM, flash memory, or disk storage, which, when executed by the CPU 612, stores one or more software applications 626 (e.g., embedded applications) that perform the functions described herein related to the computing device 600.

[0094] In one example, the user controls the computing device 600 using the UI 620. In another example, while running the software application 626, the user provides input to the computing device 600 via the UI 620 and receives output from the computing device 600. In some examples, the output is provided via a display 622, indicator lights, a speaker, vibration, etc. Inputs are received using audio and / or video inputs (e.g., using voice or image recognition) and electronic and / or mechanical devices such as keypads, switches, proximity detectors, gyroscopes, accelerometers, etc.

[0095] The CPU 612 and power supply 616 are coupled to I / O port 618. In one example, I / O port 618 provides an interface configured to receive input from (and / or provide output to) network device 624. Network device 624 may include any device (including test equipment) capable of point-to-point and / or network communication with computing device 600. Computing device 600 is often coupled to peripherals and / or computing devices, including tangible non-temporary media (such as flash memory) and / or wired or wireless media. These and other input / output devices are selectively coupled to computing device 600 by external devices using wireless or wired connections. Storage 614 is accessible, for example, by network device 624. The CPU 612, storage 614, and power supply 616 are also optionally coupled to an external power supply (not shown) configured to receive power from a power source (battery, solar cell, "live" power cord, inductive field, fuel cell, capacitor, etc.).

[0096] In one example, the power supply 616 is located in the same physical assembly as the computing device 600 or is coupled to the computing device 600. Although not shown in Figure 6, the power supply 616 includes power generating components. The power generating components include one or more power switches. Each switch is independently controlled to generate power to supply power in various energy-saving modes, thereby supplying (and / or turning off) individual voltages by these power switches according to the selected energy-saving mode and the various components arranged within a particular power domain.

[0097] The term “to combine” is used throughout this specification. This term may encompass connections, communications, or signaling paths that enable a functional relationship consistent with the descriptions herein. For example, if device A generates a signal to control control device B to perform a certain action, in the first example device A is combined with device B, and in the second example device A is combined with device B via an intervening component C, however, in this case the intervening component C does not substantially alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0098] A device “configured” to perform a certain task or function may be configured by the manufacturer at the time of manufacture to perform that function (e.g., by programming and / or hardwiring), or may be configured (or reconfigurable) by a user after manufacture to perform such function and / or other additional or alternative functions. Such configuration may be via the device’s firmware and / or software programming, or via the configuration and / or layout of hardware components, or via the interconnection of devices, or a combination thereof.

[0099] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more power sources (such as voltage and / or current power sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), which may be adapted to be coupled to at least some of the passive elements and / or power sources, thereby forming the described structure, for example, by an end user and / or a third party, either at the time of manufacture or at a later point in time. Certain components are described herein as belonging to a particular process technology, but these components may be interchangeable with components of other process technologies. Circuits described herein are reconfigurable to include the replaced components and may provide functionality at least partially similar to the functionality available before the replacement of the components.

Claims

1. A circuit comprising: a plurality of processor cores, each processor core including a plurality of memory blocks; a plurality of power control circuits respectively coupled to the plurality of processor cores; a plurality of isolation circuits respectively coupled to the plurality of processor cores; a controller circuit element coupled to each processor core of the plurality of processor cores, each power control circuit of the plurality of power control circuits, and each isolation circuit of the plurality of isolation circuits, selecting a subset of processor cores of the plurality of processor cores and a subset of memory blocks of the processor cores for testing; non-selected processor cores of the plurality of processor cores are at least one of power-gated, clock-gated, and isolated from the selected memory block; the controller circuitry configured to The circuit includes:

2. The circuit of claim 1, a first common controller coupled to the common data path; and a second common controller coupled to the first common data path.

3. The circuit according to claim 2, a circuit wherein each of the plurality of interfaces includes a local data path coupling each memory block of the plurality of memory blocks of the associated processor core to the common data path;

4. The circuit of claim 2, The circuit, wherein the controller circuitry further includes a second common controller coupled to the first common controller, the second common controller configured to be coupled to a user interface.

5. The circuit of claim 4, a circuit configured to receive test conditions from the second common controller based on program instructions stored in the second common controller or obtained by the second common controller from the user interface; 6. The circuit of claim 5, To apply the test conditions, the first common controller, based on the program instructions: selecting a subset of processor cores of the plurality of processor cores and a subset of memory blocks of the subset of processor cores for testing; applying a clock signal to each memory block of the selected subset of memory blocks; clock-gating the unselected memory blocks by turning off the clock signal to the unselected memory blocks; a test is performed on the selected memory block; The circuit is further configured as follows.

7. The circuit of claim 6, the selected subset of processor cores includes a first processor core of the plurality of processor cores, and the selected subset of memory blocks includes a subset of memory blocks of the first processor core; a circuit in which a selected subset of memory blocks of the first processor core are tested one at a time, a clock signal is applied to each memory block for testing during the testing of the memory block, and no clock signal is applied before and after the testing of the memory block.

8. The circuit of claim 5, To apply the test conditions, the first common controller, based on the program instructions: selecting a subset of processor cores of the plurality of processor cores and a subset of memory blocks of the subset of processor cores for testing; applying a power signal to each memory block of the selected memory block; applying a power gating signal to the unselected memory blocks to power off the unselected memory blocks; a test is performed on the selected subset of memory blocks; The circuit is further configured as follows.

9. The circuit of claim 8, the selected subset of processor cores includes a first processor core of the plurality of processor cores, and the selected subset of memory blocks includes a subset of memory blocks of the first processor core; a circuit in which a selected subset of memory blocks of the first processor core are tested one at a time, a power signal is applied to each memory block selected for testing during testing of that memory block, and no power signal is applied before and after testing of that memory block.

10. The circuit of claim 5, To apply the test conditions, the first common controller, based on the program instructions: selecting a subset of processor cores of the plurality of processor cores and a subset of memory blocks of the subset of processor cores for testing; isolating the unselected memory blocks by setting the output values ​​of the unselected memory blocks to a set value; a test is performed on the selected subset of memory blocks; The circuit is further configured as follows.

11. The circuit of claim 10, the selected subset of processor cores includes a first processor core of the plurality of processor cores, and the selected subset of memory blocks includes a subset of memory blocks of the first processor core; a circuit in which a subset of selected memory blocks of the first processor core are tested one at a time, and a memory block selected for testing is isolated between testing of another memory block selected for testing.

12. The circuit of claim 4, the first common controller: receiving a plurality of test conditions from the second common controller based on program instructions stored in the second common controller or obtained by the second common controller from the user interface; applying each test condition of the plurality of test conditions in a particular order; A circuit configured as follows.

13. The circuit of claim 12, The plurality of test conditions are: a first test condition that selects a first subset of processor cores of the plurality of processor cores and a first subset of memory blocks of the first subset of processor cores for testing; a second test condition that selects a second subset of processor cores of the plurality of processor cores and a second subset of memory blocks of the second subset of processor cores; Including, the first subset of memory blocks and the second subset of memory blocks are mutually exclusive.

14. A method comprising: receiving, by a first controller, test conditions including a selection of one or more processor cores of a plurality of processor cores and one or more memory blocks of the selected one or more processor cores to be tested; applying, by the first controller, the test conditions to the selected one or more processor cores, the applying including power gating, clock gating, or isolating unselected memory blocks; testing each memory block of the selected one or more memory blocks; A method comprising:

15. The method of claim 14, The method further comprising receiving, by the first controller, the test conditions from the second controller based on program instructions stored in or obtained by the second controller.

16. The method of claim 14, the test conditions include selecting a first processor core of the plurality of processor cores and selecting all memory blocks of the first processor core; The application of applying the test conditions to the first processor core and all memory blocks of the first processor core by the first controller; power gating, clock gating, or isolating all processor cores of the plurality of processor cores except for the first processor core; A method comprising:

17. The method of claim 14, the receiving includes receiving, by the first controller, a plurality of test conditions including the test condition, each of the plurality of test conditions including a selection of one or more processor cores of a plurality of processor cores and one or more memory blocks of the selected one or more processor cores to be tested; the applying includes serially applying, by the first controller, each of the plurality of test conditions to the selected processor core, and the applying each of the plurality of test conditions includes power gating, clock gating, or isolating unselected memory blocks; The method, wherein the testing includes testing each memory block of the selected one or more memory blocks for the corresponding test condition for each of the plurality of test conditions.

18. The method of claim 17, The method wherein the plurality of test conditions are applied in a specific order.

19. The method of claim 14, the test conditions include selecting a first processor core of the plurality of processor cores and a subset of memory blocks of the first processor core; wherein said applying includes applying the test conditions by the first controller to a subset of memory blocks of the first processor core, one at a time, wherein power and clock signals are applied to each memory block selected for testing during testing of that memory block, and power and clock signals are not applied while other memory blocks selected for testing are tested.

20. The method of claim 14, The method further includes receiving, by the first controller, instructions to perform the test in response to receiving a trigger signal from a test device.

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